Wiring board

Abstract

Improved connection quality of conductor layers using via conductors. [Solution] The wiring board 1 of the embodiment has a first surface 1F and a second surface opposite to the first surface 1F, and includes a first build-up section 10 which includes a plurality of laminated insulating layers 11 and a plurality of conductor layers 12, and a second build-up section 20 which includes a laminated insulating layer 21 and a conductor layer and is laminated on the second surface side of the first build-up section 10. The minimum wiring width of the wiring included in the conductor layer 12 of the first build-up section 10 is smaller than the minimum wiring width of the wiring included in the conductor layer of the second build-up section 20, and the first build-up section 10 includes single-layer through-via conductors 13a, 13b which penetrate only one insulating layer, and skip via conductors 131, 132 which continuously penetrate two or more adjacent insulating layers.

Description

Technical Field

[0001] The present invention relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses a wiring board including a first build-up portion including a plurality of insulating layers and conductor layers, and a second build-up portion laminated on the first build-up portion. The width and pitch of the wiring of the conductor layers included in the first build-up portion are smaller than the width and pitch of the wiring of the conductor layers included in the second build-up portion, respectively. The conductor layers above and below each insulating layer included in the first build-up portion are connected by via conductors penetrating each insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the wiring board disclosed in Patent Document 1, in the first build-up portion, conductor layers designed with a fine wiring rule, with two or more insulating layers sandwiched between them, are connected by two or more laminated via conductors (stacked via conductors) penetrating each insulating layer. In the first build-up portion of Patent Document 1, positional deviation of each via conductor constituting the stacked via conductor may occur with respect to a small via pad designed with a fine wiring rule. For example, it is presumed that open defects such as missing contacts and an increase in contact resistance may occur.

Means for Solving the Problems

[0005] The wiring board of the present invention has a first surface and a second surface opposite to the first surface, and includes a first build-up section containing a plurality of laminated insulating layers and a plurality of conductor layers, and a second build-up section containing laminated insulating layers and conductor layers, which is laminated on the second surface side of the first build-up section. The minimum wiring width of the wiring included in the conductor layer of the first build-up section is smaller than the minimum wiring width of the wiring included in the conductor layer of the second build-up section, and the first build-up section includes a single-layer through-via conductor that penetrates only one insulating layer, and a skip via conductor that continuously penetrates two or more adjacent insulating layers.

[0006] According to embodiments of the present invention, adjacent conductor layers containing fine wiring are connected by short paths, and conductor layers sandwiching two or more insulating layers are appropriately connected. Furthermore, it is believed that a wiring board that can be produced more efficiently is provided compared to the case where through holes for via conductors are formed in each insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2] Enlarged view of part II in Figure 1. [Figure 3] A cross-sectional view of the first build-up portion in another example of the wiring board of the embodiment. [Figure 4A] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4B] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4C] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4D] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4E] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4F] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4G]A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4H] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4I] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4J] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4K] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Figure 4L] A cross-sectional view showing an example of a wiring board in one embodiment of the manufacturing process. [Modes for carrying out the invention]

[0008] <Structure of the wiring board in the embodiment> The wiring boards of the embodiments will be described with reference to the drawings. Figure 1 shows a cross-sectional view of wiring board 1, which is an example of a wiring board of the embodiment. Figure 2 shows an enlarged view of part II of Figure 1. Note that the wiring boards illustrated in each drawing referenced in the following description are merely examples of wiring boards of the embodiments. The laminated structure of the wiring boards of the embodiments is not limited to the laminated structure of the wiring boards shown in each drawing, and the number of conductive layers and insulating layers included in the wiring boards of the embodiments is not limited to the number of conductive layers and insulating layers included in the wiring boards shown in each drawing. In addition to the insulating layers and conductive layers that the wiring boards shown in each drawing have, the wiring boards of the embodiments may include any number of insulating layers and conductive layers, and may not include all of the insulating layers and conductive layers that the wiring boards shown in each drawing have. Furthermore, in each drawing referenced in the following description, certain parts may be enlarged to make the disclosed embodiments easier to understand. Therefore, the components of the wiring boards of the embodiments may not be depicted in the exact proportions between them in terms of size and length.

[0009] As shown in Figure 1, the wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) perpendicular to the thickness direction of the wiring board 1. The wiring board 1 includes a first build-up section 10 and a second build-up section 20. The wiring board 1 in Figure 1 further includes a third build-up section 30. The second build-up section 20 is laminated on the second surface 1B side of the first build-up section 10. The third build-up section 30 is laminated on the second surface 1B side of the second build-up section 20. The lamination direction of the first build-up section 10, the second build-up section 20, and the third build-up section 30 is the thickness direction of the wiring board 1. The first build-up section 10 and the second build-up section 20 completely overlap each other, and the second build-up section 20 and the third build-up section 30 completely overlap each other. The wiring board 1 in Figure 1 further includes a solder resist 40 covering the surface of the third build-up section 30. The wiring board of this embodiment may be a coreless wiring board that does not include a core layer, as shown in wiring board 1 of Figure 1.

[0010] In the description of the wiring board 1, the first surface 1F side of the wiring board 1 is also referred to as the "top" or "upper side," and the second surface 1B side of the wiring board 1 is also referred to as the "bottom" or "lower side." Furthermore, in each component, the surface facing the first surface 1F side of the wiring board 1 is also referred to as the "top surface," and the surface facing the second surface 1B side of the wiring board 1 is also referred to as the "bottom surface."

[0011] The first surface 1F of the wiring board 1 includes a component area Ea1 on which mounted components (not shown) are mounted when the wiring board 1 is in use. The first surface 1F of the wiring board 1 may be a component mounting surface that is at least partially covered by mounted components when the wiring board 1 is in use. The components mounted on the wiring board 1 are not particularly limited, but may be, for example, semiconductor integrated circuit devices or electronic components such as transistors.

[0012] The first build-up portion 10 has a first surface 10F that is a common surface with the first surface 1F of the wiring board 1, and a second surface 10B that is a surface opposite to the first surface 1F. As shown in FIG. 1, the first build-up portion 10 includes a plurality of stacked conductor layers 12 and a plurality of insulating layers 11. Each conductor layer of the plurality of conductor layers 12 and each insulating layer of the plurality of insulating layers 11 are alternately stacked.

[0013] Each conductor layer of the plurality of conductor layers 12 includes an arbitrary conductor pattern. The conductor layer located on the side closest to the first surface 1F among the plurality of conductor layers 12 includes a component mounting pad 12p formed of a conductor pad, and is embedded in the insulating layer located on the side closest to the first surface 1F among the plurality of insulating layers 11, with its upper surface exposed on the first surface 1F. Therefore, the upper surface of the component mounting pad 12p is also exposed on the first surface 1F. The exposed surface of the component mounting pad 12p may be connected to an electrode (not shown) of a component mounted on the wiring board.

[0014] A part of the plurality of conductor layers 12 included in the first build-up portion 10 includes a plurality of wirings 12L as shown in FIG. 1. Each wiring 12L has a wiring width W1. The plurality of wirings 12L are arranged with a wiring interval G1 between each wiring.

[0015] The first build-up portion 10 further includes a plurality of via conductors 13 penetrating each insulating layer 11. Each via conductor 13 is formed in an opening 11a or an opening 11b penetrating each insulating layer 11. Each via conductor 13 connects the conductor layer 12 or the conductor layer 221 below each insulating layer 11 including each via conductor 13 to the upper conductor layer 12. Each via conductor 13 is integrally formed with the conductor layer 12 or the conductor layer 221 that it contacts at its lower end. The second surface 10B of the first build-up portion 10 is constituted by the end face on the side of the second build-up portion 20 of the via conductor 13 contacting the conductor layer 221 and the lower surface of the insulating layer contacting the conductor layer 221 among the plurality of insulating layers 11.

[0016] The second build-up section 20 has a first surface 20F, which is the surface on the first surface 1F side of the wiring board 1, and a second surface 20B, which is the surface opposite to the first surface 20F. The first surface 20F of the second build-up section 20 faces the second surface 10B of the first build-up section 10. The second build-up section 20 includes alternately stacked insulating layers 21 and conductor layers 22, as well as via conductors 23 that penetrate each insulating layer 21. The second build-up section 20 further includes a conductor layer 221 (first conductor layer) that is located furthest towards the first build-up section 10 among the conductor layers constituting the second build-up section 20. Each via conductor 23 connects the lower conductor layer 22 of the insulating layer 21 that each via conductor 23 penetrates to the upper conductor layer 22 or conductor layer 221.

[0017] Each conductor layer 22 and conductor layer 221 contains an arbitrary conductor pattern. For example, in Figure 1, the conductor layer 22 one level below conductor layer 221 contains multiple wires 22L as a conductor pattern. Each wire 22L has a wire width W2. The multiple wires 22L are arranged with a wire spacing G2 between them.

[0018] In the wiring board of this embodiment, the minimum wiring width W1 of each wiring 12L included in the conductor layer 12 of the first build-up section 10 is smaller than the minimum wiring width W2 of each wiring 22L included in any of the conductor layers constituting the second build-up section 20. That is, the conductor patterns such as the wiring 12L of each conductor layer 12 of the first build-up section 10 are designed with finer design rules than the conductor patterns such as the wiring 22L of each conductor layer 22 and conductor layer 221 of the second build-up section 20. Therefore, the minimum wiring spacing G1 of the spacing between each wiring 12L included in the conductor layer 12 of the first build-up section 10 may be smaller than the minimum wiring spacing G2 of the spacing between each wiring 22L included in any of the conductor layers constituting the second build-up section 20.

[0019] The minimum wiring width and minimum wiring spacing of the wiring 12L included in the conductor layer 12 of the first build-up section 10 are preferably 1 μm or more and 3 μm or less, respectively. Multiple wirings 12L can be arranged at a fine pitch, and as a result, a small wiring board 1 may be realized. The aspect ratio of the wiring 12L included in the conductor layer 12 of the first build-up section 10 is preferably 2.0 or more and 4.0 or less. High-frequency signals may be transmitted with small insertion loss. The aspect ratio of the wiring 12L is the ratio of the thickness of the wiring 12L to the wiring width W1 on the surface of the wiring board 1 on the first surface 1F side.

[0020] On the other hand, the minimum wiring width of the wiring 22L, etc., included in the conductor layers such as the conductor layer 22 and conductor layer 221 that constitute the second build-up section 20 may be approximately 4 μm, and the minimum wiring spacing may be approximately 6 μm, for example. The formation of the conductor layers of the second build-up section 20 may be relatively easy.

[0021] Furthermore, the thickness of each conductor layer constituting the second build-up section 20 is preferably greater than the thickness of each conductor layer 12 of the first build-up section 10. For example, the thickness of conductor layer 221 may be greater than the thickness of all the conductor layers 12 constituting the first build-up section 10. In other words, the thickness of each conductor layer 12 constituting the first build-up section 10 is preferably smaller than the thickness of each conductor layer constituting the second build-up section 20. Conductor layers 12 having a relatively small thickness can easily form wiring 12L arranged at a fine pitch.

[0022] For example, the thickness of a conductor layer included in the first build-up section 10, such as conductor layer 12, may be 4 μm or more and 7 μm or less. This makes it less likely for etching residue to occur during manufacturing, and is therefore advantageous for arranging wiring 12L and the like at fine intervals. The thickness of an insulating layer 11 included in the first build-up section 10 may be, for example, about 7.5 to 10 μm. On the other hand, the thickness of a conductor layer included in the second build-up section 20, such as conductor layers 22 and 221, may be 10 μm or more and less than 20 μm. Also, the thickness of an insulating layer included in the second build-up section 20, such as insulating layer 21, may be 20 μm or more and less than 100 μm.

[0023] Thus, in this embodiment, the first build-up section 10 may be a laminate of a conductor layer having a different thickness than the conductor layer of the second build-up section 20 and an insulating layer. Alternatively, in this embodiment, the first build-up section 10 may be a laminate of an insulating layer having a different thickness than the insulating layer of the second build-up section 20 and a conductor layer.

[0024] In the wiring board of this embodiment, conductor patterns requiring arrangement at fine widths and spacing can be concentrated in the first build-up section 10, while conductor patterns that do not require arrangement at fine widths or spacing can be concentrated in the second build-up section 20. By doing so, a process suitable for forming fine conductor patterns can be applied to the first build-up section 10, and a process that is more advantageous than forming fine conductor patterns, for example in terms of cost and ease, can be applied to the second build-up section 20. Furthermore, it may be possible to mount components (not shown) having electrodes arranged at a fine pitch on the first surface 1F, which may be a component mounting surface.Therefore, it is presumed that the wiring board of this embodiment can be easily manufactured and offered to the market at low cost, even while including fine wiring.

[0025] In the wiring board 1, the second build-up section 20 is formed on the second surface 10B of the first build-up section 10 by a build-up method. That is, in the wiring board 1 of Figure 1, the first build-up section 10 and the second build-up section 20 are not joined together via, for example, prepreg after being formed separately. Therefore, the conductor layer constituting the first build-up section 10 and the conductor layer constituting the second build-up section 20 are not connected by so-called through-hole conductors that penetrate the entire first build-up section 10 and the second build-up section 20.

[0026] In other words, as shown in Figure 1, the conductor layer 12 constituting the first build-up section 10 and the conductor layer 221 constituting the second build-up section 20 are connected by a so-called non-through via conductor, also known as a buried via or interstitial via. Specifically, the conductor layer 12 and the conductor layer 221 are connected by a via conductor 13 that does not penetrate the entire first build-up section 10 and the second build-up section 20. Since the conductor layers of the first build-up section 10 and the conductor layers of the second build-up section 20 are connected by a non-through via conductor, it is not necessarily required to secure an area for arranging through-hole conductors in all the conductor layers constituting each build-up section. Therefore, it is thought that the miniaturization of the wiring board 1 will be promoted.

[0027] The third build-up section 30 includes a laminated insulating layer 31 and a conductor layer 32, and further includes a via conductor 33. The conductor layer 32 includes an arbitrary conductor pattern, such as a conductor pad 32p. The via conductor 33 connects the conductor layer 32 to the conductor layer 22 included in the second build-up section 20.

[0028] Furthermore, the minimum wiring width of each wiring 22L included in any of the conductor layers constituting the second build-up section 20 is preferably smaller than the minimum wiring width of the conductor pattern included in the conductor layer 32 of the third build-up section 30. Also, the minimum wiring spacing between each wiring 22L included in any of the conductor layers constituting the second build-up section 20 is preferably smaller than the minimum wiring spacing of the conductor pattern included in the conductor layer 32 of the third build-up section 30.

[0029] The solder resist 40 is formed on the surface of the wiring board 1 on the second surface 1B side, in both the insulating layer 31 and the conductive layer 32. The solder resist 40 has openings that expose the conductive pads 32p. The solder resist 40 is formed using, for example, a photosensitive polyimide resin or epoxy resin.

[0030] In the example shown in Figure 1, the second surface 1B of the wiring board 1 consists of the surface of the solder resist 40 on the second surface side 1B of the wiring board 1 and the exposed surface of the conductor layer 32 exposed from the solder resist 40. However, the wiring board of the embodiment does not necessarily include the third build-up portion 30 and / or the solder resist 40. In the embodiment that does not include the third build-up portion 30, the second surface of the wiring board consists of the second surface 20B of the second build-up portion 20, or the solder resist formed on the second surface 20B of the second build-up portion 20 and the exposed portion of the second surface 20B from the solder resist.

[0031] The second surface 1B of the wiring board 1 may be a connection surface that connects to an external element (not shown) when the wiring board 1 itself is mounted on an external wiring board (for example, the motherboard of any electrical device). In the example of Figure 1, the conductor pad 32p of the third build-up section 30 may be connected to any board, electrical component, or mechanical component.

[0032] The insulating layers 11, 21, and 31 can be formed using thermosetting insulating resins such as epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. The insulating layers 11, 21, and 31 may also be formed using thermoplastic insulating resins such as fluororesin, liquid crystal polymer (LCP), fluoroethylene fluoride resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI). The insulating layers 11, 21, and 31 may contain the same insulating resin or different insulating resins. The insulating layers 11, 21, and 31 may contain a core material (reinforcement) made of glass fibers or the like. In the example in Figure 1, the insulating layer 31 contains a core material 31a. The insulating layers 11, 21, and 31 may further contain inorganic particles (not shown) made of, for example, silica (SiO2), alumina, or mullite.

[0033] The conductor layers 12, 22, 221, 32, and via conductors 13, 23, 33 are formed using metals with suitable conductivity, such as copper, copper alloys, nickel, and titanium. Although each of these conductor layers and via conductors is depicted as a single layer in Figure 1, they may each have a multilayer structure, as shown in conductor layer 12 and via conductor 13 in Figure 2. That is, each conductor layer and via conductor shown in Figure 1 may include a first metal film layer 1α and a second metal film layer 1β shown in Figure 2. The second metal film layer 1β is formed on the lower surface of the first metal film layer 1α. The first metal film layer 1α may be, for example, an electroless plating film or a sputtering film. On the other hand, the second metal film layer 1β may be an electroplated film formed by electroplating using the first metal film layer 1α as a power supply layer.

[0034] <Different via conductors included in the first build-up section> In the wiring board of the embodiment, the first build-up section 10, as shown in Figure 1, includes a via conductor 13 consisting of a single-layer through-via conductor that penetrates only one insulating layer 11 and a skip via conductor that continuously penetrates two or more adjacent insulating layers 11. Specifically, as shown in Figure 2, the first build-up section 10 includes via conductors 13a and 13b as single-layer through-via conductors that penetrate only one insulating layer, and via conductors 131 and 132 as skip via conductors that continuously penetrate two or more adjacent insulating layers.

[0035] via conductor 13a is a single-layer through via conductor formed integrally with the conductor layer 221 (first conductor layer), and via conductor 13b is a single-layer through via conductor formed integrally with each conductor layer 12 in the first build-up section 10. On the other hand, via conductor 131 is a skip via conductor formed integrally with the conductor layer 221, and via conductor 132 is a skip via conductor formed integrally with each conductor layer 12 in the first build-up section 10.

[0036] In other words, the multiple via conductors 13 in Figure 1 include via conductor 131, via conductor 132, via conductor 13a, and via conductor 13b. Also, as shown in Figure 2, the first build-up section 10 includes multiple conductor layers 12 as shown in Figure 1, namely conductor layer 121, conductor layer 122, conductor layer 123, conductor layer 124 (second conductor layer), and conductor layer 125 (third conductor layer). Conductor layer 125 is formed on the second build-up section 20 side of conductor layer 124. The first build-up section 10 also includes multiple insulating layers 11 as shown in Figure 1, namely insulating layers 111 to 115. Insulating layers 111 to 115 are interlayer insulating layers formed between any one of the conductor layers 121 to 125 and other conductor layers. For example, insulating layer 114 is formed between conductor layer 124 and conductor layer 125.

[0037] The via conductor 13a, which is a single-layer through-via conductor, penetrates only one insulating layer 115 and connects the conductor layers that sandwich the insulating layer 115. That is, in Figure 2, the via conductor 13a connects conductor layer 221 and conductor layer 125. Among the other single-layer through-via conductors (via conductors 13b), the via conductor 13b that penetrates insulating layer 111 connects conductor layer 121 and conductor layer 122, the via conductor 13b that penetrates insulating layer 113 connects conductor layer 123 and conductor layer 124, and the via conductor 13b that penetrates insulating layer 114 connects conductor layer 124 and conductor layer 125.

[0038] On the other hand, the via conductor 131, which is a skip via conductor, continuously penetrates two adjacent insulating layers (insulating layer 114 and insulating layer 115), connecting the conductor layers that sandwich insulating layer 114 and insulating layer 115. In Figure 2, the via conductor 131 connects conductor layer 221 and conductor layer 124. The via conductor 131 penetrates insulating layer 114 and insulating layer 115 in one go. Therefore, the side surface of the via conductor 131 within insulating layer 114 and the side surface of the via conductor 131 within insulating layer 115 are continuously connected. In addition, the via conductor 131 penetrates insulating layer 114 and insulating layer 115 without touching conductor layer 125 between conductor layer 221 and conductor layer 124, connecting conductor layer 221 and conductor layer 124.

[0039] Furthermore, via conductor 132, another skip via conductor in Figure 2, continuously penetrates insulating layer 111 and insulating layer 112, connecting the conductor layers that sandwich insulating layer 111 and insulating layer 112. Specifically, via conductor 132 connects conductor layer 121 and conductor layer 123. Via conductor 132 penetrates insulating layer 111 and insulating layer 112 in one step without touching conductor layer 122 between conductor layer 121 and conductor layer 123, connecting conductor layer 121 and conductor layer 123.

[0040] In this embodiment, the wiring board includes a first build-up section containing wiring arranged according to fine design rules, which includes both a single-layer through-via conductor that penetrates only one insulating layer 11, and a skip via conductor that continuously penetrates two or more insulating layers 11. Therefore, two adjacent conductor layers, at least one of which contains fine wiring, can be connected by a short path of a single-layer through-via conductor. Furthermore, two conductor layers, separated by two or more insulating layers and at least one of which contains fine wiring, can be connected by a single skip via conductor.

[0041] In other words, two conductor patterns contained within a conductor layer sandwiched between two or more insulating layers, and which do not need to be connected to the conductor layers between each of those insulating layers, can be connected with a single via conductor instead of multiple stacked via conductors. Therefore, the occurrence of open-circuit failures and increases in contact resistance due to misalignment of individual via conductors within the stacked via conductor relative to the two conductor patterns being connected can be reduced. As a result, it is believed that the conductor layers sandwiching two or more insulating layers are connected with better quality than in conventional methods. At the same time, two adjacent conductor layers can be connected with low impedance using a single-layer through-via conductor.

[0042] In particular, in the wiring board of the embodiment, the conductor layer within the first build-up section includes a conductor pattern arranged according to fine design rules, as shown in the conductor layer 12 of the wiring board 1 in Figure 1. Therefore, the structure of the embodiment in which conductor layers sandwiching two or more insulating layers are connected by a single skip via conductor with minimal misalignment relative to the conductor pattern, such as a via pad, within each conductor layer is particularly advantageous.

[0043] Furthermore, in the first build-up section 10 of Figure 2, the via conductor 13a of the single-layer through-via conductor and the via conductor 131 of the skip via conductor are integrally formed with the same conductor layer. Specifically, both the via conductor 13a and the via conductor 131 are integrally formed with the conductor layer 221. The conductor layer 221 is one of the conductor layers that constitute the second build-up section 20. The conductor layer 221 is formed on the surface of the insulating layer 115 on the second build-up section 20 side. The insulating layer 115 is the insulating layer that is located furthest towards the second build-up section 20 among the insulating layers 11 that constitute the first build-up section 10.

[0044] When skip via conductors and single-layer through via conductors are formed that connect to the same conductor layer, such as via conductors 13a and 131 in the example of Figure 2, it is efficient to form them integrally with the conductor layer by electroplating. If the conductor layer formed integrally with both the single-layer through via conductor and the skip via conductor is the conductor layer of the second build-up section 20, as shown by conductor layer 221 in the example of Figure 2, then thickness variations that may occur in that conductor layer are less likely to be a problem.

[0045] In other words, because single-layer through-via conductors and skip via conductors have different volumes, the time required to form single-layer through-via conductors by electroplating is different from the time required to form skip via conductors by electroplating. Therefore, in the conductor layer formed integrally with single-layer through-via conductors and skip via conductors, there is a difference in thickness between the vicinity of the single-layer through-via conductors and the vicinity of the skip via conductors, making it easy for overall thickness inconsistencies and unevenness to occur.

[0046] In this regard, as mentioned above, in the wiring board 1, it is preferable that the thickness of each insulating layer 11 constituting the first build-up section 10 is smaller than the thickness of each insulating layer constituting the second build-up section 20. That is, by forming the single-layer through-via conductors 13a and 13b and the skip via conductors 131 and 132 in the relatively thin insulating layer 11 included in the first build-up section, the volume difference between the single-layer through-via conductor 13a or the single-layer through-via conductor 13b and the skip via conductor 131 or the skip via conductor 132 can be made relatively small. Therefore, the non-uniformity and unevenness of the thickness in the conductor layer formed integrally with the single-layer through-via conductor and the skip via conductor can be reduced.

[0047] Furthermore, in the example shown in Figure 2, the conductor layer in which both the via conductor 13a (single-layer through-via conductor) and the via conductor 131 (skip via conductor) are integrally formed is the conductor layer 221 that constitutes the second build-up section 20. As mentioned above, the thickness of the conductor layer 221 that constitutes the second build-up section 20 may be greater than the thickness of each of the conductor layers 12 that constitute the first build-up section 10. Therefore, even if there is some unevenness in the thickness of the conductor layer 221, the ratio of the magnitude of that unevenness (the difference between the thickness of the thickest part and the thickness of the thinnest part) to the design thickness of the conductor layer 221 is smaller than the same ratio when similar unevenness occurs in the conductor layers within the first build-up section 10. In other words, compared to the conductor layers that constitute the first build-up section 10, the effect of unevenness caused by integral formation with the single-layer through-via conductor and the skip via conductor is mitigated in the conductor layer 221. Therefore, the influence on the formation of insulating and conductive layers laminated on top of the conductive layer 221 after its formation is relatively small, and thus, for example, the quality of the wiring board 1 with respect to the second build-up section 20 is considered to be stable.

[0048] <Positional relationship between single-layer through-via conductor and skip-through via conductor> In the first build-up section 10 of Figure 2, one insulating layer pierced by a single-layer through-via conductor is one of two or more adjacent insulating layers pierced by a skip via conductor. For example, via conductor 13a pierces insulating layer 115, which is one of insulating layers 114 and 115 pierced by via conductor 131. Also, insulating layer 111 pierced by one of the via conductors 13b is one of insulating layers 111 and 112 pierced by via conductor 132. In other words, in the wiring board of the embodiment, the first build-up section 10 may include single-layer through-via conductors that pierce only one of the insulating layers pierced by a skip via conductor. In other words, the first build-up section 10 may contain a mixture of single-layer through-via conductors and skip via conductors that pierce the same insulating layer.

[0049] Furthermore, in the first build-up section 10 of Figure 2, two conductor layers sandwiching two or more adjacent insulating layers through which a skip via conductor penetrates are connected by the skip via conductor and also by a plurality of stacked single-layer through-via conductors. That is, the conductor layer 221 and conductor layer 124 sandwiching two insulating layers (insulating layer 114 and insulating layer 115) through which the via conductor 131, which is a skip via conductor, penetrates are connected by the via conductor 131 and also by stacked via conductors consisting of via conductors 13a and 13b, both of which are single-layer through-via conductors. In other words, in the wiring board of this embodiment, the first build-up section may include a plurality of single-layer through-via conductors, each penetrating only one of the insulating layers of the two or more insulating layers penetrated by the skip via conductor. And these plurality of single-layer through-via conductors may be stacked. It is believed that including single-layer through-via conductors and skip via conductors in this way increases the degree of freedom in the wiring layout design of the wiring board.

[0050] <Shape of each via conductor> As shown in Figure 2, in the wiring board 1, the skip via conductors and single-layer through via conductors have a tapered shape that narrows in width on the first surface 1F side of the wiring board 1. That is, in the example in Figure 2, via conductors 13a, 13b, 131, and 132 all have a tapered shape that narrows in width on the first surface 1F side. The "width" of each via conductor is the longest distance between any two points on the outer circumference of the cross section or end face perpendicular to the Z direction of each via conductor.

[0051] In the first build-up section 10 shown in Figure 2, the widths of the end faces on the second build-up section 20 side of each via conductor 13a, via conductor 13b, via conductor 131, and via conductor 132 are approximately the same. For example, the width Ws2 of the end face on the second build-up section 20 side of via conductor 131, which is a skip via conductor, is approximately the same as the width Wm2 of the end face on the second build-up section 20 side of via conductor 13a, which is a single-layer through via conductor. The width Ws2 of the end face of via conductor 131 is also approximately the same as the width of the end face on the second build-up section 20 side of each via conductor 13b.

[0052] Thus, in the wiring board of this embodiment, the width of the end face on the second build-up portion side of the single-layer through-via conductor and the width of the end face on the second build-up portion side of the skip via conductor may be approximately the same. Note that "approximately the same" widths means that the difference between the two widths being compared is 5% or less of the width of either of the two widths.

[0053] Furthermore, in the example in Figure 2, the taper angles θs of via conductors 131 and 132 and the taper angles θm of via conductors 13a and 13b are approximately the same. That is, in the wiring board of the embodiment, the taper angles of the skip via conductors and the taper angles of the single-layer through-via conductors may be approximately the same. Note that the "taper angle" of each via conductor is the angle between the side wall of each via conductor and its central axis in a cross-section passing through the central axis of each via conductor. Also, "approximately the same" for two taper angles means that the difference between the two taper angles being compared is 5% or less of the angle of either one of the two taper angles.

[0054] When the width of the end face on the second side of the wiring board for a single-layer through-via conductor is approximately the same as the width of the end face on the second side of the skip via conductor, and the taper angle of the skip via conductor is approximately the same as the taper angle of the single-layer through-via conductor, it is sometimes possible to efficiently form each via conductor. In other words, when the openings for forming each via conductor are formed by irradiating each insulating layer with laser light, it is possible to form the openings for the skip via conductor and the openings for the single-layer through-via conductor without changing the spot diameter of the laser light.

[0055] The width of the end face on the second build-up side of the skip via conductor and the width of the end face on the second build-up side of the single-layer through via conductor are, for example, 10 μm or more and 20 μm or less. The taper angle of the skip via conductor and the taper angle of the single-layer through via conductor are, for example, 0° or more and 20° or less, respectively.

[0056] Note that the width of the end face on the first side of the wiring board in the case of a skip via conductor and the width of the end face on the first side of the wiring board in the case of a single-layer through via conductor may be different, as shown in Figure 2 where the width Ws1 of via conductor 132 and the width Wm1 of via conductor 13b are different.

[0057] <Other examples of wiring boards in the embodiment> Figure 3 shows the first build-up section 10 in another example of the wiring board of the embodiment. The first build-up section 10 in the example shown in Figure 3 includes, in addition to the same via conductor 132 as in Figure 2, a via conductor 133 that continuously penetrates three adjacent insulating layers as a skip via conductor that continuously penetrates two or more adjacent insulating layers. The via conductor 133 penetrates insulating layers 115, 114, and 113 together. The via conductor 133 connects conductor layer 221 and conductor layer 123 without touching conductor layer 125 located between insulating layer 115 and insulating layer 114, and conductor layer 124 located between insulating layer 114 and insulating layer 113. The conductor patterns of conductor layer 221 and conductor layer 123, which do not need to be connected to conductor layers 125 and 124, are connected by a single via conductor at approximately the shortest distance, so that no misalignment occurs between the multiple via conductors.

[0058] As shown in the example in Figure 3, in the wiring board of the embodiment, the first build-up portion may include a skip via conductor that continuously penetrates three adjacent insulating layers. The number of insulating layers continuously penetrated by the skip via conductor included in the first build-up portion may be any number of two or more. Furthermore, in the wiring board of the embodiment, the first build-up portion may include a plurality of skip via conductors that continuously penetrate a different number of insulating layers.

[0059] <An example of a method for manufacturing a wiring board according to an embodiment> Next, with reference to Figures 4A to 4L, an example of a method for manufacturing the wiring board of this embodiment will be described, using the case where the wiring board 1 illustrated in Figures 1 and 2 is manufactured as an example. Unless otherwise stated, any of the materials previously described for each component of the wiring board 1 can be used to form each component.

[0060] As shown in Figure 4A, a support substrate SP is prepared, which includes a core layer GS and metal film layers ML1 and ML2 laminated on both sides of the core layer GS, respectively. The core layer GS is composed of, for example, glass material or glass epoxy material. The metal film layers ML1 and ML2 are metal layers formed by electroless plating or sputtering, for example, using copper or titanium as the material. The metal film layer ML1 and the metal film layer ML2 are joined by an adhesive layer AL, which is composed of, for example, an adhesive whose adhesive properties change upon light irradiation.

[0061] In the following explanation, the side of the support substrate SP closer to the core layer GS will also be referred to as "bottom" or "lower side," and the side further from the core layer GS will also be referred to as "top" or "upper side." Therefore, the side of each component of the manufactured wiring board that faces the support substrate SP will also be referred to as the "bottom surface," and the side that faces away from the support substrate SP will also be referred to as the "top surface."

[0062] A conductive layer 121 containing multiple component mounting pads 12p is formed on a support substrate SP. In the formation of the conductive layer 121, for example, a resist film (not shown) is formed on a metal film layer ML2. A plating resist is formed by creating openings in the resist film corresponding to the formation areas of the component mounting pads 12p using photolithography technology. A plating film is formed within the openings in the plating resist by electroplating using the metal film layer ML2 as a power supply layer. After that, the plating resist is removed. A conductive layer 121 as shown in Figure 4A is obtained.

[0063] As shown in Figure 4B, an insulating layer 111 is formed to cover the conductive layer 121, and an opening 11a is formed that penetrates the insulating layer 111. Note that in Figure 4B, and in Figures 4C to 4L which are referenced below, only one surface side of the support substrate SP is shown for each step, and the state of the other surface side is omitted. However, the insulating layer and conductive layer may be formed on the surface of the support substrate SP on the side that is omitted from the illustration, in the same way as on the illustrated side, or such conductive layer and insulating layer may not be formed.

[0064] The insulating layer 111 is formed from, for example, a thermosetting resin such as epoxy resin, BT resin, or phenolic resin, or a thermoplastic resin such as fluororesin or LCP. The insulating layer 111 is formed by heat-compressing these resins, which have been molded into a film. The opening 11a is formed by irradiating the formation position of the via conductor 13b (see Figure 4C) with laser light, such as UV laser light or carbon dioxide laser light having a wavelength in the ultraviolet region. The formation of the opening 11a may be carried out while protecting the upper surface of the insulating layer 111 with a protective film (not shown) made of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Preferably, after the formation of the opening 11a, resin residue (smear) that tends to form inside the opening 11a is removed by dry desmearing with plasma gas or wet desmearing with a permanganate solution.

[0065] In addition, during the process of forming the opening 11a in the insulating layer 111, no opening is formed at the location where the via conductor 132 (Figure 4F) that penetrates the insulating layer 111 is formed.

[0066] After the opening 11a is formed, a metal film 1αa is formed on the inner wall of the opening 11a and the surface of the insulating layer 111 by any method such as sputtering or electroless plating.

[0067] After the formation of the metal film 1αa, a plating resist PR is formed on the metal film 1αa, for example, by lamination of a dry film. Multiple apertures PR1 corresponding to the formation area of ​​the conductive pattern to be included in the conductive layer 122 (see Figure 4C) are formed in the plating resist PR by exposure using an appropriate exposure mask and development. The minimum width of the multiple apertures PR1 formed may be 1 μm or more and 3 μm or less, and the minimum spacing between the formed apertures PR1 may be 1 μm or more and 3 μm or less.

[0068] After the opening PR1 is formed, a plating film is formed inside the opening PR1 by electroplating using the metal film 1αa as a power supply layer. Subsequently, the plating resist PR is removed, and then the exposed portion of the metal film 1αa is removed by etching or other means.

[0069] As a result, a conductor layer 122 containing a desired conductor pattern, such as multiple wirings 12L, is formed, as shown in Figure 4C. A via conductor 13b, which is a single-layer through-via conductor that penetrates only the insulating layer 111, is formed within the opening 11a. The conductor layer 122 and the via conductor 13b are composed of a first metal film layer 1α, which is the remaining portion of the metal film 1αa (see Figure 4B), and a second metal film layer 1β, which is a plating film formed by electroplating. The minimum wiring width of the multiple wirings 12L may be 1 μm or more and 3 μm or less, and the minimum wiring spacing may be 1 μm or more and 3 μm or less. The conductor layer 122 is formed so as not to have a conductor pattern at the formation position of the via conductor 132 (see Figure 4F).

[0070] As shown in Figure 4D, the insulating layer 112 covering the conductive layer 122 is formed, for example, by thermocompression bonding of a resin film, similar to the method used to form the insulating layer 111.

[0071] As shown in Figure 4E, an opening 11b is formed that continuously penetrates the insulating layer 112 and the insulating layer 111. In addition, an opening 11a is formed that penetrates only the insulating layer 112. The opening 11b is formed at the location where the via conductor 132 (see Figure 4F) is formed, and the opening 11a that penetrates only the insulating layer 112 is formed at the location where the via conductor 13b (see Figure 4F) that penetrates only the insulating layer 112 is formed. The openings 11b and 11a are formed by irradiation with laser light, such as UV laser light or carbon dioxide laser light. Laser irradiation may be performed while protecting the upper surface of the insulating layer 112 with a protective film (not shown) made of PET or PEN. After the formation of the openings 11b and 11a, desmearing treatment such as dry desmearing or wet desmearing may be performed.

[0072] In addition, during the process of forming openings 11b and 11a in the insulating layer 112, no openings are formed at the locations where via conductors 132 (see Figure 4H) that penetrate the insulating layer 112 and the insulating layer 113 are formed.

[0073] As shown in Figure 4F, a conductor layer 123 is formed on top of the insulating layer 112. A via conductor 132, which is a skip via conductor that continuously penetrates the insulating layer 112 and the insulating layer 111, is formed in the opening 11b. A via conductor 13b, which is a single-layer through via conductor, is formed in the opening 11a that penetrates only the insulating layer 112. The conductor layer 123, the via conductor 132, and the via conductor 13b are formed by a semi-additive method, similar to, for example, the conductor layer 121 and the via conductor 13b that penetrates only the insulating layer 111. That is, a series of steps are performed, such as forming a metal film on the surface of the insulating layer 112, forming a plating resist, forming a plating film, removing the plating resist, and removing the exposed portion of the metal film.

[0074] The conductor layer 123 may include a plurality of wirings 12L having a wiring width of 1 μm or more and a wiring spacing of 3 μm or less. The conductor layer 123 is formed such that it does not have a conductor pattern at the formation positions of via conductors 132 (see Figure 4H) that penetrate the insulating layer 112 and the insulating layer 113.

[0075] As shown in Figure 4G, the insulating layer 113 covering the conductor layer 123 is formed, for example, by thermocompression bonding of a resin film, similar to the method for forming the insulating layer 111. Then, an opening 11b is formed that continuously penetrates the insulating layer 113 and the insulating layer 112. In addition, an opening 11a is formed that penetrates only the insulating layer 113. The opening 11b that continuously penetrates the insulating layer 113 and the insulating layer 112 is formed at the position where a via conductor 132 (see Figure 4H) that continuously penetrates the insulating layer 113 and the insulating layer 112 is formed, and the opening 11a that penetrates only the insulating layer 113 is formed at the position where a via conductor 13b (see Figure 4H) that penetrates only the insulating layer 113 is formed. The opening 11b that continuously penetrates the insulating layer 113 and the insulating layer 112, and the opening 11a that penetrates only the insulating layer 113 are formed, for example, by irradiation with UV laser light, similar to the previously formed openings 11b and 11a. Subsequently, desmearing treatments such as dry desmearing or wet desmearing may be performed.

[0076] In addition, during the process of forming openings 11b and 11a in the insulating layer 113, no openings are formed at the locations where via conductors 132 (see Figure 4I) that penetrate the insulating layer 113 and the insulating layer 114 are formed.

[0077] As shown in Figure 4H, a conductor layer 124 is formed on top of the insulating layer 113. Within the opening 11b that continuously penetrates the insulating layer 113 and the insulating layer 112, a via conductor 132, which is a skip via conductor that continuously penetrates the insulating layer 113 and the insulating layer 112, is formed. Within the opening 11a that penetrates only the insulating layer 113, a via conductor 13b, which is a single-layer through-via conductor, is formed. The conductor layer 124, the via conductor 132, and the via conductor 13b are formed, for example, by a semi-additive method, similar to the previously formed conductor layer and via conductor. The conductor layer 124 may include a plurality of wirings 12L having the same minimum wiring width and minimum wiring spacing as the wirings 12L included in the conductor layer 123, etc. The conductor layer 124 is formed so as not to have a conductor pattern at the formation location of the via conductor 132 (see Figure 4I) that penetrates the insulating layer 113 and the insulating layer 114.

[0078] As shown in Figure 4I, an insulating layer 114, an insulating layer 125, and an insulating layer 115 are formed sequentially on the conductor layer 124. In addition, a via conductor 132, which is a skip via conductor that continuously penetrates the insulating layers 114 and 113, and a via conductor 13b, which is a single-layer through via conductor that penetrates only the insulating layer 114, are formed. The insulating layers 114 and 115 are formed, for example, in the same way as the insulating layer 111. The conductor layer 125, as well as the via conductor 132 that continuously penetrates the insulating layers 114 and 113, and the via conductor 13b that penetrates only the insulating layer 114, are formed, for example, by a semi-additive method, similar to the conductor layers and via conductors formed earlier. The conductor layer 125 may include a plurality of wirings 12L having the same minimum wiring width and minimum wiring spacing as the wirings 12L included in the conductor layer 123, etc. The conductor layer 125 is formed such that it does not have a conductor pattern at the location where via conductors 131 (see Figure 4J) that penetrate the insulating layer 114 and the insulating layer 115 are formed.

[0079] After the insulating layer 115 is formed, an opening 11b that penetrates both the insulating layer 115 and the insulating layer 114, and an opening 11a that penetrates only the insulating layer 115, are formed, for example, by irradiation with UV laser light. The opening 11b that penetrates both the insulating layer 115 and the insulating layer 114 is formed at the location where the via conductor 131 (see Figure 4J) is formed, and the opening 11a that penetrates only the insulating layer 115 is formed at the location where the via conductor 13a (see Figure 4J) is formed.

[0080] As shown in Figure 4J, a conductor layer 221 is formed on top of an insulating layer 115. A via conductor 131, which is a skip via conductor, is formed in an opening 11b that continuously penetrates both the insulating layer 115 and the insulating layer 114. A via conductor 13a, which is a single-layer through-via conductor, is formed in an opening 11a that penetrates only the insulating layer 115. The conductor layer 221, the via conductor 131, and the via conductor 13a are formed by any method. For example, the conductor layer 221, the via conductor 131, and the via conductor 13a are formed by a semi-additive method. The conductor layer 221 is formed thicker than the conductor layers 121 to 125 that constitute the first build-up section. Therefore, as mentioned above, in a conductor layer formed integrally with both a single-layer through-via conductor and a skip via conductor, thickness variations that tend to occur due to the difference in formation time between the single-layer through-via conductor and the skip via conductor are less likely to be a problem.

[0081] As shown in Figure 4K, a second build-up section 20 is formed. That is, an insulating layer 21 and an insulating layer 22 are alternately laminated in a desired number on top of the conductive layer 221 and the insulating layer 115. In Figure 4K, three sets of insulating layers 21 and conductive layers 22 are laminated. Each insulating layer 21 has via conductors 23 that connect the upper and lower conductive layers to each other. The insulating layer 21 is formed, for example, in the same manner as the method for forming the insulating layer 111 described earlier. In forming the insulating layer 21, instead of a film-like resin, a core-filled resin molded into a sheet, such as a prepreg, may be used.

[0082] The conductor layer 22 and via conductors 23 are formed using any method, for example, by a semi-additive method. The conductor layer 22 is formed with a minimum wiring width greater than the minimum wiring width of the wiring 12L included in the first build-up section 10, and with a spacing between adjacent wirings greater than the minimum wiring spacing between wirings 12L.

[0083] A third build-up section 30 is formed on top of the second build-up section 20. First, an insulating layer 31 is formed in the same manner as the insulating layer 21. In the example of Figure 4K, the insulating layer 31 is formed using a prepreg containing a core material 31a made of, for example, glass fiber. A prepreg with copper foil may also be used. Through holes are formed in the insulating layer 31 at the locations where the via conductors 33 are to be formed by laser irradiation or drilling. Then, a conductor layer 32 is formed on the surface of the insulating layer 31, and via conductors 33 are formed in the through holes of the insulating layer 31. The conductor layer 32 and the via conductors 33 are formed by any method, for example, a suitable method such as a semi-additive method or a subtractive method.

[0084] After the formation of the third build-up section 30, a solder resist 40 is formed on the surfaces of the insulating layer 31 and the conductive layer 32 using a photosensitive epoxy resin or polyimide resin. Then, an opening defining the conductive pad 32p is formed using photolithography technology.

[0085] As shown in Figure 4L, the core layer GS of the support substrate SP is removed. The underside of the metal film layer ML2 beneath the component mounting pad 12p is exposed. During the removal of the support substrate SP, for example, the adhesive layer AL is softened by laser irradiation, and then the metal film layer ML2 is peeled off from the adhesive layer AL. The metal film layer ML2 is then removed by etching, exposing the underside of the component mounting pad 12p and the underside of the insulating layer 111. The wiring board 1 shown in Figure 1 is completed.

[0086] The wiring boards of the embodiments are not limited to those having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. As stated above, the wiring boards of the embodiments may have any laminated structure. The wiring boards of the embodiments may have any number of conductor layers and insulating layers. Each conductor layer may include any conductor pattern in addition to the wiring 12L or wiring 22L. The first surface of the wiring board of the embodiments does not have to be a component mounting surface.

[0087] Furthermore, one or both of the single-layer through-via conductor and the skip-via conductor do not have to have a tapered shape. The first build-up section does not have to include one or both of the skip-via conductor and the single-layer through-via conductor that are integrally formed with the first conductor layer located furthest towards the first build-up section among the conductor layers of the second build-up section. Alternatively, the first build-up section may include only a skip-via conductor that is integrally formed with the first conductor layer as the skip-via conductor. [Explanation of symbols]

[0088] 1 Wiring board 1st Floor, Side 1 1B 2nd side 10. First Build-up Department 11 Multiple insulating layers 111-115 Insulating layer 12 Multiple conductor layers 121-125 Conductor layer 12L wiring 13 Multiple via conductors 131-133 Via conductor (Skip via conductor) 13a, 13b Via conductors (single-layer through-via conductors) 20. Second Build-up Department 21 Insulating layer 22 Conductor layer 22L wiring 221 Conductor layer (first conductor layer) 30. Third Build-up Department G1 Wiring spacing of the first build-up section G2 Wiring spacing in the second build-up section W1 Wiring width of the first build-up section Width of the wiring in the second build-up section of W2 Ws2 width of the end face on the second build-up side of the skip via conductor Width of the end face on the second build-up side of the single-layer through-via conductor Wm2 θs Taper angle of skip via conductor θm Taper angle of single-layer through-via conductor

Claims

1. It has a first surface and a second surface opposite to the first surface, A first build-up section comprising multiple laminated insulating layers and multiple conductor layers, A second build-up portion is laminated on the second surface side of the first build-up portion and includes a laminated insulating layer and a conductor layer, A wiring board including, The minimum wiring width of the wiring included in the conductor layer of the first build-up portion is smaller than the minimum wiring width of the wiring included in the conductor layer of the second build-up portion. The first build-up portion includes a single-layer through-via conductor that penetrates only one insulating layer, and a skip-via conductor that continuously penetrates two or more adjacent insulating layers.

2. The wiring board according to claim 1, wherein the single-layer through-via conductor and the skip via conductor are integrally formed with the same conductor layer.

3. The wiring board according to claim 1, wherein the thickness of each of the plurality of insulating layers laminated in the first build-up portion is smaller than the thickness of the insulating layer laminated in the second build-up portion.

4. The wiring board according to claim 1, wherein the conductor layer constituting the first build-up portion and the conductor layer constituting the second build-up portion are connected by via conductors that do not penetrate the entire first build-up portion and the entire second build-up portion.

5. The wiring board according to claim 1, wherein the one insulating layer is one of the two or more adjacent insulating layers.

6. A wiring board according to claim 1, The second build-up portion includes a first conductor layer that is located furthest towards the first build-up portion among the conductor layers constituting the second build-up portion, The skip via conductor is formed integrally with the first conductor layer.

7. A wiring board according to claim 6, The single-layer through-via conductor is formed integrally with the first conductor layer.

8. The wiring board according to claim 6, wherein the first conductor layer is formed on the surface of the one insulating layer on the side of the second build-up portion.

9. The wiring board according to claim 6, wherein the thickness of the first conductor layer is greater than the thickness of each of the conductor layers constituting the first build-up portion.

10. The wiring board according to claim 6, wherein the first build-up portion is The second conductor layer, A third conductor layer formed on the second build-up side of the second conductor layer, An insulating layer formed between the second conductor layer and the third conductor layer, Includes, The aforementioned single-layer through-via conductor connects the first conductor layer and the third conductor layer. The skip via conductor connects the first conductor layer and the second conductor layer without touching the third conductor layer.

11. The wiring board according to claim 1, wherein the width of the end face on the second build-up portion side of the single-layer through-via conductor and the width of the end face on the second build-up portion side of the skip via conductor are substantially the same.

12. A wiring board according to claim 1, The skip via conductor and the single-layer through via conductor have a tapered shape that narrows in width on the first surface side. The taper angle of the skip via conductor and the taper angle of the single-layer through via conductor are approximately the same.

13. The wiring board according to claim 1, wherein two conductor layers sandwiching two or more adjacent insulating layers are connected by the skip via conductor and also connected by a plurality of stacked single-layer through-via conductors.

14. The wiring board according to claim 1, wherein the minimum wiring width and minimum wiring spacing of the wiring included in the conductor layer of the first build-up portion are 3 μm or less, each.

15. The wiring board according to claim 1, wherein the aspect ratio of the wiring included in the conductor layer of the first build-up portion is 2.0 or more and 4.0 or less.

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