Display system and driver circuit

Abstract

We provide a display system that can reduce noise. [Solution] The display system comprises a display device having a plurality of horizontal column signal lines, a plurality of vertical first row signal lines and a plurality of vertical second row signal lines, a plurality of first image elements and a plurality of second image elements, a plurality of first drive circuits provided for each first row signal line that supply charge to the first image element in a first period and withdraw charge from the first image element in a second period different from the first period, and a plurality of second drive circuits provided for each second row signal line that supply charge to the second image element in a third period that overlaps with the second period and withdraw charge from the second image element in a fourth period that overlaps with at least a part of the first period, and a driver circuit in which the first drive circuits and second drive circuits are alternately connected in series, wherein the first drive circuits initialize the information to be held after the operation of the second drive circuits in the next stage and subsequent stages, and the second drive circuits initialize the information to be held after the operation of the first drive circuits in the next stage and subsequent stages.

Description

Technical Field

[0001] The present invention relates to a display system, and particularly to a display system, a control method of the display system, and a driver circuit mounted on the display system.

Background Art

[0002] Conventionally, a display system having a flat display surface such as a liquid crystal display has been known. In such a display system, pixel elements are arranged at intersections of a plurality of column signal lines arranged horizontally on a plane and a plurality of row signal lines arranged vertically, and further, a driver circuit for charging and discharging the pixel elements is provided. The display system drives each row signal line in order by the driver circuit and applies the charges applied to the column signal lines to the corresponding pixel elements to display an image.

[0003] Regarding this, Patent Document 1 discloses a liquid crystal display device including a liquid crystal display panel in which pixel elements are arranged at intersections of a plurality of gate lines and a plurality of source lines arranged orthogonally to each other, and a gate driver for driving the plurality of gate lines.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, with the increasing size and resolution of display systems, the load capacity of the row signal lines has increased, leading to a trend of increasing magnetic field noise and electric field noise emitted from these lines. Furthermore, the driving frequency of the row signal lines has also increased, shortening the generation period of magnetic field and electric field noise. Such magnetic field and electric field noise can cause malfunctions and reduced accuracy in various electronic components, such as sensors, installed in the display system.

[0006] This invention has been made in view of these problems, and its objective is to provide a display system capable of reducing noise, a control method for the display system, and a driver circuit mounted on the display system. [Means for solving the problem]

[0007] To solve the above problems, the first display system according to the present invention comprises a display device having a plurality of column signal lines arranged horizontally, a plurality of first row signal lines and a plurality of second row signal lines arranged vertically, a plurality of first image elements arranged at the intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at the intersections of the second row signal lines and the column signal lines; and a driver circuit having a plurality of first drive circuits provided for each of the first row signal lines and driving the first image elements via the corresponding first row signal line, and a plurality of second drive circuits provided for each of the second row signal lines and driving the second image elements via the corresponding second row signal line, wherein the first drive circuits supply charge to the first image elements in a first period and withdraw charge from the first image elements in a second period different from the first period, and the second drive circuits supply charge to the second image elements in a third period which overlaps at least a part with the second period, or withdraw charge from the second image elements in a fourth period which overlaps at least a part with the first period.

[0008] Furthermore, the second display system according to the present invention further comprises a first clock line that supplies a first clock to the first drive circuit and a second clock line that supplies a second clock to the second drive circuit, wherein the first drive circuit either supplies charge to or extracts charge from the first image element in accordance with the alternation of the first clock, and the second drive circuit either supplies charge to or extracts charge from the second image element in accordance with the alternation of the second clock, and the first clock line and the second clock line are arranged parallel and adjacent to each other.

[0009] Furthermore, the third display system according to the present invention further comprises a first clock line that supplies a first clock to the first drive circuit and a second clock line that supplies a second clock to the second drive circuit, wherein the first drive circuit either supplies charge to or extracts charge from the first image element according to the alternation of the first clock, and the second drive circuit either supplies charge to or extracts charge from the second image element according to the alternation of the second clock, and the first clock line and the second clock line are arranged to intersect each other at regular intervals.

[0010] Furthermore, in the fourth display system according to the present invention, the first drive circuit and the second drive circuit are each connected alternately in series, the first drive circuit holds information indicated by a signal output from the second drive circuit connected to the preceding stage, and outputs a signal including the information held in the first period to the second drive circuit connected to the next stage, the second drive circuit holds information indicated by a signal output from the first drive circuit connected to the preceding stage, and outputs a signal including the information held in the third period to the first drive circuit connected to the next stage, the first drive circuit initializes the information it holds according to a signal output from the first drive circuit connected to the next-next stage or later, or a signal output from the second drive circuit connected to the next-next stage or later, and the second drive circuit initializes the information it holds according to a signal output from the first drive circuit connected to the next-next stage or later, or a signal output from the second drive circuit connected to the next-next stage or later.

[0011] Furthermore, in the fifth display system according to the present invention, the plurality of first drive circuits are connected alternately in series, and each first drive circuit holds information indicated by the signal output from the first drive circuit connected to the preceding stage, and outputs a signal including the information held in the first period to the first drive circuit connected to the next stage, and the plurality of second drive circuits are connected alternately in series, and each second drive circuit holds information indicated by the signal output from the second drive circuit connected to the preceding stage, and outputs a signal including the information held in the third period to the second drive circuit connected to the next stage.

[0012] Furthermore, the sixth display system according to the present invention further comprises a position indicator having a resonant circuit, a drive coil for supplying power to the position indicator, and a position detector having an electromagnetic induction type detection coil for detecting the position indicated by the position indicator.

[0013] Furthermore, in the seventh display system according to the present invention, the driver circuit is located between the position detector and the drive coil and on the side of the display device, the first clock line and the second clock line are located between the position detector and the drive coil and on the side of the driver circuit opposite to the display device, the position detector is located on the display surface side of the display device with respect to the display device, the driver circuit, the first clock line and the second clock line, and the drive coil is located on the back side of the display device with respect to the display device, the driver circuit, the first clock line and the second clock line.

[0014] Furthermore, in the eighth display system according to the present invention, the display device has a touch sensor in which a plurality of detection electrodes are arranged in a planar manner.

[0015] Furthermore, in the ninth display system according to the present invention, the driver circuit is located on the side of the display device and on the back of the touch sensor, the first clock line and the second clock line are located on the back of the touch sensor and on the side of the driver circuit opposite to the display device, and the touch sensor is located on the display surface side of the display device with respect to the display device, the driver circuit, the first clock line and the second clock line.

[0016] Furthermore, the tenth driver circuit according to the present invention is a driver circuit for driving the first image elements and the second image elements in a display device having a plurality of column signal lines arranged horizontally, a plurality of first row signal lines and a plurality of second row signal lines arranged vertically, a plurality of first image elements arranged at the intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at the intersections of the second row signal lines and the column signal lines, comprising: a plurality of first drive circuits provided for each of the first row signal lines and driving the first image element via the corresponding first row signal line; and a plurality of second drive circuits provided for each of the second row signal lines and driving the second image element via the corresponding second row signal line, wherein the first drive circuits supply charge to the first image element in a first period and withdraw charge from the first image element in a second period different from the first period, and the second drive circuits supply charge to the second image element in a third period which overlaps at least a part with the second period, or withdraw charge from the second image element in a fourth period which overlaps at least a part with the first period.

[0017] Furthermore, the eleventh control method for a display system according to the present invention is a control method for a display system comprising: a plurality of column signal lines arranged horizontally; a plurality of first row signal lines and a plurality of second row signal lines arranged vertically; a plurality of first image elements arranged at the intersections of the first row signal lines and the column signal lines; and a plurality of second image elements arranged at the intersections of the second row signal lines and the column signal lines, wherein the method comprises supplying charge to the first image elements via the first row signal lines during a first period; withdrawing charge from the second image elements via the second row signal lines during a third period that overlaps at least a portion with the first period; withdrawing charge from the first image elements via the first row signal lines during a second period different from the first period; and a third period that overlaps at least a portion with the second period. three This includes supplying charge to the second image element via the second row signal line during the specified period. [Effects of the Invention]

[0018] According to the present invention, the display system can reduce noise.

Brief Description of Drawings

[0019] [Figure 1] It is a diagram showing an example of a display system. [Figure 2] It is a diagram showing an example of a pixel device. [Figure 3A] It is a diagram showing an example of the circuit configuration of a clock line and a gate driver circuit. [Figure 3B] It is a diagram showing an example of the circuit configuration of the first shift register. [Figure 3C] It is a diagram showing an example of the circuit configuration of a block. [Figure 4] It is a diagram showing an example of the circuit configuration of a drive circuit. [Figure 5A] It is a diagram showing a second example of the arrangement of clock lines. [Figure 5B] It is a diagram showing a third example of the arrangement of clock lines. [Figure 5C] It is a diagram showing a fourth example of the arrangement of clock lines. [Figure 6] It is a timing chart showing a first example of the potential transition of each clock in a display system. [Figure 7] It is a timing chart showing an example of the potential transition of each signal in a drive circuit. [[ID=,39]] [Figure 8] It is a timing chart showing a second example of the potential transition of each clock in a display system. [Figure 9A] It is a cross-sectional view showing a fourth example of a display system. [Figure 9B] It is a cross-sectional view showing a fifth example of a display system. [Figure 10] It is a graph showing the relationship between the alternation of the clock and the electromotive force generated in the position detector. [Figure 11] It is a flowchart showing an example of the flow of a series of operations of a display system.

Modes for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention (hereinafter referred to as "this embodiment") will be described with reference to the attached drawings. To facilitate understanding of the description, the same reference numerals are used for the same components and steps in each drawing whenever possible, and redundant explanations are omitted.

[0021] ---First Embodiment--- First, let me describe the first embodiment.

[0022] <Structure> Figure 1 shows an example of a display system 1A according to the first embodiment. The display system 1A is a computer, monitor, or television held by the user, for example, a tablet. ッ Examples include smartphones, personal computer monitors, and television receivers. In this example, we will describe the case where the display device 10 included in the display system 1A is a liquid crystal display. The display system 1A is composed of, for example, the display device 10, a gate driver circuit 20, a source driver circuit 30, a control circuit 40, and clock lines WCL1 to WCL8 (see Figure 3).

[0023] The display device 10 is, for example, a liquid crystal display. The display device 10 is composed of, for example, a display module 11 and a backlight module 12.

[0024] The display module 11 comprises vertically arranged row signal lines GL1 to GLn, horizontally arranged column signal lines SL1 to SLm, and image elements 110 positioned at each intersection of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm. The display module 11 drives one of the row signal lines GL1 to GLn according to the gate signals VG1 to VGn transmitted from the gate driver circuit 20, and drives each image element 110 corresponding to the source signals VS1 to VSm with the brightness indicated by the source signals VS1 to VSm transmitted from the source driver circuit 30.

[0025] Row signal lines GL1 to GLn are, for example, gate lines, and n of them are arranged vertically in the display device 10. Row signal lines GL1 to GLn are driven by corresponding gate signals VG1 to VGn transmitted from the gate driver circuit 20 and relay the exchange of charge between the gate electrode of the image element 110 at the intersection with the column signal lines SL1 to SLm and the gate driver circuit 20.

[0026] The column signal lines SL1 to SLm are, for example, source lines, and m of them are arranged horizontally in the display device 10. The column signal lines SL1 to SLm are driven by the corresponding source signals VS1 to VSm transmitted from the source driver circuit 30, and relay the charge exchange between the source electrodes of the image element 110 and the source driver circuit 30 at the intersections with the row signal lines GL1 to GLn.

[0027] The image element 110 is, for example, a liquid crystal image element, and a total of n × m of them are arranged in the display device 10 at the intersections of row signal lines GL1 to GLn and column signal lines SL1 to SLm. One of the row signal lines GL1 to GLn of the image element 110 is connected to the gate electrode, and one of the column signal lines SL1 to SLm is connected to the source electrode. When charge is supplied to the gate electrode via the row signal lines GL1 to GLn connected to the gate electrode, the image element 110 displays the corresponding image with a brightness according to the potential of the column signal lines SL1 to SLm connected to the source electrode.

[0028] The backlight module 12 is a light source located on the back side of the display module 11, and illuminates the display module 11 with light from the back.

[0029] The gate driver circuit 20 is a circuit that drives the row signal lines GL1 to GLn, and is located to the left of the display device 10 when the display system 1A is viewed from the display surface side. The gate driver circuit 20 drives the row signal lines GL1 to GLn sequentially by outputting gate signals VG1 to VGn to the corresponding row signal lines GL1 to GLn at timings according to the clocks CLK1 to CLK8 output from the control circuit 40. The gate driver circuit 20 also supplies and extracts charge to the gate electrodes of the corresponding image elements 110 via the driven row signal lines GL1 to GLn.

[0030] The source driver circuit 30 is a circuit that drives the column signal lines SL1 to SLm, and is located below the display device 10 when the display system 1A is viewed from the display surface side. The source driver circuit 30 drives source signals VS1 to VSm, which have a potential set each time by the control circuit 40 for each column signal line SL1 to SLm, at timings according to the control circuit 40, to the corresponding column signal lines SL1 to SLm. m The output is sent to the source. The source driver circuit 30 supplies the potentials of the source signals VS1 to VSm corresponding to the image element 110 to the source electrodes of the image element 110 corresponding to the intersections of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm driven by the gate driver circuit 20.

[0031] The control circuit 40 is a circuit for controlling the display device 10. The control circuit 40 controls the row signal lines GL1~GL by the gate driver circuit 20. n When starting the drive, the control circuit 40 generates start signals ST1 to ST4, which are signals indicating the start of the drive, and outputs the start signals ST1 to ST4 to the gate driver circuit 20. The control circuit 40 also generates clocks CLK1 to CLK8 to operate the gate driver circuit 20, and outputs the clocks CLK1 to CLK8 to the gate driver circuit 20 via clock lines WCL1 to WCL8.

[0032] Furthermore, the control circuit 40 generates a clock for operating the source driver circuit 30 and outputs the clock to the source driver circuit 30. The control circuit 40 also sets the potential supplied to the source electrode of the corresponding image element 110 via the column signal lines SL1 to SLm and outputs a signal containing the information of the set potential to the source driver circuit 30.

[0033] Figure 2 shows an example of an image element 110 according to the first embodiment. As shown in Figure 2, the image element 110 is composed of, for example, a thin-film transistor TFT, a liquid crystal electrode Clc, and a capacitive element Cpx.

[0034] The thin-film transistor TFT functions as a switching element in the image element 110. The gate electrode of the thin-film transistor TFT is connected to the row signal line GL, the source electrode is connected to the column signal line SL, and the drain electrode is connected to one end of the liquid crystal electrode Clc and the capacitive element Cpx. When charge is supplied to the gate electrode via the row signal line GL, the thin-film transistor TFT makes the state between the source electrode and the drain electrode conductive. Conversely, when charge is withdrawn from the gate electrode via the row signal line GL, the thin-film transistor TFT makes the state between the source electrode and the drain electrode non-conductive. Furthermore, the thin-film transistor TFT maintains the state between the source electrode and the drain electrode when there is no change in the potential applied to the gate electrode.

[0035] The liquid crystal electrode Clc is an electrode that supplies potential to the liquid crystal. One end of the liquid crystal electrode Clc is connected to the drain electrode of the thin-film transistor TFT and one end of the capacitive element Cpx, while the other end is connected to the common electrode COM via the liquid crystal. The liquid crystal electrode Clc supplies the potential supplied from the capacitive element Cpx to the liquid crystal.

[0036] The capacitive element Cpx is, for example, a capacitor, and holds a potential to supply to the liquid crystal electrode Clc. One end of the capacitive element Cpx is connected to the drain electrode of the thin-film transistor TFT and one end of the liquid crystal electrode Clc, and the other end is connected to the common electrode COM. When the thin-film transistor TFT is in a conducting state, the capacitive element Cpx holds the potential supplied from the column signal line SL. When the thin-film transistor TFT is in a non-conducting state, the capacitive element Cpx supplies the held potential to the liquid crystal electrode Clc.

[0037] The image element 110, configured as described above, when charge is supplied to the gate electrode of the thin-film transistor TFT via the row signal line GL, turns the thin-film transistor TFT into a conductive state, supplies the potential of the column signal line SL to the capacitive element Cpx, and holds the potential supplied via the column signal line SL to the capacitive element Cpx. Furthermore, when charge is withdrawn from the gate electrode of the thin-film transistor TFT via the row signal line GL, the image element 110 turns the thin-film transistor TFT into a non-conductive state, supplies the potential held by the capacitive element Cpx to the liquid crystal electrode Clc, and controls the state of the liquid crystal to conform to the supplied potential.

[0038] Figure 3A is a diagram showing an example of the circuit configuration of the clock lines WCL1 to WCL8 and the gate driver circuit 20 according to the first embodiment. As shown in Figure 3A, the gate driver circuit 20 is configured to include, for example, n drive circuits DRV.

[0039] The drive circuit DRV is provided in the gate driver circuit 20, with n DRVs for each of the n row signal lines GL1 to GLn. The DRV outputs a gate signal VG to the corresponding row signal line GL1 to GLn at a timing according to one of the clocks CLK1 to CLK8 supplied from the control circuit 40 to the clock lines WCL1 to WCL8.

[0040] Furthermore, the drive circuit DRV, together with other drive circuits DRV, constitutes the shift register 201 (see Figure 3B). In this embodiment, the gate driver circuit 20 is configured to include four shift registers 201, each consisting of a different group of drive circuits DRV. Furthermore, the drive circuit DRV is a shift register 201 Block 202 is formed by drive circuits DRVs that are in the same stage, and within this block 202, the drive circuits DRVs for the first shift register 201 are arranged vertically in order from the drive circuit DRV for the first shift register 201 to the drive circuit DRV for the fourth shift register 201 (see Figure 3C). In the gate driver circuit 20, this block 202 is arranged vertically in order from the frontmost stage to the backmost stage of the shift register 201.

[0041] Furthermore, the drive circuit DRV has its clock terminal CK connected to one of the clock lines WCL1 to WCL8, its input terminal I connected to the output terminal O of the previous drive circuit DRV, its output terminal O connected to one of the row signal lines GL1 to GLn, its input terminal I of the next drive circuit DRV, and its reset terminal R of the previous-previous stage, with the reset terminal R connected to the output terminal O of the next-previous drive circuit DRV. Note that in each shift register 201, the input terminal I of the foremost drive circuit DRV is connected to the control circuit 40 instead of the output terminal O of the previous drive circuit DRV, and one of the start signals ST1 to ST4 output from the control circuit 40 is input. Also, in each shift register 201, the reset terminal R of the drive circuit DRV for which there is no next-previous stage is connected to the control circuit 40, and the reset signal RST output from the control circuit 40 is input.

[0042] Here, the shift register 201 will be explained with reference to Figure 3B. Figure 3B is a diagram showing an example of the circuit configuration of the first shift register 201 according to the first embodiment. As shown in Figure 3B, the shift register 201 includes, for example, drive circuits DRV1, DRV5, DRV9...DRVn -3 It is composed of including the following.

[0043] As shown in Figure 3B, the drive circuit DRV1 outputs a gate signal VG1 containing information indicated by the start signal ST1 input to input terminal I to the drive circuit DRV5 via output terminal O, at a timing according to the clock CLK1. Similarly, drive circuits DRV5, DRV9…DRVn -3 The input terminal I Gate signals VG5, VG9…VGn contain information about the signals input to the gate signals. -3 This is output from output terminal O to the subsequent drive circuit DRV.

[0044] Next, block 202 will be described with reference to Figure 3C. Figure 3C is a diagram showing an example of the circuit configuration of block 202 according to the first embodiment. As shown in Figure 3C, block 202 is configured to include, for example, drive circuits DRV1 to DRV4.

[0045] As shown in Figure 3C, the drive circuits DRV1 to DRV4 output gate signals VG1 to VG4 from the output terminal O, each containing information indicated by the start signal ST1 input to the input terminal I, at timings corresponding to the clocks CLK1 to CLK4.

[0046] Returning to Figure 3A, the clock lines WCL1 to WCL8 are signal lines that supply the clocks CLK1 to CLK8 output from the control circuit 40 to the gate driver circuit 20. When the display system 1A is viewed from the display side, the clock lines WCL1 to WCL8 are arranged horizontally in the order of WCL1, WCL5, WCL2, WCL6, WCL3, WCL7, WCL4, and WCL8 from left to right, to the left of the gate driver circuit 20.

[0047] The clock line WCL1 supplies the clock CLK1 input from the control circuit 40 to the clock terminal CK of the odd-numbered stage drive circuits DRV1, DRV9...DRVn-7 in the first of the four shift registers 201.

[0048] The clock line WCL5 supplies the clock CLK5 input from the control circuit 40 to the clock terminal CK of the even-numbered stage drive circuits DRV5, DRV13...DRVn-3 in the first of the four shift registers 201. Note that the clock CLK5 is generated by the control circuit 40 so that its phase is inverse with respect to the clock CLK1.

[0049] The clock line WCL2 supplies the clock CLK2 input from the control circuit 40 to the clock terminal CK of the odd-numbered stage drive circuits DRV2, DRV10...DRVn-6 in the second of the four shift registers 201.

[0050] The clock line WCL6 supplies the clock CLK6 input from the control circuit 40 to the clock terminal CK of the even-numbered stage drive circuits DRV6, DRV14…DRVn-2 in the second of the four shift registers 201. Note that the clock CLK6 is generated by the control circuit 40 so that its phase is inverse with respect to the clock CLK2.

[0051] The clock line WCL3 supplies the clock CLK3 input from the control circuit 40 to the clock terminal CK of the odd-numbered stage drive circuits DRV3, DRV11...DRVn-5 in the third of the four shift registers 201.

[0052] The clock line WCL7 supplies the clock CLK7 input from the control circuit 40 to the clock terminal CK of the even-numbered stage drive circuits DRV7, DRV15…DRVn-1 in the third of the four shift registers 201. Note that the clock CLK7 is generated by the control circuit 40 so that its phase is inverse with respect to the clock CLK3.

[0053] The clock line WCL4 supplies the clock CLK4 input from the control circuit 40 to the clock terminal CK of the odd-numbered stage drive circuits DRV4, DRV12…DRVn-4 in the fourth of the four shift registers 201.

[0054] The clock line WCL8 supplies the clock CLK8 input from the control circuit 40 to the clock terminal CK of the even-numbered stage drive circuits DRV8, DRV16…DRVn in the fourth of the four shift registers 201. Note that the clock CLK8 is generated by the control circuit 40 so that its phase is inverse with respect to the clock CLK4.

[0055] Figure 4 shows an example of the circuit configuration of the drive circuit DRV according to the first embodiment. As shown in Figure 4, the drive circuit DRV is composed of transistors TR1 to TR8 and a capacitive element Cd.

[0056] Transistors TR1 to TR8 are, for example, NMOS transistors. On the one hand, when the potential difference between the gate terminal and the source terminal of transistors TR1 to TR8 is greater than or equal to a predetermined value, the state between the drain terminal and the source terminal becomes conductive. On the other hand, when the potential difference between the gate terminal and the source terminal of transistors TR1 to TR8 is less than a predetermined value, the state between the drain terminal and the source terminal becomes non-conductive. In this embodiment, the case where transistors TR1 to TR8 are NMOS transistors has been described, but it is not limited to this, and transistors TR1 to TR8 may also be PMOS transistors.

[0057] Transistor TR1 has its drain and gate terminals connected to the input terminal I of the drive circuit DRV by a diode connection. As long as the potential of the gate and drain terminals is higher than the potential of the source terminal, it supplies charge from the input terminal I to the capacitive element Cd via node BT from the source terminal. Transistor TR1 has its gate and drain terminals connected to the input terminal I of the drive circuit DRV, and its source terminal connected to node BT.

[0058] Transistor TR2 has its drain and gate terminals connected to the power line W_VGH via a diode connection. As long as the potential of the gate and drain terminals is higher than the potential of the source terminal, it supplies the potential from the power line W_VGH to the gate terminals of transistors TR4 and TR5 from the source terminal. Transistor TR2 has its gate and drain terminals connected to the power line W_VGH, and its source terminal is connected to the drain terminal of transistor TR3 and the gate terminals of transistors TR4 and TR5.

[0059] Transistor TR3 supplies the potential of the reference line W_VGL connected to its source terminal to the gate terminals of transistors TR4 and TR5 from its drain terminal, according to the potential of node BT input to its gate terminal. 3 The gate terminal is connected to node BT, the drain terminal is connected to the source terminal of transistor TR2 and the gate terminals of transistors TR4 and TR5, and the source terminal is connected to the reference line W_VGL.

[0060] Transistor TR4 supplies the potential of the reference line W_VGL, which is connected to its source terminal, to node BT via its drain terminal, according to the potential input to its gate terminal. Transistor TR4's gate terminal is connected to the source terminal of transistor TR2, the drain terminal of transistor TR3, and the gate terminal of transistor TR5, its drain terminal is connected to node BT, and its source terminal is connected to the reference line W_VGL.

[0061] Transistor TR5 supplies the potential of the reference line W_VGL, which is connected to its source terminal, to the output terminal O of the drive circuit DRV via its drain terminal, according to the potential input to its gate terminal. Transistor TR5's gate terminal is connected to the source terminal of transistor TR2, the drain terminal of transistor TR3, and the gate terminal of transistor TR4, its drain terminal is connected to the output terminal O of the drive circuit DRV, and its source terminal is connected to the reference line W_VGL.

[0062] Transistor TR6 supplies the potential of the reference line W_VGL, which is connected to its source terminal, to node BT via its drain terminal, according to the potential input to its gate terminal. Transistor TR6 has its gate terminal connected to the reset terminal R of the drive circuit DRV, its drain terminal connected to node BT, and its source terminal connected to the reference line W_VGL.

[0063] Transistor TR7 supplies the potential of the reference line W_VGL, which is connected to the source terminal, to the output terminal O of the drive circuit DRV via its drain terminal, according to the potential input to the gate terminal. Transistor TR7 has its gate terminal connected to the reset terminal R of the drive circuit DRV, its drain terminal connected to the output terminal O of the drive circuit DRV, and its source terminal connected to the reference line W_VGL.

[0064] Transistor TR8 adjusts the potential of the clock CLK supplied from the clock terminal CK of the drive circuit DRV connected to its drain terminal, according to the potential input to its gate terminal. sauce The terminal supplies power to the output terminal O of the drive circuit DRV. Transistor TR8 has its gate terminal connected to node BT, its drain terminal connected to the clock terminal CK of the drive circuit DRV, and its source terminal connected to the output terminal O of the drive circuit DRV.

[0065] The capacitive element Cd is, for example, a capacitor, and maintains the potential of node BT by charging with the charge supplied from the source terminal of transistor TR1 through node BT. One end of the capacitive element Cd is connected to node BT, and the other end is connected to the output terminal O of the drive circuit DRV.

[0066] In the drive circuit DRV configured as described above, when the potential of the reset terminal R and node BT is at the potential VGL (low level) of the reference line W_VGL, transistors TR3, TR6, TR7, and TR8 become non-conductive. Consequently, the potential of the source terminal of transistor TR2, which is diode-connected to the power line W_VGH, becomes at the potential VGH (high level) of the power line W_VGH, and transistors TR4 and TR5 become conductive. As transistors TR4 and TR5 become conductive, node BT and output terminal O are short-circuited to the reference line W_VGL via transistors TR4 and TR5, respectively, so the potential of node BT and output terminal O becomes low level. Therefore, the drive circuit DRV outputs a gate signal VG from output terminal O with a low potential.

[0067] Next, when the potential of node BT is low and a high potential is supplied to input terminal I, transistor TR1 supplies charge to one end of the capacitive element Cd via node BT, thereby charging the capacitive element Cd. When the capacitive element Cd is charged and the potential of node BT reaches a high level, the states of transistors TR1, TR3, and TR8 become "non-conductive," "conductive," and "conductive," respectively. Consequently, the states of transistors TR4 and TR5 become non-conductive. Therefore, the drive circuit DRV uses the clock CLK input from clock terminal CK as the gate signal VG and outputs the gate signal VG from output terminal O.

[0068] Next, when the potential of node BT is high and a high potential is supplied to the reset terminal R, transistors TR6 and TR7 become conductive. Consequently, node BT and output terminal O are short-circuited to the reference line W_VGL via transistors TR6 and TR7, respectively, so the potentials of node BT and output terminal O become low. Furthermore, transistors TR3 and TR8 become non-conductive, and accordingly, transistors TR4 and TR5 become conductive. Therefore, the drive circuit DRV outputs the gate signal VG from output terminal O with a low potential.

[0069] Furthermore, if a low-level potential is supplied to the reset terminal R while the potential of node BT is low, the states of transistors TR6 and TR7 become non-conductive. Since the states of transistors TR4 and TR5 remain non-conductive, the drive circuit DRV continues to output a gate signal VG with a low potential from output terminal O.

[0070] The configuration of the display system 1 has been described above. Next, the potential transitions of the clocks CLK1 to CLK8 in the display system 1A will be described in detail. Figure 6 is a timing chart showing a first example of the potential transitions of the clocks CLK1 to CLK8 in the display system 1A according to the first embodiment.

[0071] At time t61, the control circuit 40 transitions the potential of clock CLK1 from a low level to a high level, and also transitions the potential of clock CLK5 from a high level to a low level.

[0072] At time t62, the control circuit 40 transitions the potential of clock CLK2 from a low level to a high level, and also transitions the potential of clock CLK6 from a high level to a low level.

[0073] At time t63, the control circuit 40 transitions the potential of clock CLK3 from a low level to a high level, and also transitions the potential of clock CLK7 from a high level to a low level.

[0074] At time t64, the control circuit 40 transitions the potential of clock CLK4 from a low level to a high level, and also transitions the potential of clock CLK8 from a high level to a low level.

[0075] At time t65, the control circuit 40 transitions the potential of clock CLK1 from a high level to a low level, and also transitions the potential of clock CLK5 from a low level to a high level.

[0076] At time t66, the control circuit 40 transitions the potential of clock CLK2 from a high level to a low level, and also transitions the potential of clock CLK6 from a low level to a high level.

[0077] At time t67, the control circuit 40 transitions the potential of clock CLK3 from a high level to a low level, and also transitions the potential of clock CLK7 from a low level to a high level.

[0078] At time t68, the control circuit 40 transitions the potential of clock CLK4 from a high level to a low level, and also transitions the potential of clock CLK8 from a low level to a high level.

[0079] From time t69 onward, the control circuit 40 transitions the potentials of clocks CLK1 to CLK8, similar to the transitions from time t61 to time t68.

[0080] In this example, the control circuit 40 generates clocks CLK1 to CLK8 such that the phases of the clocks CLK1 to CLK4 input to the odd-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 are inverse phase with the phases of the clocks CLK5 to CLK8 input to the even-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20, which correspond to clocks CLK1 to CLK4 respectively. However, it is not limited to this. The control circuit 40 may also set the phases of clocks CLK5 to CLK8 to be shifted from the opposite phase with respect to the phases of clocks CLK1 to CLK4, as long as it is within the period until the image element 110, which is driven by the drive circuits DRV supplied with clocks CLK1 to CLK4 via the row signal line GL, completes charging or discharging.

[0081] The potential transitions of clocks CLK1 to CLK8 in the display system 1A have been described above. Next, the potential transitions of each signal in the drive circuit DRV of the display system 1A will be described in detail. Figure 7 is a timing chart showing an example of the potential transitions of each signal in the drive circuit DRV according to the first embodiment. In Figure 7, nodes BT(1), BT(5), and BT(9) are nodes BT of the 1st to 3rd stage drive circuits DRV1, DRV5, and DRV9 of the shift register 201, respectively.

[0082] At time t70, the control circuit 40 sets the potential of the start signal ST1 to a high level and outputs the start signal ST1 to the input terminal I of the first-stage drive circuit DRV1. At time t70, with the supply of a high-level potential to the input terminal I, the capacitive element Cd in the first-stage drive circuit DRV1 is charged, and the potential of node BT(1) transitions to a high level.

[0083] At time t71, the control circuit 40 transitions the potential of the clock CLK1 from a low level to a high level and outputs the clock CLK1 to the clock terminal CK of the first and third stage drive circuits DRV1 and DRV9. At time t71, with the supply of a high-level potential to the clock terminal CK, the potential of one end of the capacitive element Cd in the first stage drive circuit DRV1 is raised, and the potential of node BT(1) begins to transition from a high level to twice the high level. Also at time t71, the potential of the gate signal VG1 output from the first stage drive circuit DRV1 to the row signal line GL1 and to the input terminal I of the second stage drive circuit DRV5 begins to transition from a low level to a high level.

[0084] Furthermore, at time t71, the control circuit 40 transitions the potential of the clock CLK5 from a high level to a low level and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t71, with the input of the gate signal VG1 from the first-stage drive circuit DRV1 to the input terminal I of the second-stage drive circuit DRV5, the potential of node BT(5) begins to transition from a low level to a high level.

[0085] At time t72, the potential of gate signal VG1 reaches a high level. Consequently, at time t72, the potential of node BT(1) reaches twice the high level. Furthermore, at time t72, the potential of node BT(5) reaches a high level.

[0086] At time t73, control circuit 40 transitions the potential of clock CLK1 from a high level to a low level and outputs clock CLK1 to the clock terminal CK of the first and third stage drive circuits DRV1 and DRV9. Also at time t73, control circuit 40 transitions the potential of start signal ST1 from a high level to a low level. At time t73, with the supply of a low level potential to the clock terminal CK, the potential of one end of the capacitive element Cd in the first stage drive circuit DRV1 is lowered, and the potential of node BT(1) begins to transition from twice the high level to a high level. Also at time t73, the potential of gate signal VG1, which is output from the first stage drive circuit DRV1 to the row signal line GL1 and to the input terminal I of the second stage drive circuit DRV5, begins to transition from a high level to a low level.

[0087] Also, at time t73, the control circuit 40 transitions the potential of the clock CLK5 from a low level to a high level and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t73, with the supply of a high-level potential to the clock terminal CK, the potential of one end of the capacitive element Cd in the second-stage drive circuit DRV5 is raised, and the potential of node BT(5) begins to transition from a high level to twice the high level. Also at time t73, the potential of the gate signal VG5 output from the second-stage drive circuit DRV5 to the row signal line GL5 and the input terminal I of the third-stage drive circuit DRV9 begins to transition from a low level to a high level.

[0088] Furthermore, at time t73, the potential of node BT(9) begins to transition from a low level to a high level as the gate signal VG5 is input from the second-stage drive circuit DRV5 to the input terminal I of the third-stage drive circuit DRV9.

[0089] At time t74, the potential of gate signal VG1 reaches a low level. Consequently, at time t74, the potential of node BT(1) reaches a high level. Also at time t74, the potential of gate signal VG5 reaches a high level. Consequently, at time t74, the potential of node BT(5) reaches twice the high level. Furthermore, at time t74, the potential of node BT(9) reaches a high level.

[0090] At time t75, the control circuit 40 transitions the potential of clock CLK1 from a low level to a high level and outputs clock CLK1 to the clock terminal CK of the first and third stage drive circuits DRV. At time t75, upon input of the gate signal VG9 to the reset terminal R, the potential of node BT(1) begins to transition from a high level to a low level.

[0091] Furthermore, at time t75, the control circuit 40 transitions the potential of the clock CLK5 from a high level to a low level and outputs the clock CLK5 to the clock terminal CK of the second stage drive circuit DRV5. At time t75, the low level of the clock terminal CK Electric potential As the supply is activated, the potential of one end of the capacitive element Cd in the second-stage drive circuit DRV5 is lowered, and the potential of node BT(5) begins to transition from twice the high level potential to the high level.

[0092] Furthermore, at time t75, with the input of the gate signal VG5 to input terminal I, the potential of one end of the capacitive element Cd in the third stage drive circuit DRV9 is raised, and the potential of node BT(9) begins to transition from high level to twice the high level. Also at time t75, the row signal line GL9 and the fourth stage drive circuit DRV1 3 The potential of the gate signal VG9, which is output to input terminal I and reset terminal R of the first-stage drive circuit DRV1, begins to transition from a low level to a high level.

[0093] At time t76, the potential of gate signal VG1 remains at a low level. At time t76, the potential of gate signal VG5 reaches a low level. Consequently, at time t76, the potential of node BT(5) reaches a high level. Also at time t76, the potential of gate signal VG9 reaches a high level. Consequently, at time t76, the potential of node BT(1) reaches a low level. Furthermore, at time t76, the potential of node BT(9) reaches twice the high level.

[0094] At time t77, the control circuit 40 transitions the potential of the clock CLK1 from a high level to a low level and outputs the clock CLK1 to the clock terminals CK of the first and third stage drive circuits DRV1 and DRV9.

[0095] Furthermore, at time t77, the control circuit 40 transitions the potential of clock CLK5 from a low level to a high level and outputs clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t77, upon input of the gate signal VG13 to the reset terminal R, the potential of node BT(5) begins to transition from a high level to a low level.

[0096] Furthermore, at time t77, a low level is sent to the clock terminal CK. Electric potential As the power is supplied, the potential of one end of the capacitive element Cd in the third stage drive circuit DRV9 is lowered, and the potential of node BT(9) begins to transition from twice the high level to the high level. Also, at time t75, the potential of the gate signal VG9 begins to transition from the high level to the low level.

[0097] At time t78, the potentials of gate signals VG1 and VG5 remain at low levels. Also at time t78, the potential of gate signal VG9 reaches a low level. Furthermore, at time t78, as the potential of gate signal VG13 reaches a low level, the potential of node BT(5) also reaches a low level.

[0098] At time t79, control circuit 40 transitions the potential of clock CLK1 from a low level to a high level and outputs clock CLK1 to the clock terminals CK of the first and third stage drive circuits DRV1 and DRV9. Also at time t79, control circuit 40 transitions the potential of clock CLK5 from a high level to a low level and outputs clock CLK5 to the clock terminal CK of the second stage drive circuit DRV5. Furthermore, at time t79, in conjunction with the input of gate signal VG17 to reset terminal R, the potential of node BT(9) begins to transition from a high level to a low level.

[0099] At time t80, the potentials of gate signals VG1, VG5, and VG9 remain at low levels. Also at time t80, as the potential of gate signal VG17 reaches a low level, the potential of node BT(9) also reaches a low level.

[0100] In this example, the control circuit 40 generates clock CLK1 and CLK5 such that the phase of clock CLK1 input to the odd-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 is in opposite phase to the phase of clock CLK5 input to the even-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20, which corresponds to clock CLK1. However, it is not limited to this. The control circuit 40 may set the phase of clock CLK5 to a phase shifted from the opposite phase to the phase of clock CLK1, as long as it is within the period until the image element 110, driven by drive circuits DRV1 and DRV9 supplied with clock CLK1 via row signal lines GL1 and GL9, completes charging or discharging.

[0101] The potential transitions of each signal in the drive circuit DRV of the display system 1A have been described above. Next, the sequence of processing steps of the display system 1A will be described in detail. Figure 11 is a flowchart showing an example of the sequence of processing steps of the display system 1A according to the first embodiment.

[0102] (Step SP10) The control circuit 40 determines whether the time is the timing to raise the clock (clock CLK1 in Figure 7) supplied to the odd-numbered drive circuits DRV in any of the shift registers 201 of the gate driver circuit 20, or the first timing (times t71, t75, and t79 in Figure 7) to lower the clock (clock CLK5 in Figure 7) supplied to the even-numbered drive circuits DRV in the same shift register 201. If the determination is affirmative, the process proceeds to the process of step SP12. If the determination is negative, the process proceeds to the process of step SP14.

[0103] (Step SP12) The control circuit 40 has a first period (the period from time t75 to t76 in Figure 7) during which it supplies charge to the image element 110 (first image element) corresponding to the odd-numbered drive circuit DRV, and a second period during which it extracts charge from the image element 110 (second image element) corresponding to the even-numbered drive circuit DRV. four The drive circuit DRV drives the corresponding row signal line GL so that it overlaps with the period (the period from time t75 to t76 in Figure 7). As a result, the control circuit 40 charges the image element 110 (first image element) and discharges the image element 110 (second image element). Then, the process proceeds to step SP14.

[0104] (Step SP14) The control circuit 40 determines whether the time is the timing to lower the clock (clock CLK1 in Figure 7) supplied to the odd-numbered drive circuits DRV in any of the shift registers 201 of the gate driver circuit 20, or the second timing (times t73 and t77 in Figure 7) to raise the clock (clock CLK5 in Figure 7) supplied to the even-numbered drive circuits DRV in the same shift register 201. If the determination is affirmative, the process proceeds to step SP16. If the determination is negative, the series of processes shown in Figure 11 terminates.

[0105] (Step SP16) The control circuit 40 performs a second period (the period from time t73 to t74 in Figure 7) to extract charge from the image element 110 (first image element) corresponding to the odd-numbered drive circuit DRV, and a second period to supply charge to the image element 110 (second image element) corresponding to the even-numbered drive circuit DRV. three The drive circuit DRV drives the corresponding row signal line GL so that it overlaps with the period (the period from time t73 to t74 in Figure 7). As a result, the control circuit 40 discharges the image element 110 (first image element) and charges the image element 110 (second image element).

[0106] <Effects> In the first embodiment described above, the display system 1A comprises a plurality of column signal lines SL1 to SLm arranged horizontally and a plurality of row signal lines GL (first row signal lines: GL1 to GL4, GL9 to GL1) arranged vertically. 2 The display device 10 includes a plurality of row signal lines GL (second row signal lines: GL5 to GL8, GL13 to GL16, ... GLn-3 to GLn), a plurality of image elements 110 (first image elements) located at the intersections of the first row signal lines and column signal lines SL1 to SLm, and a plurality of image elements 110 (second image elements) located at the intersections of the second row signal lines and column signal lines SL1 to SLm. The display system 1A further includes a gate driver circuit 20 (driver circuit) having a plurality of drive circuits DRV (first drive circuits) provided for each first row signal line and driving the first image element via the corresponding first row signal line, and a drive circuit DRV (second drive circuit) provided for each second row signal line and driving the second image element via the corresponding second row signal line. Furthermore, in the display system 1A, the first drive circuit supplies charge to the first image element during the first period (times t75-t76 in Figure 7) and extracts charge from the first image element during the second period (times t73-t74 in Figure 7), which is different from the first period. Also, in the display system 1A, the second drive circuit supplies charge to the second image element during the third period (times t73-t74 in Figure 7), which overlaps at least partially with the second period, and extracts charge from the second image element during the fourth period (times t75-t76 in Figure 7), which overlaps at least partially with the first period.

[0107] In this configuration, at least a portion of the magnetic field noise and electric field noise emitted from the display system 1A during the first period when charge is supplied to the first image element is canceled out by the magnetic field noise and electric field noise emitted from the display system 1A during the third period when charge is extracted from the second image element. Furthermore, at least a portion of the magnetic field noise and electric field noise emitted from the display system 1A during the second period when charge is extracted from the first image element may be canceled out by the magnetic field noise and electric field noise emitted from the display system 1A during the fourth period when charge is supplied to the second image element. Therefore, the display system 1A can reduce the noise it emits.

[0108] Furthermore, in this embodiment, the display system 1A further comprises first clock lines WCL1 to WCL4 that supply the first clock CLK1 to CLK4 to the first drive circuit, and second clock lines WCL5 to WCL8 that supply the second clock CLK5 to CLK8 to the second drive circuit. In the display system 1A, the first drive circuit either supplies charge to or extracts charge from the first image element according to the alternation of the first clock CLK1 to CLK4. Furthermore, in the display system 1A, the second drive circuit either supplies charge to or extracts charge from the second image element according to the alternation of the second clock CLK5 to CLK8. In addition, in the display system 1A, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are arranged parallel to each other and adjacent to one another.

[0109] According to this configuration, the display system 1A uses the first clock line WCL1~ WCL At least a portion of the magnetic field noise and electric field noise emitted from 4 is directed to the second clock line WCL5, which is arranged parallel and adjacent to the first clock lines WCL1 to WCL4. WCL It is canceled out by the magnetic field noise and electric field noise emitted from 8. Also, the second clock line WCL5~ WCL At least a portion of the magnetic field noise and electric field noise emitted from 8 is also transmitted via the first clock line WCL1~ WCLThe magnetic field noise and electric field noise emitted from 4 cancel each other out. Therefore, the display system 1A can reduce the noise emitted from the display system 1A.

[0110] Furthermore, in this embodiment, the first drive circuit and the second drive circuit are connected alternately in series, and the first drive circuit holds the information indicated by the gate signals (VG5~VG8, VG13~VG16, ... VGn-11~VGn-8) output from the second drive circuit connected to the preceding stage, and the gate signals (VG9~VG12, VG17~VG20, ... VG9~VG12, ... VG17~VG20) containing the information held in the first period. V Gn-7~ V The gate signals (VG1~VG4, VG9~VG12, ...VGn-) output from the first drive circuit connected to the preceding stage are output to the second drive circuit. 15 ~VGn- 12 The first drive circuit holds the information indicated by the gate signals (VG5~VG8, VG13~VG16, ...VGn-11~VGn-8) containing the information held during the third period and outputs them to the first drive circuit connected to the next stage. Furthermore, the first drive circuit initializes the information it holds according to the gate signals (VG9~VG12, ...VGn-7~VGn-4) output from the first drive circuit connected to the next stage or beyond, or the gate signals (VG13~VG16, ...VGn-3~VGn) output from the second drive circuit connected to the next stage or beyond. The second drive circuit also initializes the information it holds according to the gate signals (VG13~VG16, ...VGn-3~VGn) output from the second drive circuit connected to the next stage or beyond, or the gate signals (VG17~VG20, ...VGn-7~VGn-4) output from the first drive circuit connected to the next stage or beyond.

[0111] In this configuration, the display system 1A initializes according to the gate signal VG output from the first or second drive circuit, which is connected to the next stage or later, respectively. This ensures that the display system 1A has a sufficient margin period between the time the first and second drive circuits drive the first and second row signal lines and the time they initialize.

[0112] ---Second Embodiment--- Next, a second embodiment will be described.

[0113] <Structure> Figure 5A shows the clock line WCL1 and W This figure shows a second example of the CL5 arrangement. Figure 5B also shows the clock line WCL1 and W This figure shows a third example of the CL5 arrangement. Figure 5C also shows the clock line WCL1 and W This figure shows a fourth example of the CL5 arrangement. Although not shown in the figures, in Figures 5A, 5B, and 5C, clock lines WCL2 to WCL8 are also included, as well as clock line WCL1 and W It is assumed that the components are arranged in the same way as LK5. Furthermore, since the display system 1B is the same as the display system 1A in the first embodiment except for the different arrangement of clock lines WCL1 to WCL8, the explanation of the similar parts will be omitted.

[0114] As shown in Figures 5A, 5B, and 5C, in the display system 1B, the clock lines WCL1 and WCL5 are arranged to be adjacent to each other and parallel, and intersect each other at regular intervals.

[0115] In Figure 5A, in the display system 1B, clock line WCL5 is placed on the layer above the layer where clock line WCL1 is placed. Furthermore, clock lines WCL1 and WCL5 are arranged in the display system 1B in a rectangular wave shape, moving back and forth between the right and left lanes at regular intervals. In addition, clock lines WCL1 and WCL5 are arranged so that the vertical positions of their horizontal lines overlap when they move to the opposite lane. In this example, the case where clock line WCL5 is placed on the layer above the layer where clock line WCL1 is placed has been described, but this is not the only case, and clock line WCL1 may be placed on the layer above the layer where clock line WCL5 is placed.

[0116] In Figure 5B, in the display system 1B, clock line WCL5 is positioned above the layer on which clock line WCL1 is located. Furthermore, clock lines WCL1 and WCL5 are arranged in the display system 1B in a trapezoidal wave pattern, moving back and forth between the right and left lanes at regular intervals. In addition, clock lines WCL1 and WCL5 are positioned such that their vertical positions when moving to the opposite lane are the same. Note that this example describes the case where clock line WCL5 is positioned above the layer on which clock line WCL1 is located, but this is not the only case; clock line WCL1 may also be positioned above the layer on which clock line WCL5 is located.

[0117] In Figure 5C, in the display system 1B, the clock lines WCL1 and WCL5 are formed by a lower line located in the lower layer, an upper line located in the upper layer, and vias that electrically connect the lower line and the upper line.

[0118] The lower line extends downward from the top end along the right lane, then downward to the left along the left lane, and finally downward along the left lane to the bottom end. The bottom and top ends of the lower line are connected to the top and bottom ends of the upper line, respectively, via vias.

[0119] The upper line extends downward from the top end down the left lane, then downward to the right lane, and finally downward along the right lane to the bottom end. The bottom and top ends of the upper line are connected to the top and bottom ends of the lower line, respectively, via vias.

[0120] Furthermore, in the display system 1B, clock lines WCL1 and WCL5 are arranged such that the lower line of clock line WCL1 intersects with the upper line of clock line WCL5, and the upper line of clock line WCL1 intersects with the lower line of clock line WCL5.

[0121] <Effects> In the second embodiment described above, the display system 1B further comprises first clock lines WCL1 to WCL4 that supply first clocks CLK1 to CLK4 to the first drive circuit, and second clock lines WCL5 to WCL8 that supply second clocks CLK5 to CLK8 to the second drive circuit. In the display system 1B, the first drive circuit either supplies charge to or extracts charge from the first image element according to the alternation of the first clocks CLK1 to CLK4. Furthermore, in the display system 1B, the second drive circuit either supplies charge to or extracts charge from the second image element according to the alternation of the second clocks CLK5 to CLK8. In addition, in the display system 1B, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are arranged to intersect each other at regular intervals.

[0122] According to the configuration shown in Figure 5A, the display system 1B can further reduce noise emitted from the display system 1B compared to the case where the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8 do not intersect, because the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8 intersect each other at regular intervals.

[0123] Furthermore, according to the configuration shown in Figure 5B, the display system 1B has a smaller overlap area between the upper and lower layers of the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8. Therefore, compared to the configuration shown in Figure 5A, the noise emitted from the display system 1B can be further reduced.

[0124] Furthermore, as shown in the configuration in Figure 5C, the display system 1B uses the upper layer only in a portion of the area where the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8 intersect. Therefore, compared to the configurations shown in Figures 5A and 5B, variations in electrical characteristics (wiring resistance) due to differences between the upper and lower layers can be reduced.

[0125] ---Third Embodiment--- Next, a third embodiment will be described.

[0126] Figure 8 is a timing chart showing an example of the potential transition of clocks CLK1 to CLK8 in the display system 1C according to the third embodiment. In the display system 1C, the gate signal VG output from the drive circuit DRV connected to the next stage in the shift register 201 is input to the reset terminal R of the drive circuit DRV in the gate driver circuit 20 (not shown). The display system 1C is the same as the display system 1A in the first embodiment, except that the phase difference of clocks CLK1 to CLK8 is different and the drive circuit DRV that outputs the gate signal VG input to the reset terminal R of the drive circuit DRV is different, so the explanation of the similar parts is omitted.

[0127] At time t81, the control circuit 40 transitions the potential of clock CLK1 from a low level to a high level, transitions the potential of clock CLK4 from a high level to a low level, and further transitions the potential of clock CLK7 from a low level to a high level.

[0128] At time t82, the control circuit 40 transitions the potential of clock CLK2 from a low level to a high level, transitions the potential of clock CLK5 from a high level to a low level, and further transitions the potential of clock CLK8 from a low level to a high level.

[0129] At time t83, the control circuit 40 transitions the potential of clock CLK3 from a low level to a high level, and also transitions the potential of clock CLK6 from a high level to a low level.

[0130] At time t84, the control circuit 40 transitions the potential of clock CLK1 from a high level to a low level, transitions the potential of clock CLK4 from a low level to a high level, and further transitions the potential of clock CLK7 from a high level to a low level.

[0131] At time t85, the control circuit 40 transitions the potential of clock CLK2 from a high level to a low level, transitions the potential of clock CLK5 from a low level to a high level, and further transitions the potential of clock CLK8 from a high level to a low level.

[0132] At time t86, the control circuit 40 transitions the potential of the clock CLK3 from a high level to a low level, and the clock CLK 6 The potential is transitioned from a low level to a high level.

[0133] From time t87 onward, the control circuit 40 transitions the potentials of clocks CLK1 to CLK8 in the same manner as from time t81 to time t86.

[0134] <Effects> In the third embodiment described above, in the display system 1C, multiple drive circuits DRV (first drive circuits) are connected alternately in series, and each holds the information indicated by the gate signals (VG1, VG5, ... VGn-7) output from the first drive circuit connected to the preceding stage, and outputs gate signals (VG5, VG9, ... VGn-3) containing the information held in the first period to the first drive circuit connected to the next stage. Furthermore, in the display system 1C, multiple drive circuits DRV (second drive circuits) are connected alternately in series, and each second drive circuit holds the information indicated by the gate signals (VG4, VG8, ... VGn-4) output from the second drive circuit connected to the preceding stage, and outputs gate signals (VG8, VG12, ... VGn) containing the information held in the third period to the second drive circuit connected to the next stage.

[0135] In this configuration, the first drive circuits are connected in series with each other, and the second drive circuits are connected in series with each other. Furthermore, the period during which the first drive circuits supply and extract charge to the first image element overlaps with the period during which the second drive circuits extract and supply charge to the second image element. Because the connection systems of the first drive circuits and the second drive circuits are different, the display system 1C can have a larger time margin for initializing the information held by the first drive circuits and the information held by the second drive circuits.

[0136] ---Fourth Embodiment--- Next, a fourth embodiment will be described.

[0137] <Structure> Figure 9A is a cross-sectional view showing a display system 1D according to the fourth embodiment. As shown in Figure 9A, the display system 1D further comprises a drive coil 13, a position detector 14, and a position indicator 50.

[0138] The drive coil 13 transmits a signal having a predetermined frequency to the position indicator 50 for detecting the position of the position indicator 50. The drive coil 13 is provided in a planar manner on the back side of the display device 10 such that, when the display system 1D is viewed from the display surface side, it includes at least the area of ​​the display surface of the display module 11.

[0139] The position indicator 50 is a pointing device that indicates a predetermined position in the display module 11. The position indicator 50 is composed of a resonant circuit 51 which consists of an inductive element such as a coil and a capacitive element such as a capacitor. The position indicator 50 transmits the predetermined position in the display module 11 to the position detector 14 by causing the resonant circuit 51 to resonate in response to a signal transmitted from the drive coil 13 and transmitting the resonant signal generated by this resonance to the position detector 14.

[0140] The position detector 14 is, for example, an electromagnetic induction (EMR) sensor, and detects a predetermined position in the display module 11 indicated by the position indicator 50 by receiving a resonant signal transmitted from the position indicator 50. The position detector 14 is configured to include a plurality of electromagnetic induction type detection coils that are provided planarly on the display surface side of the display device 10 so as to include at least the range of the display surface of the display module 11 when the display system 1D is viewed from the display surface side. The position detector 14 detects the position of the detection coil with the highest level of received signal as the predetermined position in the display module 11 indicated by the position indicator 50.

[0141] Figure 10 is a graph showing the relationship between the alternation of clocks CLK1 and CLK5 in the display system 1D and the electromotive force generated in the position detector 14.

[0142] At time t101, the control circuit 40 transitions the potential of clock CLK1 from a low level to a high level. Consequently, the current ICLK1 flowing through clock line WCL1 rises sharply, then gradually decreases and returns to zero. ICLK1 As the value of changes, the electromotive force dI / dt(CLK1) generated in the detection coil of the position detector 14 changes in the order of decreasing, increasing, decreasing, and then returning to 0.

[0143] At time t102, the control circuit 40 transitions the potential of the clock CLK5 from a high level to a low level. Consequently, the current ICLK5 flowing through the clock line WCL5 drops sharply, then rises slowly and returns to zero. Also, as shown in graph g1, the current flowing through the clock line WCL5 ICLK5 As the value of changes, the electromotive force dI / dt(CLK5) generated in the detection coil of the position detector 14 changes in the order of rising, falling, rising, and then returning to 0.

[0144] Graph g2 shows the electromotive force generated in the detection coil of the position detector 14 when the rising edge timing of clock CLK1 (time t101) and the falling edge timing of clock CLK5 (time t102) are closer together, compared to graph g1. Furthermore, graph g3 shows the electromotive force generated in the detection coil of the position detector 14 when the rising edge timing of clock CLK1 (time t101) and the falling edge timing of clock CLK5 (time t102) are closer together, compared to graph g2.

[0145] Furthermore, the right side of Figure 10 shows the electromotive force, which is the sum of the electromotive force generated in the detection coil by the rising edge of clock CLK1 and the electromotive force generated in the detection coil by the falling edge of clock CLK1.

[0146] As shown in Figure 10, it can be seen that as the rising edge timing of clock CLK1 (time t101) and the falling edge timing of clock CLK5 (time t102) approach, the electromotive force generated in the detection coil by the alternation of clocks CLK1 and CLK5 decreases.

[0147] <Effects> In the fourth embodiment described above, the display system 1D further comprises a position indicator 50 having a resonant circuit 51, a drive coil 13 for supplying power to the position indicator 50, and a position detector 14 having an electromagnetic induction type detection coil for detecting the position indicated by the position indicator 50.

[0148] According to this configuration, the display system 1D supplies charge to the first image element, and at least a portion of the magnetic field noise emitted from the display system 1D during the first period is used to draw charge from the second image element. four During the period, magnetic field noise emitted from the display system 1D cancels out the charge, and furthermore, at least a portion of the magnetic field noise emitted from the display system 1D during the second period, which extracts charge from the first image element, supplies charge to the second image element. three During this period, the magnetic field noise emitted from the display system 1D cancels it out. Therefore, by reducing the magnetic field noise, the display system 1D can improve the accuracy of position detection of the position indicator 50 by the position detector 14.

[0149] In the fourth embodiment, the gate driver circuit 20 is located between the position detector 14 and the drive coil 13, and on the side of the display device 10. In the display system 1D, the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8 are located between the position detector 14 and the drive coil 13, and on the side of the gate driver circuit 20 opposite to the display device 10. In the display system 1D, the position detector 14 is located on the display side of the display device 10, relative to the display device 10, the gate driver circuit 20, the first clock lines WCL1-WCL4, and the second clock lines WCL5-WCL8. Furthermore, in the display system 1D, the drive coil 13 is located on the back side of the display device 10, relative to the display device 10, the gate driver circuit 20, the first clock lines WCL1-WCL4, and the second clock lines WCL5-WCL8.

[0150] According to this configuration, the display system 1D uses magnetic field noise generated by the first clock lines WCL1-WCL4 and the second clock lines WCL5-WCL8 near the side of the gate driver circuit 20. reduction By doing so, the accuracy of position detection of the position indicator 50 near the side of the gate driver circuit 20 in the position detector 14 can be improved.

[0151] ---Fifth Embodiment--- Next, a fifth embodiment will be described.

[0152] <Structure> Figure 9B is a cross-sectional view showing the arrangement of the display system 1E when the display system 1E is equipped with a touch sensor 15. As shown in Figure 9B, the display system 1E further comprises a touch sensor 15 and a stylus 60.

[0153] The touch sensor 15 detects the position of the stylus 60 or finger 61 when the stylus 60 or finger 61 touches or approaches the touch sensor 15. The touch sensor 15 is configured to include a plurality of detection electrodes that are provided planarly on the display surface side of the display device 10 so as to include at least the area of ​​the display surface of the display module 11 when the display system 1E is viewed from the display surface side. The touch sensor 15 detects the position of the detection electrode with the highest level of received signal as a predetermined position on the display module 11 that the stylus 60 or finger 61 is pointing to.

[0154] The stylus 60 is a pointing device for indicating a predetermined position on the touch sensor 15. The stylus 60 operates when it receives a signal transmitted from the detection electrode of the touch sensor 15, and transmits position information to the touch sensor 15 by transmitting a signal to the detection electrode from the tip of the stylus 60 to indicate the position.

[0155] <Effects> In the fifth embodiment described above, the display device 10 has a touch sensor 15 in which a plurality of detection electrodes are arranged in a planar manner. Furthermore, in the display system 1E, the gate driver circuit 20 is located on the side of the display device 10 and on the back side of the touch sensor 15. In addition, in the display system 1E, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are located on the back side of the touch sensor 15 and on the side of the gate driver circuit 20 opposite to the display device 10. Furthermore, in the display system 1E, the touch sensor 15 is located on the display side of the display device 10 with respect to the display device 10, the gate driver circuit 20, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8.

[0156] According to this configuration, the display system 1E supplies charge to the first image element, and at least a portion of the electric field noise emitted from the display system 1E during the first period is used to draw charge from the second image element. fourDuring the period, the electric field noise emitted from the display system 1E cancels out the electric field noise, and furthermore, at least a portion of the electric field noise emitted from the display system 1E during the second period, which extracts charge from the first image element, supplies charge to the second image element. three During this period, the electric field noise emitted from the display system 1E cancels it out. Therefore, by reducing the electric field noise, the display system 1E can improve the accuracy of position detection of the stylus 60 or finger 61 by the touch sensor 15.

[0157] ---Revised Version--- It should be noted that the present invention is not limited to the embodiments described above. That is, any design modifications made to the above embodiments by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. Furthermore, the elements of the above embodiments and the modifications described later can be combined to the extent that it is technically possible, and any combination thereof is also included within the scope of the present invention, as long as it retains the features of the present invention.

[0158] For example, in the above embodiment, the gate driver circuit 20 is provided on one side of the display device 10, but it is not limited to this. For example, the gate driver circuit 20 may be provided on both sides of the display device 10.

[0159] With this configuration, the display system 1 can reduce noise when the gate driver circuit 20 is located on both sides of the display device 10.

[0160] Furthermore, although eight clock lines WCL are provided in the above embodiment, the number of clock lines WCL is not limited to eight; any number of lines may be provided.

[0161] With this configuration, the display system 1 can reduce noise regardless of the number of clock lines (WCL). [Explanation of Symbols]

[0162] 1A…Display system, 10…Display device, 20…Driver circuit, DRV…Drive circuit, 110…Image element, GL…Row signal line, SL…Column signal line

Claims

1. A display device comprising: a plurality of column signal lines arranged horizontally; a plurality of first row signal lines and a plurality of second row signal lines arranged vertically; a plurality of first image elements positioned at the intersections of the first row signal lines and the column signal lines; and a plurality of second image elements positioned at the intersections of the second row signal lines and the column signal lines. A driver circuit comprising: a plurality of first drive circuits provided for each first row signal line, which drive the first image element in accordance with the alternation of a first clock supplied to the corresponding first row signal line; and a plurality of second drive circuits provided for each second row signal line, which drive the second image element in accordance with the alternation of a second clock supplied to the corresponding second row signal line and having the opposite phase to the first clock, wherein the first drive circuits and the second drive circuits are each alternately connected in series. Equipped with, The first drive circuit supplies charge to the first image element during a first period, and extracts charge from the first image element during a second period different from the first period. The second drive circuit supplies charge to the second image element during a third period that overlaps at least a portion with the second period, or extracts charge from the second image element during a fourth period that overlaps at least a portion with the first period. The first drive circuit holds information indicated by the signal output from the second drive circuit connected to the preceding stage, and outputs a signal containing the information held during the first period to the second drive circuit connected to the next stage. The second drive circuit holds information indicated by the signal output from the first drive circuit connected to the preceding stage, and outputs a signal containing the information held during the third period to the first drive circuit connected to the next stage. The first drive circuit initializes the information it holds after the operation of the second drive circuit which is connected to the next stage, The second drive circuit initializes the information it has held since the operation of the first drive circuit which is connected to the next stage and beyond. Display system.

2. The first drive circuit initializes the information it holds in accordance with the signal output from the first drive circuit connected to the next stage and beyond, The second drive circuit initializes the information it holds according to the signal output from the second drive circuit connected to the next stage and beyond. The display system according to claim 1.

3. A first clock line that supplies the first clock to the first drive circuit, A second clock line that supplies the second clock to the second drive circuit, Furthermore, The first drive circuit performs either supplying or withdrawing charge to the first image element in accordance with the alternation of the first clock. The second drive circuit performs either supplying or withdrawing charge to the second image element in accordance with the alternation of the second clock. The first clock line and the second clock line are arranged parallel to and adjacent to each other. The display system according to claim 1.

4. A first clock line that supplies the first clock to the first drive circuit, A second clock line that supplies the second clock to the second drive circuit, Furthermore, The first drive circuit performs either supplying or withdrawing charge to the first image element in accordance with the alternation of the first clock. The second drive circuit performs either supplying or withdrawing charge to the second image element in accordance with the alternation of the second clock. The first clock line and the second clock line are arranged so as to intersect each other at regular intervals. The display system according to claim 1.

5. A position indicator having a resonant circuit, A drive coil for supplying power to the position indicator, A position detector having an electromagnetic induction type detection coil for detecting the position indicated by the position indicator, The display system according to claim 3 or 4, further comprising:

6. The driver circuit is located between the position detector and the drive coil, and on the side of the display device. The first clock line and the second clock line are located between the position detector and the drive coil, and on the side of the driver circuit opposite to the display device. The position detector is positioned on the display side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line. The drive coil is positioned on the back side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line. The display system according to claim 5.

7. The display device has a touch sensor in which a plurality of detection electrodes are arranged in a planar manner. The display system according to claim 3 or 4.

8. The driver circuit is located on the side of the display device and on the back of the touch sensor. The first clock line and the second clock line are located on the back side of the touch sensor and on the side of the driver circuit opposite to the display device. The touch sensor is positioned on the display surface side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line. The display system according to claim 7.

9. A driver circuit for driving the first image elements and the second image elements in a display device having a plurality of column signal lines arranged horizontally, a plurality of first row signal lines and a plurality of second row signal lines arranged vertically, a plurality of first image elements positioned at the intersections of the first row signal lines and the column signal lines, and a plurality of second image elements positioned at the intersections of the second row signal lines and the column signal lines, A plurality of first drive circuits are provided for each of the first row signal lines and drive the first image element in accordance with the alternation of the first clock supplied to the corresponding first row signal line, A plurality of second drive circuits are provided for each of the second row signal lines and drive the second image element according to the alternation of a second clock supplied to the corresponding second row signal line and having a phase opposite to that of the first clock, Equipped with, The first drive circuit and the second drive circuit are connected alternately in series, The first drive circuit supplies charge to the first image element during a first period, and extracts charge from the first image element during a second period different from the first period. The second drive circuit supplies charge to the second image element during a third period that overlaps at least a portion with the second period, or extracts charge from the second image element during a fourth period that overlaps at least a portion with the first period. The first drive circuit holds information indicated by the signal output from the second drive circuit connected to the preceding stage, and outputs a signal containing the information held during the first period to the second drive circuit connected to the next stage. The second drive circuit holds information indicated by the signal output from the first drive circuit connected to the preceding stage, and outputs a signal containing the information held during the third period to the first drive circuit connected to the next stage. The first drive circuit initializes the information it holds after the operation of the second drive circuit which is connected to the next stage, The second drive circuit initializes the information it has held since the operation of the first drive circuit which is connected to the next stage and beyond. Driver circuit.

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