Memory system and method for controlling the memory system

Abstract

The present invention provides a memory system and a control method for the memory system that can reduce the circuit size used for decoding error correction codes. [Solution] The memory system 1 according to the embodiment includes a non-volatile memory 20 that stores data encoded with an error correction code that corrects errors of t bits (where t is an integer of 2 or more), and a memory controller 10. The memory controller 10 uses the received word read from the non-volatile memory 20 to process k (where k is 1 ≤ k).

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a memory system and a method for controlling the memory system. [Background technology]

[0002] In memory systems, data encoded with error correction codes is generally stored so that errors can be detected and corrected if they occur in the stored data. Therefore, when reading data stored in a memory system, decoding of the data encoded with error correction codes is performed.

[0003] Error correction codes include BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes. Among these, BCH code decoding methods include the PGZ (Peterson-Gorenstein-Zierler) method and the BM (Berlekamp-Massey) method. The PGZ method, also known as the Peterson method, solves a system of equations between the coefficients of the error location polynomial and the syndrome by calculating the determinant. The BM method solves a system of equations between the coefficients and the syndrome sequentially using two polynomials. There is also the ri (Reformulated Inversionless) BM method, which can speed up the BM method. Furthermore, a relay-type BM method, combining the PGZ and BM methods, has been proposed to improve latency in BCH code decoding. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 11831335 [Non-patent literature]

[0005] [Non-Patent Document 1] Dilip V. Sarwate and Naresh R. Shanbhag, "High-Speed ​​Architectures for Reed-Solomon Decoders", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.9, NO.5, OCTOBER 2001 pp.641-655. [Overview of the project] [Problems that the invention aims to solve]

[0006] Traditionally, a problem has been the large size of the circuits used to decode error correction codes.

[0007] Embodiments of the present invention aim to provide a memory system and a method for controlling the memory system that can reduce the scale of the circuit used for decoding error correction codes. [Means for solving the problem]

[0008] The memory system according to the embodiment includes a non-volatile memory that stores data encoded with an error correction code for correcting errors of t bits or less (t is an integer of 2 or more), and a memory controller that controls writing to the non-volatile memory and reading from the non-volatile memory. The memory controller calculates a syndrome using the received word read from the non-volatile memory, and executes a first calculation for obtaining a first error position polynomial of a degree in which the parity matches k among error position polynomials from the first to the k-th (k is an integer satisfying 1 ≦ k < t) using the syndrome. The memory controller determines whether it is possible to calculate the error position using the first error position polynomial. When the memory controller determines that it is possible to calculate the error position using the first error position polynomial, the memory controller calculates the error position using the first error position polynomial. When the memory controller determines that it is not possible to calculate the error position using the first error position polynomial, the memory controller obtains an initial value of a parameter used in a second calculation for obtaining a second error position polynomial up to the t-th degree using the first error position polynomial, executes the second calculation using the initial value, and calculates the error position using the second error position polynomial obtained by the second calculation. The memory controller corrects an error in the received word at either the error position calculated using the first error position polynomial or the error position calculated using the second error position polynomial.

Brief Description of Drawings

[0009] [Figure 1] FIG. 1 is a block diagram of a memory system according to the first embodiment. [Figure 2] FIG. 2 is a block diagram of a decoding unit according to the first embodiment. [Figure 3] FIG. 3 is a block diagram of an error position polynomial calculation unit according to the first embodiment. [Figure 4] FIG. 4 is a block diagram of a selector circuit included in the determination unit according to the first embodiment. [Figure 5] FIG. 5 is a block diagram of a parameter creation unit according to the first embodiment. [Figure 6] FIG. 6 is a block diagram of an auxiliary polynomial calculation unit according to the first embodiment. [Figure 7] Figure 7 is a block diagram of the difference value calculation unit according to the first embodiment. [Figure 8] Figure 8 is a flowchart of the decoding process according to the first embodiment. [Figure 9] Figure 9 is a block diagram of the error location polynomial calculation unit for the comparative example. [Figure 10] Figure 10 is a block diagram of the parameter creation section for the comparative example. [Figure 11] Figure 11 is a block diagram of the error location polynomial calculation unit according to the second embodiment. [Figure 12] Figure 12 is a block diagram of the parameter creation unit according to the second embodiment. [Figure 13] Figure 13 is a block diagram of the difference value calculation unit according to the second embodiment. [Modes for carrying out the invention]

[0010] Embodiments will be described with reference to the drawings. In the drawings described below, identical or similar parts are denoted by the same or similar reference numerals and their descriptions are omitted. The drawings are schematic.

[0011] Furthermore, the embodiments described below are illustrative examples of apparatus and methods for realizing the technical idea, and do not specify the material, shape, structure, arrangement, etc., of each component. Various modifications can be made to these embodiments within the scope of the claims.

[0012] (First embodiment) First, a memory system according to the first embodiment will be described with reference to the drawings. Figure 1 is a block diagram showing an example configuration of the memory system 1 according to the first embodiment. The memory system 1 comprises a memory controller 10 and a non-volatile memory 20. The memory system 1 may be a storage device such as a Storage Class Memory (SCM), an SSD (Solid State Drive), or a USB (Universal Serial Bus) memory. The memory system 1 is connectable to a host 30, and Figure 1 shows the system connected to the host 30. The host 30 may be an electronic device such as a personal computer or a mobile terminal.

[0013] Non-volatile memory 20 is memory that retains data even without a power supply. In the following explanation, NAND flash memory is used as an example of non-volatile memory 20. However, other storage devices such as MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and ReRAM (Resistive Random Access Memory) may also be used as non-volatile memory 20.

[0014] The memory controller 10 is a semiconductor integrated circuit configured, for example, as a System On a Chip (SoC). The memory controller 10 comprises a control unit 11, a data buffer 12, a memory interface (I / F) 13, an encoding / decoding unit 14, and a host interface 15. The control unit 11, data buffer 12, memory interface 13, encoding / decoding unit 14, and host interface 15 are interconnected by an internal bus 16. The memory controller 10 can control writing to the non-volatile memory 20 in accordance with write requests from the host 30. The memory controller 10 can also control reading from the non-volatile memory 20 in accordance with read requests from the host 30.

[0015] The host I / F 15 is connected to the host 30 and the internal bus 16. It performs processing according to the interface standard between the host 30 and the host 30, and outputs commands received from the host 30, user data to be written, etc., to the internal bus 16. The host I / F 15 also transmits user data read and restored from the non-volatile memory 20, responses from the control unit 11, etc., to the host 30.

[0016] The control unit 11 comprehensively controls each component of the memory system 1 via the internal bus 16. The control unit 11 may be, for example, a CPU (Central Processing Unit), or a logic circuit specially synthesized using RTL (register transfer level), etc. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control according to that instruction. For example, the control unit 11 instructs the memory I / F 13 to write the codeword, which encodes user data, to the non-volatile memory 20, according to an instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read the received word, which is stored or transmitted, from the non-volatile memory 20, according to an instruction from the host 30. Furthermore, when the control unit 11 receives a write request or read request from the host 30, it converts the logical address received from the host 30 into a physical address indicating a storage area on the non-volatile memory 20 and instructs the memory I / F 13 to do so.

[0017] The memory interface 13 is connected to the encoding / decoding unit 14, the internal bus 16, and the non-volatile memory 20. Based on instructions from the control unit 11, it is a circuit that performs write operations to the non-volatile memory 20 and read operations from the non-volatile memory 20.

[0018] The data buffer 12 is connected to the internal bus 16 and temporarily stores user data received from the host 30 by the memory controller 10 until it is stored in the non-volatile memory 20. The data buffer 12 also temporarily stores user data read from the non-volatile memory 20 and restored until it is sent to the host 30.

[0019] The encoding / decoding unit 14 comprises an encoding unit 17 and a decoding unit 18, and is connected to the internal bus 16 and the memory I / F 13. The encoding / decoding unit 14 encodes user data stored in the non-volatile memory 20 to generate codewords. As encoding methods, for example, encoding methods using algebraic codes such as BCH codes and RS codes, and encoding methods such as product codes that use these codes as row and column component codes can be employed. The encoding / decoding unit 14 also decodes the received codewords read from the non-volatile memory 20 to restore the user data.

[0020] When writing to the non-volatile memory 20 of memory system 1, the encoding and writing of user data are performed as follows.

[0021] When writing to the non-volatile memory 20, the control unit 11 instructs the encoding unit 17 to encode the user data and instructs the memory interface 13 to write the codeword. Based on the instructions from the control unit 11, the encoding unit 17 encodes the user data on the data buffer 12 and generates a codeword. The memory interface 13 controls the writing of the codeword to the storage location on the non-volatile memory 20 as instructed by the control unit 11.

[0022] Furthermore, when reading from the non-volatile memory 20 of the memory system 1, the reading of the received word and the restoration of user data are performed as follows.

[0023] When reading from the non-volatile memory 20, the control unit 11 instructs the memory interface 13 to read the received word and also instructs the decoding unit 18 to decode it. The memory interface 13 reads the received word from the specified address in the non-volatile memory 20 according to the instructions of the control unit 11 and inputs the read received word to the decoding unit 18. The decoding unit 18 decodes the received word read from the non-volatile memory 20 to restore the user data and outputs the user data to the internal bus 16.

[0024] In the following explanation, we will use a BCH code that corrects errors of t bits or less (where t is an integer greater than or equal to 2) as the error correction code, and a relay-type BM method that combines the PGZ method and the BM method as the decoding method.

[0025] Figure 2 is a block diagram of the decoding unit 18 of the memory system 1 according to the first embodiment.

[0026] The decoding unit 18 includes a buffer 181, a syndrome calculation unit 182, an error location polynomial calculation unit 183, an error sequence calculation unit 184, and an error correction unit 185. The decoding unit 18 receives a received word r(x) read from the non-volatile memory 20 as input, decodes the received word r(x), restores the corrected user data y(x), and outputs it. The decoding unit 18 performs the decoding of the BCH code as follows (a) to (e).

[0027] (a) The received word r(x) read from the non-volatile memory 20 is held in the buffer 181 and input to the syndrome calculation unit 182.

[0028] (b) The syndrome calculation unit 182 calculates the syndromes S1, S2, ..., S from the received word r(x). 2t-2 S 2t-1 The following is calculated. Although not shown in detail in Figure 2, the decoding unit 18 determines whether all syndrome values ​​are 0, and if all syndrome values ​​are 0, it determines that there is no error in the received word r(x) and can terminate the decoding process. Syndrome S1, S2, ..., S 2t-2 S 2t-1 However, this is input to the error location polynomial calculation unit 183.

[0029] (c) Error position polynomial calculation unit 183 calculates syndrome S1, S2, ..., S 2t-2 S 2t-1 From this, the error location polynomial σ(x) is calculated. The method for calculating the error location polynomial σ(x) will be described later. The error location polynomial σ(x) is input to the error sequence calculation unit 184.

[0030] (d) The error sequence calculation unit 184 calculates the error sequence e(x) by calculating the roots of the error location polynomial σ(x). The process of calculating the roots of the error location polynomial σ(x) can be implemented by any method, but for example, a chien search can be used. A chien search is a method that sequentially substitutes values ​​into the error location polynomial and searches for the error location based on the value that causes the output of the error location polynomial to be 0. The error sequence e(x) is input to the error correction unit 185.

[0031] (e) The error correction unit 185 performs error correction using the received word r(x) and error sequence e(x) held in the buffer 181 and generates corrected user data y(x). The error correction unit 185 performs error correction, for example, by inverting the bits at the error positions indicated by the error sequence e(x) for the received word r(x).

[0032] Here, the total number of cycles required for the entire decoding operation, which is the sum of the number of cycles required for processing by the syndrome calculation unit 182, the error location polynomial calculation unit 183, the error sequence calculation unit 184, and the error correction unit 185, is called the decoding latency. Generally, the cycles required for processing by the error location polynomial calculation unit 183 account for a large proportion of the decoding latency. In contrast, in the error location polynomial calculation unit 183 in the first embodiment, the decoding latency is reduced by using the relay-type BM method, as will be described later.

[0033] Figure 3 is a block diagram of the error location polynomial calculation unit 183 in the decoding unit 18 according to the first embodiment. The error location polynomial calculation unit 183 comprises a PGZ method calculation unit 183a, a parameter creation unit 183b, a BM method calculation unit 183c, and a selection unit 183d.

[0034] The relay-type BM method calculates the first error-location polynomial of the lowest degree among the t error-location polynomials of the first to t-th order corresponding to errors from 1 bit to t bits, as the first calculation, using the PGZ method that allows parallel processing and is fast. Here, the lowest degree refers to the degrees from the first to the k-th order (k is an integer satisfying 1 ≤ k < t) where the increase in the calculation amount is suppressed. By calculating the first error-location polynomial of the lowest degree using the PGZ method, the decoding latency can be reduced. Also, the relay-type BM method calculates the second error-location polynomials from the degree greater than k to the t-th order, as the second calculation, using the BM method with a small calculation amount and a small circuit scale.

[0035] Here, the degree k is determined in advance according to the calculation amount and the like. Below, taking the case of k = 4 as an example, a BCH code that corrects errors of 10 bits (t = 10) or less will be described. The error-location polynomial calculation unit 183 according to the first embodiment calculates the first error-location polynomial up to the fourth order in the PGZ method calculation unit 183a, and calculates the second error-location polynomials from the degree greater than the fourth order to the tenth order in the BM method calculation unit 183c.

[0036] The circuit included in the PGZ method calculation unit 183a in FIG. 3 will be described. The PGZ method calculation unit 183a includes a second-order error-location polynomial calculation circuit 183a1, a second-order error-location polynomial constraint condition check circuit 183a2, a fourth-order error-location polynomial calculation circuit 183a3, and a fourth-order error-location polynomial constraint condition check circuit 183a4.

[0037] Regarding the second-order error-location polynomial calculation circuit 183a1 and the fourth-order error-location polynomial calculation circuit 183a3, generalizing the degree to a natural number N, it becomes an N-th order error-location polynomial calculation circuit. The N-th order error-location polynomial calculation circuit outputs the first error-location polynomial σ 2t-2 , S 2t-1 with respect to syndromes S1, S2, ···, S N shown by the following formula (1). <​​​​​​ Furthermore, the second-order error location polynomial constraint check circuit 183a2 and the fourth-order error location polynomial constraint check circuit 183a4 are generalized to a natural number N, resulting in an N-order error location polynomial constraint check circuit. The N-order error location polynomial constraint check circuit is the first error location polynomial σ N For syndrome S1, ..., the system checks whether the error location polynomial constraint condition expressed by equation (2) below is true (True: T) or false (False: F), and determines whether the error location can be calculated. The Nth-order error location polynomial constraint check circuit determines that the error location can be calculated using the first Nth-order error location polynomial when equation (2) is true.

number

[0039] The Nth-order error location polynomial constraint check circuit uses a flag signal f to indicate whether or not it has determined that the error location can be calculated using the first Nth-order error location polynomial. N And the first error position polynomial σ N Outputs the flag signal f. N When equation (2) is true, f N =1, when false, f N = 0.

[0040] Some or all of the calculations performed by the quadratic error location polynomial calculation circuit 183a1 and the quartic error location polynomial calculation circuit 183a3 may be performed in parallel. Furthermore, some or all of the calculations performed by the quadratic error location polynomial constraint check circuit 183a2 and the quartic error location polynomial constraint check circuit 183a4 may also be performed in parallel. Parallel execution makes it possible to reduce the decoding latency.

[0041] Generally, the circuit size of the error location polynomial constraint check circuit in the PGZ method is large. Therefore, the PGZ method calculation unit 183a according to the first embodiment reduces the circuit size by performing the calculation and check only for orders where k is even or odd, rather than calculating the error location polynomial and checking the error location polynomial constraint for all orders from 1 to k.

[0042] In Figure 3, the PGZ method calculation unit 183a according to the first embodiment calculates the error location polynomial and checks the error location polynomial constraints for the second and fourth orders, where k is even or odd, for the highest order k=4 calculated using the PGZ method. The circuit size is reduced by removing the first and third order error location polynomial calculation circuits and error location polynomial constraint check circuits. The method for restoring or replacing the functions performed by the removed first and third order error location polynomial calculation circuits and error location polynomial constraint check circuits will be described later.

[0043] The PGZ method calculation unit 183a outputs flag signals f2 and f4, and the first error position polynomial σ 2 , σ 4 This is input to the selection unit 183d. The selection unit 183d includes selector circuits 183d1 and 183d2. To explain the operation of the selection unit 183d, first, the operation of the selector circuits used in the selection unit 183d will be explained.

[0044] Figure 4 is a block diagram of the selector circuit 183d1 used in the selection unit 183d. The selector circuit 183d1 receives the flag signal f i ,f j and error position polynomial σ i , σ j The input signal f and the error position polynomial σ are output. Here, i and j are integers greater than or equal to 1. The relationship between the input signal and the output signal is shown in the table in Figure 4. Flag signal f i When = 1, i.e., T, the flag signal f i The error position polynomial σ is output as the flag signal f. i It outputs the error position polynomial σ. Flag signal f iWhen = 0, i.e., F, the flag signal f j The error position polynomial σ is output as the flag signal f. j It outputs the incorrect position polynomial σ.

[0045] The selector circuit 183d2 used in the selection unit 183d is different from the selector circuit 183d1 in that it controls the flag signal f i ,f j The difference lies in the fact that a flag signal f is input, but no flag signal f is output. When the flag signal f=1, i.e., T, the selector circuit 183d2 is the error position polynomial σ i The error location polynomial σ is output, and when the flag signal f=0, i.e., F, the error location polynomial σ j It outputs the error position polynomial σ. Selector circuit 183d2 is equivalent to selector circuit 183d1 with fewer input and output signals, so its block diagram is omitted.

[0046] Returning to the explanation of Figure 3, the selector circuit 183d1 of the selection unit 183d is configured to receive flag signals f2 and f4 and the first error position polynomial σ 2 , σ 4 The input is received, and the flag signal f and the first error location polynomial σP are output. As described above, the selector circuit 183d1 selects either the flag signal f2 or f4 according to the table in Figure 4 and outputs it as the flag signal f, and the first error location polynomial σ 2 , σ 4 Select one of the following and output it as the first error location polynomial σP.

[0047] The selector circuit 183d2 of the selection unit 183d receives a flag signal f, a first error location polynomial σP, and a second error location polynomial σB as inputs, and outputs an error location polynomial σ(x). When the flag signal f=1, i.e., T, it means that it has been determined that the error location can be calculated using either the second-order or fourth-order first error location polynomial calculated by the PGZ method calculation unit 183a, and the first error location polynomial σP is output as the error location polynomial σ(x). When the flag signal f=0, i.e., F, it means that it has been determined that the error location cannot be calculated using either the second-order or fourth-order first error location polynomial calculated by the PGZ method calculation unit 183a. In this case, the second error location polynomial σB, calculated by the BM method calculation unit 183c as described later, is output as the error location polynomial σ(x).

[0048] Here, if the PGZ method calculation unit 183a determines that the error location can be calculated using the PGZ method, the first-order and third-order error location polynomials can be replaced with second-order and fourth-order error location polynomials, respectively, as follows.

[0049] If it is determined that the error location can be calculated using the PGZ method, the first error location polynomial σP output from the selection unit 183d is σ 1 from σ 4 It is the one that is not 0 and has the highest degree. 3rd order error position polynomial σ 3 If it is not 0 and has the highest degree, then it is the third-order error position polynomial σ 3 =σ0 3 / σ0 4 ×σ 4 (Here, the coefficient σ0 3 , σ0 4 These are the error location polynomials σ, respectively. 3 The coefficient of the 0th order, error position polynomial σ 4 This is the coefficient of the 0th order. ) holds. Therefore, the 3rd order error position polynomial σ 3 This is the fourth-order error position polynomial σ 4 It can be replaced by the first-order error position polynomial σ. 1 If it is not 0 and has the highest degree, then it is the first-order error position polynomial σ 1 =σ0 1 / σ0 2 ×σ 2 (Here, the coefficient σ0 1 , σ0 2 These are the error location polynomials σ, respectively. 1 The coefficient of the 0th order, error position polynomial σ 2 This is the coefficient of the 0th order. ) holds. Therefore, the 1st order error position polynomial σ 1 This is the second-order error position polynomial σ 2 It can be replaced by this.

[0050] If the PGZ method calculation unit 183a obtains a first error location polynomial that can calculate the error location, the subsequent processing by the parameter creation unit 183b and the BM method calculation unit 183c can be omitted. For example, the parameter creation unit 183b may be configured to start processing only if no information indicating that the selection unit 183d has obtained a first error location polynomial that can calculate the error location is output.

[0051] Next, the parameter creation unit 183b in Figure 3 will be described. The parameter creation unit 183b functions as an interface that converts the calculation results of the PGZ method calculation unit 183a into information used in the calculation of the BM method calculation unit 183c when it is determined that the error location cannot be calculated using the first error location polynomial calculated by the PGZ method calculation unit 183a. For example, when it is determined that the error location cannot be calculated using the second-order and fourth-order first error location polynomials calculated by the PGZ method calculation unit 183a, the parameter creation unit 183b uses the second-order and fourth-order first error location polynomials to determine the initial values ​​of the parameters used in the BM method.

[0052] To perform calculations using the BM method following calculations using the PGZ method, the parameters used in the BM method are, for example, the following: The error location polynomial C is updated by iterative processing using the BM method. Auxiliary polynomial A used to update the error location polynomial using the BM method. • Initial loop value i represents the initial number of iterations for the loop process. • The initial difference value d-bar used to update the error location polynomial using the BM method (where "d-bar" represents the letter 'd' with a bar above it).

[0053] The parameter creation unit 183b generates the first error position polynomial σ output from the PGZ method calculation unit 183a. 2 , σ 4 And the error position polynomial σ is a constant. 0 The input is used to output the initial loop value i, error location polynomial C, auxiliary polynomial A, and difference value d bars to the BM method calculation unit 183c. Error location polynomial σ 0 Since it is 1, it does not need to be calculated from syndrome S1, ... in the PGZ method calculation unit 183a. As mentioned above, the error location polynomial calculation unit 183 in the decoding unit 18 of the first embodiment does not calculate first-order and third-order error location polynomials. For this reason, the parameter creation unit 183b is set up so that information that cannot be obtained from the first-order and third-order error location polynomials can be recovered from the second-order and fourth-order error location polynomials as follows.

[0054] Figure 5 is a block diagram of the parameter creation unit 183b in the error position polynomial calculation unit 183 according to the first embodiment. The parameter creation unit 183b includes selector circuits 183b1 and 183b2, an auxiliary polynomial calculation unit 183b3, and a difference value calculation unit 183b4.

[0055] The selector circuit 183b1 uses the error position polynomial σ 0 , σ 2 , σ 4 The following is entered: Error position polynomial σ 2 The coefficient σ² is the coefficient of the second order. 2 Let σ0 be the coefficient of the 0th order. 2 It has the error position polynomial σ. 4 The coefficient σ4 is the coefficient of the fourth order. 4 Let σ0 be the coefficient of the 0th order. 4 The selector circuit 183b1 has the coefficient σ0 according to the table attached to the selector circuit 183b1 in Figure 5. 4 , σ0 2Output the initial loop value i, error location polynomial C, temporary auxiliary polynomial A_t, and temporary difference value d bar_t according to the value of, for example, σ0 4 ≠0 and σ0 2 ≠0, the initial loop value i = 4, error location polynomial C = σ 4 temporary auxiliary polynomial A_t = σ 2 x 3 temporary difference value d bar_t = σ0 4 are output.

[0056] The error location polynomial C is the error location polynomial with the largest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a. Also, the temporary auxiliary polynomial A_t is a polynomial obtained from the error location polynomial with the second largest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a.

[0057] The initial loop value i and the error location polynomial C are output from the parameter creation unit 183b and input to the BM method calculation unit 183c. The error location polynomial C and the temporary auxiliary polynomial A_t are input to the auxiliary polynomial calculation unit 183b3. The temporary difference value d bar_t is input to the difference value calculation unit 183b4.

[0058] The selector circuit 183b2 is input with the error location polynomials σ 2 σ 4 and outputs the first correction value m 4 and the second correction value m 4 σ2 2 σ0 2 according to the values of σ4 A σ0 dバー For example, when σ4 4 ]≠0 and σ0 4 ≠0 and σ2 2 ≠0 and σ0 2 ≠0, the first correction value m A = σ2 2 x, the second correction value m dバー = σ4 4 are output.

[0059] The first correction value m A the second correction value mdバー This is determined from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a. First correction value m A This is input to the auxiliary polynomial calculation unit 183b3. Second correction value m dバー This is input to the auxiliary polynomial calculation unit 183b3 and the difference value calculation unit 183b4.

[0060] Figure 6 is a block diagram of the auxiliary polynomial calculation unit 183b3 in the parameter creation unit 183b according to the first embodiment. The auxiliary polynomial calculation unit 183b3 includes multiplication circuits 183b3_1 and 183b3_2 and an addition circuit 183b3_3. The auxiliary polynomial calculation unit 183b3 takes the error position polynomial C, the provisional auxiliary polynomial A_t, and the first correction value m as input. A , second correction value m dバー The input is used to calculate and output the auxiliary polynomial A. Specifically, the auxiliary polynomial calculation unit 183b3 uses the multiplication circuit 183b3_1 to apply a first correction value m to the error position polynomial C. A Multiply by this, and the second modification value m is applied to the provisional auxiliary polynomial A_t by the multiplication circuit 183b3_2. dバー Multiply by . Then, the outputs of the multiplication circuits 183b3_1 and 183b3_2 are added together by the adder circuit 183b3_3 to calculate the auxiliary polynomial A. The auxiliary polynomial A is input to the BM method calculation unit 183c.

[0061] Figure 7 is a block diagram of the difference value calculation unit 183b4 in the parameter creation unit 183b according to the first embodiment. The difference value calculation unit 183b4 includes a multiplication circuit 183b4_1. The difference value calculation unit 183b4 calculates a provisional difference value d_bar_t and a second correction value m dバー The input is used, and the multiplication circuit 183b4_1 converts the provisional difference value d bar_t to a second correction value m dバー The difference value d-bar is calculated and output by multiplying by . The difference value d-bar is input to the BM method calculation unit 183c.

[0062] As described above, the parameter creation unit 183b according to the first embodiment can recover information that cannot be obtained from the first-order and third-order error location polynomials from the second-order and fourth-order error location polynomials, and create the initial loop value i, the error location polynomial C, the auxiliary polynomial A, and the difference value d bar.

[0063] Returning to the explanation of Figure 3, the BM method calculation unit 183c receives the initial loop value i, the error location polynomial C, the auxiliary polynomial A, and the difference value d bar from the parameter creation unit 183b, and uses these parameters to calculate the second error location polynomial σB using the BM method.

[0064] As described above, the selection unit 183d selects one of the first error location polynomial σP and the second error location polynomial σB and outputs it as the error location polynomial σ(x). In other words, if the PGZ method calculation unit 183a determines that the error location can be calculated using either the second-order or fourth-order first error location polynomial, the selection unit 183d selects the first error location polynomial σP, which was determined to be able to calculate the error location. If the PGZ method calculation unit 183a determines that the error location cannot be calculated using either the second-order or fourth-order first error location polynomial, the selection unit 183d selects the second error location polynomial σB calculated by the BM method calculation unit 183c.

[0065] The configuration and operation of the memory system 1 have been described above, and the configuration and operation of the decoding unit 18, including the error location polynomial calculation unit 183, which is provided in the memory system 1, have been described in detail. Next, the flow of the decoding process by the memory system 1 will be summarized using a flowchart. Figure 8 is a flowchart of an example of the decoding process in the first embodiment.

[0066] In step S101, the control unit 11 instructs the memory interface 13 to read the received word from the non-volatile memory 20, and the memory interface 13 inputs the read received word r(x) to the decoding unit 18. The control unit 11 also instructs the decoding unit 18 to decode the received word r(x). In the decoding unit 18, the received word r(x) is held in the buffer 181.

[0067] In step S102, the syndrome calculation unit 182 of the decoding unit 18 calculates the syndromes S1, S2, ..., S from the received word r(x). 2t-2 S 2t-1 The calculation is performed. In step S103, the decoding unit 18 determines whether the calculated values ​​of all syndromes are 0.

[0068] In step S103, if all syndrome values ​​are 0, it can be determined that there is no error in the received word r(x), so the process proceeds to "Yes" and the decoding unit 18 terminates the decoding process. In step S103, if all syndrome values ​​are not 0, the process proceeds to step S104 according to "No". In step S104, the PGZ method calculation unit 183a of the error location polynomial calculation unit 183 calculates a first error location polynomial using the PGZ method, such that the highest degree k calculated by the PGZ method matches the parity.

[0069] In step S105, the PGZ method calculation unit 183a and a part of the selection unit 183d determine whether the error location can be calculated using the first error location polynomial calculated by the PGZ method. If it is determined in step S105 that the error location can be calculated, the first error location polynomial for which the error location was determined to be calculable is output as the first error location polynomial σP, and the process proceeds to step S108 according to "Yes".

[0070] If it is determined in step S105 that the error location cannot be calculated, the process proceeds to step S106 according to "No". In step S106, the parameter creation unit 183b calculates the difference value d bar with the auxiliary polynomial A using the first error location polynomial of an even / odd degree that matches k, and calculates the initial values ​​of the parameters to be used in the BM method. In step S107, the BM method calculation unit 183c calculates the second error location polynomial σB using the BM method with the calculated initial values.

[0071] In step S108, the selection unit 183d selects either the first error location polynomial σP or the second error location polynomial σB as the error location polynomial σ(x). Specifically, in step S105, if it is determined that the error location can be calculated by the first error location polynomial calculated by the PGZ method, in step S108, the selection unit 183d selects the first error location polynomial σP calculated by the PGZ method. In step S105, if it is determined that the error location cannot be calculated by the first error location polynomial calculated by the PGZ method, in step S108, the selection unit 183d selects the second error location polynomial σB calculated by the BM method.

[0072] In step S109, the error sequence calculation unit 184 searches for the error location based on the selected error location polynomial σ(x) and calculates the error sequence e(x). In step S110, the error correction unit 185 corrects the error at the error location indicated by the error sequence e(x) for the received word r(x) and ends the decoding process.

[0073] Here, to facilitate understanding of the features of the embodiments of the present invention, a memory system of a comparative example will be described. The memory system 91 of the comparative example, similar to the memory system 1 according to the first embodiment, uses a BCH code that corrects errors of t bits (t is an integer of 2 or more) or less as an error correction code, and uses the relay-type BM method for decoding. In the relay-type BM method, the memory system 91 of the comparative example calculates the first error location polynomials of low orders from the first order to the k-th order (k is an integer satisfying 1≦k<t) using the PGZ method, and calculates the second error location polynomials from the order greater than the k-th order to the t-th order using the BM method.

[0074] A block diagram showing a configuration example of the memory system 91 of the comparative example is the same as the block diagram of the memory system 1 according to the first embodiment shown in FIG. 1, so the illustration and description thereof are omitted. Also, a block diagram of the decoding unit 18 of the memory system 91 of the comparative example is the same as the block diagram of the decoding unit 18 according to the first embodiment shown in FIG. 2, so the illustration and description thereof are omitted.

[0075] Figure 9 is a block diagram of the error position polynomial calculation unit 183 in the decoding unit 18 of the comparative example memory system 91.

[0076] The PGZ method calculation unit 183a of the comparative example's error location polynomial calculation unit 183 includes a second-order error location polynomial calculation circuit 183a1, a second-order error location polynomial constraint condition check circuit 183a2, a fourth-order error location polynomial calculation circuit 183a3, and a fourth-order error location polynomial constraint condition check circuit 183a4. The PGZ method calculation unit 183a of the comparative example further includes a first-order error location polynomial calculation circuit 183a5, a first-order error location polynomial constraint condition check circuit 183a6, a third-order error location polynomial calculation circuit 183a7, and a third-order error location polynomial constraint condition check circuit 183a8.

[0077] Compared with the PGZ method calculation unit 183a of the comparative example described above, the PGZ method calculation unit 183a of the first embodiment of the present invention shown in Figure 3 differs in the following respects. The PGZ method calculation unit 183a of the first embodiment of the present invention does not have a first-order error location polynomial calculation circuit 183a5, a first-order error location polynomial constraint condition check circuit 183a6, a third-order error location polynomial calculation circuit 183a7, or a third-order error location polynomial constraint condition check circuit 183a8.

[0078] As mentioned above, the circuit size of the error location polynomial constraint check circuit in the PGZ method is generally large. The PGZ method calculation unit 183a according to the first embodiment calculates the error location polynomial and checks the error location polynomial constraints in the second and fourth orders, where the parity of k=4, the highest order calculated using the PGZ method, is the same. The PGZ method calculation unit 183a according to the first embodiment reduces the circuit size by eliminating the error location polynomial calculation circuit and the error location polynomial constraint check circuit in the first and third orders.

[0079] Furthermore, in Figure 9, the selection unit 183d of the error position polynomial calculation unit 183 of the comparative example includes selector circuits 183d1, 183d2, 183d3, and 183d4.

[0080] In comparison with the selection unit 183d of the comparative example, the selection unit 183d of the first embodiment of the present invention shown in Figure 3 does not have selector circuits 183d3 and 183d4.

[0081] Figure 10 is a block diagram of the parameter creation unit 183b of the error position polynomial calculation unit 183 of the comparative example. The parameter creation unit 183b of the comparative example includes a selector circuit 183b1.

[0082] The selector circuit 183b1 of the parameter creation unit 183b of the comparative example uses the error position polynomial σ 0 , σ 1 , σ 2 , σ 3 , σ 4 The input is given. The selector circuit 183b1 uses the coefficient σ4 according to the table attached to the selector circuit 183b1. 4 , σ0 4 σ2 2 , σ0 2 Depending on the value of σ, the initial loop value i, error position polynomial C, auxiliary polynomial A, and difference value d bars are output. For example, σ4 4 ≠0 and σ0 4 ≠0 and σ² 2 When ≠0, the initial loop value i=4, and the error position polynomial C=σ 4 , auxiliary polynomial A=σ 3 x, difference value d bar = σ4 4 The following is output. The initial loop value i, error position polynomial C, auxiliary polynomial A, and difference value d bar are output from the parameter creation unit 183b and input to the BM method calculation unit 183c.

[0083] Compared with the parameter creation unit 183b of the comparative example described above, the parameter creation unit 183b of the first embodiment of the present invention, shown in Figure 5, differs in the following respects.

[0084] The parameter creation unit 183b according to the first embodiment generates the error position polynomial σ, which is the output of the first-order error position polynomial calculation circuit 183a5 of the comparative example. 1 And the error location polynomial σ is the output of the third-order error location polynomial calculation circuit 183a7. 3The input is not provided. However, the parameter creation unit 183b according to the first embodiment can recover information that cannot be obtained from the first-order and third-order error location polynomials from the second-order and fourth-order error location polynomials, and create the initial loop value i, the error location polynomial C, the auxiliary polynomial A, and the difference value d bar.

[0085] Although a detailed explanation is omitted, the parameters created by the parameter creation unit 183b according to the first embodiment shown in Figure 5 are identical to or a constant multiplier of the parameters created by the parameter creation unit 183b of the comparative example shown in Figure 9. Even if the error location polynomial C is multiplied by a constant, the error location polynomial obtained by the BM method is the same except that it is multiplied by a constant, and even if the auxiliary polynomial A and the difference value d bar are multiplied by the same constant, the resulting error location polynomial is the same except that it is multiplied by a constant.

[0086] In other words, the parameter creation unit 183b according to the first embodiment generates the error position polynomial σ 1 , σ 3 Even if no input is provided, the error location polynomial σ 2 , σ 4 From this, we can create an initial loop value i, an error position polynomial C, an auxiliary polynomial A, and a difference value d bar, similar to those in the comparative example.

[0087] The circuit size of the auxiliary polynomial calculation unit 183b3 shown in Figure 6 and the difference value calculation unit 183b4 shown in Figure 7, according to the first embodiment, is sufficiently smaller compared to the first-order error location polynomial constraint check circuit 183a6 and the third-order error location polynomial constraint check circuit 183a8 shown in Figure 9. In the memory system 1 according to the first embodiment, the first-order error location polynomial calculation circuit 183a5, the first-order error location polynomial constraint check circuit 183a6, the third-order error location polynomial calculation circuit 183a7, and the third-order error location polynomial constraint check circuit 183a8 are removed. According to the memory system 1 according to the first embodiment, the circuit size of the PGZ method calculation unit 183a can be reduced by removing circuits of orders where k and even / odd do not match. As a result, for example, when t=10 and k=4, the overall circuit size of the error location polynomial calculation unit 183 can be reduced to approximately 4 / 7.

[0088] Although the memory system 1 according to the first embodiment has been described above, the error correction control method used by the memory system 1 is not limited to the memory system 1 and may be applied to other systems that use error correction. In other words, the control method according to the first embodiment can reduce the size of the circuit used for decoding the error correction code.

[0089] (Effects of the first embodiment) According to the memory system of the first embodiment, the circuit size of the error location polynomial calculation unit 183 can be reduced by removing circuits of an order where k and the parity do not match among the Nth-order error location polynomial calculation circuit and the Nth-order error location polynomial constraint condition check circuit of the PGZ method calculation unit 183a. For example, when t=10 and k=4, the overall circuit size of the error location polynomial calculation unit 183 can be reduced to approximately 4 / 7. Furthermore, according to the control method of the first embodiment, the size of the circuit used for decoding the error correction code can be reduced.

[0090] (Second embodiment) Next, a memory system 1 according to the second embodiment will be described. The memory system 1 according to the second embodiment differs from the memory system 1 according to the first embodiment in that it uses a relay-type riBM method, which is different from the relay-type BM method, as a decoding method.

[0091] The block diagram showing an example configuration of the memory system 1 according to the second embodiment is the same as the block diagram of the memory system according to the first embodiment shown in Figure 1, and therefore its illustration and description are omitted. Furthermore, the block diagram of the decoding unit 18 of the memory system 1 according to the second embodiment is the same as the block diagram of the decoding unit 18 according to the first embodiment shown in Figure 2, and therefore its illustration and description are omitted.

[0092] Figure 11 is a block diagram of the error position polynomial calculation unit 183 in the decoding unit 18 of the memory system 1 according to the second embodiment.

[0093] The relay-type riBM method used in the second embodiment calculates the first error-location polynomials of the first to k-th order (where k is an integer satisfying 1 ≤ k < t) among the t error-location polynomials of the first to t-th order corresponding to errors from 1 to t bits, as the first calculation, using the PGZ method. Further, the relay-type riBM method calculates the second error-location polynomials from the order greater than k to the t-th order, as the second calculation, using the riBM method.

[0094] Here, the order k is determined in advance according to the calculation amount and the like. In the following, similar to the first embodiment, a case where k = 4 will be described as an example using a BCH code that corrects errors of 10 bits (t = 10) or less.

[0095] In FIG. 11, the error-location polynomial calculation unit 183 according to the second embodiment is different in that a riBM method calculation unit 183e different from the BM method calculation unit 183c is used, as compared with the error-location polynomial calculation unit 183 according to the first embodiment of FIG. 3. The error-location polynomial calculation unit 183 according to the second embodiment calculates the first error-location polynomials up to the fourth order in the PGZ method calculation unit 183a, and calculates the second error-location polynomials from the order greater than the fourth order to the tenth order in the riBM method calculation unit 183e.

[0096] In the riBM method calculation unit 183e, an input signal different from that of the BM method calculation unit 183c is used. Therefore, in the error-location polynomial calculation unit 183 according to the second embodiment, the parameter creation unit 183b that outputs a signal to the riBM method calculation unit 183e is different from the error-location polynomial calculation unit 183 according to the first embodiment. Relatedly, in the error-location polynomial calculation unit 183 according to the second embodiment, the PGZ method calculation unit 183a that outputs a signal to the parameter creation unit 183b is also different.

[0097] In order to perform the calculation by the riBM method following the calculation by the PGZ method, the parameters used in the riBM method calculation unit 183e are, for example, the following parameters.<00,00620>·The error-location polynomial C updated by the iterative process by the riBM method Auxiliary polynomial Ax used to update the error location polynomial using the riBM method • Initial loop value i represents the initial number of iterations for the loop process. • The first evaluation value series D shown by the following formula (3) C • The second evaluation value series D shown by the following formula (4) Ax

number

number

[0098] First evaluation value series D C , Second evaluation value series D Ax This is the evaluation value D calculated in the process of determining whether or not the error location can be calculated within the Nth-order error location polynomial constraint check circuit of the PGZ method calculation unit 183a. σ N Since it matches a part of it, the result can be used. In other words, compared to the PGZ method calculation unit 183a of the first embodiment shown in Figure 3, the PGZ method calculation unit 183a of the second embodiment shown in Figure 11 uses the evaluation value D as the output signal of the Nth order error position polynomial constraint condition check circuit. σ N This has been added.

[0099] In the second embodiment shown in Figure 11, the parameter creation unit 183b of the error location polynomial calculation unit 183 generates the syndrome S1, ... and the error location polynomial σ output from the PGZ method calculation unit 183a. 2 , σ 4 and evaluation value D σ 2 , D σ 4 And the error position polynomial σ is a constant. 0 The following is input. The parameter creation unit 183b provides the riBM method calculation unit 183e with the initial loop value i, the error position polynomial C, the auxiliary polynomial Ax, and the first evaluation value sequence D. C、 Second evaluation value series D Ax Outputs.

[0100] Figure 12 is a block diagram of the parameter creation unit 183b according to the second embodiment. The parameter creation unit 183b includes selector circuits 183b1 and 183b2, an auxiliary polynomial calculation unit 183b3, and a difference value calculation unit 183b4.

[0101] The selector circuit 183b1 is based on syndrome S1, ... and error position polynomial σ 0 , σ 2 , σ 4 And, evaluation value D σ 2 , D σ 4 The following is entered: Error position polynomial σ 2 The coefficient σ² is the coefficient of the second order. 2 Let σ0 be the coefficient of the 0th order. 2 It has the error position polynomial σ. 4 The coefficient σ4 is the coefficient of the fourth order. 4 Let σ0 be the coefficient of the 0th order. 4 The selector circuit 183b1 has the coefficient σ0 according to the table attached to the selector circuit 183b1 in Figure 12. 4 , σ0 2 Depending on the value of , the initial loop value i, the error position polynomial C, the provisional auxiliary polynomial Ax_t, and the first evaluation value sequence D C , Second provisional evaluation value series D Ax Outputs _t. For example, σ0 4 ≠0 and σ0 2 When ≠0, the initial loop value i=4, and the error position polynomial C=σ 4 , temporary auxiliary polynomial Ax_t=σ 2 x 4 , First evaluation value series D C =D σ 4 , Second provisional evaluation value series D Ax _t=D σ 2 >>2 Output.

[0102] Here, for a natural number N, ">>N" means an operation to shift the matrix by N rows. That is, it means shifting the matrix down by N rows, inserting zeros into the N empty rows from the top, and displacing N rows from the bottom. For example, "D σ2 >>2" has an evaluation score of D σ 2 This operation shifts the matrix down by two rows, inserting zeros into the two empty rows from the top and displacing the two rows below it.

[0103] Furthermore, in the table attached to the selector circuit 183b1 in Figure 12, σ0 4 =0 and σ0 2 Second provisional evaluation value series D when = 0 Ax The value of _t is "D σp 0 >>2" is written. Here, "σp" means σ prime, and "D σp 0 " is an even-order syndrome in the row direction, S2, ..., S 2t-4、 S 2t-2 S 2t This is a matrix of the values ​​of D σp 0 >>2 is "D σp 0 The result of performing an operation to shift the row by two rows is 0, 0, S2, ..., S 2t-4 This results in a matrix with the values ​​[value].

[0104] The error location polynomial C is the error location polynomial with the highest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a. The provisional auxiliary polynomial Ax_t is a polynomial obtained from the error location polynomial with the second highest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a. First evaluation value series D C This is calculated in the process of determining whether the error location can be calculated using the error location polynomial with the highest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a. Second provisional evaluation value series D Ax _t is obtained by performing a shift operation on the evaluation value sequence calculated in the process of determining whether or not the error location can be calculated using the error location polynomial with the second highest degree among the first error location polynomials calculated by the PGZ method calculation unit 183a.

[0105] Initial loop value i, error position polynomial C, first evaluation value sequence DC The parameter creation unit 183b outputs the result, which is then input to the riBM method calculation unit 183e. The error position polynomial C and the provisional auxiliary polynomial Ax_t are input to the auxiliary polynomial calculation unit 183b3. First evaluation value sequence D C and the second provisional evaluation value series D Ax _t is input to the difference value calculation unit 183b4.

[0106] The selector circuit 183b2 uses the error position polynomial σ 2 , σ 4 The input is given. The selector circuit 183b2 uses the coefficient σ4 according to the table attached to the selector circuit 183b2 in Figure 12. 4 , σ0 4 σ2 2 , σ0 2 Depending on the value of, the first correction value m Ax , second correction value m dバー , Third corrected value m DAx [1], fourth modified value m DAx Output [2]. For example, σ4 4 ≠0 and σ0 4 ≠0 and σ² 2 ≠0 and σ0 2 When ≠ 0, the first correction value m Ax =σ2 2 x 2 , second correction value m dバー =σ4 4 , Third corrected value m DAx [1]=1, 4th correction value m DAx [2]=σ² 2 Outputs.

[0107] First corrected value m Ax , second correction value m dバー , Third corrected value m DAx [1], fourth modified value m DAx [2] is determined from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials calculated by the PGZ calculation unit 183a. First correction value m Ax This is input to the auxiliary polynomial calculation unit 183b3. Second correction value m dバー This is input to the auxiliary polynomial calculation unit 183b3 and the difference value calculation unit 183b4. Third correction value m DAx[1] and the fourth corrected value m DAx [2] is input to the difference value calculation unit 183b4.

[0108] The block diagram of the auxiliary polynomial calculation unit 183b3 in Figure 12 is the same as the block diagram of the auxiliary polynomial calculation unit 183b3 in the first embodiment shown in Figure 6. The auxiliary polynomial calculation unit 183b3 in Figure 12 differs from the auxiliary polynomial calculation unit 183b3 in Figure 6 in the following respects: The auxiliary polynomial calculation unit 183b3 in Figure 12 is input with a provisional auxiliary polynomial Ax_t that is different from the provisional auxiliary polynomial A_t in Figure 6, and the first correction value m A The first modified value m is different from the first modified value m. Ax The input is given, and the output is an auxiliary polynomial Ax, which is different from auxiliary polynomial A. Everything else is the same, so the diagram and explanation are omitted.

[0109] Figure 13 is a block diagram of the difference value calculation unit 183b4 according to the second embodiment. The difference value calculation unit 183b4 includes a shift operation circuit 183b4_2, multiplication circuits 183b4_3 and 183b4_4, and an addition circuit 183b4_5. The difference value calculation unit 183b4 calculates the first evaluation value sequence D C , Second provisional evaluation value series D Ax _t, third correction value m DAx [1], fourth modified value m DAx [2], second modified value m dバー The following was entered, and the second evaluation value series D Ax Calculate and output the result.

[0110] The shift calculation circuit 183b4_2 is the first evaluation value sequence D C and the third corrected value m DAx [1] is input. The shift calculation circuit 183b4_2 performs the first evaluation value sequence D C For the third modified value m DAx [1] Performs a shift operation and outputs the result. The multiplication circuit 183b4_3 outputs the first evaluation value sequence D C For the third modified value m DAx [1] The result of the shift operation is given by the fourth modification value m. DAx [2] is multiplied and output. The multiplication circuit 183b4_4 is the second provisional evaluation value sequence D Ax _t has a second correction value mdバー The output is obtained by multiplying by [value]. The adder circuit 183b4_5 outputs the first evaluation value sequence D C For the third modified value m DAx [1] The result of the shift operation and the fourth correction value m DAx [2] The result of multiplication with the second provisional evaluation value series D Ax _t and the second modification value m dバー The results of the multiplications are added together to obtain the second evaluation value series D Ax It is output as follows. Returning to Figure 12, the second evaluation value series D Ax This is output from the parameter creation unit 183b and input to the riBM method calculation unit 183e.

[0111] Returning to the explanation of Figure 11, the riBM method calculation unit 183e receives the initial loop value i, the error position polynomial C, the auxiliary polynomial Ax, and the first evaluation value sequence D from the parameter creation unit 183b. C、 Second evaluation value series D Ax Using this method, the second error location polynomial σB is calculated by the riBM method.

[0112] The circuit size of the auxiliary polynomial calculation unit 183b3 shown in Figure 6 and the difference value calculation unit 183b4 shown in Figure 13 is sufficiently smaller compared to the first-order and third-order error location polynomial constraint condition check circuits that have been removed in the PGZ method calculation unit 183a shown in Figure 11. According to the second embodiment, even with the addition of the auxiliary polynomial calculation unit 183b3 and the difference value calculation unit 183b4, the circuit size of the PGZ method calculation unit 183a can be reduced by removing the first-order and third-order error location polynomial constraint condition check circuits. As a result, for example, when t=10 and k=4, the overall circuit size of the error location polynomial calculation unit 183 can be reduced to approximately 5 / 7.

[0113] Although the memory system 1 according to the second embodiment has been described above, the error correction control method used by the memory system 1 is not limited to the memory system 1 and may be applied to other systems that use error correction. In other words, the control method according to the second embodiment can reduce the size of the circuit used for decoding the error correction code.

[0114] (Effects of the second embodiment) In the memory system 1 according to the second embodiment, even when the relay-type riBM method is used, circuits of the order in which k does not match the parity of k are deleted from the Nth-order error location polynomial calculation circuit and the Nth-order error location polynomial constraint condition check circuit of the PGZ method calculation unit 183a. According to the memory system 1 according to the second embodiment, the circuit size of the error location polynomial calculation unit 183 can be reduced by deleting circuits of the order in which k does not match the parity of k. Furthermore, according to the control method according to the second embodiment, the size of the circuit used for decoding the error correction code can be reduced.

[0115] [Other embodiments] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0116] For example, in the memory system 1 according to the first embodiment, a BCH code is used to correct errors of t=10 bits or less, and an example is shown in which error location polynomials up to order k=4 are calculated by the PGZ method, and error location polynomials from order greater than k=4 to order 10 are calculated by the BM method. However, the values ​​of t and k are not limited to this combination and can be set according to the number of bits to be corrected and the amount of computation required.

[0117] Furthermore, in the memory systems 1 according to the first and second embodiments, a case was shown in which NAND flash memory was used as the non-volatile memory 20. However, the non-volatile memory 20 is not limited to semiconductor memory, but may be various storage media other than semiconductor memory. [Explanation of Symbols]

[0118] 1. Memory System 10 Memory Controllers 11 Control Unit 12 data buffers 13 Memory I / F 14. Encoding / Decoding Section 15 Host I / F 16 Internal bus 17 Encoding section 18 Decoding section 20 Non-volatile memory 30 hosts 181 buffers 182 Syndrome Calculation Unit 183 Error Location Polynomial Calculation Unit 183a PGZ method calculation section 183a1 Quadratic Error Position Polynomial Calculation Circuit 183a2 Quadratic Error Position Polynomial Constraint Check Circuit 183a3 Quadratic Error Position Polynomial Calculation Circuit 183a4 Fourth-order error position polynomial constraint check circuit 183b Parameter creation section 183b1, 183b2 Selector Circuit 183b3 Auxiliary polynomial calculator 183b4 Difference Value Calculation Unit 183c BM method calculation section 183d Selection section 183e riBM method calculation section 184 Error Sequence Calculation Unit 185 Correction Section A, Ax auxiliary polynomial C, σ error locator polynomial d-bar difference value D Ax Second evaluation value series, D Ax _t Second provisional evaluation value series, D C First evaluation value series m A , m Ax First revised value m dバー Second revised value m DAx [1] Third revised value m DAx [2] Fourth revised value

Claims

1. A non-volatile memory that stores data encoded with an error correction code that corrects errors of t bits (where t is an integer greater than or equal to 2), A memory controller that controls writing to and reading from the non-volatile memory, Equipped with, The aforementioned memory controller The syndrome is calculated using the received word read from the non-volatile memory. Using the aforementioned syndrome, a first calculation is performed to find the first error location polynomial of a degree that matches the parity of k among the error location polynomials from degree 1 to degree k (where k is an integer satisfying 1 ≤ k < t). Determine whether the error location can be calculated using the first error location polynomial. If it is determined that the error location can be calculated using the first error location polynomial, the error location is calculated using the first error location polynomial. If it is determined that the error location cannot be calculated using the first error location polynomial, initial values ​​for the parameters used in the second calculation to obtain a second error location polynomial up to the tth order using the first error location polynomial are determined, the second calculation is performed using the initial values, and the error location is calculated using the second error location polynomial obtained in the second calculation. Correct the error in the received word at either the error location calculated using the first error location polynomial or the error location calculated using the second error location polynomial. Memory system.

2. The error correction code is a BCH (Bose-Chaudhuri-Hocquenghem) code. The first calculation described above is performed using the PGZ (Peterson Gorenstein Zierler) method. The second calculation described above is performed using the Berlekamp-Massey (BM) method. The memory system according to claim 1.

3. The aforementioned initial value includes an auxiliary polynomial, The first and second correction values ​​are calculated from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials. The auxiliary polynomial is calculated by adding together the result of multiplying the error location polynomial with the highest degree by the first correction value, and the result of multiplying the polynomial obtained from the error location polynomial with the second highest degree by the second correction value. The memory system according to claim 2.

4. The second calculation described above is performed using the ri (Reformulated Inversionless) BM method. The memory system according to claim 2.

5. The aforementioned initial values ​​include a first evaluation value series and a second evaluation value series. The second, third, and fourth correction values ​​are calculated from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials. The first evaluation value series is calculated in the process of determining whether or not the error location can be calculated using the error location polynomial with the highest degree. The second evaluation value series is calculated by adding together the result of multiplying the first evaluation value series by the fourth correction value after performing a shift operation for the third correction value, and the second provisional evaluation value series obtained by performing a shift operation on the evaluation value series calculated in the process of determining whether or not the error location can be calculated using the error location polynomial of the second highest degree, multiplied by the second correction value. The memory system according to claim 4.

6. A control method for a memory system comprising: a non-volatile memory that stores data encoded with an error correction code that corrects errors of t bits or less (where t is an integer of 2 or more); and a memory controller that controls writing to and reading from the non-volatile memory, The syndrome is calculated using the received word read from the non-volatile memory. Using the aforementioned syndrome, a first calculation is performed to find the first error location polynomial of a degree that matches the parity of k among the error location polynomials from degree 1 to degree k (where k is an integer satisfying 1 ≤ k < t). Determine whether the error location can be calculated using the first error location polynomial. If it is determined that the error location can be calculated using the first error location polynomial, the error location is calculated using the first error location polynomial. If it is determined that the error location cannot be calculated using the first error location polynomial, initial values ​​for the parameters used in the second calculation to obtain a second error location polynomial up to the tth order using the first error location polynomial are determined, the second calculation is performed using the initial values, and the error location is calculated using the second error location polynomial obtained in the second calculation. Correct the error in the received word at either the error location calculated using the first error location polynomial or the error location calculated using the second error location polynomial. A method for controlling a memory system, including the following.

7. The error correction code is a BCH (Bose-Chaudhuri-Hocquenghem) code. The first calculation described above is performed using the PGZ (Peterson Gorenstein Zierler) method. The second calculation described above is performed using the Berlekamp-Massey (BM) method. A method for controlling a memory system according to claim 6.

8. The aforementioned initial value includes an auxiliary polynomial, The first and second correction values ​​are calculated from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials. The auxiliary polynomial is calculated by adding together the result of multiplying the error location polynomial with the highest degree by the first correction value, and the result of multiplying the polynomial obtained from the error location polynomial with the second highest degree by the second correction value. A method for controlling a memory system according to claim 7.

9. The second calculation described above is performed using the ri (Reformulated Inversionless) BM method. A method for controlling a memory system according to claim 7.

10. The aforementioned initial values ​​include a first evaluation value series and a second evaluation value series. The second, third, and fourth correction values ​​are calculated from the error location polynomial with the highest degree and the error location polynomial with the second highest degree among the first error location polynomials. The first evaluation value series is calculated in the process of determining whether or not the error location can be calculated using the error location polynomial with the highest degree. The second evaluation value series is calculated by adding together the result of multiplying the first evaluation value series by the fourth correction value after performing a shift operation for the third correction value, and the second provisional evaluation value series obtained by performing a shift operation on the evaluation value series calculated in the process of determining whether or not the error location can be calculated using the error location polynomial of the second highest degree, multiplied by the second correction value. A method for controlling a memory system according to claim 9.

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