Light-emitting element driving system

Abstract

This invention provides a light-emitting element driving system that can achieve good brightness accuracy for multiple light-emitting elements driven by a matrix. [Solution] The light-emitting element driving system (SYS3') comprises a horizontal synchronization signal generation circuit (OSC7) configured to generate a horizontal synchronization signal, and control units (70, 71, 72) configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system. The horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal.

Description

Technical Field

[0001] The present disclosure relates to a light-emitting element driving system.

Background Art

[0002] In a liquid crystal display device, a backlight that irradiates light onto the back surface of a liquid crystal display panel is often used. In recent years, in order to support HDR (High Dynamic Range), a backlight capable of local dimming has been demanded.

[0003] Local dimming is realized, for example, by driving a plurality of light-emitting elements in a matrix (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In a backlight that drives a plurality of light-emitting elements in a matrix, it is desired that the luminance of each of the plurality of light-emitting elements be as intended.

[0006] The light-emitting element driving system disclosed in this specification includes a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal, and a control unit configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system. The horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal.

Brief Description of the Drawings

[0007] [Figure 1]Figure 1 shows an LED (Light Emitting Diode) driving system according to the first comparative example. [Figure 2] Figure 2 shows an LED driving system according to the second comparative example. [Figure 3] Figure 3 shows an example of a signal waveform used in the LED driving system according to the second comparative example. [Figure 4] Figure 4 shows an example of the brightness distribution of multiple LEDs connected to the LED driving system according to the second comparative example. [Figure 5] Figure 5 shows an LED driving system according to the first embodiment. [Figure 6] Figure 6 shows a schematic configuration of the LED driver. [Figure 7] Figure 7 shows an example of a signal waveform used in the LED driving system according to the first embodiment. [Figure 8] Figure 8 shows an example of a signal waveform used in the LED driving system according to the first embodiment. [Figure 9] Figure 9 is a flowchart showing an example of LED driver operation. [Figure 10] Figure 10 shows an LED driving system according to the second embodiment. [Figure 11] Figure 11 shows an LED driving system according to the third embodiment. [Figure 12] Figure 12 is a flowchart showing an example of LED driver operation. [Figure 13] Figure 13 shows an LED driving system according to the fourth embodiment.

[0008] [Detailed explanation] <Comparative Example 1> Figure 1 shows an LED driving system according to the first comparative example. The LED driving system SYS1 includes LED drivers D1 to D3. Each of the LED drivers D1 to D3 drives multiple LEDs in a matrix based on the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC supplied from the local dimming control device CNT1. Furthermore, each of the LED drivers D1 to D3 adjusts the brightness of each of the multiple LEDs according to the communication signal S1 supplied from the local dimming control device CNT1. For example, an SPI (Serial Peripheral Interface) signal is used as the communication signal S1.

[0009] The local dimming control device CNT1 and the LED driving system SYS1 are mounted on separate boards. Therefore, inter-board wiring is required to transmit the horizontal synchronization signal HSYNC, which is a high-frequency clock signal of several MHz, creating a problem where noise countermeasures become more difficult.

[0010] <Comparative Example 2> Figure 2 shows an LED driving system according to the second comparative example. The LED driving system SYS2 includes LED drivers D4 to D6.

[0011] The LED driver D4 includes an oscillator OSC4 that generates a horizontal synchronization signal HSYNC. The LED driver D4 matrix drives multiple LEDs connected to it based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0012] The LED driver D5 includes an oscillator OSC5 that generates a horizontal synchronization signal HSYNC. The LED driver D5 matrix drives multiple LEDs connected to it based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC5.

[0013] The LED driver D6 includes an oscillator OSC6 that generates a horizontal synchronization signal HSYNC. The LED driver D6 matrix-drives a plurality of LEDs connected to itself based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC6.

[0014] Furthermore, each of the LED drivers D4 to D6 adjusts the brightness of each of the plurality of LEDs according to the communication signal S1 supplied from the local dimming control device CNT2. For example, an SPI signal is used as the communication signal S1.

[0015] When the LED drive system SYS2 is used, the inter-board wiring for transmitting the horizontal synchronization signal HSYNC becomes unnecessary, and noise countermeasures become easier.

[0016] However, when the LED drive system SYS2 is used, there is a possibility that the brightness may vary due to variations in the horizontal synchronization signal HSYNC between the LED drivers D4 to D6.

[0017] Hereinafter, it is assumed that each of the LED drivers D4 to D6 matrix-drives 64 LEDs (8 rows × 8 columns).

[0018] Each of the LED drivers D4 to D6 updates the luminance data for each frame to be reflected in the matrix drive at the rising edge timing of the vertical synchronization signal VSYNC.

[0019] The LED driver D4 generates a matrix trigger signal MT1 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0020] The LED driver D5 generates a matrix trigger signal MT2 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC5.

[0021] The LED driver D6 generates a matrix trigger signal MT3 based on the vertical sync signal VSYNC supplied from the local dimming control device CNT2 and the horizontal sync signal HSYNC output from the oscillator OSC6.

[0022] Figure 3 shows example waveforms of the vertical synchronization signal VSYNC and matrix trigger signals MT1 to MT3. In the example shown in Figure 3, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC4 is the ideal frequency, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC5 is higher than the ideal frequency, and the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC6 is lower than the ideal frequency.

[0023] Each of the matrix trigger signals MT1 to MT3 has a pulse corresponding to the first period of the first column, synchronized with the pulse of the vertical synchronization signal VSYNC. For each of the matrix trigger signals MT1 to MT3, when 32768 periods of the horizontal synchronization signal HSYNC have elapsed from the rising edge timing of the k-th period pulse corresponding to the k-th column, the (k+1)-th period pulse corresponding to the (k+1)-th column rises. Here, k is a natural number greater than or equal to 1. In Figure 3, k=7, but there is no particular upper limit set for k. The period from the rising edge timing of the k-th period pulse corresponding to the k-th column to the rising edge timing of the (k+1)-th period pulse corresponding to the (k+1)-th column is the maximum drive (lighting) period of the LED in the k-th column. The period from the rising edge timing of the (k+1)th pulse corresponding to the 8th column to the timing when 32768 cycles of the horizontal synchronization signal HSYNC have elapsed or the rising edge timing of the vertical synchronization signal VSYNC, whichever comes first, is the maximum drive (illumination) period of the last column's LED.

[0024] In this comparative example, the period from the rising edge of one pulse to the rising edge of the next pulse for each of the matrix trigger signals MT1 to MT3 is set to 32768 cycles of the horizontal synchronization signal HSYNC, but this setting is for a dimming resolution of 15 bits. If a dimming resolution of X bits is required, the period from the rising edge of one pulse to the rising edge of the next pulse for each of the matrix trigger signals MT1 to MT3 should be set to 2 cycles of the horizontal synchronization signal HSYNC. X It is set to a period. For example, if a 16-bit dimming resolution is required, the period from the rising edge of one pulse to the rising edge of the next pulse in each of the matrix trigger signals MT1 to MT3 is set to 65536 (=2) of the horizontal synchronization signal HSYNC. 16 The period is set to ).

[0025] Furthermore, since the ON / OFF switching of MOSFETs (metal-oxide-semiconductor field-effect transistors) is required to perform matrix driving, in addition to the dimming resolution period mentioned above, the period for MOSFET switching time may also be counted. If the MOSFET switching period is Y, then the horizontal synchronization signal HSYNC (2 X A count of the +Y) period is required. Here, Y is a natural number greater than or equal to 1. For example, if X=15 and Y=32, a count of 32800 periods of the horizontal synchronization signal HSYNC is required.

[0026] For each of the matrix trigger signals MT1 to MT3, the period from the rising edge of one pulse to the rising edge of the next pulse corresponds to the duration the LED is lit. For example, if the matrix drive has 8 rows, then 8 matrix trigger signals MT1, 8 matrix trigger signals MT2, and 8 matrix trigger signals MT3 are required, each corresponding to a row.

[0027] When local dimming control is performed to adjust all LEDs to a predetermined brightness (brightness 100), as shown in Figure 4, the LEDs connected to LED driver D4 will have the ideal brightness, the LEDs connected to LED driver D5 will be dimmer than ideal, the LEDs connected to LED driver D5 will be brighter than ideal in rows 1-7, and dimmer than ideal in row 8.

[0028] <First Embodiment> Figure 5 shows an LED driving system according to the first embodiment. The LED driving system SYS3 includes LED drivers D7 to D9.

[0029] The LED driving system SYS3 is used, for example, as part of the backlight of a liquid crystal display device that includes a SoC (System on Chip) 1, a liquid crystal display panel 2, and a local dimming control device CNT2.

[0030] The System on Chip (SOC) 1 outputs the vertical sync signal VSYNC and video signals such as LVDS (Low Voltage Differential Signal) to the local dimming control device CNT2. The local dimming control device CNT2 outputs the video signals to the liquid crystal display panel 2. The local dimming control device CNT2 outputs the vertical sync signal VSYNC and communication signals such as SPI signals S1 to LED drivers D7 to D9, respectively.

[0031] The LED driver D7 comprises terminals T71 to T74, an oscillator OSC7, a counter C7, and a register R7.

[0032] Terminal T71 is configured to receive the vertical synchronization signal VSYNC. Terminal T72 is configured to receive the communication signal S1. Terminal T73 is connected to the output terminal of oscillator OSC7 inside the LED driver D7. Terminal T74 is connected to the output terminal of counter C7 inside the LED driver D7.

[0033] The oscillator OSC7 is configured to generate the horizontal synchronization signal HSYNC. However, in the sub-configurations described later, the oscillator OSC7 will cease operation.

[0034] Counter C7 is configured to generate a vertical synchronization signal VSYNC based on the horizontal synchronization signal HSYNC output from oscillator OSC7. Counter C7 is configured to generate the vertical synchronization signal VSYNC' by, for example, generating a pulse every 262144 (=32768 × 8) periods of the horizontal synchronization signal HSYNC. However, in sub-configurations, counter C7 stops operating.

[0035] Register R7 stores the register values ​​V0 to V4.

[0036] If register value V0 is "0", it is the main setting; if register value V0 is "1", it is the sub setting. In the sub setting, the horizontal sync signal HSYNC, the vertical sync signal VSYNC, and the vertical sync signal VSYNC' must be supplied externally. Register R7 stores "0" as the register value V0.

[0037] Register values ​​V1 and V2 are only valid when they are the main settings.

[0038] If register value V1 is "0", the internally generated horizontal synchronization signal HSYNC is used; if register value V1 is "1", the externally supplied horizontal synchronization signal HSYNC is used. Register R7 stores "0" as the register value V1.

[0039] When register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is output externally. When register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is not output externally. Register R7 stores "0" as register value V2. Therefore, terminal T73 is configured to supply the horizontal synchronization signal HSYNC externally.

[0040] If register value V3 is "0", the system is configured to use the internally generated vertical synchronization signal VSYNC', and if register value V3 is "1", the system is configured to use the externally supplied vertical synchronization signal VSYNC'. Register R7 stores "0" as the register value V3.

[0041] When register value V4 is "0", the internally generated vertical synchronization signal VSYNC' is output externally. When register value V4 is "1", the internally generated vertical synchronization signal VSYNC' is not output externally. Register R7 stores "0" as register value V4. Therefore, terminal T74 becomes a terminal configured to supply the vertical signal VSYNC' externally.

[0042] LED drivers D7 to D9 have the same configuration, and their operating modes can be changed by changing the settings of register values ​​V0 to V4. Alternatively, each of LED drivers D7 to D9 may be fixed to a single operating mode. For example, the oscillator and counter may be removed from LED drivers D8 and D9, and the operating modes of LED drivers D8 and D9 may be fixed to the operating mode corresponding to the sub-setting.

[0043] LED drivers D7 to D9 are mounted on the same circuit board 3.

[0044] Figure 6 shows a schematic configuration of the LED driver D7. The LED driver D7 comprises a matrix trigger signal generation circuit 70, a gate controller 71, and a current driver 72.

[0045] The matrix trigger signal generation circuit 70 is supplied with the vertical synchronization signal VSYNC, the communication signal S1, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC'. The matrix trigger signal generation circuit 70 generates matrix trigger signals MT_R1 to MT_R8 corresponding to rows 1 to 8. Each of the matrix trigger signals MT_R1 to MT_R8 is a signal that has 8 pulses (pulses corresponding to 8 columns) in one period of the vertical synchronization signal VSYNC.

[0046] The gate controller 71 generates and outputs gate signals G1 to G8 corresponding to the 1st to 8th columns, with the LOW level period sequentially switching based on the matrix trigger signal MT_R1 corresponding to the 1st row. Alternatively, the gate controller 71 may be supplied with any of the matrix trigger signals MT_R2 to MT_R8 corresponding to the 2nd to 8th rows, instead of the matrix trigger signal MT_R1 corresponding to the 1st row.

[0047] The current driver 72 generates pull currents I1 to I8 in response to the pulses of the matrix trigger signals MT_R1 to MT_R8, which correspond to rows 1 to 8, respectively.

[0048] The matrix trigger signal generation circuit 70, gate controller 71, and current driver 72 are control circuits configured to control the matrix drive of 64 (8 rows x 8 columns) light-emitting elements based on matrix trigger signals MT_R1 to MT_R8 corresponding to each of the 1st to 8th rows based on the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC. Hereinafter, when it is not necessary to distinguish between the matrix trigger signals MT_R1 to MT_R8 corresponding to each of the 1st to 8th rows, they may be referred to as the matrix trigger signal MT.

[0049] Figure 7 shows an example of a signal waveform used in the LED driving system SYS1. In Figure 7, the luminance data "ab" refers to the luminance data in column b of frame a.

[0050] Since the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC' are generated from the same oscillation source, the relationship between the vertical synchronization signal VSYNC' and the matrix trigger signal MT can be made ideal, as shown in Figure 3 with the vertical synchronization signal VSYNC and the matrix trigger signal MT1. In other words, each period of the matrix trigger signal MT is constant and is 1 / 8 of that of the vertical synchronization signal VSYNC'.

[0051] In the example, the luminance data for each frame is reflected in the matrix drive at the rising edge timing t3 of the vertical sync signal VSYNC'. Because the vertical sync signal VSYNC and the vertical sync signal VSYNC' are not synchronized, in the example, the timing of reflecting the luminance data for each frame in the matrix drive cannot be synchronized with the video signal.

[0052] On the other hand, in this embodiment, the luminance data for each frame is reflected in the matrix drive at the rising edge timing t2 of the matrix trigger signal MT, which appears after the rising edge timing t1 of the vertical synchronization signal VSYNC. In this embodiment, even though the vertical synchronization signal VSYNC and the vertical synchronization signal VSYNC' are not synchronized, the timing of reflecting the luminance data for each frame in the matrix drive can be synchronized with the video signal. Therefore, the LED drive system SYS3 can achieve good luminance accuracy for multiple light-emitting elements driven by the matrix.

[0053] Figure 7 shows the signal waveform when the frequencies of the vertical synchronization signal VSYNC and the vertical synchronization signal VSYNC' are the same. However, since the vertical synchronization signals VSYNC and VSYNC' are not synchronized, it is highly likely that the frequencies of the vertical synchronization signal VSYNC and the vertical synchronization signal VSYNC' will not match.

[0054] If the frequency of the vertical synchronization signal VSYNC is higher than the frequency of the vertical synchronization signal VSYNC', some luminance data will be lost. Conversely, if the frequency of the vertical synchronization signal VSYNC is lower than the frequency of the vertical synchronization signal VSYNC', some luminance data will be reused.

[0055] Figure 8 shows an example of the signal waveform used in the LED drive system SYS3 when the frequency of the vertical synchronization signal VSYNC is higher than the frequency of the vertical synchronization signal VSYNC'. In the example shown in Figure 8, the luminance data "1-6" disappears. However, since the luminance data at the same or adjacent locations between consecutive frames are expected to have similar values, even if luminance data disappears or is used repeatedly, the disappearance or repetition is considered to be at a level that cannot be visually perceived.

[0056] Figure 9 is a flowchart illustrating an example of the operation of the LED driver D7. As shown in Figure 9, the matrix trigger signal generation circuit 70 included in the LED driver D7 generates a rising edge of the matrix trigger signal each time it counts the required period of the horizontal sync signal HSYNC (for example, 32,768 periods if the dimming resolution is 15 bits). The matrix trigger signal generation circuit 70 resets the number of periods of the horizontal sync signal HSYNC that it is counting at the time it generates the rising edge of the matrix trigger signal. Furthermore, when the rising edge timing of the vertical sync signal VSYNC occurs, the LED driver D7 waits until the rising edge timing of the matrix trigger signal MT occurs, and then reflects the brightness data for each frame in the matrix drive at the rising edge timing of the matrix trigger signal MT.

[0057] The SYS3 LED drive system can eliminate variations in the horizontal synchronization signal HSYNC between LED drivers D7 and D9, thus suppressing variations in brightness when local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0058] The LED drive system SYS3 has a configuration in which LED drivers D7 to D9 are mounted on the same board 3, eliminating the need for inter-board wiring to transmit the horizontal synchronization signal HSYNC, thus simplifying noise countermeasures.

[0059] Since the LED drive system SYS3 generates the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC' from the same oscillator, the relationship between the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC' can be made into an ideal relationship, as shown in Figure 3, with the vertical synchronization signal VSYNC and the matrix trigger signal MT1.

[0060] The SYS3 LED drive system can synchronize the timing of reflecting frame-by-frame brightness data in the matrix drive with the video signal. Therefore, the SYS3 LED drive system can achieve good brightness accuracy for multiple light-emitting elements driven by the matrix.

[0061] <Second Embodiment> Figure 10 shows an LED driving system according to the second embodiment. In Figure 10, the same reference numerals are used for parts that are the same as those in Figure 5, and detailed descriptions are omitted.

[0062] The LED driving system SYS4 comprises a gate controller GC1 and LED drivers D11 and D12.

[0063] The gate controller GC1 comprises terminals T101 to T104, an oscillator OSC10, a counter C10, and a register R10.

[0064] Terminal T101 is configured to receive the vertical synchronization signal VSYNC. Terminal T102 is configured to receive the communication signal S1. Terminal T103 is connected to the output terminal of the oscillator OSC10 inside the gate controller GC1. Terminal T104 is connected to the output terminal of the counter C10 inside the gate controller GC1.

[0065] The oscillator OSC10 is configured to generate the horizontal synchronization signal HSYNC. However, the oscillator OSC10 stops operating if both register values ​​V1 and V2, which will be described later, are "1".

[0066] Counter C10 is configured to generate a vertical synchronization signal VSYNC' based on the horizontal synchronization signal HSYNC output from oscillator OSC10. For example, if the dimming resolution is 15 bits, counter C10 is configured to generate a pulse every 262144 (=32768 × 8) periods of the horizontal synchronization signal HSYNC to generate the vertical synchronization signal VSYNC'. In addition to the dimming resolution period mentioned above, a period for MOSFET switching time may also be counted. In other words, the number of counts at which counter C10 generates a pulse will change from the 262144 period example above when the dimming resolution changes or when MOSFET switching time is taken into consideration. However, if both register values ​​V3 and V4, which will be described later, are "1", counter C10 will stop operating.

[0067] Register R10 stores the register values ​​V1 to V4.

[0068] If register value V1 is "0", the internally generated horizontal synchronization signal HSYNC is used; if register value V1 is "1", the externally supplied horizontal synchronization signal HSYNC is used. Register R10 stores "0" as the register value V1.

[0069] When register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is output externally. When register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is not output externally. Register R10 stores "0" as register value V2. Therefore, terminal T103 is configured to supply the horizontal synchronization signal HSYNC externally.

[0070] If register value V3 is "0", the system is set to use the internally generated vertical synchronization signal VSYNC', and if register value V3 is "1", the system is set to use the externally supplied vertical synchronization signal VSYNC. Register R10 stores "0" as the register value V3.

[0071] When register value V4 is "0", the internally generated vertical synchronization signal VSYNC' is output externally. When register value V4 is "1", the internally generated vertical synchronization signal VSYNC' is not output externally. Register R10 stores "0" as register value V4. Therefore, terminal T104 becomes a terminal configured to supply the vertical signal VSYNC' externally.

[0072] The LED driver D11 includes terminals T111 to T114.

[0073] Terminal T111 is configured to receive the vertical synchronization signal VSYNC. Terminal T112 is configured to receive the communication signal S1. Terminal T113 is configured to receive the horizontal synchronization signal HSYNC. Terminal T114 is configured to receive the vertical synchronization signal VSYNC'.

[0074] LED driver D12 has the same configuration as LED driver D11.

[0075] The gate controller GC1 can change its operating mode by changing the settings of register values ​​V1 to V4. Alternatively, the gate controller GC1 may be fixed to a single operating mode.

[0076] The gate controller GC1 and the LED drivers D11 and D12 are mounted on the same circuit board 4.

[0077] The gate controller GC1 is similar to the configuration shown in Figure 6, but with the current driver 72 removed from the LED driver D7.

[0078] LED drivers D11 and D12 have configurations corresponding to the matrix trigger signal generation circuit 70 and current driver 72 of LED driver D7 shown in Figure 6.

[0079] The LED drive system SYS4 can eliminate variations in the horizontal synchronization signal HSYNC between the gate controller GC1, LED driver D11, and LED driver D12. Therefore, it can suppress variations in brightness when local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0080] The LED drive system SYS4 has a configuration in which the gate controller GC1, LED driver D11, and LED driver D12 are mounted on the same board 4, eliminating the need for inter-board wiring to transmit the horizontal synchronization signal HSYNC, thus simplifying noise countermeasures.

[0081] Since the LED drive system SYS4 generates the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC' from the same oscillator, the relationship between the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC' can be made into an ideal relationship, as shown in Figure 3, with the vertical synchronization signal VSYNC and the matrix trigger signal MT1.

[0082] The LED driving system SYS4 reflects the brightness data for each frame to the matrix drive at the same timing as the LED driving system SYS3 according to the first embodiment. Therefore, the LED driving system SYS4 can synchronize the timing of reflecting the brightness data for each frame to the matrix drive with the video signal. Consequently, the LED driving system SYS4 can achieve good brightness accuracy for the multiple light-emitting elements driven by the matrix.

[0083] <Third Embodiment> Figure 11 shows the configuration of the LED driving system SYS3' according to the third embodiment. The LED driving system SYS3' includes LED drivers D7' to D9'.

[0084] LED driver D7' differs from LED driver D7 shown in Figure 5 in that it lacks counter C7 and terminal T74, register 7 does not store register values ​​V3 and V4, and the specific operation of oscillator OSC7; however, it is otherwise the same as LED driver D7 shown in Figure 5.

[0085] LED drivers D7' to D9' have the same configuration.

[0086] The oscillator OSC7 is configured to adjust the frequency of the horizontal synchronization signal HSYNC based on the relationship between the period of the horizontal synchronization signal HSYNC and the period of the vertical synchronization signal VSYNC.

[0087] More specifically, oscillator OSC7 is configured to lower the frequency of the horizontal synchronization signal HSYNC when the product of the normal period of the matrix trigger signal MT (the period corresponding to all columns except the last column) and a constant (the number of columns driven by the matrix) is smaller than the period of the vertical synchronization signal VSYNC. Conversely, oscillator OSC7 is configured to increase the frequency of the horizontal synchronization signal HSYNC when the product of the normal period of the matrix trigger signal MT (the period corresponding to all columns except the last column) and a constant (the number of columns driven by the matrix) is larger than the period of the vertical synchronization signal VSYNC.

[0088] The LED driver D7' allows for the following five settings. The parameters for each setting are stored, for example, in register R7.

[0089] The oscillator OSC7 is configured to allow setting the above multiplication value to be smaller than the period of the vertical synchronization signal VSYNC. The oscillator OSC7 is also configured to allow setting the above multiplication value to be larger than the period of the vertical synchronization signal VSYNC. The oscillator OSC7 is configured to allow setting the number of clock cycles (excess clocks) of the horizontal synchronization signal HSYNC corresponding to the period obtained by subtracting the above multiplication value from the period of the vertical synchronization signal VSYNC (the OFF section shown in Figure 3).

[0090] The oscillator OSC7 is configured to mask the adjustment of the frequency of the horizontal synchronization signal HSYNC when the above multiplication value deviates from the period of the vertical synchronization signal VSYNC by a first predetermined level or more, and to allow setting of the first predetermined level. This makes it possible to suppress the misadjustment of the frequency of the horizontal synchronization signal HSYNC in cases such as when the vertical synchronization signal VSYNC contains noise or when the device that generates the vertical synchronization signal VSYNC malfunctions.

[0091] The oscillator OSC7 is configured to adjust the frequency of the horizontal synchronization signal HSYNC based on the relationship between the periods of the vertical synchronization signal VSYNC and the vertical synchronization signal VSYNC over multiple periods, allowing for settings over multiple periods. This makes it possible to suppress misadjustments due to noise, for example, by taking the average over multiple periods of the vertical synchronization signal VSYNC.

[0092] The oscillator OSC7 is configured to adjust the frequency of the horizontal synchronization signal HSYNC and set a second predetermined level when the above multiplication value deviates by a second predetermined level or more from the period of the vertical synchronization signal VSYNC. By appropriately setting the second predetermined level, frequent adjustments of the frequency of the horizontal synchronization signal HSYNC are suppressed.

[0093] The oscillator OSC7 is configured to allow setting the amount of adjustment when adjusting the frequency of the horizontal synchronization signal HSYNC.

[0094] Figure 12 is a flowchart showing an example of the operation of the LED driver D7'. When the LED driving system SYS3 starts up, the LED driver D7' begins the operation shown in the flowchart in Figure 12.

[0095] First, the LED driver D7' generates a matrix trigger signal MT so that the frame-by-frame luminance data identified by the communication signal S1 is reflected in the matrix drive in synchronization with the vertical synchronization signal VSYNC (step #1).

[0096] In step #2, following step #1, the LED driver D7' subtracts the set surplus clock count from the number of clocks of the horizontal synchronization signal HSYNC corresponding to the period obtained by subtracting the above multiplier value from the period of the vertical synchronization signal VSYNC. The calculation result in step #2 is used in steps #3 to #5 as a value indicating the discrepancy (deviation) between the above multiplier value and the period of the vertical synchronization signal VSYNC.

[0097] In step #3, following step #2, the LED driver D7' determines whether the discrepancy (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is greater than or equal to a first predetermined level.

[0098] If it is determined that the difference (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is not greater than or equal to the first predetermined level (NO in step #3), the process proceeds to step #4. On the other hand, if it is determined that the difference (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is greater than or equal to the first predetermined level (NO in step #3), the process returns to step #1.

[0099] In step #4, the LED driver D7' calculates the average relationship between the period of the matrix trigger signal MT and the period of the vertical sync signal VSYNC over multiple periods of the vertical sync signal VSYNC (e.g., 3 periods). More specifically, the LED driver D7' calculates the average difference (deviation) between the above multiplicative value and the period of the vertical sync signal VSYNC over multiple periods of the vertical sync signal VSYNC (e.g., 3, 4, 5 periods). Note that step #4 may be omitted, and the determination process in step #5, described later, may be executed for each period of the vertical sync signal VSYNC.

[0100] In step #5, following step #4, the LED driver D7' determines whether the discrepancy (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is greater than or equal to a second predetermined level.

[0101] If it is determined that the difference (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is greater than or equal to the second predetermined level (YES in step #5), the process proceeds to step #6. On the other hand, if it is determined that the difference (deviation) between the above multiplication value and the period of the vertical synchronization signal VSYNC is not greater than or equal to the second predetermined level (NO in step #5), the process returns to step #1.

[0102] In step #6, the LED driver D7' adjusts the frequency of the horizontal synchronization signal HSYNC by the set adjustment amount (e.g., ±0.001%, ±0.01%, ±0.1%, etc.). Once step #6 is complete, the process returns to step #1.

[0103] The LED drive system SYS3' can eliminate variations in the horizontal synchronization signal HSYNC between LED drivers D7' to D9', thus suppressing variations in brightness when, for example, local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0104] The LED drive system SYS3' has a configuration in which LED drivers D7' to D9' are mounted on the same board 3, eliminating the need for inter-board wiring to transmit the horizontal synchronization signal HSYNC, thus simplifying noise countermeasures.

[0105] The LED drive system SYS3' can adjust the period of the horizontal synchronization signal HSYNC in each of the LED drivers D7' to D9', thereby bringing the relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC closer to an ideal relationship. Therefore, the LED drive system SYS3 can improve the brightness accuracy of the multiple light-emitting elements driven by the matrix.

[0106] <Fourth Embodiment> Figure 13 shows that the LED driving system SYS4' according to the fourth embodiment comprises a gate controller GC1' and LED drivers D11' and D12'.

[0107] Gate controller GC1' differs from gate controller GC1 shown in Figure 10 in that it does not have counter C10 and terminal T104, register R10 does not store register values ​​V3 and V4, and the specific operation of the part of gate controller GC1' corresponding to the matrix trigger signal generation circuit 70 (see Figure 6), but is otherwise the same as gate controller GC1 shown in Figure 10.

[0108] LED driver D11' differs from LED driver D11 shown in Figure 10 in that it does not have terminal T114, but is otherwise the same as LED driver D11 shown in Figure 10.

[0109] LED driver D12' differs from LED driver D12 shown in Figure 10 in that it does not have terminal T124, but is otherwise the same as LED driver D12 shown in Figure 10.

[0110] In the LED drive system SYS4', the frequency adjustment of the horizontal synchronization signal is performed in the same manner as in the LED drive system SYS3' according to the third embodiment.

[0111] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0112] For example, in the above embodiment, an LED was used as the light-emitting element, but other light-emitting elements may be used.

[0113] For example, the specific number of LED drivers, the specific number of rows in the matrix drive, the specific number of columns in the matrix drive, etc., in the above embodiment are merely examples and are not limited to these specific numbers.

[0114] For example, in the LED drive system SYS3 shown in Figure 5, the sub-configured LED driver D8 may include a determination unit configured to determine whether the horizontal synchronization signal HSYNC is being properly supplied to terminal T83 from the main-configured LED driver D7. If the determination unit determines that the horizontal synchronization signal HSYNC is not being properly supplied to terminal T83, the LED driver D8 may rewrite the contents of register R8 to become the main-configured LED driver and output a command to instruct the LED driver D7 to change from the main-configured LED driver to the sub-configured LED driver. This ensures functional safety, as the oscillator OSC8 generates the horizontal synchronization signal HSYNC when the LED driver D7 is unable to output it, and the horizontal synchronization signal HSYNC generated by the oscillator OSC8 is supplied to LED drivers D7 and D9.

[0115] For example, the first embodiment and the third embodiment may be combined and implemented. Alternatively, the second embodiment and the fourth embodiment may be combined and implemented. Such combinations can suppress the occurrence of "vanished luminance data" or "repeatedly used luminance data" as described in the first embodiment.

[0116] For example, in the second and fourth embodiments, a gate controller may be incorporated inside the local dimming control device. In this case, the local dimming control device and the LED driver are mounted on the same circuit board. The gate controller may also be incorporated inside components other than the local dimming control device.

[0117] <Note> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0118] The light-emitting element driving systems (SYS3', SYS4') of the present disclosure include a horizontal synchronization signal generation circuit (OSC7, OSC10) configured to generate a horizontal synchronization signal, and a control unit (70, 71, 72, GC1) configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system, wherein the horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal (first configuration).

[0119] The first configuration of the light-emitting element driving system described above can bring the relationship between the period of the matrix trigger signal and the period of the first vertical synchronization signal closer to an ideal relationship. Therefore, the first configuration of the light-emitting element driving system can improve the brightness accuracy of the multiple light-emitting elements driven by the matrix.

[0120] In the light-emitting element driving system of the first configuration described above, the horizontal synchronization signal generation circuit may be configured such that the product of the normal period of the matrix trigger signal and a constant is smaller than the period of the vertical synchronization signal (second configuration).

[0121] In the light-emitting element driving system of the first or second configuration described above, the horizontal synchronization signal generation circuit may be configured to mask the adjustment when the multiplicative value of the normal period of the matrix trigger signal and a constant deviates from the period of the vertical synchronization signal by a first predetermined level or more, thereby enabling the setting of the first predetermined level (third configuration).

[0122] In the light-emitting element driving system of any of the first to third configurations described above, the horizontal synchronization signal generation circuit may be configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal over multiple periods of the vertical synchronization signal, and to allow setting of multiple periods (fourth configuration).

[0123] In the light-emitting element driving system of any of the first to fourth configurations described above, the horizontal synchronization signal generation circuit may be configured to adjust the frequency of the horizontal synchronization signal and enable the setting of the second predetermined level when the multiplicative value of the normal period of the matrix trigger signal and a constant deviates from the period of the vertical synchronization signal by a second predetermined level or more (fifth configuration).

[0124] In the light-emitting element driving system of any of the first to fifth configurations described above, the horizontal synchronization signal generation circuit may be configured such that the amount of adjustment when adjusting the frequency of the horizontal synchronization signal can be set (sixth configuration). [Explanation of Symbols]

[0125] 1 SoC 2. LCD display panel 3, 4 circuit boards 70 Matrix Trigger Signal Generation Circuit 71. GC1 Gate Controller 72, 111, 121 Current Drivers C7~C10 Counter CNT1, CNT2 Local Dimming Control Units D1~D9, D11, D12, D7'~D9', D11', D12' LED drivers OSC3~OSC10 Oscillators R7~R10 Registers SYS1~SYS4, SYS3', SYS4' LED drive system Terminals T71-T74, T81-T84, T91-T94, T101-T104, T111-T114, T121-T124

Claims

1. A light-emitting element driving system, A horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal, A control unit configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system, Equipped with, A light-emitting element driving system wherein the horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal.

2. The light-emitting element driving system according to claim 1, wherein the horizontal synchronization signal generation circuit is configured such that the product of the normal period of the matrix trigger signal and a constant is smaller than the period of the vertical synchronization signal.

3. The light-emitting element driving system according to claim 1, wherein the horizontal synchronization signal generation circuit is configured to mask the adjustment and enable setting of the first predetermined level when the product of the normal period of the matrix trigger signal and a constant deviates from the period of the vertical synchronization signal by a first predetermined level or more.

4. The light-emitting element driving system according to claim 1, wherein the horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal based on the relationship between the period of the horizontal synchronization signal and the period of the vertical synchronization signal over multiple periods of the vertical synchronization signal, and to allow setting of multiple periods.

5. The light-emitting element driving system according to claim 1, wherein the horizontal synchronization signal generation circuit is configured to adjust the frequency of the horizontal synchronization signal and set the second predetermined level when the product of the normal period of the matrix trigger signal and a constant deviates from the period of the vertical synchronization signal by a second predetermined level or more.

6. The light-emitting element driving system according to claim 1, wherein the horizontal synchronization signal generation circuit is configured to allow setting of the adjustment amount when adjusting the frequency of the horizontal synchronization signal.

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