Light-emitting element driving system

Abstract

This invention provides a light-emitting element driving system that can achieve good brightness accuracy for multiple light-emitting elements driven by a matrix. [Solution] The light-emitting element driving system comprises a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal; control circuits (71, 72) configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system; and an adjustment circuit (73) configured to adjust the number of periods of the horizontal synchronization signal corresponding to one period of the matrix trigger signal, based on the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal.

Description

Technical Field

[0001] The present disclosure relates to a light-emitting element driving system.

Background Art

[0002] In a liquid crystal display device, a backlight that irradiates light onto the back surface of a liquid crystal display panel is often used. In recent years, in order to support HDR (High Dynamic Range), a backlight capable of local dimming has been demanded.

[0003] Local dimming is achieved, for example, by driving a plurality of light-emitting elements in a matrix (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In a backlight that drives a plurality of light-emitting elements in a matrix, it is desired that the luminance of each of the plurality of light-emitting elements be as intended.

[0006] The light-emitting element driving system disclosed in this specification includes a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal, a control circuit configured to control matrix driving for a plurality of light-emitting elements based on the matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system, and an adjustment circuit configured to adjust the number of cycles of the horizontal synchronization signal corresponding to one cycle of the matrix trigger signal based on the relationship between the cycle of the matrix trigger signal and the cycle of the vertical synchronization signal.

Brief Description of the Drawings

[0007] [Figure 1]Figure 1 shows an LED (Light Emitting Diode) driving system according to the first comparative example. [Figure 2] Figure 2 shows an LED driving system according to the second comparative example. [Figure 3] Figure 3 shows an example of a signal waveform used in the LED driving system according to the second comparative example. [Figure 4] Figure 4 shows an example of the brightness distribution of multiple LEDs connected to the LED driving system according to the second comparative example. [Figure 5] Figure 5 shows an LED driving system according to the first embodiment. [Figure 6] Figure 6 shows a schematic configuration of the LED driver. [Figure 7] Figure 7 shows an example of a signal waveform used in the LED driving system according to the first embodiment. [Figure 8] Figure 8 shows another example of a signal waveform used in the LED driving system according to the first embodiment. [Figure 9] Figure 9 is a flowchart showing an example of the operation of the adjustment circuit. [Figure 10] Figure 10 shows an LED driving system according to the second embodiment. [Figure 11A] Figure 11A shows a schematic configuration of an LED driver. [Figure 11B] Figure 11B shows a schematic configuration of the LED driver. [Figure 12] Figure 12 shows an LED driving system according to the third embodiment.

[0008] [Detailed explanation] <Comparative Example 1> Figure 1 shows an LED driving system according to the first comparative example. The LED driving system SYS1 includes LED drivers D1 to D3. Each of the LED drivers D1 to D3 drives multiple LEDs in a matrix based on the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC supplied from the local dimming control device CNT1. Furthermore, each of the LED drivers D1 to D3 adjusts the brightness of each of the multiple LEDs according to the communication signal S1 supplied from the local dimming control device CNT1. For example, an SPI (Serial Peripheral Interface) signal is used as the communication signal S1.

[0009] The local dimming control device CNT1 and the LED driving system SYS1 are mounted on separate boards. Therefore, inter-board wiring is required to transmit the horizontal synchronization signal HSYNC, which is a high-frequency clock signal of several MHz, creating a problem where noise countermeasures become more difficult.

[0010] <Comparative Example 2> Figure 2 shows an LED driving system according to the second comparative example. The LED driving system SYS2 includes LED drivers D4 to D6.

[0011] The LED driver D4 includes an oscillator OSC4 that generates a horizontal synchronization signal HSYNC. The LED driver D4 matrix drives multiple LEDs connected to it based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0012] The LED driver D5 includes an oscillator OSC5 that generates a horizontal synchronization signal HSYNC. The LED driver D5 matrix drives multiple LEDs connected to it based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC5.

[0013] The LED driver D6 includes an oscillator OSC6 that generates a horizontal synchronization signal HSYNC. The LED driver D6 matrix-drives a plurality of LEDs connected to itself based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC6.

[0014] Furthermore, each of the LED drivers D4 to D6 adjusts the brightness of each of the plurality of LEDs according to the communication signal S1 supplied from the local dimming control device CNT2. For example, an SPI signal is used as the communication signal S1.

[0015] When the LED driving system SYS2 is used, inter-board wiring for transmitting the horizontal synchronization signal HSYNC becomes unnecessary, and noise countermeasures become easier.

[0016] However, when the LED driving system SYS2 is used, there is a possibility that the brightness may vary due to variations in the horizontal synchronization signal HSYNC between the LED drivers D4 to D6.

[0017] Hereinafter, it is assumed that each of the LED drivers D4 to D6 matrix-drives 64 LEDs (8 rows × 8 columns).

[0018] Each of the LED drivers D4 to D6 updates the luminance data for each frame to be reflected in the matrix drive at the rising edge timing of the vertical synchronization signal VSYNC.

[0019] The LED driver D4 generates a matrix trigger signal MT1 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0020] The LED driver D5 generates a matrix trigger signal MT2 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC5.

[0021] The LED driver D6 generates a matrix trigger signal MT3 based on the vertical sync signal VSYNC supplied from the local dimming control device CNT2 and the horizontal sync signal HSYNC output from the oscillator OSC6.

[0022] Figure 3 shows example waveforms of the vertical synchronization signal VSYNC and matrix trigger signals MT1 to MT3. In the example shown in Figure 3, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC4 is the ideal frequency, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC5 is higher than the ideal frequency, and the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC6 is lower than the ideal frequency.

[0023] Each of the matrix trigger signals MT1 to MT3 has a pulse corresponding to the first period of the first column, synchronized with the pulse of the vertical synchronization signal VSYNC. For each of the matrix trigger signals MT1 to MT3, when 32768 periods of the horizontal synchronization signal HSYNC have elapsed from the rising edge timing of the k-th period pulse corresponding to the k-th column, the (k+1)-th period pulse corresponding to the (k+1)-th column rises. Here, k is a natural number greater than or equal to 1. In Figure 3, k=7, but there is no particular upper limit set for k. The period from the rising edge timing of the k-th period pulse corresponding to the k-th column to the rising edge timing of the (k+1)-th period pulse corresponding to the (k+1)-th column is the maximum drive (lighting) period of the LED in the k-th column. The period from the rising edge timing of the (k+1)th pulse corresponding to the 8th column to the timing when 32768 cycles of the horizontal synchronization signal HSYNC have elapsed or the rising edge timing of the vertical synchronization signal VSYNC, whichever comes first, is the maximum drive (illumination) period of the last column's LED.

[0024] In this comparative example, the period from the rising edge of one pulse to the rising edge of the next pulse for each of the matrix trigger signals MT1 to MT3 is set to 32768 cycles of the horizontal synchronization signal HSYNC, but this setting is for a dimming resolution of 15 bits. If a dimming resolution of X bits is required, the period from the rising edge of one pulse to the rising edge of the next pulse for each of the matrix trigger signals MT1 to MT3 should be set to 2 cycles of the horizontal synchronization signal HSYNC. X It is set to a period. For example, if a 16-bit dimming resolution is required, the period from the rising edge of one pulse to the rising edge of the next pulse in each of the matrix trigger signals MT1 to MT3 is set to 65536 (=2) of the horizontal synchronization signal HSYNC. 16 The cycle is set to ).

[0025] Furthermore, since the ON / OFF switching of MOSFETs (metal-oxide-semiconductor field-effect transistors) is required to perform matrix driving, in addition to the dimming resolution period mentioned above, the period for MOSFET switching time may also be counted. If the MOSFET switching period is Y, then the horizontal synchronization signal HSYNC (2 X A count of the +Y) period is required. Here, Y is a natural number greater than or equal to 1. For example, if X=15 and Y=32, a count of 32800 periods of the horizontal synchronization signal HSYNC is required.

[0026] For each of the matrix trigger signals MT1 to MT3, the period from the rising edge of one pulse to the rising edge of the next pulse corresponds to the duration the LED is lit. For example, if the matrix drive has 8 rows, then 8 matrix trigger signals MT1, 8 matrix trigger signals MT2, and 8 matrix trigger signals MT3 are required, each corresponding to a row.

[0027] When local dimming control is performed to adjust all LEDs to a predetermined brightness (brightness 100), as shown in Figure 4, the LEDs connected to LED driver D4 will have the ideal brightness, the LEDs connected to LED driver D5 will be dimmer than ideal, the LEDs connected to LED driver D5 will be brighter than ideal in rows 1-7, and dimmer than ideal in row 8.

[0028] <First Embodiment> Figure 5 shows an LED driving system according to the first embodiment. The LED driving system SYS3 includes LED drivers D7 to D9.

[0029] The LED driving system SYS3 is used, for example, as part of the backlight of a liquid crystal display device that includes a SoC (System on Chip) 1, a liquid crystal display panel 2, and a local dimming control device CNT2.

[0030] The System on Chip (SOC) 1 outputs the vertical sync signal VSYNC and video signals such as LVDS (Low Voltage Differential Signal) to the local dimming control device CNT2. The local dimming control device CNT2 outputs the video signals to the liquid crystal display panel 2. The local dimming control device CNT2 outputs the vertical sync signal VSYNC and communication signals such as SPI signals S1 to LED drivers D7 to D9, respectively.

[0031] The LED driver D7 comprises terminals T71 to T73, an oscillator OSC7, and a register R7.

[0032] Terminal T71 is configured to receive the vertical synchronization signal VSYNC. Terminal T72 is configured to receive the communication signal S1. Terminal T73 is connected to the output terminal of oscillator OSC7 inside the LED driver D7.

[0033] The oscillator OSC7 is configured to generate the horizontal synchronization signal HSYNC. However, in the sub-configurations described later, the oscillator OSC7 will cease operation.

[0034] Register R7 stores the register values ​​V0, V1, and V2.

[0035] If register value V0 is "0", it is the main setting; if register value V0 is "1", it is the sub setting. In the sub setting, both the horizontal sync signal HSYNC and the vertical sync signal VSYNC must be supplied externally. Register R7 stores "0" as the register value V0.

[0036] Register values ​​V1 and V2 are only valid when they are the main settings.

[0037] If register value V1 is "0", the internally generated horizontal synchronization signal HSYNC is used; if register value V1 is "1", the externally supplied horizontal synchronization signal HSYNC is used. Register R7 stores "0" as the register value V1.

[0038] When register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is output externally. When register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is not output externally. Register R7 stores "0" as register value V2. Therefore, terminal T73 is configured to supply the horizontal synchronization signal HSYNC externally.

[0039] The LED driver D8 comprises terminals T81 to T83, an oscillator OSC8, and a register R8.

[0040] Terminal T81 is configured to receive the vertical synchronization signal VSYNC. Terminal T82 is configured to receive the communication signal S1. Terminal T83 is connected to the output terminal of the oscillator OSC8 inside the LED driver D8.

[0041] The oscillator OSC8 is configured to generate the horizontal synchronization signal HSYNC. However, under the aforementioned sub-configurations, the oscillator OSC8 will cease operation.

[0042] Register R8 stores the register values ​​V0, V1, and V2. The definitions of register values ​​V0, V1, and V2 are the same as those for LED driver D7.

[0043] Register R8 stores the value "1" as register value V0. Therefore, terminal T83 becomes a terminal configured to receive the horizontal synchronization signal HSYNC.

[0044] The LED driver D9 comprises terminals T91 to T93, an oscillator OSC9, and a register R9.

[0045] Terminal T91 is configured to receive the vertical synchronization signal VSYNC. Terminal T92 is configured to receive the communication signal S1. Terminal T93 is connected to the output terminal of the oscillator OSC9 inside the LED driver D9.

[0046] The oscillator OSC9 is configured to generate the horizontal synchronization signal HSYNC. However, under the aforementioned sub-configurations, the oscillator OSC9 will cease operation.

[0047] Register R9 stores the register values ​​V0, V1, and V2. The definitions of register values ​​V0, V1, and V2 are the same as those for LED drivers D7 and D8.

[0048] Register R9 stores the value "1" as register value V0. Therefore, terminal T93 becomes a terminal configured to receive the horizontal synchronization signal HSYNC.

[0049] LED drivers D7 to D9 have the same configuration, and their operating modes can be changed by changing the settings of register values ​​V0, V1, and V2. Alternatively, each of LED drivers D7 to D9 may be fixed to a single operating mode. For example, the oscillators may be removed from LED drivers D8 and D9, and the operating modes of LED drivers D8 and D9 may be fixed to the operating mode corresponding to the sub-setting.

[0050] LED drivers D7 to D9 are mounted on the same circuit board 3.

[0051] Figure 6 shows a schematic configuration of the LED driver D7. The LED driver D7 comprises a gate controller 71, a current driver 72, and an adjustment circuit 73.

[0052] The gate controller 71 generates and outputs gate signals G1 to G8 corresponding to the 1st to 8th columns, whose LOW level periods are sequentially switched based on the matrix trigger signal MT_R1 corresponding to the 1st row. Alternatively, the gate controller 71 may be supplied with any of the matrix trigger signals MT_R2 to MT_R8 corresponding to the 2nd to 8th rows, instead of the matrix trigger signal MT_R1 corresponding to the 1st row. Each of the matrix trigger signals MT_R1 to MT_R8 is a signal having eight pulses (equivalent to eight columns) in one period of the vertical synchronization signal VSYNC.

[0053] The current driver 72 generates pull currents I1 to I8 in response to the pulses of the matrix trigger signals MT_R1 to MT_R8, which correspond to rows 1 to 8, respectively.

[0054] The gate controller 71 and current driver 72 are control circuits configured to control the matrix drive of 64 (8 rows x 8 columns) light-emitting elements based on the horizontal synchronization signal HSYNC and the matrix trigger signals MT_R1 to MT_R8 corresponding to each of the 1st to 8th rows, and the vertical synchronization signal VSYNC. Hereinafter, when it is not necessary to distinguish between the matrix trigger signals MT_R1 to MT_R8 corresponding to each of the 1st to 8th rows, they may be referred to as the matrix trigger signal MT.

[0055] The matrix trigger signal before adjustment by the adjustment circuit 73 is similar to the matrix trigger signal generated by the LED drivers D3 to D6 described above. In other words, since the vertical sync signal VSYNC and the horizontal sync signal HSYNC are not signals generated from the same oscillator, the frequency of the horizontal sync signal HSYNC in the matrix trigger signal before adjustment by the adjustment circuit 73 may be higher or lower than the ideal frequency relative to the vertical sync signal VSYNC.

[0056] The adjustment circuit 73 adjusts the number of periods of the horizontal synchronization signal HSYNC, which corresponds to one period of the matrix trigger signal MT, based on the relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC.

[0057] More specifically, the adjustment circuit 73 is configured to increase the number of periods of the horizontal synchronization signal HSYNC, which corresponds to one period of the matrix trigger signal MT, when the product of the normal period of the matrix trigger signal MT (the period corresponding to the columns other than the last column) and a constant (the number of columns driven by the matrix) is smaller than the period of the vertical synchronization signal VSYNC. For example, the adjustment circuit 73 calculates an additional period by dividing the Δ period of the horizontal synchronization signal HSYNC, which corresponds to the OFF section in which the LED cannot be lit under the matrix drive based on the matrix trigger signal MT before adjustment, by the number of columns driven by the matrix (8). Then, the adjustment circuit 73 adds the above additional period to each period of the matrix trigger signal MT before adjustment to generate the adjusted matrix trigger signal MT (see Figure 7).

[0058] Furthermore, the adjustment circuit 73 is configured to reduce the number of periods of the horizontal synchronization signal HSYNC, which corresponds to one period of the matrix trigger signal MT, when the product of the normal period of the matrix trigger signal MT (the period corresponding to the columns other than the last column) and a constant (the number of columns driven by the matrix) is greater than the period of the vertical synchronization signal VSYNC. For example, the adjustment circuit 73 calculates a removal period by dividing the δ period of the horizontal synchronization signal HSYNC corresponding to the insufficient section by the number of columns driven by the matrix (8) because the maximum drive (lighting) period of the 8th column LED is insufficient compared to the ideal with the matrix drive based on the matrix trigger signal MT before adjustment. Then, the adjustment circuit 73 generates the adjusted matrix trigger signal MT by subtracting the above removal period from each period of the matrix trigger signal MT before adjustment (see Figure 8).

[0059] Furthermore, the adjustment circuit 73 is configured to adjust the length of the period during which the matrix trigger signal MT is at a high level, based on the relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC, and the frame-by-frame brightness data identified by the communication signal S1. For example, if the brightness data is a PWM (Pulse Width Modulation) on duty cycle of 50%, the period during which the matrix trigger signal MT is at a high level (the period during which the LED is lit) will be the length obtained by multiplying the adjusted period of the matrix trigger signal MT by a PWM (Pulse Width Modulation) on duty cycle of 50%.

[0060] Figure 9 is a flowchart showing an example of the operation of the adjustment circuit 73. When the LED driving system SYS3 is started up, the adjustment circuit 73 starts the operation shown in the flowchart in Figure 9.

[0061] First, the adjustment circuit 73 generates a matrix trigger signal MT so that the luminance data for each frame, identified by the communication signal S1, is reflected in the matrix drive in synchronization with the vertical synchronization signal VSYNC (step #1).

[0062] In step #2, following step #1, the adjustment circuit 73 calculates the average relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC over multiple periods of the vertical synchronization signal VSYNC (e.g., 3 periods). More specifically, the adjustment circuit 73 calculates the average deviation (deviation) between the product of the normal period of the matrix trigger signal MT (the period corresponding to a column other than the last column) and a constant (the number of columns driving the matrix) and the period of the vertical synchronization signal VSYNC over multiple periods of the vertical synchronization signal VSYNC (e.g., 3 periods). By taking the average, misadjustments due to noise can be suppressed. Note that step #2 may be omitted, and the determination process in step #3, described later, may be executed for each period of the vertical synchronization signal VSYNC.

[0063] In step #3, following step #2, the adjustment circuit 73 determines whether the deviation (shift) between the product of the normal period of the matrix trigger signal MT (the period corresponding to the columns other than the last column) and a constant (the number of columns driven by the matrix) and the period of the vertical synchronization signal VSYNC is above a predetermined level. The predetermined level can be defined, for example, as a predetermined number of periods of the horizontal synchronization signal HSYNC.

[0064] If it is determined that the difference between the product of the normal period of the matrix trigger signal MT (the period corresponding to all columns except the last column) and a constant (the number of columns driven by the matrix) and the period of the vertical synchronization signal VSYNC is above a predetermined level (YES in step #3), the process proceeds to step #4. On the other hand, if it is determined that the difference between the product of the normal period of the matrix trigger signal MT (the period corresponding to all columns except the last column) and a constant (the number of columns driven by the matrix) and the period of the vertical synchronization signal VSYNC is not above a predetermined level (NO in step #3), the process returns to step #1. Step #3 is provided to suppress frequent adjustments of the number of periods of the horizontal synchronization signal HSYNC, which corresponds to one period of the matrix trigger signal MT.

[0065] In step #4, the adjustment circuit 73 adjusts the number of cycles of the horizontal synchronization signal HSYNC, which corresponds to one cycle of the Trix trigger signal MT. Once step #4 is complete, the process returns to step #1.

[0066] The SYS3 LED drive system can eliminate variations in the horizontal synchronization signal HSYNC between LED drivers D7 and D9, thus suppressing variations in brightness when local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0067] The LED drive system SYS3 has a configuration in which LED drivers D7 to D9 are mounted on the same board 3, eliminating the need for inter-board wiring to transmit the horizontal synchronization signal HSYNC, thus simplifying noise countermeasures.

[0068] The LED drive system SYS3 adjusts the number of cycles of the horizontal synchronization signal HSYNC, which corresponds to one cycle of the matrix trigger signal MT, for each of the LED drivers D7 to D9, thereby bringing the relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC closer to an ideal relationship. Therefore, the LED drive system SYS3 can improve the brightness accuracy of the multiple light-emitting elements driven by the matrix.

[0069] <Second Embodiment> Figure 10 shows an LED driving system according to the second embodiment. In Figure 10, the same reference numerals are used for parts that are the same as those in Figure 5, and detailed descriptions are omitted.

[0070] The LED driving system SYS4 comprises a gate controller GC1 and LED drivers D11 and D12.

[0071] The gate controller GC1 comprises terminals T101 to T103, an oscillator OSC10, and a register R10.

[0072] Terminal T101 is configured to receive the vertical synchronization signal VSYNC. Terminal T102 is configured to receive the communication signal S1. Terminal T103 is connected to the output terminal of the oscillator OSC10 inside the gate controller GC1.

[0073] The oscillator OSC10 is configured to generate the horizontal synchronization signal HSYNC. However, the oscillator OSC10 stops operating if both register values ​​V1 and V2, which will be described later, are "1".

[0074] Register R10 stores the register values ​​V1 and V2.

[0075] If register value V1 is "0", the internally generated horizontal synchronization signal HSYNC is used; if register value V1 is "1", the externally supplied horizontal synchronization signal HSYNC is used. Register R10 stores "0" as the register value V1.

[0076] When register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is output externally. When register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is not output externally. Register R10 stores "0" as register value V2. Therefore, terminal T103 is configured to supply the horizontal synchronization signal HSYNC externally.

[0077] The LED driver D11 includes terminals T111 to T113.

[0078] Terminal T111 is configured to receive the vertical synchronization signal VSYNC. Terminal T112 is configured to receive the communication signal S1. Terminal T113 is configured to receive the horizontal synchronization signal HSYNC.

[0079] The LED driver D12 includes terminals T121 to T123.

[0080] Terminal T121 is configured to receive the vertical synchronization signal VSYNC. Terminal T122 is configured to receive the communication signal S1. Terminal T123 is configured to receive the horizontal synchronization signal HSYNC.

[0081] LED driver D12 has the same configuration as LED driver D11.

[0082] The gate controller GC1 can change its operating mode by changing the settings of register values ​​V1 and V2. Alternatively, the gate controller GC1 may be fixed to a single operating mode.

[0083] The gate controller GC1 and the LED drivers D11 and D12 are mounted on the same circuit board 4.

[0084] Figure 11A shows the schematic configuration of LED drivers D11 and D12. LED driver D11 includes a current driver 111. LED driver D12 includes a current driver 121.

[0085] The gate controller GC1 generates a matrix trigger signal, similar to the LED drivers D3 to D6 described above, and generates and outputs gate signals G1 to G16 corresponding to the 1st to 16th columns, whose LOW level periods are sequentially switched based on the matrix trigger signal. In other words, the gate controller GC1 is a control unit configured to control the column drive of the matrix drive for 128 LEDs (8 rows x 16 columns) based on the horizontal synchronization signal HSYNC and the vertical synchronization signal. Note that, as shown in Figure 8B, a MOSFET may be used in common as an external component for LED drivers D11 and D12. In this case, the gate controller GC1 only needs to generate and output gate signals G1 to G8.

[0086] Current drivers 111 and 121 each generate pull currents I1 to I8 in accordance with the pulses of the matrix trigger signal corresponding to rows 1 through 8, respectively.

[0087] The LED drive system SYS4 can eliminate variations in the horizontal synchronization signal HSYNC between the gate controller GC1, LED driver D11, and LED driver D12. Therefore, it can suppress variations in brightness when local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0088] The LED drive system SYS4 has a configuration in which the gate controller GC1, LED driver D11, and LED driver D12 are mounted on the same board 4, eliminating the need for inter-board wiring to transmit the horizontal synchronization signal HSYNC, thus simplifying noise countermeasures.

[0089] Furthermore, the gate controller GC1, LED driver D11, and LED driver D12 each include an adjustment circuit (not shown in Figure 11) similar to the adjustment circuit 73 shown in Figure 6. However, the adjustment circuit provided in the gate controller GC1 may be configured to output only a matrix trigger signal for one row instead of eight rows of matrix trigger signals.

[0090] The LED drive system SYS4 can adjust the number of cycles of the horizontal synchronization signal HSYNC, which corresponds to one cycle of the matrix trigger signal MT, in the gate controller GC1, LED driver D11, and LED driver D12, thereby bringing the relationship between the period of the matrix trigger signal MT and the period of the vertical synchronization signal VSYNC closer to an ideal relationship. Therefore, the LED drive system SYS4 can improve the brightness accuracy of the multiple light-emitting elements driven by the matrix.

[0091] <Third Embodiment> Figure 12 shows an LED driving system according to the third embodiment. The LED driving system SYS5 is a modified example of the LED driving system SYS4 shown in Figure 7.

[0092] In the LED drive system SYS5, the gate controller is integrated into the local dimming control device CNT3. The local dimming control device CNT3, LED driver D11, and LED driver D12 are mounted on the same circuit board 4.

[0093] In the third embodiment, the gate controller is incorporated inside the local dimming control device, but it may also be incorporated inside a component other than the local dimming control device.

[0094] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0095] For example, in the above embodiment, an LED was used as the light-emitting element, but other light-emitting elements may be used.

[0096] For example, the specific number of LED drivers, the specific number of rows in the matrix drive, the specific number of columns in the matrix drive, etc., in the above embodiment are merely examples and are not limited to these specific numbers.

[0097] For example, in the LED drive system SYS3 shown in Figure 5, the sub-configured LED driver D8 may include a determination unit configured to determine whether the horizontal synchronization signal HSYNC is being properly supplied to terminal T83 from the main-configured LED driver D7. If the determination unit determines that the horizontal synchronization signal HSYNC is not being properly supplied to terminal T83, the LED driver D8 may rewrite the contents of register R8 to become the main-configured LED driver and output a command to instruct the LED driver D7 to change from the main-configured LED driver to the sub-configured LED driver. This ensures functional safety, as the oscillator OSC8 generates the horizontal synchronization signal HSYNC when the LED driver D7 is unable to output it, and the horizontal synchronization signal HSYNC generated by the oscillator OSC8 is supplied to LED drivers D7 and D9.

[0098] <Note> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0099] The light-emitting element driving system (SYS3, SYS4, SYS5) of the present disclosure comprises a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal; control circuits (71, 72) configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system (first configuration); and an adjustment circuit (73) configured to adjust the number of periods of the horizontal synchronization signal corresponding to one period of the matrix trigger signal based on the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal.

[0100] The light-emitting element driving system of the first configuration described above can improve the brightness accuracy of the multiple light-emitting elements driven by the matrix by adjusting the number of cycles of the horizontal synchronization signal, which corresponds to one cycle of the matrix trigger signal, thereby bringing the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal closer to an ideal relationship.

[0101] In the first configuration of the light-emitting element driving system described above, the adjustment circuit may be configured to synchronize the timing of reflecting the frame-by-frame brightness data supplied from outside the light-emitting element driving system to the matrix drive with the vertical synchronization signal (second configuration).

[0102] In the light-emitting element driving system of the first or second configuration described above, the adjustment circuit may be configured to increase the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the product of the normal period of the matrix trigger signal and a constant is smaller than the period of the vertical synchronization signal (third configuration).

[0103] In the light-emitting element driving system of any of the first to third configurations described above, the adjustment circuit may be configured to reduce the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the product of the normal period of the matrix trigger signal and a constant is greater than the period of the vertical synchronization signal (fourth configuration).

[0104] In the third or fourth configuration of the light-emitting element driving system described above, the adjustment circuit may be configured to adjust the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the deviation between the multiplication value and the period of the vertical synchronization signal is above a predetermined level (fifth configuration).

[0105] In a light-emitting element driving system according to any of the first to fifth configurations described above, the adjustment circuit may be configured to adjust the length of the period during which the matrix trigger signal is at a first level, based on the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal and the brightness data for each frame supplied from outside the light-emitting element driving system (sixth configuration).

[0106] In a light-emitting element driving system according to any of the first to sixth configurations described above, the adjustment circuit may be configured to adjust the number of periods of the horizontal synchronization signal corresponding to one period of the matrix trigger signal based on the average of the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal over multiple periods of the vertical synchronization signal (seventh configuration). [Explanation of symbols]

[0107] 1 SoC 2. LCD display panel 3, 4 circuit boards 71. GC1 Gate Controller 72, 111, 121 Current Drivers 73 Adjustment circuit CNT1, CNT2, CNT3 Local Dimming Control Units D1-D9, D11, D12, LED driver OSC3~OSC10 Oscillators R7~R10 Registers SYS1~SYS5 LED driving system Terminals T71-T74, T81-T84, T91-T94, T101-T104, T111-T113, T121-T123

Claims

1. A light-emitting element driving system, A horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal, A control circuit configured to control matrix driving for a plurality of light-emitting elements based on a matrix trigger signal based on the horizontal synchronization signal and a vertical synchronization signal supplied from outside the light-emitting element driving system, An adjustment circuit configured to adjust the number of cycles of the horizontal synchronization signal, which corresponds to one cycle of the matrix trigger signal, based on the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal, A light-emitting element driving system comprising:

2. The light-emitting element driving system according to claim 1, wherein the adjustment circuit is configured to synchronize the timing of reflecting frame-by-frame brightness data supplied from outside the light-emitting element driving system to the matrix drive with the vertical synchronization signal.

3. The light-emitting element driving system according to claim 1, wherein the adjustment circuit is configured to increase the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the product of the normal period of the matrix trigger signal and a constant is smaller than the period of the vertical synchronization signal.

4. The light-emitting element driving system according to claim 1, wherein the adjustment circuit is configured to reduce the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the product of the normal period of the matrix trigger signal and a constant is greater than the period of the vertical synchronization signal.

5. The light-emitting element driving system according to claim 3 or 4, wherein the adjustment circuit is configured to adjust the number of periods of the horizontal synchronization signal, which corresponds to one period of the matrix trigger signal, when the deviation between the multiplication value and the period of the vertical synchronization signal is above a predetermined level.

6. The light-emitting element driving system according to claim 1, wherein the adjustment circuit is configured to adjust the length of the period during which the matrix trigger signal is at a first level, based on the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal and frame-by-frame brightness data supplied from outside the light-emitting element driving system.

7. The light-emitting element driving system according to claim 1, wherein the adjustment circuit is configured to adjust the number of periods of the horizontal synchronization signal corresponding to one period of the matrix trigger signal based on the average of the relationship between the period of the matrix trigger signal and the period of the vertical synchronization signal over multiple periods of the vertical synchronization signal.

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