Susceptors and heat treatment equipment

Abstract

The present invention provides a susceptor and heat treatment apparatus that can suppress cracking of the substrate during flash light irradiation. [Solution] Multiple substrate support pins 77 are erected on the upper surface of the holding plate 75 of the susceptor 74. The surface of the semiconductor wafer W supported by the multiple substrate support pins 77 is irradiated with flash light to perform a heat treatment. Each of the multiple substrate support pins 77 is positioned so that the stress generated by the contact between the substrate support pin 77 and the semiconductor wafer W is equal to the stress generated by the bending of the semiconductor wafer W. The risk of wafer cracking caused by scratches on the semiconductor wafer W in the previous process and the risk of wafer cracking caused by scratches on the semiconductor wafer W due to contact with the substrate support pins 77 can be equally divided, and cracking of the semiconductor wafer W during flash light irradiation can be minimized.

Description

Technical Field

[0001] The present invention relates to a susceptor that holds a substrate heated by flash light irradiation, and a heat treatment apparatus including the susceptor. Substrates to be heat-treated include, for example, semiconductor wafers, substrates for liquid crystal display devices, substrates for flat panel displays (FPDs), substrates for optical disks, substrates for magnetic disks, or substrates for solar cells.

Background Art

[0002] In the manufacturing process of semiconductor devices, flash lamp annealing (FLA) that heats a semiconductor wafer in an extremely short time has attracted attention. Flash lamp annealing is a heat treatment technique that irradiates flash light onto the surface of a semiconductor wafer using a xenon flash lamp (hereinafter, simply referred to as "flash lamp" when referring to a xenon flash lamp), thereby raising the temperature of only the surface of the semiconductor wafer in an extremely short time (several milliseconds or less).

[0003] The emission spectral distribution of a xenon flash lamp is from the ultraviolet region to the near-infrared region, and its wavelength is shorter than that of a conventional halogen lamp and almost coincides with the fundamental absorption band of a silicon semiconductor wafer. Therefore, when flash light is irradiated from a xenon flash lamp onto a semiconductor wafer, little transmitted light is present and the semiconductor wafer can be rapidly heated. It has also been found that if flash light is irradiated for an extremely short time of several milliseconds or less, only the vicinity of the surface of the semiconductor wafer can be selectively heated.

[0004] Such flash lamp annealing is used for processes that require heating in an extremely short time, for example, typically for activating impurities implanted in a semiconductor wafer. If flash light is irradiated from a flash lamp onto the surface of a semiconductor wafer into which impurities have been implanted by the ion implantation method, the temperature of the surface of the semiconductor wafer can be raised to the activation temperature in an extremely short time, and only impurity activation can be performed without deeply diffusing the impurities.

[0005] In flash lamp annealing, a flash of light with extremely high energy is instantaneously irradiated onto the surface of a semiconductor wafer. This can cause the semiconductor wafer to deform rapidly due to thermal stress, potentially leading to wafer cracking. In particular, if there are scratches on the semiconductor wafer, stress concentrates at the scratches, making the semiconductor wafer more likely to crack. When a semiconductor wafer cracks during heat treatment, it not only becomes a defective wafer, reducing yield, but also necessitates cleaning up the broken fragments, increasing equipment downtime and significantly reducing productivity. For this reason, Patent Document 1 discloses a technique in which the back surface of the semiconductor wafer is imaged with a camera before flash light irradiation to detect scratches, and processing is interrupted and flash heating is not performed on semiconductor wafers in which scratches are detected. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2024-41146 [Overview of the project] [Problems that the invention aims to solve]

[0007] The technology disclosed in Patent Document 1 allows for the detection of scratches on the back surface of a semiconductor wafer in a process prior to flash lamp annealing, thereby avoiding flash heating and preventing wafer cracking. However, in the preceding process, when a semiconductor wafer without scratches is brought into the chamber for flash lamp annealing and placed on the substrate support pins, scratches may occur on the back surface of the semiconductor wafer due to contact with the substrate support pins. It is difficult to detect scratches that occur on the back surface of a semiconductor wafer immediately before flash light irradiation, and these scratches can cause the semiconductor wafer to crack during flash light irradiation.

[0008] The present invention has been made in view of the above problems, and aims to provide a susceptor and a heat treatment apparatus that can suppress cracking of the substrate when irradiated with flash light. [Means for solving the problem]

[0009] To solve the above problems, a first aspect of the present invention provides a susceptor for holding a substrate heated by flash light irradiation, comprising a flat holding plate and a plurality of support pins erected on the upper surface of the holding plate and in contact with the lower surface of the substrate at their upper ends to support the substrate, wherein each of the plurality of support pins is positioned such that the stress generated by the contact between the support pin and the substrate is equal to the stress generated by the deflection of the substrate.

[0010] Furthermore, the second embodiment is a heat treatment apparatus for heating a substrate by irradiating the substrate with flash light, comprising: a chamber for housing the substrate; a susceptor according to the first embodiment for holding the substrate within the chamber; and a flash lamp for irradiating the substrate held by the susceptor with flash light. [Effects of the Invention]

[0011] According to the susceptor of the first embodiment, each of the plurality of support pins erected on the upper surface of the retaining plate is positioned such that the stress caused by contact between the support pin and the substrate is equal to the stress caused by the deflection of the substrate. This makes it possible to equally divide the risk of cracking caused by scratches on the substrate in the previous process with the risk of cracking caused by scratches on the substrate due to contact with the support pins, thereby suppressing cracking of the substrate when irradiated with flash light.

[0012] According to the heat treatment apparatus of the second embodiment, since it is equipped with a susceptor according to the first embodiment, cracking of the substrate during flash light irradiation can be suppressed. [Brief explanation of the drawing]

[0013] [Figure 1]This is a longitudinal cross-sectional view showing the configuration of the heat treatment apparatus according to the present invention. [Figure 2] This is a perspective view showing the overall appearance of the holding part. [Figure 3] This is a plan view of the susceptor. [Figure 4] This is a cross-section of the susceptor. [Figure 5] This is a plan view of the transfer mechanism. [Figure 6] This is a side view of the transfer mechanism. [Figure 7] This is a plan view showing the arrangement of multiple halogen lamps. [Figure 8] This diagram shows a semiconductor wafer being held in a susceptor. [Figure 9] This figure shows an example of stress acting on the back surface of a semiconductor wafer. [Figure 10] This figure shows an example of stress acting on the back surface of a semiconductor wafer. [Figure 11] This figure shows an example of stress acting on the back surface of a semiconductor wafer. [Figure 12] Figure 1 is a flowchart showing the procedure for the processing operation in the heat treatment apparatus. [Modes for carrying out the invention]

[0014] Hereinafter, embodiments of the present invention will be described in detail while referring to the drawings. In the following, expressions indicating relative or absolute positional relationships (for example, "in one direction", "along one direction", "parallel", "orthogonal", "center", "concentric", "coaxial", etc.) represent not only strictly representing the positional relationship, but also a state in which the angle or distance is displaced within a range where the same tolerance or the same function can be obtained, unless otherwise specified. Also, expressions indicating an equal state (for example, "identical", "equal", "homogeneous", etc.) represent not only a quantitatively strictly equal state, but also a state in which there is a difference where the same tolerance or the same function can be obtained, unless otherwise specified. Further, expressions indicating a shape (for example, "circular shape", "square shape", "cylindrical shape", etc.) represent not only geometrically strictly representing the shape, but also a shape within a range where the same effect can be obtained, and may have, for example, irregularities or chamfers. Also, each expression such as "comprising", "having", "including", "containing", "possessing" a component is not an exclusive expression excluding the existence of other components. Also, the expression "at least one of A, B, and C" includes "only A", "only B", "only C", "any two of A, B, and C", and "all of A, B, and C".

[0015] FIG. 1 is a longitudinal sectional view showing the configuration of a heat treatment apparatus 1 according to the present invention. The heat treatment apparatus 1 in FIG. 1 is a flash lamp annealing apparatus that heats a disk-shaped semiconductor wafer W as a substrate by performing flash light irradiation on the semiconductor wafer W. The size of the semiconductor wafer W to be processed is not particularly limited, but is, for example, φ300 mm or φ450 mm (φ300 mm in this embodiment). In addition, in FIG. 1 and each subsequent figure, for ease of understanding, the dimensions and numbers of each part are exaggerated or simplified as necessary.

[0016] The heat treatment apparatus 1 includes a chamber 6 that houses a semiconductor wafer W, a flash heating unit 5 incorporating a plurality of flash lamps FL, and a halogen heating unit 4 incorporating a plurality of halogen lamps HL. The flash heating unit 5 is provided above the chamber 6, and the halogen heating unit 4 is provided below it. Further, the heat treatment apparatus 1 includes a holding unit 7 that holds the semiconductor wafer W in a horizontal posture inside the chamber 6, and a transfer mechanism 10 that transfers the semiconductor wafer W between the holding unit 7 and the outside of the apparatus. Furthermore, the heat treatment apparatus 1 includes a control unit 3 that controls each operating mechanism provided in the halogen heating unit 4, the flash heating unit 5, and the chamber 6 to perform heat treatment of the semiconductor wafer W.

[0017] The chamber 6 is configured by mounting quartz chamber windows above and below a cylindrical chamber side portion 61. The chamber side portion 61 has a substantially cylindrical shape with openings at the top and bottom. An upper chamber window 63 is mounted and closed at the upper opening, and a lower chamber window 64 is mounted and closed at the lower opening. The upper chamber window 63 that constitutes the ceiling portion of the chamber 6 is a disk-shaped member formed of quartz and functions as a quartz window that transmits flash light emitted from the flash heating unit 5 into the chamber 6. Also, the lower chamber window 64 that constitutes the floor portion of the chamber 6 is a disk-shaped member formed of quartz and functions as a quartz window that transmits light from the halogen heating unit 4 into the chamber 6.

[0018] Furthermore, a reflective ring 68 is attached to the upper part of the inner wall surface of the chamber side portion 61, and a reflective ring 69 is attached to the lower part. Both reflective rings 68 and 69 are formed in an annular shape. The upper reflective ring 68 is attached by fitting it from the upper side of the chamber side portion 61. On the other hand, the lower reflective ring 69 is attached by fitting it from the lower side of the chamber side portion 61 and securing it with screws (not shown). In other words, both reflective rings 68 and 69 are detachably attached to the chamber side portion 61. The inner space of the chamber 6, that is, the space enclosed by the upper chamber window 63, the lower chamber window 64, the chamber side portion 61, and the reflective rings 68 and 69, is defined as the heat treatment space 65.

[0019] By attaching the reflective rings 68 and 69 to the chamber side portion 61, a recess 62 is formed on the inner wall surface of the chamber 6. Specifically, the recess 62 is formed by the central portion of the inner wall surface of the chamber side portion 61 where the reflective rings 68 and 69 are not attached, the lower end surface of the reflective ring 68, and the upper end surface of the reflective ring 69. The recess 62 is formed in an annular shape along the horizontal direction on the inner wall surface of the chamber 6 and surrounds the holding portion 7 that holds the semiconductor wafer W. The chamber side portion 61 and the reflective rings 68 and 69 are made of a metal material (for example, stainless steel) with excellent strength and heat resistance.

[0020] Furthermore, a transport opening (furnace opening) 66 is provided on the side portion 61 of the chamber for loading and unloading semiconductor wafers W into and out of the chamber 6. The transport opening 66 can be opened and closed by a gate valve 185. The transport opening 66 is connected in communication with the outer surface of the recess 62. Therefore, when the gate valve 185 is open, semiconductor wafers W can be loaded into the heat treatment space 65 from the transport opening 66 through the recess 62 and unloaded from the heat treatment space 65. When the gate valve 185 closes the transport opening 66, the heat treatment space 65 inside the chamber 6 becomes a sealed space.

[0021] Furthermore, through-holes 61a and 61b are drilled in the side portion 61 of the chamber. Through-hole 61a is a cylindrical hole for guiding infrared light emitted from the upper surface of the semiconductor wafer W held by the susceptor 74 (described later) to the infrared sensor 29 of the upper radiation thermometer 25. On the other hand, through-hole 61b is a cylindrical hole for guiding infrared light emitted from the lower surface of the semiconductor wafer W to the lower radiation thermometer 20. Through-holes 61a and 61b are provided at an inclination with respect to the horizontal direction such that their axes in the direction of penetration intersect with the main surface of the semiconductor wafer W held by the susceptor 74. A transparent window 26 made of calcium fluoride material that transmits infrared light in the wavelength range measurable by the upper radiation thermometer 25 is attached to the end of through-hole 61a facing the heat treatment space 65. Furthermore, a transparent window 21 made of barium fluoride material that transmits infrared light in the wavelength range measurable by the lower radiation thermometer 20 is attached to the end of the through hole 61b facing the heat treatment space 65.

[0022] Furthermore, a gas supply hole 81 for supplying a processing gas to the heat treatment space 65 is formed in the upper part of the inner wall of the chamber 6. The gas supply hole 81 is formed in a position above the recess 62 and may be provided in the reflecting ring 68. The gas supply hole 81 is connected to a gas supply pipe 83 via a buffer space 82 formed in an annular shape inside the side wall of the chamber 6. The gas supply pipe 83 is connected to a processing gas supply source 85. A valve 84 is also interposed in the path of the gas supply pipe 83. When the valve 84 is opened, processing gas is supplied from the processing gas supply source 85 to the buffer space 82. The processing gas that flows into the buffer space 82 spreads out within the buffer space 82, which has less fluid resistance than the gas supply hole 81, and is supplied from the gas supply hole 81 into the heat treatment space 65. As the processing gas, for example, an inert gas such as nitrogen (N2), or a reactive gas such as hydrogen (H2), ammonia (NH3), or a mixed gas of these can be used (in this embodiment, nitrogen gas).

[0023] On the other hand, a gas exhaust port 86 for exhausting gas from the heat treatment space 65 is formed in the lower part of the inner wall of the chamber 6. The gas exhaust port 86 is formed in a position below the recess 62 and may be provided in the reflecting ring 69. The gas exhaust port 86 is connected to a gas exhaust pipe 88 via a buffer space 87 formed in an annular shape inside the side wall of the chamber 6. The gas exhaust pipe 88 is connected to the exhaust section 190. A valve 89 is interposed in the path of the gas exhaust pipe 88. When the valve 89 is opened, the gas from the heat treatment space 65 is discharged from the gas exhaust port 86 through the buffer space 87 to the gas exhaust pipe 88. Note that there may be multiple gas supply holes 81 and gas exhaust holes 86 along the circumferential direction of the chamber 6, or they may be slit-shaped. Also, the processing gas supply source 85 and the exhaust section 190 may be mechanisms provided in the heat treatment apparatus 1, or they may be utilities of the factory where the heat treatment apparatus 1 is installed.

[0024] Furthermore, a gas exhaust pipe 191 for discharging gas from the heat treatment space 65 is connected to the tip of the transport opening 66. The gas exhaust pipe 191 is connected to the exhaust section 190 via a valve 192. By opening the valve 192, the gas in the chamber 6 is exhausted through the transport opening 66.

[0025] Figure 2 is a perspective view showing the overall appearance of the holding part 7. The holding part 7 is composed of a base ring 71, a connecting part 72, and a susceptor 74. The base ring 71, the connecting part 72, and the susceptor 74 are all made of quartz. In other words, the entire holding part 7 is made of quartz.

[0026] The base ring 71 is a quartz material with an arc shape, partially missing from its annular shape. This missing portion is provided to prevent interference between the transfer arm 11 of the transfer mechanism 10 (described later) and the base ring 71. The base ring 71 is supported by the wall surface of the chamber 6 by being placed on the bottom surface of the recess 62 (see Figure 1). Multiple connecting parts 72 (four in this embodiment) are erected on the upper surface of the base ring 71 along the circumferential direction of its annular shape. The connecting parts 72 are also made of quartz material and are fixed to the base ring 71 by welding.

[0027] The susceptor 74 is an element that directly holds the semiconductor wafer W, which is heated by flash light irradiation. The susceptor 74 is supported by four connecting parts 72 provided on the base ring 71. Figure 3 is a plan view of the susceptor 74. Figure 4 is a cross-sectional view of the susceptor 74. The susceptor 74 comprises a holding plate 75, a guide ring 76, and a plurality of substrate support pins 77. The holding plate 75 is a substantially circular, flat member made of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. That is, the holding plate 75 has a larger planar size than the semiconductor wafer W.

[0028] A guide ring 76 is installed on the upper peripheral edge of the retaining plate 75. The guide ring 76 is an annular member having an inner diameter larger than the diameter of the semiconductor wafer W. For example, if the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm. The inner circumference of the guide ring 76 is tapered so as to widen upward from the retaining plate 75. The guide ring 76 is made of quartz, the same material as the retaining plate 75. The guide ring 76 may be welded to the upper surface of the retaining plate 75, or it may be fixed to the retaining plate 75 by a separately processed pin or the like. Alternatively, the retaining plate 75 and the guide ring 76 may be manufactured as a single integrated member.

[0029] The area of ​​the upper surface of the retaining plate 75 that is inside the guide ring 76 is a planar retaining surface 75a for holding the semiconductor wafer W. Multiple substrate support pins 77 are erected on the retaining surface 75a of the retaining plate 75. In this embodiment, a total of 12 substrate support pins 77 are erected at 30° intervals along the circumference of the outer circumference of the retaining surface 75a (the inner circumference of the guide ring 76) concentric with the outer circumference of the retaining surface 75a. The diameter of the circle in which the 12 substrate support pins 77 are arranged (the distance between opposing substrate support pins 77) is smaller than the diameter of the semiconductor wafer W. Each substrate support pin 77 is made of quartz. Multiple substrate support pins 77 may be provided on the upper surface of the retaining plate 75 by welding, or they may be manufactured integrally with the retaining plate 75. The installation positions of the multiple substrate support pins 77 in the radial direction of the retaining plate 75 will be described further later.

[0030] Returning to Figure 2, the four connecting parts 72 erected on the base ring 71 and the peripheral edge of the holding plate 75 of the susceptor 74 are fixed by welding. In other words, the susceptor 74 and the base ring 71 are fixedly connected by the connecting parts 72. The holding part 7 is mounted in the chamber 6 by the base ring 71 of the holding part 7 being supported by the wall surface of the chamber 6. When the holding part 7 is mounted in the chamber 6, the holding plate 75 of the susceptor 74 is in a horizontal position (a position in which the normal coincides with the vertical direction). In other words, the holding surface 75a of the holding plate 75 is a horizontal plane.

[0031] The semiconductor wafer W, once loaded into the chamber 6, is placed and held in a horizontal position on the susceptor 74 of the holding unit 7 mounted on the chamber 6. At this time, the semiconductor wafer W is supported by 12 substrate support pins 77 erected on the holding plate 75 and held by the susceptor 74. More precisely, the upper ends of the 12 substrate support pins 77 contact the lower surface of the semiconductor wafer W to support it.

[0032] Furthermore, the semiconductor wafer W is supported by a plurality of substrate support pins 77 at a predetermined distance from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the substrate support pins 77. Therefore, horizontal displacement of the semiconductor wafer W supported by the plurality of substrate support pins 77 is prevented by the guide ring 76.

[0033] Furthermore, as shown in Figures 2 and 3, the holding plate 75 of the susceptor 74 has an opening 78 that penetrates vertically. The opening 78 is provided for the lower radiation thermometer 20 to receive synchrotron radiation (infrared light) emitted from the lower surface of the semiconductor wafer W. That is, the lower radiation thermometer 20 measures the temperature of the semiconductor wafer W by receiving light emitted from the lower surface of the semiconductor wafer W through the opening 78 and a transparent window 21 fitted in a through hole 61b of the chamber side portion 61. In addition, the holding plate 75 of the susceptor 74 has four through holes 79 through which the lift pins 12 of the transfer mechanism 10, which will be described later, pass for the transfer of the semiconductor wafer W.

[0034] Figure 5 is a plan view of the transfer mechanism 10. Figure 6 is a side view of the transfer mechanism 10. The transfer mechanism 10 comprises two transfer arms 11. The transfer arms 11 are shaped like arcs that generally follow the annular recess 62. Two lift pins 12 are erected on each transfer arm 11. The transfer arms 11 and lift pins 12 are made of quartz. Each transfer arm 11 is rotatable by a horizontal movement mechanism 13. The horizontal movement mechanism 13 moves the pair of transfer arms 11 horizontally between a transfer operation position (solid line position in Figure 5) where the semiconductor wafer W is transferred to the holding part 7 and a retracted position (dotted line position in Figure 5) where the semiconductor wafer W held by the holding part 7 does not overlap in a plan view. The horizontal movement mechanism 13 may consist of individual motors that rotate each transfer arm 11, or it may consist of a linkage mechanism that uses a single motor to rotate a pair of transfer arms 11 in conjunction.

[0035] Furthermore, the pair of transfer arms 11 are moved up and down together with the horizontal movement mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, a total of four lift pins 12 pass through through holes 79 (see Figures 2 and 3) drilled in the susceptor 74, and the upper ends of the lift pins 12 protrude from the upper surface of the susceptor 74. On the other hand, when the lifting mechanism 14 lowers the pair of transfer arms 11 to the transfer operation position and removes the lift pins 12 from the through holes 79, and the horizontal movement mechanism 13 moves the pair of transfer arms 11 to open, each transfer arm 11 moves to a retracted position. The retracted position of the pair of transfer arms 11 is directly above the base ring 71 of the holding part 7. Since the base ring 71 is placed on the bottom surface of the recess 62, the retracted position of the transfer arms 11 is inside the recess 62. Furthermore, an exhaust mechanism (not shown) is also provided near the area where the drive unit (horizontal movement mechanism 13 and lifting mechanism 14) of the transfer mechanism 10 is located, so that the atmosphere around the drive unit of the transfer mechanism 10 is discharged to the outside of the chamber 6.

[0036] Returning to Figure 1, the flash heating unit 5, located above the chamber 6, is configured with a light source consisting of multiple (30 in this embodiment) xenon flash lamps FL inside a housing 51, and a reflector 52 provided to cover the top of the light source. A lamp light emission window 53 is also attached to the bottom of the housing 51 of the flash heating unit 5. The lamp light emission window 53, which constitutes the floor of the flash heating unit 5, is a plate-shaped quartz window made of quartz. As the flash heating unit 5 is installed above the chamber 6, the lamp light emission window 53 faces the upper chamber window 63. The flash lamps FL irradiate the heat treatment space 65 with flash light from above the chamber 6 through the lamp light emission window 53 and the upper chamber window 63.

[0037] Each of the multiple flash lamps FL is a rod-shaped lamp with a long cylindrical shape, and they are arranged in a planar manner such that their longitudinal directions are parallel to each other along the main surface (i.e., along the horizontal direction) of the semiconductor wafer W held by the holding part 7. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane. The area in which the multiple flash lamps FL are arranged is larger than the planar size of the semiconductor wafer W.

[0038] A xenon flash lamp FL comprises a cylindrical glass tube (discharge tube) containing xenon gas, with an anode and cathode connected to capacitors at both ends, and a trigger electrode attached to the outer surface of the glass tube. Since xenon gas is an electrically insulating material, electricity does not flow through the glass tube under normal conditions, even if charge is stored in the capacitor. However, when a high voltage is applied to the trigger electrode to break the insulation, the electricity stored in the capacitor flows instantaneously through the glass tube, and light is emitted due to the excitation of xenon atoms or molecules at that time. In such a xenon flash lamp FL, the electrostatic energy previously stored in the capacitor is converted into extremely short light pulses of 0.1 milliseconds to 100 milliseconds, giving it the characteristic of being able to emit extremely strong light compared to a continuously lit light source such as a halogen lamp HL. In other words, a flash lamp FL is a pulse-emitting lamp that emits light instantaneously in an extremely short time of less than one second. Furthermore, the illumination time of the flash lamp FL can be adjusted by the coil constant of the lamp power supply that provides power to the flash lamp FL.

[0039] Furthermore, the reflector 52 is positioned above the multiple flash lamps FL so as to cover them all. The basic function of the reflector 52 is to reflect the flash light emitted from the multiple flash lamps FL towards the heat treatment space 65. The reflector 52 is made of an aluminum alloy plate, and its surface (the side facing the flash lamps FL) is roughened by blasting.

[0040] The halogen heating unit 4, located below the chamber 6, has multiple halogen lamps HL (40 in this embodiment) built into the inside of the housing 41. The halogen heating unit 4 heats the semiconductor wafer W by irradiating light from below the chamber 6 through the lower chamber window 64 into the heat treatment space 65 using the multiple halogen lamps HL.

[0041] Figure 7 is a plan view showing the arrangement of multiple halogen lamps HL. The 40 halogen lamps HL are arranged in two rows, upper and lower. Twenty halogen lamps HL are arranged in the upper row, which is closer to the holding part 7, and another 20 halogen lamps HL are arranged in the lower row, which is further from the holding part 7. Each halogen lamp HL is a rod-shaped lamp with a long cylindrical shape. In both the upper and lower rows, the 20 halogen lamps HL are arranged so that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holding part 7 (i.e., along the horizontal direction). Therefore, the planes formed by the arrangement of halogen lamps HL in both the upper and lower rows are horizontal planes.

[0042] Furthermore, as shown in Figure 7, in both the upper and lower sections, the arrangement density of halogen lamps HL is higher in the region facing the periphery of the semiconductor wafer W held by the holding section 7 than in the region facing the center. In other words, in both the upper and lower sections, the arrangement pitch of halogen lamps HL is shorter at the periphery than at the center of the lamp arrangement. Therefore, a greater amount of light can be irradiated to the periphery of the semiconductor wafer W, where temperature drops are more likely to occur during heating by light irradiation from the halogen heating section 4.

[0043] Furthermore, the lamp group consisting of halogen lamps HL in the upper row and the lamp group consisting of halogen lamps HL in the lower row are arranged to intersect in a grid pattern. In other words, a total of 40 halogen lamps HL are arranged such that the longitudinal directions of the 20 halogen lamps HL in the upper row and the longitudinal directions of the 20 halogen lamps HL in the lower row are perpendicular to each other.

[0044] The halogen lamp HL is a filament-type light source that emits light by passing an electric current through a filament placed inside a glass tube, causing the filament to become incandescent. Inside the glass tube is a gas containing trace amounts of halogen elements (iodine, bromine, etc.) introduced into an inert gas such as nitrogen or argon. By introducing halogen elements, it is possible to set the filament temperature to a high level while suppressing filament breakage. Therefore, the halogen lamp HL has the characteristics of having a longer lifespan and being able to continuously emit strong light compared to a normal incandescent light bulb. In other words, the halogen lamp HL is a continuous-lighting lamp that emits light continuously for at least 1 second or more. Furthermore, because the halogen lamp HL is a rod-shaped lamp, it has a long lifespan, and by arranging the halogen lamp HL horizontally, the radiation efficiency to the semiconductor wafer W above it is excellent.

[0045] Furthermore, a reflector 43 is also provided inside the housing 41 of the halogen heating unit 4, below the two-tiered halogen lamps HL (Figure 1). The reflector 43 reflects the light emitted from the multiple halogen lamps HL towards the heat treatment space 65.

[0046] As shown in Figure 1, the heat treatment apparatus 1 includes an upper radiation thermometer 25 and a lower radiation thermometer 20. The upper radiation thermometer 25 is installed diagonally above the semiconductor wafer W held by the susceptor 74 and measures the temperature of the upper surface by receiving infrared light emitted from the upper surface of the semiconductor wafer W. The infrared sensor 29 of the upper radiation thermometer 25 is equipped with an InSb (indium antimony) optical element to respond to rapid temperature changes on the upper surface of the semiconductor wafer W at the moment of flash light irradiation. On the other hand, the lower radiation thermometer 20 is installed diagonally below the semiconductor wafer W held by the susceptor 74 and measures the temperature of the lower surface by receiving infrared light emitted from the lower surface of the semiconductor wafer W.

[0047] The control unit 3 controls the various operating mechanisms provided in the heat treatment apparatus 1. The hardware configuration of the control unit 3 is similar to that of a general computer. Specifically, the control unit 3 includes a CPU, which is a circuit that performs various calculations; a ROM, which is a read-only memory that stores basic programs; a RAM, which is a read-write memory that stores various information; and a storage unit (for example, a magnetic disk or SSD) that stores control software and data. Processing in the heat treatment apparatus 1 proceeds when the CPU of the control unit 3 executes a predetermined processing program.

[0048] In this embodiment, the installation positions of the multiple substrate support pins 77 of the susceptor 74 are defined as follows. Figure 8 shows a state in which a semiconductor wafer W is held by the susceptor 74. The semiconductor wafer W is held by the susceptor 74 by being supported by 12 substrate support pins 77. When a φ300 mm semiconductor wafer W is supported by 12 substrate support pins 77 in point contact, the semiconductor wafer W will bend, as shown in Figure 8. That is, the central and edge portions of the semiconductor wafer W that are not in contact with the substrate support pins 77 will bend downwards due to their own weight compared to the contact points with the substrate support pins 77. Note that in Figure 8, the height of the substrate support pins 77 and the bending of the semiconductor wafer W are exaggerated for ease of understanding.

[0049] When a semiconductor wafer W is supported by 12 substrate support pins 77 and flexes, two types of stress act on the back surface of the semiconductor wafer W: "stress caused by contact with the substrate support pins 77" and "stress caused by the flexing of the semiconductor wafer W itself." The magnitude of these two types of stresses differs depending on the distance r from the center of the semiconductor wafer W to each substrate support pin 77 (the radius of the circle in which the 12 substrate support pins 77 are arranged).

[0050] Figures 9 to 11 illustrate examples of stress acting on the back surface of a semiconductor wafer W, depending on the distance r from the center of the semiconductor wafer W to the substrate support pins 77. Figure 9 shows the stress acting on the back surface of the semiconductor wafer W when the distance r from the center of the semiconductor wafer W to the substrate support pins 77 is relatively short, r1. The substrate support pins 77 support the semiconductor wafer W at a position where the distance from the center of the semiconductor wafer W is r1. Therefore, stress caused by contact with the substrate support pins 77 acts near the position where the distance from the center of the back surface of the semiconductor wafer W is r1 (the contact point with the substrate support pins 77). Stress caused by the deflection of the semiconductor wafer W itself acts on the region of the back surface of the semiconductor wafer W, excluding the area near the contact point with the substrate support pins 77.

[0051] As shown in Figure 9, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is r1, the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pin 77 is significantly greater than the stress generated by the bending of the semiconductor wafer W itself. In other words, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is relatively short, the stress acting on the back surface of the semiconductor wafer W is predominantly the stress generated by contact with the substrate support pin 77.

[0052] Next, Figure 10 shows the stress acting on the back surface of the semiconductor wafer W when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is relatively long, r3. In this example, the substrate support pin 77 supports the semiconductor wafer W at a position where the distance from the center of the semiconductor wafer W is r3. Therefore, as described above, stress caused by contact with the substrate support pin 77 acts near the position where the distance from the center of the back surface of the semiconductor wafer W is r3 (the contact point with the substrate support pin 77). Stress caused by the deflection of the semiconductor wafer W itself acts on the region of the back surface of the semiconductor wafer W excluding the area near the contact point with the substrate support pin 77.

[0053] As shown in Figure 10, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is r3, the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pin 77 is smaller than the maximum stress generated by the deflection of the semiconductor wafer W itself. In other words, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is relatively long, the stress acting on the back surface of the semiconductor wafer W is predominantly the stress generated by the deflection of the semiconductor wafer W itself.

[0054] On the other hand, Figure 11 shows the stress acting on the back surface of the semiconductor wafer W when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is r2 as described above. In this example, the substrate support pin 77 supports the semiconductor wafer W at a position where the distance from the center of the semiconductor wafer W is r2. Therefore, similar to the above, stress caused by contact with the substrate support pin 77 acts near the position where the distance from the center of the back surface of the semiconductor wafer W is r2 (the contact point with the substrate support pin 77). Stress caused by the deflection of the semiconductor wafer W itself acts on the region of the back surface of the semiconductor wafer W, excluding the area near the contact point with the substrate support pin 77.

[0055] As shown in Figure 11, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is r2, the maximum stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pin 77 is equal to the maximum stress generated by the deflection of the semiconductor wafer W itself. In other words, when the distance r from the center of the semiconductor wafer W to the substrate support pin 77 is a moderate r2, the stress acting on the back surface of the semiconductor wafer W is a balance between the stress generated by contact with the substrate support pin 77 and the stress generated by the deflection of the semiconductor wafer W itself.

[0056] As described above, the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pins 77 increases as the distance r from the center of the semiconductor wafer W to the substrate support pins 77 decreases. On the other hand, the stress generated by the deflection of the semiconductor wafer W itself varies depending on the distance r from the center of the semiconductor wafer W to the substrate support pins 77. In this embodiment, a plurality of substrate support pins 77 are provided on the upper surface of the holding plate 75 such that the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pins 77 and the stress generated by the deflection of the semiconductor wafer W itself are equal. That is, a plurality of substrate support pins 77 are provided on the upper surface of the holding plate 75 such that the distance r from the center of the semiconductor wafer W to each of the plurality of substrate support pins 77 is a moderate r2.

[0057] In addition to the above configuration, the heat treatment apparatus 1 is equipped with various cooling structures to prevent excessive temperature rise in the halogen heating section 4, flash heating section 5, and chamber 6 due to thermal energy generated from the halogen lamp HL and flash lamp FL during the heat treatment of semiconductor wafers W. For example, water cooling pipes (not shown) are provided in the wall of the chamber 6. Furthermore, the halogen heating section 4 and flash heating section 5 are air-cooled structures that dissipate heat by forming a gas flow inside. Air is also supplied to the gap between the upper chamber window 63 and the lamp light emission window 53 to cool the flash heating section 5 and the upper chamber window 63.

[0058] Next, the processing operation of the heat treatment apparatus 1 having the above configuration will be described. Figure 12 is a flowchart showing the procedure of the processing operation of the heat treatment apparatus 1. The processing procedure of the heat treatment apparatus 1 described below proceeds as the control unit 3 controls each operating mechanism of the heat treatment apparatus 1.

[0059] First, the supply valve 84 is opened, and the exhaust valves 89 and 192 are opened, initiating the supply and exhaust of air into the chamber 6. When valve 84 is opened, nitrogen gas is supplied to the heat treatment space 65 from the gas supply port 81. When valve 89 is opened, the gas inside the chamber 6 is exhausted from the gas exhaust port 86. As a result, the nitrogen gas supplied from the top of the heat treatment space 65 inside the chamber 6 flows downward and is exhausted from the bottom of the heat treatment space 65.

[0060] Furthermore, when valve 192 is opened, the gas inside chamber 6 is also exhausted from the transport opening 66. In addition, the atmosphere around the drive unit of the transfer mechanism 10 is also exhausted by an exhaust mechanism (not shown). During the heat treatment of semiconductor wafers W in the heat treatment apparatus 1, nitrogen gas is continuously supplied to the heat treatment space 65, and the amount supplied is changed as appropriate according to the processing step.

[0061] Next, the gate valve 185 opens, the transport opening 66 is opened, and the semiconductor wafer W to be processed is transported into the heat treatment space 65 inside the chamber 6 by a transport robot outside the apparatus via the transport opening 66 (step S1). At this time, there is a risk that the atmosphere outside the apparatus may be drawn in as the semiconductor wafer W is transported in, but since nitrogen gas is continuously supplied to the chamber 6, the nitrogen gas flows out from the transport opening 66, minimizing the entrainment of such external atmosphere.

[0062] The semiconductor wafer W, loaded by the transport robot, moves forward to a position directly above the holding section 7 and stops. Then, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally from the retracted position to the transfer operation position and rise, causing the lift pin 12 to protrude from the upper surface of the holding plate 75 of the susceptor 74 through the through hole 79 and receive the semiconductor wafer W. At this time, the lift pin 12 rises above the upper end of the substrate support pin 77.

[0063] After the semiconductor wafer W is placed on the lift pin 12, the transport robot exits the heat treatment space 65, and the transport opening 66 is closed by the gate valve 185. Then, as the pair of transfer arms 11 descend, the semiconductor wafer W is transferred from the transfer mechanism 10 to the susceptor 74 of the holding section 7 and held from below in a horizontal position. The semiconductor wafer W is supported by a plurality of substrate support pins 77 erected on the holding plate 75 and held by the susceptor 74 (step S2). The distance r from the center of the semiconductor wafer W to each of the plurality of substrate support pins 77 is r2 as described above.

[0064] Furthermore, the semiconductor wafer W is held in the holding section 7 with the patterned surface facing upwards. A predetermined gap is formed between the back surface (the main surface opposite to the front surface) of the semiconductor wafer W, which is supported by a plurality of substrate support pins 77, and the holding surface 75a of the holding plate 75. The pair of transfer arms 11, which have descended to below the susceptor 74, are retracted to a retracted position, i.e., inside the recess 62, by the horizontal movement mechanism 13.

[0065] After the semiconductor wafer W is held horizontally from below by the susceptor 74 of the holding part 7 made of silica, the 40 halogen lamps HL of the halogen heating part 4 are lit simultaneously to start preheating (assisted heating) (step S3). The halogen light emitted from the halogen lamps HL passes through the lower chamber window 64 and the susceptor 74 made of silica and irradiates the lower surface of the semiconductor wafer W. The semiconductor wafer W is preheated and its temperature rises due to the light irradiation from the halogen lamps HL. The transfer arm 11 of the transfer mechanism 10 is retracted inside the recess 62 and does not interfere with heating by the halogen lamps HL.

[0066] When preheating is performed using a halogen lamp HL, the temperature of the semiconductor wafer W is measured by a lower radiation thermometer 20. Specifically, the lower radiation thermometer 20 receives infrared light emitted from the lower surface of the semiconductor wafer W held by the susceptor 74 through an opening 78 via a transparent window 21 to measure the wafer temperature during heating. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 monitors whether the temperature of the semiconductor wafer W, which is heated by light irradiation from the halogen lamp HL, has reached a predetermined preheating temperature T1, and controls the output of the halogen lamp HL. In other words, the control unit 3 feedback-controls the output of the halogen lamp HL based on the measurement value from the lower radiation thermometer 20 so that the temperature of the semiconductor wafer W reaches the preheating temperature T1. Thus, the lower radiation thermometer 20 is a radiation thermometer for temperature control of the semiconductor wafer W during preheating.

[0067] After the semiconductor wafer W reaches the preheating temperature T1, the control unit 3 temporarily maintains the semiconductor wafer W at that preheating temperature T1. Specifically, when the temperature of the semiconductor wafer W, as measured by the lower radiation thermometer 20, reaches the preheating temperature T1, the control unit 3 adjusts the output of the halogen lamp HL to maintain the temperature of the semiconductor wafer W at approximately the preheating temperature T1.

[0068] By performing preheating with halogen lamps HL in this manner, the entire semiconductor wafer W is uniformly heated to the preheating temperature T1. During the preheating stage with halogen lamps HL, the temperature of the peripheral parts of the semiconductor wafer W, where heat dissipation is more likely, tends to be lower than that of the central part. However, the density of halogen lamps HL in the halogen heating section 4 is higher in the region facing the peripheral parts of the semiconductor wafer W than in the region facing the central part. As a result, more light is irradiated to the peripheral parts of the semiconductor wafer W, where heat dissipation is more likely, making it possible to achieve a uniform in-plane temperature distribution of the semiconductor wafer W during the preheating stage.

[0069] When the semiconductor wafer W reaches the preheating temperature T1 and a predetermined time has elapsed, the flash lamp FL of the flash heating unit 5 irradiates the surface of the semiconductor wafer W held by the susceptor 74 with flash light (step S4). At this time, a portion of the flash light emitted from the flash lamp FL goes directly into the chamber 6, and another portion is reflected by the reflector 52 before going into the chamber 6, and the semiconductor wafer W is flash-heated by the irradiation of these flash lights.

[0070] The flash light emitted from the flash lamp FL is an extremely short and intense flash of light with an irradiation time of approximately 0.1 milliseconds to 100 milliseconds, obtained by converting electrostatic energy previously stored in a capacitor into an extremely short light pulse. When such an extremely short and intense flash of light is emitted, the surface temperature of the semiconductor wafer W instantaneously rises to a processing temperature T2 of over 1000°C, and then rapidly decreases.

[0071] In this embodiment, a plurality of substrate support pins 77 are provided on the upper surface of the holding plate 75 such that the distance r from the center of the semiconductor wafer W to each of the plurality of substrate support pins 77 is r2 as described above, and the semiconductor wafer W is supported by these plurality of substrate support pins 77. Therefore, the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pins 77 is equal to the stress generated due to the deflection of the semiconductor wafer W itself.

[0072] Incidentally, when a semiconductor wafer W is irradiated with a very short exposure time and high intensity flash light, the semiconductor wafer W may deform rapidly and crack due to thermal stress. In particular, if there are scratches on the semiconductor wafer W, stress concentration occurs at the scratches, causing the semiconductor wafer W to easily crack when irradiated with flash light. Scratches that occur on the semiconductor wafer W can be broadly classified into two types: scratches that occur in a process prior to flash lamp annealing, and scratches that occur due to contact with the substrate support pins 77 in the heat treatment apparatus 1. Scratches that occur in a process prior to flash lamp annealing are, for example, scratches caused by contact with a chuck or the like in that prior process. It is not clearly understood which of these two types of scratches is the main cause of wafer cracking when irradiated with flash light.

[0073] Furthermore, as described above, when the semiconductor wafer W is supported by 12 substrate support pins 77 and flexes, two types of stress act on the back surface of the semiconductor wafer W: "stress caused by contact with the substrate support pins 77" and "stress caused by the flexing of the semiconductor wafer W itself." Of these, the stress caused by contact with the substrate support pins 77 is the cause of scratches on the semiconductor wafer W caused by contact with the substrate support pins 77. It is thought that the stress caused by contact with the substrate support pins 77 concentrates on the scratches on the semiconductor wafer W caused by contact with the substrate support pins 77, and thus poses a risk of the semiconductor wafer W cracking when irradiated with flash light. In other words, the stress caused by contact with the substrate support pins 77 is the main risk of wafer cracking caused by scratches on the semiconductor wafer W caused by contact with the substrate support pins 77. On the other hand, the stress caused by the flexing of the semiconductor wafer W itself is thought to concentrate mainly on scratches on the semiconductor wafer W in processes prior to flash lamp annealing, and thus poses a risk of the semiconductor wafer W cracking when irradiated with flash light. In other words, the stress caused by the bending of the semiconductor wafer W itself is the primary risk factor for wafer cracking resulting from scratches on the semiconductor wafer W in a process prior to flash lamp annealing.

[0074] Therefore, in order to prevent wafer cracking caused by scratches on the semiconductor wafer W due to contact with the substrate support pins 77, it is preferable to increase the distance r from the center of the semiconductor wafer W to the substrate support pins 77 to reduce the stress caused by contact with the substrate support pins 77. Conversely, in order to prevent wafer cracking caused by scratches on the semiconductor wafer W in a process prior to flash lamp annealing, it is preferable to decrease the distance r from the center of the semiconductor wafer W to the substrate support pins 77 to reduce the stress caused by the bending of the semiconductor wafer W itself.

[0075] However, it is not clear whether scratches on the semiconductor wafer W in a process prior to flash lamp annealing, or scratches on the semiconductor wafer W caused by contact with the substrate support pins 77, are the primary cause of wafer cracking during flash light irradiation. Therefore, in this embodiment, in order to equally distribute the risk of the semiconductor wafer W cracking during flash light irradiation due to each of these two types of scratches, the stress generated on the back surface of the semiconductor wafer W due to contact with the substrate support pins 77 and the stress generated by the bending of the semiconductor wafer W itself are made equal. In other words, multiple substrate support pins 77 are provided at positions where the stress generated by the contact between the substrate support pins 77 and the semiconductor wafer W is equal to the stress generated by the bending of the semiconductor wafer W. This reduces scratches on the semiconductor wafer W caused by contact with the substrate support pins 77, reduces the load on the semiconductor wafer W due to bending, and minimizes the risk of the semiconductor wafer W cracking during flash light irradiation by dividing the risk of the semiconductor wafer W cracking during flash light irradiation by half, each caused by the two types of scratches.

[0076] After the flash heating process is completed, the halogen lamp HL is turned off after a predetermined time has elapsed. This causes the semiconductor wafer W to rapidly cool down from the preheating temperature T1. The temperature of the semiconductor wafer W during the cooling process is measured by the lower radiation thermometer 20, and the measurement result is transmitted to the control unit 3. The control unit 3 monitors whether the temperature of the semiconductor wafer W has cooled down to a predetermined temperature based on the measurement result of the lower radiation thermometer 20. After the temperature of the semiconductor wafer W has cooled down to below the predetermined temperature, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally again from the retracted position to the transfer operation position and rise, causing the lift pin 12 to protrude from the upper surface of the susceptor 74 and receive the heat-treated semiconductor wafer W from the susceptor 74. Subsequently, the transport opening 66, which had been closed by the gate valve 185, is opened, and the semiconductor wafer W placed on the lift pin 12 is transported out of the chamber 6 by a transport robot outside the apparatus, completing the heat treatment of the semiconductor wafer W (step S5).

[0077] In this embodiment, a plurality of substrate support pins 77 are erected on the upper surface of the holding plate 75 of the susceptor 74, and the semiconductor wafer W is supported by these substrate support pins 77. Each of the plurality of substrate support pins 77 is positioned on the upper surface of the holding plate 75 such that the stress generated by the contact between the substrate support pin 77 and the semiconductor wafer W is equal to the stress generated by the deflection of the semiconductor wafer W. Therefore, the magnitudes of these two types of stress acting on the semiconductor wafer W supported by the plurality of substrate support pins 77 are equal. This makes it possible to equally divide the risk of the semiconductor wafer W cracking during flash light irradiation due to scratches on the semiconductor wafer W in a process prior to flash lamp annealing, and the risk of the semiconductor wafer W cracking during flash light irradiation due to scratches on the semiconductor wafer W caused by contact with the substrate support pins 77. As a result, cracking of the semiconductor wafer W during flash light irradiation can be minimized and the yield can be improved.

[0078] Here, it is possible to reduce the two types of stress acting on the semiconductor wafer W and suppress cracking of the semiconductor wafer W by increasing the number of substrate support pins 77 or by increasing the size of the substrate support pins 77 themselves. However, doing so would increase the total contact area between the semiconductor wafer W and the multiple substrate support pins 77, causing the contact points between the semiconductor wafer W and the substrate support pins 77 to become cold spots during the heat treatment, thus impairing the in-plane uniformity of the temperature distribution. For this reason, as in this embodiment, it is preferable to equalize the two types of stress acting on the semiconductor wafer W by adjusting the placement of the multiple substrate support pins 77 to minimize cracking of the semiconductor wafer W during flash light irradiation.

[0079] While embodiments of the present invention have been described above, various modifications can be made to this invention without departing from its spirit. For example, the size of the semiconductor wafer W is not limited to φ300 mm, but may be φ200 mm or φ450 mm, etc. Also, the number of substrate support pins 77 provided on the susceptor 74 is not limited to 12, but may be 6 or 8, for example. If the size of the semiconductor wafer W and / or the number of substrate support pins 77 are different, the distance r from the center of the semiconductor wafer W to the substrate support pins 77 at which the two types of stresses described above are equal will also be different from the above embodiment. That is, the substrate support pins 77 should be provided at an appropriate position at which the stress generated by the contact between the substrate support pins 77 and the semiconductor wafer W is equal to the stress generated by the deflection of the semiconductor wafer W.

[0080] Furthermore, although the flash heating unit 5 is equipped with 30 flash lamps FL in the above embodiment, the number of flash lamps FL is not limited to this, and can be any number. Also, the flash lamps FL are not limited to xenon flash lamps, but may be krypton flash lamps. Similarly, the number of halogen lamps HL provided in the halogen heating unit 4 is not limited to 40, but can be any number.

[0081] Furthermore, in the above embodiment, a filament-type halogen lamp HL was used as a continuous-lighting lamp that emitted light continuously for 1 second or more to perform the preheating treatment of the semiconductor wafer W. However, the invention is not limited to this, and a discharge-type arc lamp (for example, a xenon arc lamp) or an LED lamp may be used as a continuous-lighting lamp instead of the halogen lamp HL to perform the preheating treatment. [Explanation of symbols]

[0082] 1 Heat treatment apparatus 3. Control Unit 4. Halogen heating section 5. Flash heating section 6 chambers 7 Holding part 10 Transfer mechanism 20 Lower radiation thermometer 25 Upper radiation thermometer 63 Upper chamber window 64 Lower chamber window 65 Heat treatment space 74 Susceptors 75 Retaining plate 77 PCB support pins FL Flash Lamp HL Halogen Lamp W Semiconductor wafer

Claims

1. A susceptor for holding a substrate that is heated by flash light irradiation, A flat-shaped retaining plate, A plurality of support pins are erected on the upper surface of the retaining plate and contact the lower surface of the substrate at their upper ends to support the substrate, Equipped with, Each of the plurality of support pins is positioned at a location where the stress generated by the contact between the support pin and the substrate is equal to the stress generated by the deflection of the substrate.

2. A heat treatment apparatus for heating a substrate by irradiating it with a flash of light, A chamber for housing the circuit board, The susceptor according to claim 1, which holds the substrate within the chamber, A flash lamp that irradiates the substrate held by the susceptor with flash light, A heat treatment apparatus equipped with the following features.

Images