Threshold voltage regulation circuit and semiconductor integrated circuit

Abstract

This invention provides a threshold voltage adjustment circuit that allows for easy adjustment of the threshold voltage. [Solution] The threshold voltage adjustment circuit 10 includes a reference current circuit 20 and a transimpedance circuit 30. The reference current circuit 20 outputs a reference current formed on the substrate. The transimpedance circuit 30 has multiple resistors on the substrate and the threshold voltage V is expressed as a function of the combined resistance of the multiple resistors and external resistors and the reference current. TH Outputs.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a threshold voltage adjustment circuit and a semiconductor integrated circuit. [Background technology]

[0002] A commonly known method for detecting overcurrent in power elements is the non-saturated voltage detection method, which detects the non-saturated voltage of the power element. In the non-saturated voltage detection method, it is determined that an overcurrent has flowed through the power element when the non-saturated voltage of the power element exceeds a predetermined threshold voltage. In the non-saturated voltage detection method, it is necessary to adjust the threshold voltage value to various values ​​in order to accommodate various types of power elements and to resolve the trade-off between speeding up overcurrent detection operation and improving noise immunity. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 10473710 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a threshold voltage adjustment circuit that can easily adjust the threshold voltage, and a semiconductor integrated circuit equipped with the threshold voltage adjustment circuit. [Means for solving the problem]

[0005] The threshold voltage adjustment circuit of this embodiment includes a reference current circuit and a transimpedance circuit. The reference current circuit outputs a reference current formed on the substrate. The transimpedance circuit has multiple resistors on the substrate and outputs a threshold voltage expressed as a function of the reference current and the combined resistance of the multiple resistors and external resistors. [Brief explanation of the drawing]

[0006] [Figure 1] A circuit diagram showing the configuration of a semiconductor integrated circuit according to the first embodiment. [Figure 2] A timing chart showing the voltage waveforms of each terminal of the semiconductor integrated circuit of the first embodiment. [Figure 3] A circuit diagram showing the configuration of the threshold voltage adjustment circuit of the first embodiment. [Figure 4] A graph showing the calculated threshold voltage for the resistance value of an external resistor. [Figure 5] A circuit diagram showing a first modified example of the threshold voltage adjustment circuit. [Figure 6] A circuit diagram showing an example of a PTAT current source configuration. [Figure 7] A circuit diagram showing a second modified example of the threshold voltage adjustment circuit. [Figure 8] A circuit diagram showing a third modified example of the threshold voltage adjustment circuit. [Figure 9] A circuit diagram showing the configuration of a semiconductor integrated circuit according to the second embodiment. [Figure 10] A timing chart showing the voltage waveforms of each terminal of the semiconductor integrated circuit of the second embodiment. [Figure 11] A circuit diagram showing an example of the configuration of a threshold voltage detection circuit. [Figure 12] A circuit diagram showing an example of the configuration of a constant current source included in an overcurrent detection circuit. [Figure 13] A circuit diagram showing an example of a semiconductor integrated circuit 1A equipped with an insulating element. [Figure 14] A circuit diagram showing an example where the primary side chip is equipped with an insulating element. [Figure 15] A circuit diagram showing an example where an insulating chip equipped with an insulating element is placed between the primary and secondary side chips. [Figure 16] A circuit diagram showing an example where both the primary and secondary chips are equipped with insulating elements. [Figure 17] A circuit diagram showing the first example of a semiconductor integrated circuit equipped with an optical device as an insulating element. [Figure 18] A circuit diagram showing a second example of a semiconductor integrated circuit equipped with an optical device as an insulating element. [Modes for carrying out the invention]

[0007] The threshold voltage adjustment circuit and semiconductor integrated circuit of the embodiment will be described below with reference to the drawings.

[0008] (First embodiment) Figure 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit 1 according to the first embodiment. The semiconductor integrated circuit 1 is a gate drive circuit that drives the gate of a power element SW. In this embodiment, an IGBT is used as an example of a power element SW, but the power element SW that the semiconductor integrated circuit 1 drives may be other power elements such as Si-MOSFETs and SiC-MOSFETs.

[0009] As shown in Figure 1, the semiconductor integrated circuit 1 includes an input terminal P1, an output terminal P2, a power terminal P3, a ground terminal P4, an overcurrent detection terminal P5, a resistor connection terminal P6, a threshold voltage adjustment circuit 10, a comparator 11, an input buffer 12, a first output buffer 13, and an overcurrent detection circuit 14.

[0010] Input terminal P1 is a terminal to which timing signals for controlling the turn-on and turn-off timing of the power element SW are input. For example, the timing signal is a PWM signal. Output terminal P2 is a terminal that outputs a gate drive signal to drive the gate of the power element SW. The gate drive signal has approximately the same pulse width as the timing signal and has a larger amplitude than the timing signal. Output terminal P2 is electrically connected to the gate of the power element SW via gate resistor 2.

[0011] Power terminal P3 is at ground potential V GND Power supply potential V is a positive potential relative to this. CC2 This is the terminal to which the voltage is applied. The ground terminal P4 has a ground potential V GND This is the terminal to which the current is applied. The ground terminal P4 is electrically connected to ground and to the emitter of the power element SW.

[0012] The overcurrent detection terminal P5 is used to detect overcurrent in the power element SW by detecting detection current I CHG This is the output terminal. The overcurrent detection terminal P5 is electrically connected to the collector of the power element SW via resistor 3 and diode 4. The overcurrent detection terminal P5 is also electrically connected to ground via capacitor 5. One end of resistor 3 is electrically connected to the overcurrent detection terminal P5 and one end of capacitor 5, respectively. The other end of resistor 3 is electrically connected to the anode of diode 4. The cathode of diode 4 is electrically connected to the collector of the power element SW.

[0013] The resistor connection terminal P6 is a terminal for connecting an external resistor 6 to the semiconductor integrated circuit 1. One end of the external resistor 6 is electrically connected to the resistor connection terminal P6. The other end of the external resistor 6 is electrically connected to the ground terminal P4. Although Figure 1 shows the case where the external resistor 6 is connected between the resistor connection terminal P6 and the ground terminal P4, it is also possible that the external resistor 6 is connected between the resistor connection terminal P6 and the power supply terminal P3. The case where the external resistor 6 is connected between the resistor connection terminal P6 and the power supply terminal P3 will be explained later.

[0014] The threshold voltage adjustment circuit 10 is electrically connected to the power supply terminal P3, the ground terminal P4, the resistor connection terminal P6, and the non-inverting input terminal of the comparator 11. The threshold voltage adjustment circuit 10 controls the threshold voltage V TH This is output to the non-inverting input terminal of comparator 11. As will be described in detail later, the threshold voltage V output from the threshold voltage adjustment circuit 10 is output. TH This value changes depending on the resistance value of the external resistor 6 connected to the resistor connection terminal P6.

[0015] The inverting input terminal of comparator 11 is electrically connected to the overcurrent detection terminal P5. Comparator 11 is connected to the threshold voltage V output from threshold voltage adjustment circuit 10. TH The voltage of the overcurrent detection terminal P5 is compared with the voltage of the detection terminal V, and a signal indicating the comparison result is output to the overcurrent detection circuit 14. In the following explanation, the voltage of the overcurrent detection terminal P5 is compared with the voltage of the detection terminal V DESATmay be referred to as. For example, the comparator 11 has a detection terminal voltage V DESAT When it is below the threshold voltage V TH the comparator 11 outputs a signal of the first level to the overcurrent detection circuit 14. Also, when the detection terminal voltage V DESAT exceeds the threshold voltage V TH the comparator 11 outputs a signal of the second level to the overcurrent detection circuit 14. For example, the signal of the first level is a low-level signal, and the signal of the second level is a high-level signal.

[0016] For example, it is desirable that the comparator 11 be a hysteresis comparator. Although not shown in FIG. 1, it is desirable to arrange a low-pass filter, a voltage buffer, etc. between the inverting input terminal of the comparator 11 and the overcurrent detection terminal P5.

[0017] The input terminal of the input buffer 12 is electrically connected to the input terminal P1. The output terminal of the input buffer 12 is electrically connected to the input terminal of the first output buffer 13. The input buffer 12 is an example of an input circuit to which a timing signal is input via the input terminal P1. The input buffer 12 shapes the waveform of the timing signal input via the input terminal P1 and outputs the shaped timing signal to the first output buffer 13. It is desirable that a filter for removing glitches be mounted in the input buffer 12 when glitches occur at the input terminal P1. The input buffer 12 also outputs the shaped timing signal to the overcurrent detection circuit 14.

[0018] The output terminal of the first output buffer 13 is electrically connected to the output terminal P2. In addition to the timing signal output from the input buffer 12, the first output buffer 13 receives a first control signal output from the overcurrent detection circuit 14. When the level of the first control signal is low, the first output buffer 13 generates a gate drive signal in synchronization with the timing signal input via the input buffer 12 and outputs the gate drive signal via the output terminal P2.

[0019] The first output buffer 13 synchronizes with the timing signal to the ground potential V GND and power supply potential V CC2 It outputs a gate drive signal that changes between the following. The first output buffer 13 outputs a gate drive signal that changes between the following states, regardless of the timing signal, when the level of the first control signal is high. GND It outputs a gate drive signal having the following characteristics. The first output buffer 13 is an example of a first output circuit.

[0020] The overcurrent detection circuit 14 is electrically connected to the power terminal P3, the ground terminal P4, and the overcurrent detection terminal P5. The overcurrent detection circuit 14 receives the output signal from the comparator 11 and the timing signal output from the input buffer circuit 12. The overcurrent detection circuit 14 detects the rising edge of the timing signal input via the input circuit 12, and after a certain period of time has elapsed, detects the detected current I via the overcurrent detection terminal P5. CHG Outputs.

[0021] The overcurrent detection circuit 14 controls the first output buffer 13 so that after the output signal of the comparator 11 changes from a low level to a high level, a gate drive signal having a potential that turns the power element SW off is output. Specifically, the overcurrent detection circuit 14 controls the first output buffer 13 so that after the output signal of the comparator 11 changes from a low level to a high level, a gate drive signal having a potential that turns the power element SW off is output. GND The first output buffer 13 is controlled so that a gate drive signal having the following characteristics is output.

[0022] The overcurrent detection circuit 14 controls the first output buffer 13 by outputting a first control signal to the first output buffer 13. The overcurrent detection circuit 14 changes the first control signal from a low level to a high level after the output signal of the comparator 11 changes from a low level to a high level. As described above, when the level of the first control signal is high, the first output buffer 13 maintains the ground potential V regardless of the timing signal. GND It outputs a gate drive signal having the following characteristics.

[0023] The overcurrent detection circuit 14 comprises a constant current source 14a, a switch 14b, and a control circuit 14c. The constant current source 14a is electrically connected between the power supply terminal P3 and the switch 14b. The switch 14b is electrically connected between the constant current source 14a and the ground terminal P4. The connection point between the constant current source 14a and the switch 14b is electrically connected to the overcurrent detection terminal P5. The constant current source 14a detects current I CHG Outputs the detected current I from the constant current source 14a. CHG The timing of the output to the overcurrent detection terminal P5 is controlled by the control circuit 14c. Switch 14b is switched on or off by the control circuit 14c.

[0024] The control circuit 14c detects current I from the constant current source 14a based on the timing signal. CHG The timing of the output is controlled. The control circuit 14c switches switch 14b to the ON state or the OFF state based on the timing signal. The control circuit 14c outputs the first control signal to the first output buffer 13. The control circuit 14c sets the level of the first control signal to a high level or a low level based on the output signal of the comparator 11. The operation of the control circuit 14c will be described in detail below with reference to Figure 2.

[0025] Figure 2 is a timing chart showing the voltage waveforms at each terminal of the semiconductor integrated circuit 1. Specifically, the timing chart in Figure 2 shows the input terminal voltage V IN Output terminal voltage V OUT , and detection terminal voltage V DESAT The waveform is shown.

[0026] Input terminal voltage V IN The ground potential V GND This is the voltage at input terminal P1 relative to the reference. Input terminal voltage V IN This corresponds to the timing signal input to input terminal P1. Output terminal voltage V OUT The ground potential V GND This is the voltage at output terminal P2 relative to the reference. Output terminal voltage V OUTThis corresponds to the gate drive signal output from output terminal P2. Detection terminal voltage V DESAT The ground potential V GND This is the voltage of the overcurrent detection terminal P5, which is based on V. CC1 V is the high-level potential of digital signals such as timing signals. CC1 This is the power supply potential V applied to power supply terminal P3. CC2 Lower.

[0027] As shown in Figure 2, at time t1, the input terminal voltage V corresponding to the timing signal IN And the detection terminal voltage V DESAT And are at low levels (V GND Assume that the detection terminal voltage V is true. DESAT The threshold voltage V TH Since the following conditions apply, the output signal of comparator 11 is low level. At time t1, because the output signal of comparator 11 is low level, the control circuit 14c outputs a low-level first control signal to the first output buffer 13. When the level of the first control signal is low, the first output buffer 13 generates a gate drive signal in synchronization with the timing signal. As a result, at time t1, the output terminal voltage V corresponding to the gate drive signal is OUT Low level (V GND Therefore, the power element switch will be in the off state.

[0028] When the power element SW is in the off state, there is no need to detect overcurrent in the power element SW. Therefore, in this case, the control circuit 14c may disable the constant current source 14a and turn on the switch 14b, or it may turn on the switch 14b while keeping the constant current source 14a operating. The disabled state is when the detected current I from the constant current source 14a is turned on. CHG The output is not displayed. As a result, the detection terminal voltage V DESAT Ground potential V GND This is almost the same, so the charge from capacitor 5 is completely discharged.

[0029] At time t2, after time t1, the input terminal voltage V IN low level (V GND ) to high level (V CC1 When it changes to a predetermined transmission delay time T, PLH After the elapsed time, the output terminal voltage V OUT Low level (V GND ) to high level (V CC2 ) changes to this state. As a result, the power element SW switches from the off state to the on state.

[0030] When the power element SW is in the ON state, it is necessary to detect the overcurrent of the power element SW. Therefore, at time t2, the input terminal voltage V IN When it changes to a high level, the first waiting period T starts from time t2. DESAT(LEB) After the specified time has elapsed, the control circuit 14c enables the constant current source 14a and turns off the switch 14b, or turns off the switch 14b while keeping the constant current source 14a operating. The enabled state is defined as the detection current I from the constant current source 14a. CHG This is the state in which the output is generated. As a result, the detected current I is output from the overcurrent detection terminal P5. CHG The following will be output.

[0031] However, the output terminal voltage V OUT Even when the voltage changes from low to high, the power element SW does not immediately turn on. In other words, the output terminal voltage V OUT For a certain period after the voltage changes to a high level, the collector terminal voltage of the power element SW remains high, so diode 4 is biased in the reverse direction. As a result, the detected current I CHG The current flows through capacitor 5, so the detection terminal voltage V DESAT The ground potential V GND It rises from there.

[0032] Detection terminal voltage V DESAT The threshold voltage V TH Before reaching the target, when the power element SW is fully turned on, diode 4 is forward-biased. As a result, the detected current I CHGThe current flows through resistor 3 and diode 4 to the collector of power element SW, so the detection terminal voltage V DESAT It decreases. Detection terminal voltage V DESAT The value of the steady-state voltage V BLK(ON) When it reaches this point, while the power element SW is in the ON state, the detection terminal voltage V DESAT The value of is the steady-state voltage value V BLK(ON) It is held at a steady-state voltage value V. BLK(ON) This is expressed by the following equation (1). In the following equation (1), V CE(ON) V is the collector-emitter voltage of a power element SW in the ON state (saturated state), and F This is the forward voltage drop across diode 4, and R DESAT This is the resistance value of resistor 3.

[0033]

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[0034] At time t3, after time t2, the input terminal voltage V IN When the signal changes from a high level to a low level, a predetermined transmission delay time T occurs. PHL After the elapsed time, the output terminal voltage V OUT The level also changes from high to low. As a result, the power element switch switches from the on state to the off state.

[0035] As described above, when the power element SW is in the off state, there is no need to detect overcurrent in the power element SW. Therefore, at time t3, the input terminal voltage V IN When the voltage changes to a low level, the control circuit 14c may disable the constant current source 14a and turn on the switch 14b, or it may turn on the switch 14b while keeping the constant current source 14a operating. As a result, the charge from the capacitor 5 is completely discharged, so the detection terminal voltage V DESAT The value of is the steady-state voltage value V BLK(ON) From ground potential V GND Descending.

[0036] At time t4, after time t3, the input terminal voltage VIN When it changes from a low level to a high level, after a predetermined transmission delay time T PLH has elapsed, the output terminal voltage V OUT also changes from a low level to a high level. As a result, the power element SW switches from an off state to an on state.

[0037] Similar to the time t2, when the input terminal voltage V IN changes to a high level at time t4, after the first standby time T DESAT(LEB) has elapsed from time t4, the control circuit 14c enables the constant current source 14a and turns off the switch 14b, or turns off the switch 14b while operating the constant current source 14a. Here, assuming that an overcurrent flows through the power element SW, since the power element SW operates in a non-saturated state, the collector-emitter voltage of the power element SW increases. As a result, due to the diode 4 being reverse-biased, a detection current I CHG flows through the capacitor 5, so the detection terminal voltage V DESAT rises from the ground potential V GND

[0038] If an overcurrent continues to flow through the power element SW, the detection terminal voltage V DESAT continues to rise with the passage of time. And when the detection terminal voltage V DESAT exceeds the threshold voltage V TH the output signal of the comparator 11 changes from a low level to a high level.

[0039] When the detection terminal voltage V DESAT exceeds the threshold voltage V TH that is, at the time when the output signal of the comparator 11 changes to a high level, at time t5 when the second standby time T DESAT(FILTER) has elapsed, the control circuit 14c determines that an overcurrent has flowed through the power element SW and changes the first control signal output to the first output buffer 13 from a low level to a high level. The first output buffer 1, when the level of the first control signal is high, regardless of the timing signal, the ground potential V GND ​Outputs a gate drive signal having the following. Therefore, from the time when the detection terminal voltage V DESAT exceeds the threshold voltage V TH , after the elapse of the second standby time T DESAT(FILTER) , the output terminal voltage V OUT changes from the high level to the low level. As a result, when an overcurrent flows through the power element SW, the power element SW is forcibly switched to the off state.

[0040] When forcibly switching the power element SW to the off state, it is desirable to implement a soft turn-off function in the first output buffer 13 that slowly changes the output terminal voltage V OUT to the low level so that the power element SW slowly switches to the off state.

[0041] Also, from the time when the detection terminal voltage V DESAT exceeds the threshold voltage V TH , after the elapse of the second standby time T DESAT(FILTER) , the control circuit 14c disables the constant current source 14a and turns on the switch 14b, or turns on the switch 14b while operating the constant current source 14a. As a result, since the charge is completely discharged from the capacitor 5, the value of the detection terminal voltage V DESAT rapidly drops to the ground potential V GND .

[0042] As described above, even when no overcurrent flows through the power element SW, the collector terminal voltage of the power element SW is maintained at a high state for a certain period after the output terminal voltage V[[ID=3thirty]] OUT changes from the low level to the high level, so the diode 4 is reverse-biased. As a result, the detection current I CHG flows into the capacitor 5, so the detection terminal voltage V DESAT rises from the ground potential V GND . Therefore, the capacitance C of the capacitor 5 BLK needs to be set so that the detection terminal voltage V DESAT , does not exceed the threshold voltage V TH during the period when the normally operating power element SW switches from the off state to the on state.

[0043] For example, the capacitance C of capacitor 5 should satisfy equation (2) below. BLK is set. In equation (2) below, T BLK This blanking time T is called the blanking time. BLK The time must be set to be shorter than the short-circuit withstand capability of the power element switch, and longer than the on-time of the power element switch. Here, the on-time of the power element switch is the time it takes for the power element switch to switch from the off state to the on state.

[0044]

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[0045] When noise generated from the power element SW is applied to the overcurrent detection terminal P5, the detection terminal voltage V is elevated even though no overcurrent is occurring. DESAT The threshold voltage V TH This can sometimes be exceeded. In other words, noise generated from the power element SW can cause the overcurrent detection circuit 14 to incorrectly detect the occurrence of an overcurrent. In this case, even though the power element SW is functioning normally, the power element SW is forcibly switched to the off state. To avoid such false detection of overcurrent caused by noise, the above-mentioned first waiting time T DESAT(LEB) and second waiting time T DESAT(FILTER) It is set.

[0046] A low-pass filter consisting of resistor 3, diode 4, and capacitor 5 exists between the overcurrent detection terminal P5 and the collector of the power element SW. However, for high-frequency noise, the junction capacitance (CJ) of diode 4 and the capacitance C of capacitor 5 are used. BLK The divided voltage is applied to the overcurrent detection terminal P5. Therefore, the capacitance C of capacitor 5 BLK Increasing the blanking time T is also an effective way to improve noise immunity. However, BLK Since the voltage needs to be shorter than the short-circuit withstand capability of the power element SW, the capacitance C of capacitor 5 BLKThere is a limit to how much we can increase it. Also, the capacitance C of capacitor 5 BLK Increasing V hinders the speed of overcurrent detection. Also, connecting diode 4 in series to reduce junction capacitance is an effective way to improve noise immunity, but V BLK(ON) Concerns include rising costs and an increase in the number of parts.

[0047] Thus, there is a trade-off between speeding up overcurrent detection operation and improving noise immunity. Therefore, taking this trade-off into consideration, the detection terminal voltage V should be set within the period during which a normally functioning power element SW switches from the off state to the on state. DESAT The threshold voltage V TH The capacitance C of capacitor 5 should not exceed this value. BLK It is necessary to set this. Also, the required threshold voltage V depends on the type of power element SW. TH Since they are different, the threshold voltage V TH When configuring this, you need to consider the type of power element switch.

[0048] As described above, in order to accommodate various types of power element switches, and to resolve the trade-off between speeding up overcurrent detection operation and improving noise immunity, the threshold voltage V TH The value of needs to be adjusted to various values.

[0049] The threshold voltage V output from the threshold voltage adjustment circuit 10 of this embodiment TH This changes according to the resistance value of the external resistor 6 connected to the resistor connection terminal P6. In other words, according to the threshold voltage adjustment circuit 10 of this embodiment, the threshold voltage V can be easily adjusted by simply changing the resistance value of the external resistor 6. TH The threshold voltage V can be adjusted. Referring to Figure 3 below, the threshold voltage V can be easily adjusted using such a simple method. TH The configuration of the threshold voltage adjustment circuit 10, which can be adjusted, will be described in detail.

[0050] Figure 3 is a circuit diagram showing the configuration of the threshold voltage adjustment circuit 10. As shown in Figure 3, the threshold voltage adjustment circuit 10 comprises a reference current circuit 20 and a transimpedance circuit 30. The reference current circuit 20 is formed on the substrate and contains a reference current I REF The transimpedance circuit 30 has a first current mirror circuit and multiple resistors on the above board, and outputs the combined resistance of the multiple resistors and the external resistor 6 and the reference current I REF The threshold voltage V is expressed as a function of the function of TH The output is as follows: For example, the substrate in this embodiment is a silicon substrate.

[0051] The reference current circuit 20 comprises a reference voltage circuit 21 and a first voltage-controlled current source 22. The reference voltage circuit 21 controls the reference voltage V BG The first voltage-controlled current source 22 outputs the reference voltage V. For example, the reference voltage circuit 21 is a BGR (Bandgap Reference) circuit. The first voltage-controlled current source 22 outputs the reference voltage V BG A first current I1 proportional to the reference current I REF It outputs as follows: In other words, the reference current I output from the reference current circuit 20. REF This is equal to the first current I1 output from the first voltage-controlled current source 22.

[0052] The first voltage-controlled current source 22 comprises an operational amplifier 22a, a resistor 22b, and a MOSFET element 22c. For example, the MOSFET element 22c is an N-channel MOSFET. The non-inverting input terminal of the operational amplifier 22a is electrically connected to the output terminal of the reference voltage circuit 21. The reference voltage V output from the reference voltage circuit 21 BG This is input to the non-inverting input terminal of the operational amplifier 22a. The inverting input terminal of the operational amplifier 22a is electrically connected to the source of the MOSFET element 22c. The output terminal of the operational amplifier 22a is electrically connected to the gate of the MOSFET element 22c.

[0053] One end of resistor 22b is electrically connected to the source of MOSFET element 22c. The other end of resistor 22b is electrically connected to the ground terminal P4. The drain of MOSFET element 22c is electrically connected to the transimpedance circuit 30. The current flowing from the drain of MOSFET element 22c towards resistor 22b is the first current I1, i.e., the reference current I REF That is the case.

[0054] The transimpedance circuit 30 comprises a first current mirror circuit 31, a resistor 32, a resistor 33, a resistor 34, and a threshold voltage output terminal 35. In other words, the transimpedance circuit 30 of this embodiment has three resistors 32, 33, and 34 as a plurality of resistors.

[0055] The first current mirror circuit 31 is electrically connected to the power supply terminal P3. The input terminal of the first current mirror circuit 31 is electrically connected to the drain of the MOSFET element 22c of the first voltage-controlled current source 22. The first current mirror circuit 31 controls the reference current I REF The input is a reference current I REF The current I multiplied by OUT It outputs the following. For example, the first current mirror circuit 31 outputs the reference current I REF N1 times the current I OUT The output is as follows: N1 is the current mirror ratio.

[0056] One end of resistor 32 is electrically connected to the output terminal of the first current mirror circuit 31. The other end of resistor 32 is electrically connected to one end of external resistor 6 via resistor 34 and resistor connection terminal P6. Resistor 32 is an example of a first resistor. One end of resistor 33 is electrically connected to the other end of resistor 32. The other end of resistor 33 is electrically connected to the other end of external resistor 6 via ground terminal P4. Resistor 33 is an example of a second resistor.

[0057] One end of resistor 34 is electrically connected to the connection point between resistors 32 and 33. The other end of resistor 34 is electrically connected to one end of external resistor 6 via resistor connection terminal P6. Resistor 34 is not essential; the transimpedance circuit 30 may have only resistors 32 and 33 as multiple resistors. The threshold voltage output terminal 35 outputs the threshold voltage V TH This is the output terminal and is electrically connected to one end of resistor 32. The threshold voltage output terminal 35 is electrically connected to the non-inverting input terminal of comparator 11 shown in Figure 1.

[0058] In the threshold voltage adjustment circuit 10 configured as described above, the reference current I output from the reference current circuit 20 REF This is expressed by equation (3) below. In equation (3) below, ΔV BG The reference voltage V BG This is the variation ratio, where R1 is the resistance value of resistor 22b, and ΔR is the variation ratio of the resistance values ​​of each resistor formed inside the semiconductor integrated circuit 1. However, considering that the arrangement and size of each resistor are determined in order to achieve sufficient mismatch performance within the same semiconductor integrated circuit 1, the variation ratio of the resistance values ​​of each resistor is set to be the same.

[0059]

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[0060] The threshold voltage V output from the transimpedance circuit 30 TH This is expressed by equation (4) below. In equation (4) below, ΔN1 is the variation ratio of the current mirror ratio N1 of the first current mirror circuit 31, and R T This is the combined resistance of resistors 32, 33, 34, and the external resistor 6. As can be understood from equation (4) below, the threshold voltage V TH The combined resistance R of resistors 32, 33, 34, and external resistor 6 is... T And, reference current I REF It can be expressed as a function of .

[0061]

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[0062] In equation (4) above, ΔR≪1, ΔN1≪1, and ΔV BG Assuming 1, equation (4) above can be transformed into equation (5) below. In equation (5) below, R2 is the resistance value of resistor 32, R3 is the resistance value of resistor 33, R4 is the resistance value of resistor 34, and R EXT This is the resistance value of external resistor 6.

[0063]

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[0064] In equation (5) above, ε is the threshold voltage V TH This is the variation ratio and is expressed by equation (6) below.

[0065]

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[0066] Now, let's consider ε. ε is ΔR, ΔV BG And it can be expressed as the sum of the squares of ΔN1, but considering the relationship between their magnitudes, ΔV BG And while ΔN1 is 2-3%, ΔR, which is the variation ratio of the resistance values ​​of each resistor, is 12-15%. However, ΔV BG And ΔN1 directly affects ε, but ΔR takes the form of a coefficient. This coefficient is R3 / R2, R4 / R2, and R, which are normalized by R2. EXT It can be described using three variables: / R2.

[0067] To simplify the discussion, if we assume R4 = 0, then equation (6) above can be simplified to equation (7) below.

[0068]

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[0069] From equation (7) above, ε is R3 / R2 and R EXT It can be seen that this can be described using two variables, / R2. In equation (7) above, the more important point is R EXT / R2=0 and R EXT When R² = ∞, the coefficient of ΔR becomes 0, and it is a point that does not depend on ε. The threshold voltage V at this point is TH Calculating this from equation (5) above, we get equation (8) below.

[0070]

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[0071] From equation (8) above, the resistance value R of the external resistor 6 is EXT If is 0 or infinite, the threshold voltage V does not affect ΔR. TH It can be seen that it can be adjusted. Next, R EXT We calculate ε when R2 is a finite value. From equation (7) above, ε is R3 / R2 and R EXT It can be described using two variables, / R2, and from equation (8) above, R EXT / R2 determines the threshold voltage V TH This can be adjusted. Therefore, this problem reduces to the question of what R3 / R2 should be chosen to minimize ε. Here, equation (7) is R EXT Differentiating with respect to this gives equation (9) below.

[0072]

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[0073] Since ε represents the maximum or minimum value under the condition that equation (9) above is 0, ε will be the maximum or minimum value under the condition expressed in equation (10) below.

[0074]

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[0075] By substituting equation (10) above into equation (7) above, the maximum or minimum value of ε can be calculated. Maximum value of ε MAX This is expressed by equation (11) below.

[0076]

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[0077] As can be seen from equation (11) above, ε MAX Since is a monotonically increasing function with respect to R3 / R2, setting R3 / R2 to a small value reduces the coefficient of ΔR, thereby reducing the effect of ΔR on ε. On the other hand, as can be seen from equation (8) above, setting R3 / R2 to a small value, R EXT V by TH The range of change becomes narrower. Therefore, according to equation (8), the threshold voltage V TH By determining the range of change and selecting the smallest R3 / R2 within that range, an optimal design can be achieved.

[0078] As an example, the resistance value R of external resistor 6 EXT The threshold voltage V TH Let's consider the case where the range of change is determined to be in the range of 6[V] to 10[V]. According to equation (8) above, the threshold voltage V TH The relationship between R3 and R2 is expressed by equation (12) below.

[0079]

number

[0080] Threshold voltage V TH If the range of change is determined to be in the range of 6[V] to 10[V], then from equation (12) above, R3 / R2 = 2 / 3. Furthermore, V BG If we set the voltage to 1.2[V] and N1=2, then according to equation (8), R2 / R1=2.5. Here, if we set R2=60[kΩ], then R1=24[kΩ] and R3=40[kΩ].

[0081] Figure 4 shows R1=24[kΩ], R2=60[kΩ], R3=40[kΩ], V BG Assuming =1.2[V], N1=2, and ΔR=15[%], the resistance value of external resistor 6 is R EXT Threshold voltage V TH And the resistance value R of external resistor 6 EXT Threshold voltage V TH This graph shows the results of calculating the variation ratio ε. In Figure 4, the solid line curve C1 represents the threshold voltage V TH The curve C2, represented by the dashed line, shows the threshold voltage V TH This shows the variation ratio ε.

[0082] When the power element SW is an IGBT or Si-MOSFET, the threshold voltage V TH A threshold voltage of approximately 6.5[V] is often used. When the power element SW is a SiC-MOSFET, the threshold voltage V TH A value of approximately 9.5[V] is often used. As shown in Figure 4, the resistance value R of the external resistor 6 EXT When the resistance is 5.7 [kΩ], the threshold voltage V TH The voltage is 6.5[V]. The resistance value of external resistor 6 is R. EXT When the resistance is 280 [kΩ], the threshold voltage V TH The voltage is 9.5[V]. Thus, the resistance value R of external resistor 6 EXT By simply changing the threshold voltage V, the voltage value will be adjusted to match the voltage value required for each type of power element SW. TH This can be adjusted. Note that the resistance value R of external resistor 6. EXT When the resistance is 31 kΩ, the threshold voltage V TH The variation ratio ε reaches its maximum value (approximately 1.9%), but it can be seen that it is reduced to about 1 / 8 of the variation ratio ΔR (15%) of each resistor.

[0083] Furthermore, as shown in Figure 4, the resistance value R of the external resistor 6. EXT By changing the threshold voltage V TH The threshold voltage can be adjusted within the range of 6[V] to 10[V]. For example, if the power element SW is an IGBT or Si-MOSFET, the threshold voltage V THIt can be set to 6[V] or 7[V]. If the power element SW is a SiC-MOSFET, the threshold voltage V TH This can be set to 9[V] or 10[V]. This allows the capacitance C of capacitor 5 to be adjusted. BLK It can accommodate various power elements without changing the settings.

[0084] The threshold voltage adjustment circuit 10 of this embodiment uses a reference current I REF A reference current circuit 20 that outputs a reference current, and a combined resistance R of the multiple resistors and the external resistor 6, which has multiple resistors. T and reference current I REF The threshold voltage V is expressed as a function of the function of TH The circuit includes a transimpedance circuit 30 that outputs a threshold voltage adjustment circuit 10. According to such a threshold voltage adjustment circuit 10, the resistance value R of the external resistor 6 EXT The threshold voltage V can be easily changed using a simple method. TH It can be adjusted.

[0085] According to this embodiment, the threshold voltage V TH The influence of the variation ratio ΔR of the resistance values ​​of each resistor on the variation ratio ε of the threshold voltage V can be minimized. In other words, the manufacturing variation of the resistance values ​​of each resistor does not affect the threshold voltage V TH Since fluctuations are suppressed, the threshold voltage V is close to the required voltage value. TH It can be obtained stably.

[0086] As already explained, in order to accommodate various types of (individual-variable) power element switches, and to resolve the trade-off between faster overcurrent detection operation and improved noise immunity, the threshold voltage V TH The value of needs to be adjusted to various values. According to the semiconductor integrated circuit 1 of this embodiment, the resistance value R of the external resistor 6 EXT The threshold voltage V can be easily changed using a simple method. TH Since it is equipped with a threshold voltage adjustment circuit 10 that can be adjusted to various values, it can be used with various types of power element switches, and at the same time achieve high-speed overcurrent detection operation and improved noise immunity.

[0087] In the semiconductor integrated circuit 1 of this embodiment, the first output buffer 13 synchronizes with the timing signal to the ground potential V GND and power supply potential V CC2 It outputs a gate drive signal that changes between the following. The overcurrent detection circuit 14 detects the ground potential V after the output signal of the comparator 11 changes from a low level to a high level. GND The first output buffer 13 is controlled so that a gate drive signal having the following characteristics is output. According to this embodiment, if an overcurrent occurs in the power element SW (in the event of an abnormality), the power element SW is reliably and forcibly switched to the off state, thereby preventing the occurrence of failures caused by overcurrent.

[0088] In this embodiment, a first current mirror circuit 31 referenced to the power supply terminal P3 is illustrated, but the first current mirror circuit 31 may be configured using a circuit referenced to the internal power supply. Also, in this embodiment, a first voltage-controlled current source 22 composed of an operational amplifier 22a, a resistor 22b, and a MOSFET element 22c is illustrated, but the circuit configuration of the first voltage-controlled current source 22 is not limited to the configuration of this embodiment, as long as it has input / output characteristics equivalent to that of the first voltage-controlled current source 22. Furthermore, although not shown in Figure 3, it is desirable to place an ESD protection element at an appropriate location inside the threshold voltage adjustment circuit 10.

[0089] Figure 5 is a circuit diagram showing the configuration of threshold voltage adjustment circuit 10A, which is a first modified example of threshold voltage adjustment circuit 10. In the following description, components of threshold voltage adjustment circuit 10A that are the same as those of threshold voltage adjustment circuit 10 are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0090] As shown in Figure 5, the threshold voltage adjustment circuit 10A comprises a reference current circuit 20A and a transimpedance circuit 30. The reference current circuit 20A comprises a reference current I REFAlthough it is the same as the reference current circuit 20 in that it outputs the same current, it has a different circuit configuration than the reference current circuit 20. The reference current circuit 20A comprises a reference voltage circuit 21, a first voltage-controlled current source 22, a PTAT (Proportional to Absolute Temperature) current source 23, and a second current mirror circuit 24.

[0091] The PTAT current source 23 is electrically connected to the second current mirror circuit 24 and the ground terminal P4. The PTAT current source 23 outputs a second current I2 that is proportional to the absolute temperature. The second current mirror circuit 24 is electrically connected to the power supply terminal P3. The input terminal of the second current mirror circuit 24 is electrically connected to the PTAT current source 23. The second current mirror circuit 24 takes the second current I2 as input and outputs a third current I3 that is a multiple of the second current I2. For example, the second current mirror circuit 24 outputs a third current I3 that is N2 times the second current I2, where N2 is the current mirror ratio.

[0092] The output terminal of the second current mirror circuit 24 is electrically connected to the drain of the MOSFET element 22c of the first voltage-controlled current source 22 and to the input terminal of the first current mirror circuit 31 of the transimpedance circuit 30. That is, the reference current circuit 20A uses the difference between the first current I1 output from the first voltage-controlled current source 22 and the third current I3 output from the second current mirror circuit 24 as the reference current I REF It outputs as follows. In other words, the first current mirror circuit 31 of the transimpedance circuit 30 has a reference current I represented by the difference between the first current I1 and the third current I3. REF The following is input: The first current I1 is greater than the third current I3.

[0093] Figure 6 is a circuit diagram showing an example of the configuration of the PTAT current source 23. As shown in Figure 6, the PTAT current source 23 comprises four transistors 23a, 23b, 23c, and 23d, and two resistors 23e and 23f. For example, transistors 23a, 23b, 23c, and 23d are NPN bipolar transistors.

[0094] The collector of transistor 23a is electrically connected to the power supply terminal P3 via resistor 23e. The base of transistor 23a is electrically connected to the collector of transistor 23a and the base of transistor 23c. The collector of transistor 23b is electrically connected to the emitter of transistor 23a and the base of transistor 23d. The collector of transistor 23d is electrically connected to the emitter of transistor 23c and the base of transistor 23b. The emitter of transistor 23b is electrically connected to the ground terminal P4.

[0095] The collector of transistor 23c is electrically connected to the input terminal of the second current mirror circuit 24. The emitter of transistor 23d is electrically connected to the ground terminal P4 via resistor 23f. The current flowing from the collector of transistor 23c to the ground terminal P4 is the second current I2.

[0096] The second current I2 output from the PTAT current source 23 is expressed by equation (13) below. In equation (13) below, V T is the thermal voltage, k is the size ratio of transistors 23b and 23d, and R5 is the resistance value of resistor 23f. The resistance value of resistor 23e does not affect the second current I2. Therefore, a resistor element with a different sheet resistance than the other resistors 23f, 22b, 32, 33, and 34 may be used as resistor 23e.

[0097]

number

[0098] As represented by the following formula (14), the reference current I output from the reference current circuit 20A REF is represented by the difference between the first current I1 output from the first voltage - controlled current source 22 and the third current I3 output from the second current mirror circuit 24.

[0099]

Equation

[0100] As represented by the following formula (15), the current I output from the first current mirror circuit 31 of the trans - impedance circuit 30 OUT is the current which is N1 times the reference current I represented by formula (14). REF

[0101]

Equation

[0102] When substituting formula (3) into formula (15) as the first current I1 output from the first voltage - controlled current source 22 and substituting formula (13) into formula (15) as the second current I2 output from the PTAT current source 23, the following formula (16) is obtained.

[0103]

Equation

[0104] The threshold voltage V output from the trans - impedance circuit 30 TH is calculated by multiplying the output current I of the first current mirror circuit 31 OUT by the combined resistance R of the resistors 32, 33, 34, and the external resistor 6. Assuming ΔR≪1, ΔN1≪1, ΔN2≪1, and ΔV T ≪1, the threshold voltage V BG is represented by the following formula (17). In the following formula (17), R2 is the resistance value of the resistor 32, R3 is the resistance value of the resistor 33, R4 is the resistance value of the resistor 34, and R TH ​​EXT This is the resistance value of external resistor 6.

[0105]

number

[0106] In equation (17) above, ε T This is expressed by equation (18) below.

[0107]

number

[0108] To simplify the discussion, if we assume R4 = 0, equation (18) above can be simplified to equation (19) below.

[0109]

number

[0110] From equation (19) above, similar to the threshold voltage adjustment circuit 10, the threshold voltage V is determined by the variation ratio ΔR of the resistance values ​​of each resistor. TH Since fluctuations are suppressed, the threshold voltage V can be changed by changing the ratio of the first current I1 to the second current I2. TH An arbitrary negative temperature characteristic can be assigned to it. The temperature coefficient is T. C1 If we define , then equation (17) above can be written as equation (20) below.

[0111]

number

[0112] In equation (20) above, the temperature coefficient T C1 This is expressed by equation (21) below. As can be seen from equation (21) below, according to the threshold voltage adjustment circuit 10A, the threshold voltage V TH An arbitrary negative temperature characteristic can be imparted to it.

[0113] [Number]

[0114] According to the threshold voltage adjustment circuit 10A having such a configuration, the threshold voltage V can be easily adjusted by a simple method of only changing the resistance value R of the external resistor 6. EXT In addition to being able to adjust it, an arbitrary negative temperature characteristic can be imparted to the threshold voltage V. TH Normally, the threshold voltages of power devices SW such as IGBTs, Si-MOSFETs, and SiC-MOSFETs have a negative temperature characteristic. Therefore, by imparting a negative temperature characteristic to the threshold voltage V output from the threshold voltage adjustment circuit 10A to the comparator 11, the overcurrent detection sensitivity at high temperatures can be improved, and as a result, a safer overcurrent protection operation can be realized. TH TH

[0115] In the first modification example, the second current mirror circuit 24 with reference to the power supply terminal P3 is illustrated, but the second current mirror circuit 24 may be constituted by a circuit with reference to an internal power supply. Also, in the first modification example, the PTAT current source 23 constituted by four NPN bipolar transistors and two resistors is illustrated, but the circuit configuration of the PTAT current source 23 is not limited to the configuration of the first modification example as long as it is a circuit having input / output characteristics equivalent to those of the PTAT current source 23. Also, although not illustrated in FIG. 5, it is desirable to arrange an ESD protection element at an appropriate position inside the threshold voltage adjustment circuit 10A.

[0116] FIG. 7 is a circuit diagram showing the configuration of a threshold voltage adjustment circuit 10B, which is a second modification example of the threshold voltage adjustment circuit 10. In the following description, among the components included in the threshold voltage adjustment circuit 10B, the same components as those included in the threshold voltage adjustment circuit 10A are denoted by the same reference numerals, and the description thereof is omitted or simplified.

[0117] ​​As shown in Figure 7, the threshold voltage adjustment circuit 10B comprises a reference current circuit 20B and a transimpedance circuit 30. The reference current circuit 20B comprises a reference current I REF Although it is the same as the reference current circuit 20A in that it outputs a current, it has a different circuit configuration from the reference current circuit 20A. The reference current circuit 20B comprises a reference voltage circuit 21, a first voltage-controlled current source 22, and a PTAT current source 23.

[0118] The PTAT current source 23 is electrically connected to the drain of the MOSFET element 22c and to the ground terminal P4, respectively. The PTAT current source 23 outputs a second current I2 that is proportional to the absolute temperature. That is, the reference current circuit 20B defines the current as the sum of the first current I1 output from the first voltage-controlled current source 22 and the second current I2 output from the PTAT current source 23 as the reference current I REF It outputs as follows. In other words, the first current mirror circuit 31 of the transimpedance circuit 30 has a reference current I represented by the sum of the first current I1 and the second current I2. REF The following is input. In this case, the current I output from the first current mirror circuit 31 is input. OUT This is expressed by equation (22) below.

[0119]

number

[0120] Substituting equation (3) into equation (22) as the first current I1 output from the first voltage-controlled current source 22, and substituting equation (13) into equation (22) as the second current I2 output from the PTAT current source 23, we obtain the following equation (23).

[0121]

number

[0122] The threshold voltage V output from the transimpedance circuit 30 TH This is the output current I of the first current mirror circuit 31. OUTThe combined resistance R of resistors 32, 33, 34, and external resistor 6. T It is calculated by multiplying by ΔR≪1, ΔN1≪1, and ΔV BG Assuming it is 1, the threshold voltage V TH This is expressed by equation (24) below. In equation (24) below, R2 is the resistance value of resistor 32, R3 is the resistance value of resistor 33, R4 is the resistance value of resistor 34, and R EXT This is the resistance value of external resistor 6.

[0123]

number

[0124] In equation (24) above, ε T This is expressed by equation (25) below.

[0125]

number

[0126] Similar to the first modified example, the temperature coefficient T C1 If we define this, the temperature coefficient T in the second modified example is C1 This is expressed by equation (26) below. As can be seen from equation (26) below, according to the threshold voltage adjustment circuit 10B, the threshold voltage V TH An arbitrary positive temperature characteristic can be assigned to it.

number

[0127] According to the threshold voltage adjustment circuit 10B having such a configuration, the resistance value R of the external resistor 6 EXT The threshold voltage V can be easily changed using a simple method. TH In addition to being able to adjust the threshold voltage V THAn arbitrary positive temperature characteristic can be imparted to it. For example, a PTC (Positive Temperature Coefficient) thermistor is sometimes used for overheat protection of a three-phase induction motor. A PCT thermistor is a device in which the resistance value increases sharply when it exceeds the Curie temperature, and its IV characteristic depends on the ambient temperature. That is, the voltage at which the trip current is generated has a positive temperature characteristic with respect to the ambient temperature. For this reason, it is desirable that the threshold voltage of the circuit that detects the state of the PCT thermistor has a positive temperature characteristic. The second modified threshold voltage adjustment circuit 10B is particularly suitable for the above-mentioned application examples.

[0128] Furthermore, similar to the first modification, the circuit configuration of the PTAT current source 23 in the second modification is not limited to the configuration of the first modification. Also, although not shown in Figure 7, it is desirable to place an ESD protection element at an appropriate location inside the threshold voltage adjustment circuit 10B.

[0129] Figure 8 is a circuit diagram showing the configuration of a threshold voltage adjustment circuit 10C, which is a third modified example of the threshold voltage adjustment circuit 10. In the following description, components of the threshold voltage adjustment circuit 10C that are the same as those of the threshold voltage adjustment circuit 10 are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0130] As shown in Figure 8, the threshold voltage adjustment circuit 10C comprises a reference current circuit 20 and a transimpedance circuit 30C. The transimpedance circuit 30C controls the threshold voltage V which changes according to the resistance value of the external resistor 6. TH Although it is the same as the transimpedance circuit 30 in that it outputs a voltage, it has a different circuit configuration from the transimpedance circuit 30. The transimpedance circuit 30C comprises a resistor 32, a resistor 33, a resistor 34, a threshold voltage output terminal 35, a second voltage-controlled current source 36, and a resistor 37. In the example shown in Figure 8, an external resistor 6 is connected between the resistor connection terminal P6 and the power supply terminal P3.

[0131] One end of resistor 32 is electrically connected to one end of external resistor 6 via power terminal P3. The other end of resistor 32 is electrically connected to the other end of external resistor 6 via resistor 34 and resistor connection terminal P6. One end of resistor 33 is electrically connected to the other end of resistor 32. The other end of resistor 33 is electrically connected to the output terminal of the first voltage-controlled current source 22 of the reference current circuit 20. That is, the other end of resistor 33 is electrically connected to the drain of the MOSFET element 22c of the first voltage-controlled current source 22.

[0132] One end of resistor 34 is electrically connected to the connection point between resistors 32 and 33. The other end of resistor 34 is electrically connected to the other end of external resistor 6 via resistor connection terminal P6. Resistor 34 is not essential; the transimpedance circuit 30C may have only resistors 32 and 33 as multiple resistors.

[0133] The second voltage-controlled current source 36 controls a current I proportional to the voltage at the resistor connection terminal P6. OUT The second voltage-controlled current source 36 comprises an operational amplifier 36a, a resistor 36b, and a MOSFET element 36c. For example, the MOSFET element 36c is a P-channel MOSFET. The non-inverting input terminal of the operational amplifier 36a is electrically connected to the resistor connection terminal P6. That is, the voltage of the resistor connection terminal P6 is input to the non-inverting input terminal of the operational amplifier 36a. The inverting input terminal of the operational amplifier 36a is electrically connected to the source of the MOSFET element 36c. The output terminal of the operational amplifier 36a is electrically connected to the gate of the MOSFET element 36c.

[0134] One end of resistor 36b is connected to the power supply potential V. CC2It is electrically connected to the power supply terminal P3 to which the current is applied. The other end of resistor 36b is electrically connected to the source of MOSFET element 36c. One end of resistor 37 is electrically connected to the output terminal of the second voltage-controlled current source 36. Specifically, one end of resistor 37 is electrically connected to the drain of MOSFET element 36c. The other end of resistor 37 is electrically connected to the ground terminal P4. The current flowing from the drain of MOSFET element 36c to resistor 37 is the output current I of the second voltage-controlled current source 36. OUT The threshold voltage output terminal 35 outputs the threshold voltage V TH This is the output terminal and is electrically connected to one end of resistor 37. In the third modified example, resistor 32 is an example of the first resistor, resistor 33 is an example of the second resistor, and resistor 37 is an example of the third resistor.

[0135] The threshold voltage V output from the transimpedance circuit 30C TH This is expressed by equation (27) below. In equation (27) below, R2 is the resistance value of resistor 32, R3 is the resistance value of resistor 33, R4 is the resistance value of resistor 34, R7 is the resistance value of resistor 36b, R8 is the resistance value of resistor 37, and R EXT This is the resistance value of external resistor 6.

[0136]

number

[0137] As can be seen by comparing equation (27) and equation (5), in the third modified example, the threshold voltage V TH Equation (27), which represents this, is obtained by replacing N1 in equation (5) with R8 / R7. Thus, it can be seen that the threshold voltage adjustment circuit 10C of the third modified example can achieve the same effect as the threshold voltage adjustment circuit 10.

[0138] According to the third modified example, the threshold voltage adjustment circuit 10C, the same effect as the threshold voltage adjustment circuit 10 can be obtained. That is, according to the threshold voltage adjustment circuit 10C, the resistance value R of the external resistor 6 EXTThe threshold voltage V can be easily changed using a simple method. TH The threshold voltage V can be adjusted. Also, according to the threshold voltage adjustment circuit 10C, the threshold voltage V TH The influence of the variation ratio ΔR of the resistance values ​​of each resistor on the variation ratio ε can be minimized.

[0139] In the third modified example, a second voltage-controlled current source 36 composed of an operational amplifier 36a, a resistor 36b, and a MOSFET element 36c is shown as an example. However, the circuit configuration of the second voltage-controlled current source 36 is not limited to the configuration of the third modified example, as long as it has input / output characteristics equivalent to that of the second voltage-controlled current source 36. Also, although not shown in Figure 8, it is desirable to place an ESD protection element at an appropriate location inside the threshold voltage adjustment circuit 10C.

[0140] (Second embodiment) Figure 9 is a circuit diagram showing the configuration of the semiconductor integrated circuit 1A of the second embodiment. In the following description, components described in the second embodiment that are the same as those described in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0141] Similar to the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 1A of the second embodiment includes an input terminal P1, an output terminal P2, a power supply terminal P3, a ground terminal P4, an overcurrent detection terminal P5, a resistor connection terminal P6, a threshold voltage adjustment circuit 10, a comparator 11, an input buffer 12, a first output buffer 13, and an overcurrent detection circuit 14. Furthermore, the semiconductor integrated circuit 1A includes a negative power supply terminal P7, an abnormality notification terminal P8, an ULVO (Under Voltage Lock-Out) circuit 15, and a second output buffer 16.

[0142] Note that in Figure 9, the constant current source 14a, switch 14b, and control circuit 14c included in the overcurrent detection circuit 14 are not shown. Also, the semiconductor integrated circuit 1A may be equipped with one of the threshold voltage adjustment circuits 10A, 10B, or 10C instead of the threshold voltage adjustment circuit 10.

[0143] The negative power supply terminal P7 is at ground potential V. GND The negative power supply potential V is a negative potential relative to the power supply potential. EE This is the terminal to which the voltage is applied. For example, the potential difference between the ground terminal P4 and the negative power supply terminal P7, i.e., the ground potential V GND and negative power supply potential V EE If the potential difference between and is V1, then the ground potential V GND The voltage at the negative power supply terminal P7, which is the reference point, will be -V1. However, the silicon substrate potential must be at the lowest possible potential, so the silicon substrate potential is V EE The abnormality notification terminal P8 is a terminal that outputs an abnormality notification signal to notify of the occurrence of an abnormality. For example, the abnormality notification signal output from the abnormality notification terminal P8 under normal conditions is a third-level signal. If an overcurrent flows through the power element SW, or if an abnormality occurs in the power supply voltage, the abnormality notification signal becomes a fourth-level signal. For example, the third level is a high level, and the fourth level is a low level.

[0144] The ULVO circuit 15 is electrically connected to the power supply terminal P3 and the ground terminal P4, respectively. The ULVO circuit 15 compares the power supply voltage with a predetermined value and outputs a voltage determination signal indicating the comparison result to the first output buffer 13 and the second output buffer 16. The power supply voltage is the potential difference between the power supply terminal P3 and the ground terminal P4, i.e., the power supply potential V CC2 and ground potential V GND This is the potential difference between the two points.

[0145] For example, the ULVO circuit 15 outputs a low-level voltage determination signal to the first output buffer 13 and the second output buffer 16 when the power supply voltage is above a predetermined value. The ULVO circuit 15 also outputs a high-level voltage determination signal to the first output buffer 13 and the second output buffer 16 when the power supply voltage is below a predetermined value. A power supply voltage below a predetermined value indicates an abnormality in the power supply voltage. In other words, the ULVO circuit 15 outputs a high-level voltage determination signal when an abnormality occurs in the power supply voltage.

[0146] In the second embodiment, the first output buffer 13 receives a timing signal output from the input buffer 12, a first control signal output from the overcurrent detection circuit 14, and a voltage determination signal output from the ULVO circuit 15. When both the first control signal and the voltage determination signal are at a low level, the first output buffer 13 generates a gate drive signal in synchronization with the timing signal input via the input circuit 12 and outputs the gate drive signal via the output terminal P2.

[0147] The first output buffer 13 synchronizes with the timing signal to the negative power supply potential V EE and power supply potential V CC2 It outputs a gate drive signal that changes between the following. The first output buffer 13 outputs a negative power supply potential V when at least one of the first control signal and the voltage determination signal is at a high level, regardless of the timing signal. EE It outputs a gate drive signal having the following characteristics.

[0148] The second output buffer 16 receives the voltage determination signal output from the ULVO circuit 15 and the second control signal output from the overcurrent detection circuit 14. The output terminal of the second output buffer 16 is electrically connected to the abnormality notification terminal P8. The second output buffer 16 generates an abnormality notification signal based on the voltage determination signal and the second control signal, and outputs the abnormality notification signal via the abnormality notification terminal P8. For example, if at least one of the voltage determination signal and the second control signal is high level, the second output buffer 16 outputs a low-level abnormality notification signal. If both the voltage determination signal and the second control signal are low level, the second output buffer 16 outputs a high-level normality notification signal.

[0149] In the second embodiment, the overcurrent detection circuit 14 detects the negative power supply potential V after the output signal of the comparator 11 changes from a low level to a high level. EE The first output buffer 13 is controlled so that a gate drive signal having the above characteristics is output. The overcurrent detection circuit 14 controls the first output buffer 13 by outputting a first control signal to the first output buffer 13.

[0150] The overcurrent detection circuit 14 changes the first control signal from a low level to a high level after the output signal of the comparator 11 changes from a low level to a high level. As described above, when the level of the first control signal is high, the first output buffer 13 maintains the negative power supply potential V regardless of the timing signal. EE It outputs a gate drive signal having the following characteristics.

[0151] Figure 10 is a timing chart showing the voltage waveforms at each terminal of the semiconductor integrated circuit 1A. Specifically, the timing chart in Figure 10 shows the input terminal voltage V IN Output terminal voltage V OUT , detection terminal voltage V DESAT , and abnormality notification terminal voltage V FAULT The waveform is shown.

[0152] Input terminal voltage V IN The ground potential V GND This is the voltage at input terminal P1 relative to the reference. Input terminal voltage V IN This corresponds to the timing signal input to input terminal P1. Output terminal voltage V OUT This is the negative power supply potential V EE This is the voltage at output terminal P2 relative to the reference. Output terminal voltage V OUT This corresponds to the gate drive signal output from output terminal P2. Detection terminal voltage V DESAT The ground potential V GND This is the voltage at the overcurrent detection terminal P5, which is based on the reference. The abnormality notification terminal voltage V FAULT The ground potential V GND This is the voltage of the abnormality notification terminal P8, relative to the reference point. Abnormality notification terminal voltage V FAULT This corresponds to the abnormal notification signal output from the abnormal notification terminal P8. Note that in Figure 10, V CC1 This is the high-level potential of digital signals such as timing signals and anomaly notification signals. CC1 This is the power supply potential V applied to power supply terminal P3. CC2 Lower.

[0153] As shown in Figure 10, at time t11, the input terminal voltage V corresponding to the timing signal IN And the detection terminal voltage V DESAT And are at low levels (V GND Assume that the detection terminal voltage V is true. DESAT The threshold voltage V TH Since the following conditions apply, the output signal of comparator 11 is low level. At time t11, because the output signal of comparator 11 is low level, the control circuit 14c outputs a low-level first control signal to the first output buffer 13. When the level of the first control signal is low, the first output buffer 13 generates a gate drive signal in synchronization with the timing signal. As a result, at time t11, the output terminal voltage V corresponding to the gate drive signal is OUT Low level (V EE Therefore, the power element switch will be in the off state.

[0154] When the power element SW is in the off state, there is no need to detect overcurrent in the power element SW. Therefore, in this case, the control circuit 14c may disable the constant current source 14a and turn on the switch 14b, or it may turn on the switch 14b while keeping the constant current source 14a operating. As a result, the detection terminal voltage V DESAT Ground potential V GND This is almost the same, so the charge from capacitor 5 is completely discharged.

[0155] At time t11, since the output signal of comparator 11 is low level, control circuit 14c outputs a low-level second control signal to the second output buffer 16. Also, assume that at time t11, a low-level voltage determination signal is output from ULVO circuit 15 to the second output buffer 16. At this time t11, the abnormal notification terminal voltage V corresponds to the abnormal notification signal output from the second output buffer 16. FAULT is high level (V CC1 )

[0156] At time t12, after time t11, the input terminal voltage VIN low level (V GND ) to high level (V CC1 When it changes to a predetermined transmission delay time T, PLH After the elapsed time, the output terminal voltage V OUT Low level (V EE ) to high level (V CC2 ) changes to this state. As a result, the power element SW switches from the off state to the on state.

[0157] When the power element switch is in the ON state, it is necessary to detect the overcurrent of the power element switch. Therefore, at time t12, the input terminal voltage V IN High level (V CC1 When it changes to ), the first waiting time T starts from time t12. DESAT(LEB) After the elapsed time, the control circuit 14c enables the constant current source 14a and turns off the switch 14b. Alternatively, the control circuit 14c enables the constant current source 14a before time t12, and then the first waiting time T DESAT(LEB) After the elapsed time, switch 14b may be turned off. As a result, the first waiting time T starts from time t12. DESAT(LEB) After the elapsed time, the detected current I is detected from the overcurrent detection terminal P5. CHG The following will be output.

[0158] However, the output terminal voltage V OUT low level (V EE ) to high level (V CC2 Even if the output terminal voltage V changes, the power element SW does not immediately turn on. OUT High level (V CC2 For a certain period after the change, the collector terminal voltage of the power element SW is maintained at a high state, so diode 4 is biased in the reverse direction. As a result, the detected current I CHG The current flows through capacitor 5, so the detection terminal voltage V DESAT The ground potential V GND It rises from there.

[0159] Detection terminal voltage V DESAT The threshold voltage V THBefore reaching the target, when the power element SW is fully turned on, diode 4 is forward-biased. As a result, the detected current I CHG The current flows through resistor 3 and diode 4 to the collector of power element SW, so the detection terminal voltage V DESAT It decreases. Detection terminal voltage V DESAT The value of the steady-state voltage V BLK(ON) When it reaches this point, while the power element SW is in the ON state, the detection terminal voltage V DESAT The value of is the steady-state voltage value V BLK(ON) It is held there.

[0160] At time t13, after time t12, the input terminal voltage V IN High level (V CC1 ) to low level (V GND When it changes to a predetermined transmission delay time T, PHL After the elapsed time, the output terminal voltage V OUT High level (V CC2 ) to low level (V EE ) changes to this state. As a result, the power element SW switches from the ON state to the OFF state.

[0161] As described above, when the power element SW is in the off state, there is no need to detect overcurrent in the power element SW. Therefore, at time t13, the input terminal voltage V IN low level (V GND When this changes, the control circuit 14c may disable the constant current source 14a and turn on the switch 14b, or it may turn on the switch 14b while keeping the constant current source 14a operating. As a result, the charge from the capacitor 5 is completely discharged, so the detection terminal voltage V DESAT The value of is the steady-state voltage value V BLK(ON) From ground potential V GND Descending.

[0162] At time t14, after time t13, the input terminal voltage V IN low level (V GND ) to high level (V CC1 When it changes to a predetermined transmission delay time T, PLHAfter the elapsed time, the output terminal voltage V OUT Low level (V EE ) to high level (V CC2 ) changes to this state. As a result, the power element SW switches from the off state to the on state.

[0163] Similar to time t12, at time t14 the input terminal voltage V IN High level (V CC1 When it changes to ), the first waiting time T starts from time t14. DESAT(LEB) After the specified time has elapsed, the control circuit 14c enables the constant current source 14a and turns off the switch 14b, or turns off the switch 14b while keeping the constant current source 14a operating. Here, assuming that an overcurrent flows through the power element SW, the power element SW operates in a non-saturated state, causing the collector-emitter voltage of the power element SW to rise. As a result, the diode 4 is biased in the reverse direction, causing a detected current I to flow through the capacitor 5. CHG Because a current flows, the detection terminal voltage V DESAT The ground potential V GND It rises from there.

[0164] If an overcurrent continues to flow through the power element SW, the detection terminal voltage V DESAT It continues to rise over time. And the detection terminal voltage V DESAT The threshold voltage V TH When it exceeds this value, the output signal of comparator 11 changes from a low level to a high level.

[0165] Detection terminal voltage V DESAT The threshold voltage V TH The second waiting period T begins from the point when the value exceeds a certain threshold, that is, when the output signal of comparator 11 changes from a low level to a high level. DESAT(FILTER) At time t15, when the time has elapsed, the control circuit 14c determines that an overcurrent has flowed through the power element SW and changes the first control signal output to the first output buffer 13 from a low level to a high level. When the level of the first control signal is high, the output buffer 13, regardless of the timing signal, maintains the negative power supply potential V EEIt outputs a gate drive signal having the detection terminal voltage V. DESAT The threshold voltage V TH From the point where it exceeds this, the second waiting period T begins. DESAT(FILTER) After the elapsed time, the output terminal voltage V OUT is high level (V CC2 ) to low level (V EE The state changes gradually. As a result, if an overcurrent flows through the power element switch, the power element switch is forcibly switched to the off state.

[0166] Furthermore, the second waiting time T begins from the point when the output signal of comparator 11 changes from a low level to a high level. DESAT(FILTER) After this time has elapsed, the control circuit 14c disables the constant current source 14a and turns on the switch 14b, or turns on the switch 14b while keeping the constant current source 14a operating. As a result, the charge from the capacitor 5 is completely discharged, so the detection terminal voltage V DESAT The value of is quickly determined by the ground potential V GND Descending.

[0167] Furthermore, a third waiting time T occurs from the moment the output signal of comparator 11 changes from a low level to a high level. DESAT(FAULT) After the elapsed time, the control circuit 14c changes the second control signal output to the second output buffer 16 from a low level to a high level. As a result, the third waiting time T begins from the point when the output signal of the comparator 11 changes from a low level to a high level. DESAT(FAULT) After the elapsed time, the abnormal notification terminal voltage V, which corresponds to the abnormal notification signal output from the second output buffer 16, FAULT is high level (V CC1 ) to low level (V GND ) changes to.

[0168] The control circuit 14c has an abnormality notification terminal voltage V FAULT low level (V GND From the point when it changes to ), the fourth waiting period T DESAT(MUTE) The overcurrent protection operation continues until the specified time has elapsed. In other words, the control circuit 14c will continue the overcurrent protection operation until the abnormality notification terminal voltage V FAULT low level (VGND From the point when it changes to ), the fourth waiting period T DESAT(MUTE) The first output buffer 13 maintains a high level of the first control signal output to the first output buffer 13 until the specified time has elapsed. The first output buffer 13 maintains a high level of the negative power supply potential V EE It continuously outputs a gate drive signal having the following characteristics. Anomaly notification terminal voltage V FAULT low level (V GND From the point when it changes to ), the fourth waiting period T DESAT(MUTE) After the specified time has elapsed, the control circuit 14c terminates the overcurrent protection operation by changing the level of the first control signal from a high level to a low level.

[0169] Anomaly notification terminal voltage V FAULT low level (V GND From the point when it changes to ), the fourth waiting period T DESAT(MUTE) After the elapsed time, at time t16, the input terminal voltage V IN High level (V CC1 ) changes. The control circuit 14c operates from time t16 through the fifth waiting time T RESET(FAULT) After the specified time has elapsed, the second control signal output to the second output buffer 16 is changed from a high level to a low level. As a result, the input terminal voltage V IN High level (V CC1 ) changed from time t16 to the fifth waiting period T RESET(FAULT) After the elapsed time, the abnormal notification terminal voltage V, which corresponds to the abnormal notification signal output from the second output buffer 16, FAULT is low level (V GND ) to high level (V CC1 ) changes to.

[0170] As described above, the overcurrent detection circuit 14 has a third waiting period T from the moment the output signal of the comparator 11 changes from a low level to a high level. DESAT(FAULT) After the elapsed time, the second output buffer 16 is controlled so that the abnormality notification signal output from the second output buffer 16 changes from a high level to a low level. Third waiting time T DESAT(FAULT)This is an example of the first time. The overcurrent detection circuit 14 controls the second output buffer 16 by outputting a second control signal to the second output buffer 16.

[0171] The overcurrent detection circuit 14 has a third waiting period T from the moment the output signal of the comparator 11 changes from a low level to a high level. DESAT(FAULT) After the specified time has elapsed, the second control signal is changed from a low level to a high level. As described above, the second output buffer 16 outputs a low-level abnormality notification signal when the level of the second control signal is high.

[0172] Specifically, the control circuit 14c of the overcurrent detection circuit 14 outputs a first control signal and a second control signal. Based on the output signal of the comparator 11, the control circuit 14c sets the levels of the first control signal and the second control signal to a high level or a low level.

[0173] In the second embodiment, the threshold voltage adjustment circuit 10, comparator 11, overcurrent detection circuit 14, ULVO circuit 15, and second output buffer 16 are each electrically connected to the ground terminal P4. These circuits are connected to the ground potential V GND It operates based on this. In the second embodiment, the input buffer 12 and the first output buffer 13 are electrically connected to the negative power supply terminal P7, respectively. These circuits are connected to the negative power supply potential V EE It operates based on [this].

[0174] As described above, when an overcurrent is detected in the power element SW, the power element SW is forcibly switched to the OFF state, and the abnormality notification terminal voltage V, which corresponds to the abnormality notification signal, is also activated. FAULT The level changes from high to low. As a result, it is possible to prevent malfunctions caused by overcurrent and to notify external devices of the abnormality.

[0175] On the other hand, let's consider the case where an abnormality occurs in the power supply voltage, that is, when the power supply voltage falls below a predetermined value. In this case, the ULVO circuit 15 outputs a high-level voltage determination signal to the first output buffer 13 and the second output buffer 16. If the voltage determination signal is high level, the first output buffer 13 outputs the negative power supply potential V EE It outputs a gate drive signal having the following characteristics. The second output buffer 16 outputs a low-level abnormality notification signal when the voltage determination signal is high level. As a result, even if an abnormality occurs in the power supply voltage, the power element SW is forcibly switched to the off state, and the abnormality notification terminal voltage V corresponding to the abnormality notification signal is output. FAULT The voltage changes from high to low. As a result, it is possible to prevent malfunctions caused by abnormal power supply voltage and to notify external devices of the abnormality.

[0176] The semiconductor integrated circuit 1A of the second embodiment includes, in addition to the components of the semiconductor integrated circuit 1 of the first embodiment, a negative power supply potential V which is a negative potential relative to the ground potential. EE The semiconductor integrated circuit 1A further includes a negative power supply terminal P7 to which the negative power supply potential V is applied. EE and power supply potential V CC2 It outputs a gate drive signal that changes between the following. The overcurrent detection circuit 14 detects the negative power supply potential V after the output signal of the comparator 11 changes from a low level to a high level. EE The first output buffer 13 is controlled so that a gate drive signal having is output. According to such a semiconductor integrated circuit 1A, the negative power supply potential V is applied to the gate of the power element SW. EE and power supply potential V CC2 Since a gate drive signal that changes between the two is supplied, self-turn-on of the power element SW can be prevented.

[0177] Furthermore, the semiconductor integrated circuit 1A includes an abnormality notification terminal P8 that outputs an abnormality notification signal to notify of the occurrence of an abnormality, and a second output buffer 16 that generates an abnormality notification signal based on a control signal (second control signal) from the overcurrent detection circuit 14 and outputs the abnormality notification signal via the abnormality notification terminal P8. The overcurrent detection circuit 14 has a third waiting time T from the time the output signal of the comparator 11 changes from a low level to a high level. DESAT(FAULT) After the specified time has elapsed, the second output buffer 16 is controlled so that the abnormality notification signal output from the second output buffer 16 changes from a high level to a low level. With such a semiconductor integrated circuit 1A, when an overcurrent is detected in the power element SW, the power element SW is forcibly switched to the off state, and the abnormality notification terminal voltage V, which corresponds to the abnormality notification signal, is also controlled. FAULT The level changes from high to low. As a result, it is possible to prevent malfunctions caused by overcurrent and to notify external devices of the abnormality.

[0178] To avoid false detection of overcurrent caused by noise from the power element SW, a threshold voltage V is always maintained during the period when the semiconductor integrated circuit 1A is operating. TH Instead of detecting the noise from the power element SW, the threshold voltage V is detected in the region where the noise from the power element SW is low. TH It is desirable to detect the output terminal voltage V. As shown in Figure 10, as a first example, OUT It drops to a low level and the 6th waiting time T EN From the point when the time has elapsed, the output terminal voltage V OUT The period T until the point when it starts to rise to a high level. D1 The threshold voltage V TH It detects the abnormality notification terminal voltage V. FAULT The level changes from high to low, and the fourth waiting time T DESAT(MUTE) From the point when the time has elapsed, the output terminal voltage V OUT The period T until the point when it starts to rise to a high level. D2 The threshold voltage V TH Detect these periods T D1 and T D2This is the period during which the power element SW is definitely in the OFF state. In either case, the threshold voltage V is maintained during the period when the power element SW is in the OFF state. TH Because it detects the threshold voltage V, it becomes less susceptible to noise from power element SW. TH Because the adjustments are made intermittently, it is possible to follow temperature changes in the unit.

[0179] As described above, the threshold voltage V during the period when the power element SW is in the off state. TH To detect the threshold voltage V, the semiconductor integrated circuit 1A may include a threshold voltage detection circuit 40 positioned between the threshold voltage adjustment circuit 10 and the comparator 11. In the first period, the threshold voltage detection circuit 40 detects the threshold voltage V output from the threshold voltage adjustment circuit 10. TH The voltage is passed through comparator 11, and the threshold voltage V TH The capacitor 64 is charged by this, and in the second period other than the first period, the threshold voltage V output from the threshold voltage adjustment circuit 10 is charged. TH The voltage across the terminals of capacitor 64 is output to comparator 11 without passing through comparator 11. The first period is when the gate drive signal falls and the sixth waiting time T EN The period T from the time when the period has elapsed until the gate drive signal starts to rise. D1 Alternatively, the abnormality notification signal changes from high level to low level, and a fourth waiting period T occurs. DESAT(MUTE) The period T from the time when the period has elapsed until the gate drive signal starts to rise. D2 The sixth waiting time T EN This is an example of the second hour. The fourth waiting time T DESAT(MUTE) This is an example of the third hour.

[0180] Figure 11 is a circuit diagram showing an example of the configuration of the threshold voltage detection circuit 40. As shown in Figure 11, the threshold voltage detection circuit 40 comprises a timing generation circuit 50 and a sample-and-hold circuit 60.

[0181] The timing generation circuit 50 is electrically connected to the output terminal P2 and the abnormality notification terminal P8. The timing generation circuit 50 has an output terminal voltage V OUT And, abnormality notification terminal voltage V FAULT The gate drive signal and the abnormality notification signal are input to the timing generation circuit 50. Based on the gate drive signal and the abnormality notification signal, the timing generation circuit 50 sets a threshold voltage V TH A sample timing signal CTR is generated to control the sample timing, and the sample timing signal CTR is output to the sample-hold circuit 60.

[0182] The timing generation circuit 50 outputs a high-level sample timing signal CTR during the first period and a low-level sample timing signal CTR during the second period other than the first period. The timing generation circuit 50 comprises a first NOR circuit 51, a second NOR circuit 52, a first delay circuit 53, a second delay circuit 54, a first NAND circuit 55, a second NAND circuit 56, and a third NAND circuit 57.

[0183] Of the two input terminals of the first NOR circuit 51, one input terminal is electrically connected to the output terminal P2, and the other input terminal is electrically connected to the output terminal P2 via the first delay circuit 53. The first delay circuit 53 delays the gate drive signal for a sixth waiting time T EN This circuit delays the signal by a certain amount of time. Of the two input terminals of the second NOR circuit 52, one input terminal is electrically connected to the abnormality notification terminal P8, and the other input terminal is electrically connected to the abnormality notification terminal P8 via the second delay circuit 54. The second delay circuit 54 delays the abnormality notification signal for a fourth waiting time T DESAT(MUTE) This is a circuit that delays the signal by a certain amount.

[0184] Of the two input terminals of the first NAND circuit 55, one input terminal is electrically connected to the output terminal of the first NOR circuit 51, and the other input terminal is electrically connected to the error notification terminal P8. Of the two input terminals of the second NAND circuit 56, one input terminal is electrically connected to the output terminal of the second NOR circuit 52, and the other input terminal is electrically connected to the output terminal P2. Of the two input terminals of the third NAND circuit 57, one input terminal is electrically connected to the output terminal of the first NAND circuit 55, and the other input terminal is electrically connected to the output terminal of the second NAND circuit 56. The output terminal of the third NAND circuit 57 is electrically connected to the sample-and-hold circuit 60. The signal output from the third NAND circuit 57 is the sample timing signal CTR.

[0185] The sample-and-hold circuit 60 uses a threshold voltage V based on the sample timing signal CTR. TH The sample-and-hold circuit 60 includes an analog switch 61, an INV circuit 62, a voltage follower 63, and a capacitor 64.

[0186] The output terminal of the timing generation circuit 50, that is, the output terminal of the third NAND circuit 57, is electrically connected to the gate of the N-channel MOSFET of the analog switch 61. Furthermore, the output terminal of the timing generation circuit 50 is electrically connected to the gate of the P-channel MOSFET of the analog switch 61 via the INV circuit 62. The INV circuit 62 inverts the level of the sample timing signal CTR. When the sample timing signal CTR is at a high level, the analog switch 61 is ON. When the sample timing signal CTR is at a low level, the analog switch 61 is OFF.

[0187] The input terminal of the analog switch 61 is electrically connected to the output terminal (threshold voltage output terminal 35) of the threshold voltage adjustment circuit 10 via the voltage follower 63. The output terminal of the analog switch 61 is electrically connected to the non-inverting input terminal of the comparator 11. One end of the capacitor 64 is electrically connected to the output terminal of the analog switch 61. The other end of the capacitor 64 is electrically connected to the ground terminal P4.

[0188] When the timing generation circuit 50 outputs a high-level sample timing signal CTR in the first period, the analog switch 61 turns ON, and the sample-and-hold circuit 60 enters sample mode. Specifically, in the first period, the sample-and-hold circuit 60 receives the threshold voltage V output from the threshold voltage adjustment circuit 10. TH The voltage is passed through comparator 11, and the threshold voltage V TH This charges capacitor 64.

[0189] When the timing generation circuit 50 outputs a low-level sample timing signal CTR in the second period, the analog switch 61 turns off and the sample-and-hold circuit 60 enters hold mode. Specifically, in the second period, the sample-and-hold circuit 60 uses the threshold voltage V output from the threshold voltage adjustment circuit 10. TH The voltage across the terminals of capacitor 64 is output to comparator 11 without passing through comparator 11.

[0190] With the configuration of the threshold voltage detection circuit 40 described above, the threshold voltage V output from the threshold voltage adjustment circuit 10 is maintained only during the first period when the power element SW is in the off state. TH This is directly input to the comparator 11, and in the second period other than the first period, the terminal voltage of the capacitor 64 charged in the first period is equal to the threshold voltage V. TH This is output to the comparator 11. As a result, false detection of overcurrent caused by noise from the power element SW can be more reliably avoided.

[0191] As shown in Figure 10, the first period (T) is relatively short.D1 , T D2 Sufficient sampling is necessary, but the output impedance of the threshold voltage adjustment circuit 10 is relatively high. Therefore, it is desirable to perform impedance conversion of the output of the threshold voltage adjustment circuit 10 using the voltage follower 63 before sampling. Alternatively, instead of the sample-and-hold circuit 60, an A / D conversion circuit that takes the sample timing signal CTR output from the timing generation circuit 50 as the clock signal may be used.

[0192] In both the semiconductor integrated circuit 1 of the first embodiment and the semiconductor integrated circuit 1A of the second embodiment, the overcurrent detection circuit 14 controls the threshold voltage V output from the threshold voltage adjustment circuit 10. TH The current detected is proportional to the current I CHG A constant current source 14a that outputs as is may be provided. Considering the short-circuit withstand capability of the power element SW, the detection terminal voltage V should be quickly detected within a certain time. DESAT The threshold voltage V TH It is desirable to raise it to the threshold voltage V TH The larger the detection current I, the larger the detection current I. CHG It is desirable to output the threshold voltage V from the overcurrent detection terminal P5. TH The detection current I is proportional to CHG A constant current source 14a that outputs the above can meet the requirements.

[0193] Figure 12 shows the threshold voltage V TH The detection current I is proportional to CHG This is a circuit diagram showing an example of the configuration of a constant current source 14a that outputs a current. As shown in Figure 12, the constant current source 14a comprises a third voltage-controlled current source 70 and a third current mirror circuit 80.

[0194] The third voltage-controlled current source 70 has a threshold voltage V THIt outputs a fourth current I4 that is proportional to the value. The third voltage-controlled current source 70 comprises an operational amplifier 71, a resistor 72, and a MOSFET element 73. For example, the MOSFET element 73 is an N-channel MOSFET. The non-inverting input terminal of the operational amplifier 71 is electrically connected to the output terminal (threshold voltage output terminal 35) of the threshold voltage adjustment circuit 10. The threshold voltage V output from the threshold voltage adjustment circuit 10 TH This is input to the non-inverting input terminal of the operational amplifier 71. The inverting input terminal of the operational amplifier 71 is electrically connected to the source of the MOSFET element 73. The output terminal of the operational amplifier 71 is electrically connected to the gate of the MOSFET element 73.

[0195] One end of resistor 72 is electrically connected to the source of MOSFET element 73. The other end of resistor 72 is electrically connected to the ground terminal P4. The drain of MOSFET element 73 is electrically connected to the input terminal of the third current mirror circuit 80. The current flowing from the drain of MOSFET element 73 towards resistor 72 is the fourth current I4.

[0196] The third current mirror circuit 80 is electrically connected to the power supply terminal P3. The input terminal of the third current mirror circuit 80 is electrically connected to the drain of the MOSFET element 73. The third current mirror circuit 80 takes the fourth current I4 as input and detects the current I4 as a multiple of the fourth current I4. CHG It outputs as follows. For example, the third current mirror circuit 80 detects a current I that is N3 times the fourth current I4. CHG The output is N3, which is the current mirror ratio. The output terminal of the third current mirror circuit 80 is electrically connected to the ground terminal P4 via switch 14b. The output terminal of the third current mirror circuit 80 is also electrically connected to the overcurrent detection terminal P5.

[0197] The current I output from the constant current source 14a configured as described above CHGThis is expressed by equation (28) below. In equation (28) below, R9 is the resistance value of resistor 72, and ΔN3 is the variation ratio of the current mirror ratio N3 of the third current mirror circuit 80. As can be seen from equation (28) below, the current I output from the constant current source 14a CHG The resistance of each resistor is directly affected by the variation ratio ΔR, but the threshold voltage V TH It is proportional to.

[0198]

number

[0199] With the configuration of the constant current source 14a described above, the threshold voltage V output from the threshold voltage adjustment circuit 10 TH The detection current I is proportional to CHG Since the overcurrent detection voltage V is output from the overcurrent detection terminal P5, TH The larger the detection current I, the larger the detection current I. CHG This can be output from the overcurrent detection terminal P5. As a result, if an overcurrent occurs in the power element SW, the threshold voltage V TH Depending on the magnitude, the detection terminal voltage V is detected within a certain time. DESAT The threshold voltage V TH It can be raised to that level.

[0200] Figure 13 is a circuit diagram showing an example of a semiconductor integrated circuit 1A equipped with an insulating element. As shown in Figure 13, the semiconductor integrated circuit 1A may further include a first insulating element 100 positioned between the input terminal P1 and the input buffer 12, and a second insulating element 200 positioned between the abnormality notification terminal P8 and the second output buffer 16. In the following description, the semiconductor integrated circuit 1A may be referred to as the secondary side chip. Note that in Figure 13, components other than the input buffer 12 and the second output buffer 16 are not shown.

[0201] A timing signal is output from the primary chip 300 to the secondary chip 1A, and an abnormality notification signal is output from the secondary chip 1A to the primary chip 300. The primary chip 300 includes a transmitting circuit 310 that transmits the timing signal input to the primary chip 300 via the primary input terminal P10 to the secondary chip 1A. The input buffer 12 of the secondary chip 1A receives the timing signal transmitted from the transmitting circuit 310 via the first insulating element 100. The primary chip 300 includes a receiving circuit 320 that receives the abnormality notification signal transmitted from the second output buffer 16 of the secondary chip 1A via the second insulating element 200. The receiving circuit 320 outputs the abnormality notification signal via the primary abnormality notification terminal P11.

[0202] For example, the primary side chip 300 and the secondary side chip 1A are connected by a bonding wire. The first insulating element 100 and the second insulating element 200 are insulated by a polyimide layer or an oxide film. The first insulating element 100 and the second insulating element 200 may be either an isolation transformer using a transformer or an insulating capacitance using a capacitor. The primary side chip 300 includes a primary side power supply terminal P12 and a primary side ground terminal P13 as terminals to which the power supply voltage used in the transmitting circuit 310 and the receiving circuit 320 is input. By using the primary side chip 300 as described above, it is possible to transmit signals while isolating the control side and the power element SW side.

[0203] Figure 14 is a circuit diagram showing an example in which the primary side chip 300 is equipped with an insulating element. As shown in Figure 14, the primary side chip 300 may be equipped with a first insulating element 100 and a second insulating element 200. Figure 15 is a circuit diagram showing an example in which an insulating chip 400 equipped with an insulating element is placed between the primary side chip 300 and the secondary side chip 1A. As shown in Figure 15, the insulating chip 400 placed between the primary side chip 300 and the secondary side chip 1A may be equipped with a first insulating element 100 and a second insulating element 200. Figure 16 is a circuit diagram showing an example in which both the primary side chip 300 and the secondary side chip 1A are equipped with insulating elements. As shown in Figure 16, the secondary side chip 1A may be equipped with a first insulating element 100 and a second insulating element 200, and the primary side chip 300 may be equipped with a third insulating element 110 and a fourth insulating element 210.

[0204] Figure 17 is a circuit diagram showing a first example of a semiconductor integrated circuit 1A that includes an optical device as an insulating element. As shown in Figure 17, the semiconductor integrated circuit 1A may include a first photodiode 510 connected to the input side of the input buffer 12 and a first light-emitting diode 520 connected to the output side of the second output buffer 16 as insulating elements.

[0205] A second light-emitting diode 600 is connected between terminals P21 and P22. By passing current from terminal P21 to terminal P22, the second light-emitting diode 600 emits light. The light emitted from the second light-emitting diode 600 is received by the first photodiode 510 and converted into current. The input buffer 12 converts the current output from the first photodiode 510 into a voltage signal and outputs it. When using an optical device as an insulating element, it is desirable for the input buffer 12 to include a TIA (Trans-Impedance Amplifier) ​​circuit.

[0206] The first light-emitting diode 520 emits light when driven by the second output buffer 16. The light emitted from the first light-emitting diode 520 is received by the second photodiode 710 included in the primary chip 700 and converted into an electric current. In the primary chip 700, the second photodiode 710 is connected between terminal P31 and the base of transistor 720, and when current flows through the second photodiode 710, transistor 720 turns on.

[0207] Although not shown in the diagram, an external resistor is connected between terminals P31 and P32. Terminal P33 is connected to ground. When the first light-emitting diode 520 lights up, the transistor 720 turns on, and the voltage at terminal P32 becomes low level (ground potential). In this way, the primary chip 700 outputs the voltage at terminal P32 as an abnormality notification signal. Since a small noise current flowing through the first photodiode 510 and the second photodiode 710 can cause malfunctions, it is desirable to provide electrostatic shields to the first photodiode 510 and the second photodiode 710. For example, in Figure 17, the second light-emitting diode 600, the primary chip 700, the first light-emitting diode 520, and the semiconductor integrated circuit 1A are mounted in a single semiconductor package. The second light-emitting diode 600 and the primary chip 700 are mounted on a single die pad, and terminals P21, P22, P31, P32, and P33 are connected to the outer leads of the semiconductor package. The first light-emitting diode 520 and the semiconductor integrated circuit 1A are mounted on a different die pad, and terminals P2, P3, P4, P5, P6, and P7 are connected to the outer leads of the semiconductor package.

[0208] Figure 18 is a circuit diagram showing a second example of a semiconductor integrated circuit 1A equipped with an optical device as an insulating element. In the example shown in Figure 17, the anode and cathode of the second light-emitting diode 600 are connected to terminals P21 and P22, which are primary-side input terminals, respectively, and the collector of the transistor 720 is connected to terminal P32, which is a primary-side output terminal. Therefore, in the example shown in Figure 17, the transmission delay time, which is the time from when a signal is input until it is output, is long. In the example shown in Figure 18, the second light-emitting diode 600 is driven by the transmitting circuit 310 of the primary-side chip 300, and the current output of the second photodiode 710 is received by the receiving circuit 320, thereby outputting an abnormality notification signal from the primary-side abnormality notification terminal P11. According to the example shown in Figure 18, the transmission delay time can be shortened compared to the example shown in Figure 17. The primary-side abnormality notification terminal P11 is generally bundled with other terminals that output abnormality notification signals using a wired OR connection. Therefore, it is desirable that the output terminal of the receiving circuit 320 be of the open collector or open drain type.

[0209] According to at least one embodiment described above, a threshold voltage adjustment circuit can be provided that includes a reference current circuit that outputs a reference current formed on a substrate, and a transimpedance circuit that has multiple resistors on the substrate and outputs a threshold voltage expressed as a function of the combined resistance of the multiple resistors and an external resistor and the reference current, thereby allowing the threshold voltage to be easily adjusted in a simple manner by simply changing the resistance value of the external resistor.

[0210] The threshold voltage adjustment circuit and semiconductor integrated circuit of the embodiment include the following appended embodiments. (Note 1) A reference current circuit that outputs a reference current formed on the substrate, The substrate has a plurality of resistors, and a transimpedance circuit that outputs a threshold voltage expressed as a function of the combined resistance of the plurality of resistors and an external resistor and the reference current, A threshold voltage adjustment circuit equipped with the following features. (Note 2) The aforementioned transimpedance circuit is A first current mirror circuit that takes the aforementioned reference current as input and outputs a current that is a multiple of the aforementioned reference current, A first resistor having one end electrically connected to the output terminal of the first current mirror circuit and the other end electrically connected to one end of the external resistor via a resistor connection terminal, A second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of which is electrically connected to the other end of the external resistor via a ground terminal, A threshold voltage output terminal is electrically connected to one end of the first resistor and outputs the threshold voltage, A threshold voltage adjustment circuit as described in Appendix 1, comprising the above. (Note 3) The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the aforementioned reference voltage as the reference current, A threshold voltage adjustment circuit as described in Appendix 1, comprising the above. (Note 4) The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the aforementioned reference voltage, A PTAT current source that outputs a second current proportional to the absolute temperature, A second current mirror circuit that takes the second current as input and outputs a third current which is a multiple of the second current, Equipped with, The reference current circuit outputs a current represented by the difference between the first current and the third current as the reference current. The threshold voltage adjustment circuit described in Appendix 1, wherein the first current is greater than the third current. (Note 5) The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the aforementioned reference voltage, A PTAT current source that outputs a second current proportional to the absolute temperature, Equipped with, The reference current circuit is a threshold voltage adjustment circuit as described in Appendix 1, which outputs a current represented by the sum of the first current and the second current as the reference current. (Note 6) The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the aforementioned reference voltage as the reference current, Equipped with, The aforementioned transimpedance circuit is A first resistor having one end electrically connected to one end of the external resistor via a power terminal, and the other end electrically connected to the other end of the external resistor via a resistor connection terminal, A second resistor, one end of which is electrically connected to the other end of the first resistor and the other end of which is electrically connected to the output terminal of the first voltage-controlled current source, A second voltage-controlled current source that outputs a current proportional to the voltage at the resistor connection terminal, A third resistor having one end electrically connected to the output terminal of the second voltage-controlled current source and the other end electrically connected to the ground terminal, A threshold voltage output terminal is electrically connected to one end of the third resistor and outputs the threshold voltage, A threshold voltage adjustment circuit as described in Appendix 1, comprising the above. (Note 7) A semiconductor integrated circuit for driving the gate of a power element, An input terminal to which a timing signal is input, An output terminal that outputs a gate drive signal for driving the aforementioned gate, An overcurrent detection terminal that outputs a detection current for detecting overcurrent of the power element, A resistor connection terminal for connecting an external resistor, A ground terminal to which the ground potential is applied, A power supply terminal to which a power supply potential that is positive relative to the ground potential is applied, An input circuit to which the timing signal is input via the input terminal, A first output circuit generates the gate drive signal in synchronization with the timing signal input via the input circuit and outputs the gate drive signal via the output terminal, An overcurrent detection circuit that, after detecting the rising edge of the timing signal input via the input circuit, outputs the detected current via the overcurrent detection terminal, A threshold voltage adjustment circuit described in any one of the appendices 1 to 6, A comparator that compares the threshold voltage output from the threshold voltage adjustment circuit with the detection terminal voltage, which is the voltage of the overcurrent detection terminal, and outputs a signal indicating the comparison result to the overcurrent detection circuit, Equipped with, The comparator outputs a first-level signal when the detection terminal voltage is less than or equal to the threshold voltage, and outputs a second-level signal when the detection terminal voltage exceeds the threshold voltage. The overcurrent detection circuit is a semiconductor integrated circuit that controls the first output circuit so that after the output signal of the comparator changes from a first level to a second level, a gate drive signal having a potential that turns the power element off is output. (Note 8) The first output circuit outputs the gate drive signal which changes between the ground potential and the power supply potential in synchronization with the timing signal. The semiconductor integrated circuit according to Appendix 7, wherein the overcurrent detection circuit controls the first output circuit so that the gate drive signal having the ground potential is output after the output signal of the comparator changes from the first level to the second level. (Note 9) The system further includes a negative power supply terminal to which a negative power supply potential, which is a negative potential relative to the ground potential, is applied. The first output circuit outputs the gate drive signal which changes between the negative power supply potential and the power supply potential in synchronization with the timing signal. The semiconductor integrated circuit according to Appendix 7, wherein the overcurrent detection circuit controls the first output circuit so that the gate drive signal having the negative power supply potential is output after the output signal of the comparator changes from the first level to the second level. (Note 10) An abnormality notification terminal that outputs an abnormality notification signal to notify of the occurrence of an abnormality, A second output circuit generates the abnormality notification signal based on the control signal from the overcurrent detection circuit and outputs the abnormality notification signal via the abnormality notification terminal, Furthermore, The semiconductor integrated circuit described in Appendix 7, wherein the overcurrent detection circuit controls the second output circuit so that the abnormality notification signal output from the second output circuit changes from the third level to the fourth level after a first time has elapsed from the time the output signal of the comparator changes from the first level to the second level. (Note 11) The system further comprises a threshold voltage detection circuit positioned between the threshold voltage adjustment circuit and the comparator, The threshold voltage detection circuit is, During the first period, the threshold voltage output from the threshold voltage adjustment circuit is passed through the comparator, and the capacitor is charged by the threshold voltage. In the second period other than the first period, the threshold voltage output from the threshold voltage adjustment circuit is not passed through the comparator, and the terminal voltage of the capacitor is output to the comparator. The semiconductor integrated circuit as described in Appendix 10, wherein the first period is the period from the time when the gate drive signal has fallen for two hours until the gate drive signal begins to rise, or the period from the time when the abnormality notification signal has changed from the third level to the fourth level and three hours have elapsed until the gate drive signal begins to rise. (Note 12) A first isolation circuit is disposed between the input terminal and the input circuit, A second isolation circuit is disposed between the abnormality notification terminal and the second output circuit, A semiconductor integrated circuit as described in Appendix 10 or Appendix 11, further comprising the above. (Note 13) The semiconductor integrated circuit according to any one of the appendices 7 to 12, wherein the overcurrent detection circuit includes a constant current source that outputs a current proportional to the threshold voltage output from the threshold voltage adjustment circuit as the detection current.

[0211] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0212] 1, 1A…Semiconductor integrated circuit, 10, 10A, 10B, 10C…Threshold voltage adjustment circuit, 11…Comparator, 12…Input buffer, 13…First output buffer, 14…Overcurrent detection circuit, 15…ULVO circuit, 16…Second output buffer, 20, 20A, 20B…Reference current circuit, 30, 30C…Transimpedance circuit, SW…Power element

Claims

1. A reference current circuit that outputs a reference current formed on the substrate, The substrate has a plurality of resistors, and a transimpedance circuit that outputs a threshold voltage expressed as a function of the combined resistance of the plurality of resistors and an external resistor and the reference current, A threshold voltage adjustment circuit equipped with the following features.

2. The aforementioned transimpedance circuit is A first current mirror circuit that takes the aforementioned reference current as input and outputs a current that is a multiple of the aforementioned reference current, A first resistor having one end electrically connected to the output terminal of the first current mirror circuit and the other end electrically connected to one end of the external resistor via a resistor connection terminal, A second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of which is electrically connected to the other end of the external resistor via a ground terminal, A threshold voltage output terminal is electrically connected to one end of the first resistor and outputs the threshold voltage, A threshold voltage adjustment circuit according to claim 1, comprising:

3. The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the reference voltage as the reference current, A threshold voltage adjustment circuit according to claim 1, comprising:

4. The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the reference voltage, A PTAT current source that outputs a second current proportional to the absolute temperature, A second current mirror circuit that takes the second current as input and outputs a third current which is a multiple of the second current, Equipped with, The reference current circuit outputs a current represented by the difference between the first current and the third current as the reference current. The threshold voltage adjustment circuit according to claim 1, wherein the first current is greater than the third current.

5. The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the reference voltage, A PTAT current source that outputs a second current proportional to the absolute temperature, Equipped with, The threshold voltage adjustment circuit according to claim 1, wherein the reference current circuit outputs a current represented by the sum of the first current and the second current as the reference current.

6. The aforementioned reference current circuit is A reference voltage circuit that outputs a reference voltage, A first voltage-controlled current source that outputs a first current proportional to the reference voltage as the reference current, Equipped with, The aforementioned transimpedance circuit is A first resistor having one end electrically connected to one end of the external resistor via a power terminal, and the other end electrically connected to the other end of the external resistor via a resistor connection terminal, A second resistor, one end of which is electrically connected to the other end of the first resistor and the other end of which is electrically connected to the output terminal of the first voltage-controlled current source, A second voltage-controlled current source that outputs a current proportional to the voltage at the resistor connection terminal, A third resistor, one end of which is electrically connected to the output terminal of the second voltage-controlled current source and the other end of which is electrically connected to the ground terminal, A threshold voltage output terminal is electrically connected to one end of the third resistor and outputs the threshold voltage, A threshold voltage adjustment circuit according to claim 1, comprising:

7. A semiconductor integrated circuit for driving the gate of a power element, An input terminal to which a timing signal is input, An output terminal that outputs a gate drive signal for driving the aforementioned gate, An overcurrent detection terminal that outputs a detection current for detecting overcurrent of the power element, A resistor connection terminal for connecting an external resistor, A ground terminal to which the ground potential is applied, A power supply terminal to which a power supply potential that is positive relative to the ground potential is applied, An input circuit to which the timing signal is input via the input terminal, A first output circuit that generates the gate drive signal in synchronization with the timing signal input via the input circuit and outputs the gate drive signal via the output terminal, An overcurrent detection circuit that, after detecting the rising edge of the timing signal input via the input circuit, outputs the detected current via the overcurrent detection terminal, A threshold voltage adjustment circuit according to any one of claims 1 to 6, A comparator that compares the threshold voltage output from the threshold voltage adjustment circuit with the detection terminal voltage, which is the voltage of the overcurrent detection terminal, and outputs a signal indicating the comparison result to the overcurrent detection circuit, Equipped with, The comparator outputs a first-level signal when the detection terminal voltage is less than or equal to the threshold voltage, and outputs a second-level signal when the detection terminal voltage exceeds the threshold voltage. The overcurrent detection circuit is a semiconductor integrated circuit that controls the first output circuit so that after the output signal of the comparator changes from a first level to a second level, a gate drive signal having a potential that turns the power element off is output.

8. The first output circuit outputs the gate drive signal which changes between the ground potential and the power supply potential in synchronization with the timing signal. The semiconductor integrated circuit according to claim 7, wherein the overcurrent detection circuit controls the first output circuit so that the gate drive signal having the ground potential is output after the output signal of the comparator changes from a first level to a second level.

9. The system further includes a negative power supply terminal to which a negative power supply potential, which is a negative potential relative to the ground potential, is applied. The first output circuit outputs the gate drive signal which changes between the negative power supply potential and the power supply potential in synchronization with the timing signal. The semiconductor integrated circuit according to claim 7, wherein the overcurrent detection circuit controls the first output circuit so that the gate drive signal having the negative power supply potential is output after the output signal of the comparator changes from a first level to a second level.

10. An abnormality notification terminal that outputs an abnormality notification signal to notify of the occurrence of an abnormality, A second output circuit that generates the abnormality notification signal based on the control signal from the overcurrent detection circuit and outputs the abnormality notification signal via the abnormality notification terminal, Furthermore, The semiconductor integrated circuit according to claim 7, wherein the overcurrent detection circuit controls the second output circuit so that the abnormality notification signal output from the second output circuit changes from the third level to the fourth level after a first time has elapsed from the time the output signal of the comparator changes from the first level to the second level.

11. The system further comprises a threshold voltage detection circuit positioned between the threshold voltage adjustment circuit and the comparator, The threshold voltage detection circuit is, During the first period, the threshold voltage output from the threshold voltage adjustment circuit is passed through the comparator, and the capacitor is charged by the threshold voltage. In the second period other than the first period, the threshold voltage output from the threshold voltage adjustment circuit is not passed through the comparator, and the terminal voltage of the capacitor is output to the comparator. The semiconductor integrated circuit according to claim 10, wherein the first period is the period from the time when the gate drive signal has fallen for a second time until the gate drive signal begins to rise, or the period from the time when the abnormality notification signal has changed from the third level to the fourth level for a third time until the gate drive signal begins to rise.

12. A first isolation circuit is disposed between the input terminal and the input circuit, A second isolation circuit is disposed between the abnormality notification terminal and the second output circuit, The semiconductor integrated circuit according to claim 10, further comprising:

13. The semiconductor integrated circuit according to claim 7, wherein the overcurrent detection circuit includes a constant current source that outputs a current proportional to the threshold voltage output from the threshold voltage adjustment circuit as the detection current.

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