Communication system

Abstract

The goal is to provide highly reliable communication systems. [Solution] The communication system comprises a first isolated transmission circuit, a second isolated transmission circuit, and a control logic circuit. The first isolated transmission circuit comprises a first transmitter, an isolated transmission unit, and a first receiver. The first transmitter converts a first input signal into a first transmission signal. The isolated transmission unit transmits the first transmission signal isolatedly from a primary chip to a secondary chip. The first receiver demodulates the first transmission signal. The second isolated transmission circuit comprises a second transmitter, an isolated transmission unit, and a second receiver. The second transmitter converts a second input signal into a second transmission signal. The isolated transmission unit transmits the second transmission signal isolatedly from a secondary chip to a primary chip. The second receiver demodulates the second transmission signal. The control logic circuit detects the reception of the first transmission signal in the first receiver and transmits a transmission start signal to the second transmitter. The second transmitter transmits the second transmission signal based on the transmission start signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a communication system.

Background Art

[0002] A communication system that performs bidirectional insulated transmission between a primary chip and a secondary chip is known. In such a communication system, when the insulated transmission from the primary chip to the secondary chip and the insulated transmission from the secondary chip to the primary chip overlap, there is a risk that switching noises interfere with each other and cause malfunction.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a communication system with excellent reliability.

Means for Solving the Problems

[0005] The communication system of this embodiment is a communication system that performs isolated transmission between a primary chip and a secondary chip. The communication system has a first isolated transmission circuit, a second isolated transmission circuit, and a control logic circuit. The first isolated transmission circuit transmits a first input signal isolatedly from the primary chip to the secondary chip. The second isolated transmission circuit transmits a second input signal isolatedly from the secondary chip to the primary chip. The control logic circuit connects the first isolated transmission circuit and the second isolated transmission circuit at the secondary chip. The first isolated transmission circuit has a first transmitter, an isolated transmission unit, and a first receiver. The first transmitter receives a first input signal at the primary chip and converts it into a first transmission signal. The isolated transmission unit transmits the first transmission signal isolatedly from the primary chip to the secondary chip. The first receiver receives the first transmission signal at the secondary chip, demodulates it, and outputs a first output signal. The second isolated transmission circuit has a second transmitter, an isolated transmission unit, and a second receiver. The second transmitter receives the second input signal at the secondary chip and converts it into a second transmission signal. The isolated transmission unit transmits the second transmission signal isolatedly from the secondary chip to the primary chip. The second receiver receives the second transmission signal at the primary chip, demodulates it, and outputs a second output signal. The control logic circuit detects the reception of the first transmission signal at the first receiver and sends a transmission start signal to the second transmitter. The second transmitter transmits the second transmission signal based on the transmission start signal. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a communication system in one embodiment. [Figure 2] A waveform diagram showing an example of the operation of a communication system in one embodiment. [Figure 3] A schematic diagram showing examples of first and second pulses that can be used in a communication system 1 according to one embodiment. [Figure 4] A block diagram showing an example of the configuration of a modified communication system. [Modes for carrying out the invention]

[0007] The communication system of the embodiment will be described below with reference to the drawings.

[0008] Figure 1 is a block diagram showing an example of the configuration of a communication system 1 according to one embodiment. The communication system 1 according to this embodiment is, for example, a digital isolator.

[0009] The communication system 1 of this embodiment comprises a primary chip 10, a secondary chip 20, and an isolated transmission unit 30. The communication system 1 performs bidirectional transmission of digital logic signals between the electrically isolated primary chip 10 and the secondary chip 20. In other words, the communication system 1 performs isolated transmission between the primary chip 10 and the secondary chip 20.

[0010] The primary chip 10 is equipped with a first transmitting unit 11 and a second receiving unit 22. The secondary chip 20 is equipped with a first receiving unit 12, a second transmitting unit 21, and a control logic circuit 40. The isolated transmission unit 30 connects the primary chip 10 and the secondary chip 20. The isolated transmission unit 30 has a first insulating element 31 and a second insulating element 32.

[0011] The communication system 1 includes a first isolated transmission circuit T1, a second isolated transmission circuit T2, and a control logic circuit 40. The first isolated transmission circuit T1 spans both the primary chip 10 and the secondary chip 20. Similarly, the second isolated transmission circuit T2 spans both the primary chip 10 and the secondary chip 20. The control logic circuit 40 is located on the secondary chip 20.

[0012] The first isolated transmission circuit T1 transmits the first input signal Si1 from the primary chip 10 to the secondary chip 20 in isolation. The first isolated transmission circuit T1 includes a first transmitting unit 11, a first insulating element 31, and a first receiving unit 12. The first input signal Si1 is, for example, a gate control signal.

[0013] The second isolated transmission circuit T2 transmits the second input signal Si2 from the secondary chip 20 to the primary chip 10 in an isolated manner. The second isolated transmission circuit T2 includes a second transmitting unit 21, a second insulating element 32, and a second receiving unit 22. The second isolated transmission circuit T2 of this embodiment transmits a plurality of second input signals Si2 in an isolated manner. The plurality of second input signals Si2 include a second input signal Si2A (second input signal A) and a second input signal Si2B (second input signal B). The second input signals Si2A and Si2B are, for example, a Ready signal and a Fault signal, respectively.

[0014] As described above, the first insulating element 31 and the second insulating element 32 are each part of the insulating transmission section 30. Therefore, the insulating transmission section 30 is shared by the first insulating transmission circuit T1 and the second insulating transmission circuit T2. The first insulating transmission circuit T1 and the second insulating transmission circuit T2 each have the insulating transmission section 30. In this embodiment, the first insulating element 31 and the second insulating element 32 are both isolation transformers, but are not limited to these.

[0015] Figure 2 is a waveform diagram illustrating an example of the operation of communication system 1. As shown in Figure 2, in communication system 1, the first isolated transmission circuit T1, the second isolated transmission circuit T2, and the control logic circuit 40 communicate using the first pulse P1 and the second pulse P2. Note that in Figure 2, the first pulse P1 and the second pulse P2 are shown in a simplified manner, but the actual first pulse P1 and the second pulse P2 have more complex pulse waveforms. That is, the first pulse P1 and the second pulse P2 have different signal configurations.

[0016] Figure 3 is a schematic diagram showing examples of pulse waveforms of the first pulse P1 and the second pulse P2 in the first isolated transmission circuit T1 of this embodiment. The waveform in Example 1 is, for example, the encoded waveform in the first transmitting unit 11. The waveform in Example 2 is, for example, the pulse waveform of the first transmission signal St1 transmitted by the first transmitting unit 11. The waveform in Example 3 is, for example, the waveform of the first transmission signal St1 output from the first insulating element 31 and received by the first receiving circuit 12c. The waveform in Example 4 is, for example, the waveform of the received pulse obtained by shaping and amplified the pulse waveform shown in Example 3 by the first receiving circuit 12c. The waveform in Example 5 is, for example, the waveform of the received pulse obtained by binarizing the received pulse of Example 4 by the first receiving circuit 12c. Therefore, the first receiving circuit 12c demodulates the waveform of Example 5 and outputs the first output signal So1. In this way, the first pulse P1 and the second pulse P2 used in the first isolated transmission circuit T1 have different signal forms. Furthermore, the first pulse P1 and the second pulse P2 used in the first isolated transmission circuit T1 may be pulse waveforms other than the example pulse waveform shown in Figure 3, as long as they have different signal configurations. Also, the pulse waveform used in the second isolated transmission circuit T2 may be the same as the pulse waveform shown in Figure 3, or it may be a different pulse waveform. In other words, the first pulse P1 and the second pulse P2 used in the second isolated transmission circuit T2 may be the same as or different from those in the first isolated transmission circuit T1, as long as they have different signal configurations.

[0017] The following describes the configuration of each component of communication system 1 in detail, based on Figures 1 and 2. As shown in Figure 1, the first transmitting unit 11 includes, for example, a first detection circuit 11a, a first transmitting circuit 11b, and a refresh timing generation circuit 11c. The first transmitting unit 11 receives a first input signal Si1 at the primary chip 10 and converts it into a first transmission signal St1. The first input signal Si1 changes between a first level and a second level, which have different voltage levels. In this embodiment, the first level is a high level, and the second level is a low level with a lower voltage level than the first level. However, the high level and low level of the first input signal Si1 may be the opposite of those in this embodiment.

[0018] The refresh timing generation circuit 11c is connected to the first detection circuit 11a. The refresh timing generation circuit 11c transmits a refresh timing signal Sr1 to the first detection circuit 11a. The refresh timing signal Sr1 is transmitted to the first detection circuit 11a, for example, at every predetermined fixed time interval (hereinafter referred to as a refresh period ta).

[0019] The first detection circuit 11a is connected to an external control device (not shown), the first transmission circuit 11b, and the refresh timing generation circuit 11c. The first detection circuit 11a receives, for example, a first input signal Si1 from the external control device. Also, the first detection circuit 11a receives the refresh timing signal Sr1 from the refresh timing generation circuit 11c. The first detection circuit 11a detects the state of the first input signal Si1, that is, whether the first input signal Si1 is at a high level (first level) or a low level (second level).

[0020] The first detection circuit 11a transmits a first detection signal Sd1 corresponding to the level of the first input signal Si1 to the first transmission circuit 11b, for example, at the timing when the first input signal Si1 changes from a low level to a high level (rising edge) and at the timing when it changes from a high level to a low level (that is, falling edge). Further, the first detection circuit 11a transmits the first detection signal Sd1 corresponding to the level of the first input signal Si1 to the first transmission circuit 11b at the timing when it receives the refresh timing signal Sr1 from the refresh timing generation circuit 11c. That is, the first detection circuit 11a transmits the first detection signal Sd1 to the first transmission circuit 11b at every fixed time interval (refresh period ta).

[0021] The first transmission circuit 11b is, for example, an encoder. The first transmission circuit 11b is connected to the first detection circuit 11a and the first insulator 31. The first transmission circuit 11b generates a first transmission signal St1 according to the first detection signal Sd1 received from the first detection circuit 11a, and transmits it to the first insulator 31. Also, the first transmission circuit 11b generates a first transmission signal St1 according to the level of the first input signal Si1 and transmits it to the first insulator 31.

[0022] As shown in FIG. 2, the first transmission signal St1 includes a first pulse P1 and a second pulse P2. The first transmission circuit 11b transmits, for example, the first pulse P1 or the second pulse P2 as the first transmission signal St1 in synchronization with the rising or falling of the first input signal Si1. Also, the first transmission circuit 11b generates the first pulse P1 when the first input signal Si1 is at a high level, and generates the second pulse P2 when the first input signal Si1 is at a low level.

[0023] Based on FIG. 2, the timing for the first transmission unit 11 to generate and transmit the first pulse P1 and the second pulse P2 will be described in detail. When the first input signal Si1 changes from a low level to a high level (at the rising edge), the first transmission unit 11 generates the first pulse P1 and transmits it to the first insulator 31. Also, when the first input signal Si1 is continuously at a high level, the first transmission unit 11 generates the first pulse P1 at a constant time interval (refresh period ta) and transmits it to the first insulator 31.

[0024] Furthermore, when the first input signal Si1 changes from a high level to a low level (at the falling edge), the first transmission unit 11 generates the second pulse P2 and transmits it to the first insulator 31. In addition, when the first input signal Si1 is continuously at a low level, the first transmission unit 11 generates the second pulse P2 at a constant time interval (refresh period ta) and transmits it to the first insulator 31.

[0025] According to this embodiment, the first transmitting unit 11 transmits either the first pulse P1 or the second pulse P2 at a refresh cycle ta, and also transmits either the first pulse P1 or the second pulse P2 regardless of the refresh cycle ta when the level changes between a low level and a high level. Therefore, the first pulse P1 and the second pulse P2 as the first transmission signal St1 are transmitted at intervals of at least the refresh cycle ta or less. In other words, as long as the communication system 1 is running, the first transmitting unit 11 continues to transmit either the first pulse P1 or the second pulse P2 at intervals of at least the refresh cycle ta or less.

[0026] As shown in Figure 1, the first insulating element 31 is positioned across the primary chip 10 and the secondary chip 20. The first insulating element 31 is connected to the first transmitting circuit 11b and the first receiving circuit 12c. The first insulating element 31 transmits the first transmission signal St1 generated by the first transmitting unit 11 to the first receiving unit 12. In other words, the first insulating element 31 transmits the first transmission signal St1 from the primary chip 10 to the secondary chip 20 with isolation.

[0027] The first insulating element 31 transmits the first pulse P1 and the second pulse P2, which are the first transmission signals St1, from the primary chip 10 to the secondary chip 20 while ensuring galvanic isolation, and outputs them to the first receiving unit 12.

[0028] The first receiving unit 12 includes, for example, a first receiving circuit 12c. The first receiving unit 12 receives and demodulates the first transmission signal St1 on the secondary chip to generate a first output signal So1. The first receiving unit 12 also outputs the generated first output signal So1 to the outside.

[0029] The first receiving circuit 12c is composed of, for example, a decoder, a comparator, and an amplifier. The first receiving circuit 12c is connected to the first insulating element 31 and an external device (not shown). The first receiving circuit 12c generates a first output signal So1 based on a first pulse P1 and a second pulse P2, which are the first transmission signal St1 received from the first insulating element 31.

[0030] As shown in Figure 2, when the first receiving circuit 12c receives the first pulse P1, it generates a high-level first output signal So1 and outputs it externally until it receives the next pulse. Also, when the first receiving circuit 12c receives the second pulse P2, it generates a low-level first output signal So1 and outputs it externally until it receives the next pulse.

[0031] Furthermore, as shown in Figure 1, the first receiving circuit 12c is connected to the control logic circuit 40. The first receiving circuit 12c can generate a reception completion signal Sc and transmit it to the control logic circuit 40.

[0032] As shown in Figure 2, the reception completion signal Sc is, for example, a rectangular pulse signal. However, the signal form of the reception completion signal Sc is not limited. The first receiving unit 12 generates a reception completion signal Sc each time it receives a first pulse P1 and a second pulse P2 as the first transmission signal St1 and transmits it to the control logic circuit 40. The first receiving unit 12 transmits a reception completion signal Sc with the same signal form regardless of whether the first transmission signal St1 is the first pulse P1 or the second pulse P2.

[0033] As shown in Figure 1, the control logic circuit 40 is connected to the first receiving unit 12 and the second transmitting unit 21. That is, the control logic circuit 40 connects the first isolated transmission circuit T1 and the second isolated transmission circuit T2 in the secondary chip 20. The control logic circuit 40 receives a reception completion signal Sc from the first receiving unit 12. The control logic circuit 40 also transmits a transmission start signal Sb to the second transmitting unit 21. In this embodiment, the transmission start signal Sb includes a first transmission start signal SbA and a second transmission start signal SbB.

[0034] The control logic circuit 40 detects that the first receiving unit 12 has received the first transmission signal St1 by receiving a reception completion signal Sc from the first receiving unit 12. Furthermore, when the control logic circuit 40 receives the reception completion signal Sc, it generates a transmission start signal Sb and transmits it to the second transmitting unit 21. In other words, the control logic circuit 40 detects the reception of the first transmission signal St1 in the first receiving unit 12 and transmits the transmission start signal Sb to the second transmitting unit 21.

[0035] As shown in Figure 2, the transmission start signal Sb in this embodiment includes a first transmission start signal SbA and a second transmission start signal SbB. The first transmission start signal SbA and the second transmission start signal SbB are generated at different timings. The second transmission start signal SbB is generated with a delay relative to the first transmission start signal SbA. The control logic circuit 40 transmits the first transmission start signal SbA and the second transmission start signal SbB consecutively to the second transmission unit 21. Note that, as shown in Figure 1, the first transmission start signal SbA and the second transmission start signal SbB are transmitted to the second transmission unit 21 via different signal lines.

[0036] As shown in Figure 1, the second transmitting unit 21 includes, for example, a second detection circuit 21a and a second transmitting circuit 21b. The second transmitting unit 21 receives a second input signal Si2 in the secondary chip 20 and converts it into a second transmission signal St2.

[0037] The second detection circuit 21a is connected to an external device (not shown) and a second transmission circuit 21b. The second detection circuit 21a receives, for example, two second input signals Si2A and Si2B from the external device. The second input signal Si2A changes between a third level and a fourth level, which have different voltage levels. In this embodiment, the third level is a high level, and the fourth level is a low level, which has a lower voltage level than the third level. However, the high and low levels of the second input signal Si2A may be reversed from those in this embodiment. Similarly, the second input signal Si2B changes between a fifth level and a sixth level, which have different voltage levels. In this embodiment, the fifth level is a high level, and the sixth level is a low level, which has a lower voltage level than the fifth level. However, the high and low levels of the second input signal Si2B may be reversed from those in this embodiment. The second detection circuit 21a individually detects the state of the second input signals Si2A and Si2B, that is, whether the second input signals Si2A and Si2B are at a high level or a low level, respectively.

[0038] The second detection circuit 21a is connected to the second transmission circuit 21b. The second detection circuit 21a is capable of transmitting two types of second detection signals Sd2, corresponding to the two second input signals Si2A and Si2B. In the following description, when distinguishing between the two types of second detection signals, the signal corresponding to the second input signal Si2A will be called the second detection signal Sd2A, and the signal corresponding to the second input signal Si2B will be called the second detection signal Sd2B.

[0039] The second detection circuit 21a transmits the second detection signal Sd2A to the second transmission circuit 21b at the timing when the second input signal Si2A changes from a low level (fourth level) to a high level (third level) (rising edge). The second detection circuit 21a also transmits the second detection signal Sd2B to the second transmission circuit 21b at the timing when the second input signal Si2B changes from a low level (sixth level) to a high level (fifth level) (rising edge).

[0040] The second transmitting circuit 21b is, for example, an encoder. The second transmitting circuit 21b is connected to the control logic circuit 40, the second detection circuit 21a, and the second insulating element 32. The second transmitting circuit 21b generates a second transmission signal St2 in response to the transmission start signal Sb received from the control logic circuit 40 and the second detection signal Sd2 received from the second detection circuit 21a, and transmits it to the second insulating element 32.

[0041] As shown in Figure 2, the second transmission signal St2 includes a first pulse P1 and a second pulse P2. The second transmission circuit 21b transmits either the first pulse P1 or the second pulse P2 when it receives the second detection signal Sd2. That is, the second transmission circuit 21b transmits either the first pulse P1 or the second pulse P2, respectively, when the second input signal Si2A or the second input signal Si2B changes from a low level to a high level (rising edge). Furthermore, the second transmission circuit 21b transmits the first pulse P1 when it receives the first transmission start signal SbA, and transmits the second pulse P2 when it receives the second transmission start signal SbB. In addition, the second transmission circuit 21b generates the first pulse P1 when the second input signal Si2A is at a high level, and generates the second pulse P2 when the second input signal Si2B is at a high level. The second transmission circuit 21b does not transmit the second transmission signal St2 if both the second input signal Si2A and the second input signal Si2B are at a low level.

[0042] Based on Figure 2, the timing of when the second transmitter 21 transmits the first pulse P1 and the second pulse P2 will be explained in detail. As described above, the second transmission signal St2 is transmitted by the second transmission unit 21 at the timing when the second input signals Si2A and Si2B rise, and at the timing when the second transmission unit 21 receives the transmission start signal Sb.

[0043] The second transmitting unit 21 generates a first pulse P1 and transmits it to the second insulating element 32 when the second input signal Si2A changes from a low level to a high level (rising edge). The second transmitting unit 21 also generates a second pulse P2 and transmits it to the second insulating element 32 when the second input signal Si2B changes from a low level to a high level (rising edge).

[0044] The second transmitter 21 generates a first pulse P1 and transmits it to the second insulating element 32 when it receives the first transmission start signal SbA and the second input signal Si2A is at a high level. The second transmitter 21 also transmits a second pulse P2 when it receives the second transmission start signal SbB and the second input signal Si2B is at a high level.

[0045] In this embodiment, the control logic circuit 40 transmits a transmission start signal Sb to the second transmission unit 21 after receiving a reception completion signal Sc. Therefore, the transmission of the transmission start signal Sb by the control logic circuit 40 is delayed by at least the pulse width of the reception completion signal Sc compared to the transmission of the first transmission signal St1 by the first transmission unit 11. As a result, according to this embodiment, the transmission of the second transmission signal St2 can be staggered relative to the transmission of the first transmission signal St1, and simultaneous transmission of the first transmission signal St1 and the second transmission signal St2 can be suppressed.

[0046] Next, we will explain the operation of the second transmitter 21 when the rising edge timings of the second input signals Si2A and Si2B coincide with the timing at which the second transmitter 21 receives the transmission start signal Sb.

[0047] For example, consider the case where a virtual transmission start signal VSb is transmitted at the same time as the rising edge of the second input signal Si2B, as shown by the dashed line (double-dotted line) in Figure 2. Although not shown in Figure 2, the virtual transmission start signal VSb is transmitted, for example, due to the rising or falling edge of the first input signal Si1. In other words, here we will explain the processing when the rising or falling edge of the first input signal Si1 and the rising edge of the second input signal Si2B occur simultaneously. In this case, the second transmission circuit 21b receives the pulse of the transmission start signal VSb and the pulse of the second detection signal Sd2B simultaneously.

[0048] If the virtual transmission start signal VSb is not transmitted (i.e., as shown by the solid line in Figure 2), the second transmission circuit 21b receives only the pulse of the second detection signal Sd2B corresponding to the rising edge of the second input signal Si2B. In this case, as shown by the solid line in Figure 2, the second transmission circuit 21b transmits the second pulse P2.

[0049] In contrast, as shown as a dashed line in Figure 2, the second transmitting circuit 21b simultaneously receives the pulse of the second detection signal Sd2B, which indicates the rising edge of the second input signal Si2B, and the pulse of the transmission start signal VSb. In this case, ideally, the second transmitting circuit 21b would be required to simultaneously perform processing for the reception of the second detection signal Sd2B (transmission of the second pulse P2) and processing for the reception of the transmission start signal VSb (transmission of the first pulse P1). However, the second transmitting circuit 21b cannot transmit the first pulse P1 and the second pulse P2 simultaneously. Therefore, in this embodiment, the second transmitting circuit 21b prioritizes processing for the reception of the transmission start signal VSb and transmits the first pulse P1 (shown as a dashed line in Figure 2). Furthermore, the second transmitting circuit 21b stops the transmission of the second pulse P2 (shown as a solid line in Figure 2), which is processing for the reception of the second detection signal Sd2B. In other words, if the processing for receiving the second detection signal Sd2B and the processing for receiving the transmission start signal VSb overlap, the second transmission circuit 21b prioritizes processing for receiving the transmission start signal VSb. Processing for the stopped second detection signal Sd2B is carried over until the next pulse of the transmission start signal Sb is received.

[0050] According to this embodiment, the second transmitting unit 21 can execute each process while ensuring reliability when signals requiring different processing are received simultaneously. Furthermore, by prioritizing the processing corresponding to the transmission start signal VSb, it is possible to suppress the time interval between the transmission of the first pulse P1 (or second pulse P2) from exceeding the refresh period ta. This ensures the reliability of the demodulation of the second output signal So2 in the second receiving unit 22, which will be described later.

[0051] As shown in Figure 1, the second insulating element 32 is positioned across the primary chip 10 and the secondary chip 20. The second insulating element 32 is connected to the second transmitting circuit 21b and the second receiving circuit 22c. The second insulating element 32 transmits the second transmission signal St2 generated by the second transmitting unit 21 to the second receiving unit 22. In other words, the second insulating element 32 transmits the second transmission signal St2 from the secondary chip 20 to the primary chip 10 with isolation.

[0052] The second insulating element 32 transmits the first pulse P1 and the second pulse P2, which are the second transmission signals St2, from the primary chip 10 to the secondary chip 20 while ensuring galvanic isolation, and outputs them to the second receiving unit 22.

[0053] The second receiving unit 22 includes, for example, a second receiving circuit 22c, a first monitoring timer 22a, and a second monitoring timer 22b. The second receiving unit 22 receives and demodulates the second transmission signal St2 on the secondary chip to generate a second output signal So2. The second receiving unit 22 also outputs the generated second output signal So2 to the outside.

[0054] As described above, the second isolated transmission circuit T2 of this embodiment receives a plurality of second input signals Si2A and Si2B. Therefore, the second isolated transmission circuit T2 outputs a plurality of second output signals So2A and So2B corresponding to each of the second input signals Si2A and Si2B. The plurality of second output signals So2 include second output signal So2A (second output signal A) and second output signal So2B (second output signal B). Second output signal So2A (second output signal A) is a signal output in correspondence with second input signal Si2A (second input signal A). Therefore, a high level (third level) of the second input signal Si2A corresponds to a high level (third level) of the second output signal So2A, and a low level (fourth level) of the second input signal Si2A corresponds to a low level (fourth level) of the second output signal So2A. Furthermore, the second output signal So2B (second output signal B) is a signal output in correspondence with the second input signal Si2B (second input signal B). Therefore, the high level (fifth level) of the second input signal Si2B corresponds to the high level (fifth level) of the second output signal So2B, and the low level (sixth level) of the second input signal Si2B corresponds to the low level (sixth level) of the second output signal So2B. The second receiver 22 outputs the second output signal So2A based on the first pulse P1. Also, the second receiver 22 outputs the second output signal So2B based on the second pulse P2.

[0055] The second receiving circuit 22c is composed of, for example, an amplifier, a converter, and a decoder. The second receiving circuit 22c is connected to the first insulating element 31, the first monitoring timer 22a, the second monitoring timer 22b, and an external device (not shown). The second receiving circuit 22c receives the first pulse P1 and the second pulse P2 as the second transmission signal St2, generates the second output signal So2, and outputs it to the external device.

[0056] The first monitoring timer 22a and the second monitoring timer 22b are connected to the second receiving circuit 22c. The first monitoring timer 22a measures the time elapsed since the second receiving circuit 22c received the first pulse P1. The second monitoring timer 22b measures the time elapsed since the second receiving circuit 22c received the second pulse P2.

[0057] Based on Figure 2, the operation of the first monitoring timer 22a, the second monitoring timer 22b, and the second receiving circuit 22c will be explained. The second receiving circuit 22c transmits a reset signal to the first monitoring timer 22a each time it receives the first pulse P1 from the second insulating element 32. Furthermore, the second receiving circuit 22c transmits a reset signal to the second monitoring timer 22b each time it receives the second pulse P2 from the second insulating element 32.

[0058] The first monitoring timer 22a resets (CLR) upon receiving a reset signal transmitted from the second receiving circuit 22c. Furthermore, if the time elapsed since receiving the first pulse P1 exceeds a predetermined monitoring period tb, the first monitoring timer 22a notifies the second receiving circuit 22c of a timeout (TO).

[0059] The second monitoring timer 22b receives a reset signal transmitted from the second receiving circuit 22c and resets (CLR). Furthermore, if the measurement time exceeds a predetermined monitoring period tb, the second monitoring timer 22b notifies the second receiving circuit 22c of a timeout (TO).

[0060] When the second receiving circuit 22c receives the first pulse P1, it sends a reset signal to the first monitoring timer 22a and raises the second output signal So2A from a low level to a high level. Also, when the second receiving circuit 22c receives a timeout (TO) notification from the first monitoring timer 22a, it lowers the second output signal So2A from a high level to a low level. As a result, the second receiving circuit 22c can demodulate the second output signal So2A.

[0061] When the second receiving circuit 22c receives the second pulse P2, it sends a reset signal to the second monitoring timer 22b and raises the second output signal So2B from a low level to a high level. Also, when the second receiving circuit 22c receives a timeout (TO) notification from the second monitoring timer 22b, it lowers the second output signal So2B from a high level to a low level. As a result, the second receiving circuit 22c can demodulate the second output signal So2B.

[0062] In this embodiment, the first transmitter 11 transmits a first pulse P1 or a second pulse P2 at a fixed time interval (refresh period ta) when the first input signal Si1 is continuously at a high level or a low level. Furthermore, the first transmitter 11 transmits a first pulse P1 or a second pulse P2 regardless of the refresh period ta when the level of the first input signal Si1 changes. Therefore, the first transmitter 11 transmits a first pulse P1 or a second pulse P2 at intervals of at least the refresh period ta or less. The second transmitter 21 transmits a first pulse P1 or a second pulse P2 triggered by a pulse transmitted from the first transmitter 11. Therefore, the second transmitter 21 transmits a first pulse P1 at intervals of at least the refresh period ta or less when the second input signal Si2A is continuously at a high level. Similarly, the second transmitter 21 transmits a second pulse P2 at intervals of at least the refresh period ta or less when the second input signal Si2B is continuously at a high level. In this embodiment, the monitoring period tb is longer than the refresh period ta. Therefore, the first monitoring timer 22a and the second monitoring timer 22b notify a timeout (TO) based on the monitoring period tb, and the second receiving unit 22 can determine, based on the timeout (TO) notification, that the second input signals Si2A and Si2B are not maintaining a high level.

[0063] In the second isolated transmission circuit T2 of this embodiment, the second transmitting unit 21 transmits either the first pulse P1 or the second pulse P2 as the second transmission signal St2 when the second input signal Si2 is rising. Therefore, the second isolated transmission circuit T2 can minimize the delay time tc between the rising edge of the second output signal So2 and the rising edge of the second input signal Si2.

[0064] Furthermore, in the second isolated transmission circuit T2 of this embodiment, the second receiving unit 22 generates the falling edge of the second output signal So2 in accordance with the notification of a timeout (TO) of the first monitoring timer 22a or the second monitoring timer 22b. For this reason, the second isolated transmission circuit T2 can set the delay time td of the falling edge of the second output signal So2 relative to the falling edge of the second input signal Si2 to a time less than or equal to the monitoring period tb.

[0065] Next, the effects and advantages of this embodiment will be described. The communication system 1 of this embodiment is a communication system 1 that performs isolated transmission between a primary chip 10 and a secondary chip 20. The communication system 1 has a first isolated transmission circuit T1, a second isolated transmission circuit T2, and a control logic circuit 40. The first isolated transmission circuit T1 transmits a first input signal Si1 from the primary chip 10 to the secondary chip 20 in an isolated manner. The second isolated transmission circuit T2 transmits a second input signal Si2 from the secondary chip 20 to the primary chip 10 in an isolated manner. The control logic circuit 40 connects the first isolated transmission circuit T1 and the second isolated transmission circuit T2 in the secondary chip 20. The first isolated transmission circuit T1 has a first transmitting unit 11, an isolated transmission unit 30, and a first receiving unit 12. The first transmitting unit 11 receives the first input signal Si1 in the primary chip 10 and converts it into a first transmission signal St1. The isolated transmission unit 30 transmits the first transmission signal St1 from the primary chip 10 to the secondary chip 20 in isolation. The first receiving unit 12 receives the first transmission signal St1 at the secondary chip 20, demodulates it, and outputs the first output signal So1. The second isolated transmission circuit T2 includes a second transmitting unit 21, an isolated transmission unit 30, and a second receiving unit 22. The second transmitting unit 21 receives the second input signal Si2 at the secondary chip 20 and converts it into the second transmission signal St2. The isolated transmission unit 30 transmits the second transmission signal St2 from the secondary chip 20 to the primary chip 10 in isolation. The second receiving unit 22 receives the second transmission signal St2 at the primary chip 10, demodulates it, and outputs the second output signal So2. The control logic circuit 40 detects the reception of the first transmission signal St1 at the first receiving unit 12 and transmits a transmission start signal Sb to the second transmitting unit 21. The second transmitting unit 21 transmits the second transmission signal St2 based on the transmission start signal Sb.

[0066] In this configuration, the second transmitter 21 transmits the second transmission signal St2 based on the transmission start signal Sb. The transmission start signal Sb is transmitted after the first receiver 12 receives the first transmission signal St1. Therefore, the timing of the isolated transmission of the first transmission signal St1 in the first isolated transmission circuit T1 and the timing of the isolated transmission of the second transmission signal St2 in the second isolated transmission circuit T2 can be staggered. As a result, it is possible to suppress noise caused by the first transmission signal St1 and the second transmission signal St2 mutually influencing each other and causing malfunctions. In addition, it is possible to suppress electromagnetic interference (EMI) caused by the first transmission signal St1 and the second transmission signal St2 superimposing and affecting external equipment. Furthermore, in this communication system 1, because the transmission timings of the first transmission signal St1 and the second transmission signal St2 are staggered, it becomes possible to adopt a configuration in which the isolated transmission of the first input signal Si1 and the second input signal Si2 is performed using a single insulating element 131, as shown in the modified example 1 described later (see Figure 4).

[0067] In the communication system 1 described above, the first transmission signal St1 includes a first pulse P1 and a second pulse P2 having different signal modes. The first transmitting unit 11 transmits the first pulse P1 at regular time intervals when the first input signal Si1 changes from a low level to a high level, and when the first input signal Si1 remains at a high level. The first transmitting unit 11 transmits the second pulse P2 at regular time intervals when the first input signal Si1 changes from a high level to a low level, and when the first input signal Si1 remains at a low level.

[0068] According to this configuration, the first transmission signal St1 includes a first pulse P1 assigned when the first input signal Si1 is at a high level, and a second pulse P2 assigned when it is at a low level. Therefore, it is possible to convert the first input signal Si1 to the first transmission signal St1 while minimizing the delay with respect to the rising and falling edges of the first input signal Si1. In other words, according to this configuration, in a communication system 1 that performs isolated transmission bidirectionally, it is possible to suppress the delay of isolated transmission of the first input signal Si1 in at least the first isolated transmission circuit T1.

[0069] In the communication system 1 described above, the second input signal Si2 includes the second input signal Si2A and the second input signal Si2B. The second transmission signal St2 includes the first pulse P1 and the second pulse P2, which have different signal modes. The second transmitter 21 transmits the first pulse P1 when the second input signal Si2A is at a high level upon receiving the transmission start signal Sb. The second transmitter 21 transmits the second pulse P2 when the second input signal Si2B is at a high level upon receiving the transmission start signal Sb.

[0070] With this configuration, when the second input signal Si2 contains two signals (second input signals Si2A and Si2B), the two second input signals Si2A and Si2B can be converted into a second transmission signal St2 containing a first pulse P1 and a second pulse P2. Therefore, the communication system 1 does not need to increase the number of isolated transmission circuits in accordance with the number of signals contained in the second input signal Si2, and the communication system 1 can be miniaturized.

[0071] In the communication system 1 described above, the transmission start signal Sb includes a first transmission start signal SbA and a second transmission start signal SbB. The second transmission start signal SbB is generated with a delay relative to the first transmission start signal SbA. The second transmission unit 21 transmits a first pulse P1 when it receives the first transmission start signal SbA and the second input signal Si2A is at a high level. The second transmission unit 21 transmits a second pulse P2 when it receives the second transmission start signal SbB and the second input signal Si2B is at a high level.

[0072] In this configuration, the control logic circuit 40 transmits a first transmission start signal SbA corresponding to the second input signal Si2A and a second transmission start signal SbB corresponding to the second input signal Si2B, with a time delay. The second transmission unit 21 transmits a first pulse P1 triggered by the reception of the first transmission start signal SbA, and transmits a second pulse P2 triggered by the reception of the second transmission start signal SbB. Therefore, the second transmission unit 21 can transmit the first pulse P1 and the second pulse P2 with a time delay without superimposing them.

[0073] In the communication system 1 described above, the second transmitting unit 21 transmits a first pulse P1 when the second input signal Si2A changes from a low level to a high level. The second transmitting unit 21 transmits a second pulse P2 when the second input signal Si2B changes from a low level to a high level.

[0074] With this configuration, the second transmitter 21 transmits the first pulse P1 or the second pulse P2 not only when it receives the transmission start signal Sb described above, but also when it detects the rising edge of the second input signal Si2A or the second input signal Si2B. Therefore, it is possible to convert the second input signal Si2 to the second transmission signal St2 while minimizing the delay to the rising edges of the second input signals Si2A and Si2B. In other words, with this configuration, the delay of isolated transmission of the second input signal Si2 in the second isolated transmission circuit T2 can be suppressed. However, when this configuration is adopted, the second transmitter 21 transmits the second transmission signal St2 at the timing when it detects the rising edge of the second input signal Si2, regardless of the reception of the transmission start signal Sb. Therefore, when this configuration is adopted, there is a low probability that the timing of transmission of the first transmission signal St1 and the timing of transmission of the second transmission signal St2 may overlap. Therefore, this configuration is preferable when the rising edges of the second input signals Si2A and Si2B are infrequent and the occurrence of the above-mentioned timing overlap is sufficiently rare. On the other hand, instead of adopting this configuration, a configuration may be adopted in which the second transmitting unit 21 transmits the second transmission signal St2 only when it receives the transmission start signal Sb. In this case, the timing of the transmission of the first transmission signal St1 and the timing of the transmission of the second transmission signal St2 can be completely staggered, and an even more reliable communication system 1 can be constructed.

[0075] The second transmitting unit 21 includes a second detection circuit 21a and a second transmitting circuit 21b. The second detection circuit 21a transmits a second detection signal Sd2 when the level of the second input signal Si2 changes. The second transmitting circuit 21b transmits a second transmission signal St2 to the isolated transmitting unit 30 based on the second detection signal Sd2 and the transmission start signal Sb. When the processing for receiving the second detection signal Sd2 and the processing for receiving the transmission start signal VSb (which is hypothetically shown in Figure 2) overlap, the second transmitting circuit 21b prioritizes the processing for receiving the transmission start signal VSb.

[0076] With this configuration, the second transmission unit 21 can ensure reliability by prioritizing one of the predetermined processes when different processes are required to be executed simultaneously. Furthermore, as shown by the dashed lines in Figure 2, prioritizing the transmission of the second transmission signal St2 in response to the reception of the transmission start signal VSb prevents the time interval between the transmission of the first pulse P1 or the second pulse P2 from becoming too long. This makes it possible to demodulate the second transmission signal St2 into the second output signal So2 using the time interval between the first pulse P1 or the second pulse P2 of the first transmission signal St1.

[0077] In the communication system 1 described above, the second receiving unit 22 outputs a second output signal So2A as a second output signal So2 based on the first pulse P1. The second receiving unit 22 outputs a second output signal So2B as a second output signal So2 based on the second pulse P2.

[0078] With this configuration, the second output signal So2A and the second output signal So2B can be demodulated based on the first pulse P1 and the second pulse P2. With this configuration, the second isolated transmission circuit T2 can transmit the two second input signals Si2A and Si2B as second output signals So2A and So2B in isolation without requiring a complex configuration.

[0079] In the communication system 1 described above, the second receiving unit 22 includes a second receiving circuit 22c, a first monitoring timer 22a, and a second monitoring timer 22b. The second receiving circuit 22c receives a first pulse P1 and a second pulse P2 and generates a second output signal So2. The first monitoring timer 22a measures the time elapsed since the second receiving circuit 22c received the first pulse P1. The second monitoring timer 22b measures the time elapsed since the second receiving circuit 22c generated the second pulse P2. When the second receiving circuit 22c receives the first pulse P1, it changes the second output signal So2A from a low level to a high level. When the measurement time of the first monitoring timer 22a exceeds the monitoring period tb, the second receiving circuit 22c changes the second output signal So2A from a high level to a low level. When the second receiving circuit 22c receives the second pulse P2, it changes the second output signal So2B from a low level to a high level. The second receiving circuit 22c changes the second output signal So2B from a high level to a low level when the measurement time of the second monitoring timer 22b exceeds the monitoring period tb.

[0080] This configuration allows for the smooth demodulation of the two second input signals Si2A and Si2B, which have been converted into a first pulse P1 and a second pulse P2, into second output signals So2A and So2B. Furthermore, this configuration uses a first monitoring timer 22a and a second monitoring timer 22b to determine the falling edge of the second output signals So2A and So2B. Therefore, it is possible to accurately demodulate the second output signals So2A and So2B without using any special configuration in the second receiving unit 22.

[0081] In the communication system 1 described above, the first transmitting unit 11 transmits pulses at regular time intervals (refresh period ta) when the first input signal Si1 is continuously at a high level or a low level. The monitoring period tb is longer than the regular time interval (refresh period ta).

[0082] In this configuration, the first transmitter 11 transmits a pulse at each refresh cycle ta. Therefore, the period of the transmission start signal Sb is at least less than or equal to the refresh cycle ta. As a result, when the second input signals Si2A and Si2B are continuously at a high level, the interval between the first pulse P1 and the second pulse P2 received by the second receiver 22 is less than or equal to the refresh cycle ta. The second receiver 22 can determine the falling edge of the second input signals Si2A and Si2B based on a monitoring cycle tb that is longer than the refresh cycle ta. In the above embodiment, the first transmitter 11 transmits the transmission start signal Sb regardless of the refresh cycle ta when it detects the rising or falling edge of the first input signal Si1. Therefore, the timing at which the first transmitter 11 transmits the transmission start signal Sb may be shorter than the refresh cycle ta.

[0083] In the communication system 1 described above, the isolated transmission unit 30 includes a first insulating element 31 and a second insulating element 32. The first insulating element 31 transmits the first transmission signal St1 from the primary chip 10 to the secondary chip 20 in an isolated manner. The second insulating element 32 transmits the second transmission signal St2 from the secondary chip 20 to the primary chip 10 in an isolated manner.

[0084] In this embodiment, the first input signal Si1, the second input signals Si2A and Si2B, the first output signal So1, and the second output signals So2A and So2B may be reversed, as long as they each change between two voltage levels (high level and low level). The high level and low level of the first input signal Si1, the second input signals Si2A and Si2B, and the first output signal So1 and the second output signals So2A and So2B do not necessarily correspond to each other.

[0085] Figure 4 is a block diagram showing an example of the configuration of a communication system 101 in a modified form of the above-described embodiment. The communication system 101 in this modified form differs from the above-described embodiment mainly in the configuration of the isolated transmission unit 130. Components that are the same as those in the above-described embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0086] The isolated transmission unit 130 of this modified example has one insulating element 131. The insulating element 131 functions as part of the first isolated transmission circuit T1 and also as part of the second isolated transmission circuit T2. The insulating element 131 transmits the first transmission signal St1 from the primary chip 10 to the secondary chip 20 in an isolated manner, and transmits the second transmission signal St2 from the secondary chip 20 to the primary chip 10 in an isolated manner.

[0087] The communication system 101 of this modified version operates similarly to the communication system 1 of the embodiment described above. That is, the second transmitting unit 21 transmits the second transmission signal St2 at a timing staggered from the timing of the reception of the first transmission signal St1 by the first receiving unit 12. Therefore, the isolated transmission unit 130 of this modified version avoids the simultaneous transmission of the first transmission signal St1 and the second transmission signal St2. For this reason, the first transmission signal St1 and the second transmission signal St2 can be transmitted by a single insulating element 131. Furthermore, according to this modified version, since the communication system 101 has only one insulating element 131, the communication system 101 can be miniaturized.

[0088] According to at least one embodiment described above, the communication systems 1, 101 have a control logic circuit 40 that detects the reception of the first transmission signal St1 and transmits a transmission start signal that triggers the start of transmission of the second transmission signal St2. This suppresses the overlap of the transmission timings of the first transmission signal St1 and the second transmission signal St2, thereby improving the reliability of the communication system 1.

[0089] The present invention includes the following appended embodiments. (Note 1) A communication system that performs isolated transmission between a primary chip and a secondary chip, A first isolated transmission circuit that transmits a first input signal isolatedly from the primary chip to the secondary chip, A second isolated transmission circuit that transmits a second input signal isolatedly from the secondary chip to the primary chip, The secondary chip includes a control logic circuit that connects the first isolated transmission circuit and the second isolated transmission circuit, The first isolated transmission circuit is, The primary chip includes a first transmitting unit that receives the first input signal and converts it into a first transmission signal, An isolated transmission unit that transmits the first transmission signal isolatedly from the primary chip to the secondary chip, The secondary chip includes a first receiving unit that receives and demodulates the first transmission signal and outputs a first output signal, The second isolated transmission circuit is The secondary chip includes a second transmitting unit that receives the second input signal and converts it into a second transmission signal, The isolated transmission unit transmits the second transmission signal isolatedly from the secondary chip to the primary chip, The primary chip includes a second receiving unit that receives and demodulates the second transmission signal and outputs a second output signal, The control logic circuit detects the reception of the first transmission signal in the first receiving unit and transmits a transmission start signal to the second transmitting unit. The second transmitting unit transmits the second transmission signal based on the transmission start signal. Communication system. (Note 2) The first transmission signal includes a first pulse and a second pulse having different signal configurations. The first input signal changes between a first level and a second level, which have different voltage levels. The first transmitting unit is, When the first input signal changes from the second level to the first level, and when the first input signal remains at the first level, the first pulse is transmitted at regular time intervals. When the first input signal changes from a first level to a second level, and when the first input signal remains at the second level, the second pulse is transmitted at regular time intervals. The communication system described in Appendix 1. (Note 3) The aforementioned second input signal includes second input signal A and second input signal B. The second input signal A changes between a third level and a fourth level, which have different voltage levels. The second input signal B changes between a fifth level and a sixth level, which have different voltage levels. The second transmission signal includes a first pulse and a second pulse having different signal configurations. The second transmitting unit is, When the transmission start signal is received and the second input signal A is at the third level, the first pulse is transmitted. When the transmission start signal is received, if the second input signal B is at the fifth level, the second pulse is transmitted. The communication system described in Appendix 1 or 2. (Note 4) The aforementioned transmission start signal is The first transmission start signal and The system includes a second transmission start signal that is generated with a delay relative to the first transmission start signal, The second transmitting unit is, When the first transmission start signal is received and the second input signal A is at the third level, the first pulse is transmitted. When the second transmission start signal is received, if the second input signal B is at the fifth level, the second pulse is transmitted. The communication system described in Appendix 3. (Note 5) The second transmitting unit is, When the second input signal A changes from the fourth level to the third level, the first pulse is transmitted. The second pulse is transmitted when the second input signal B changes from the sixth level to the fifth level. The communication system described in Appendix 3 or 4. (Note 6) The second transmitting unit is, A detection circuit that transmits a detection signal when the level of the second input signal changes, The system includes a transmission circuit that transmits the second transmission signal to the isolated transmission unit based on the detection signal and the transmission start signal, The transmission circuit, when the processing for receiving the detection signal and the processing for receiving the transmission start signal overlap, prioritizes the processing for receiving the transmission start signal. The communication system described in Appendix 5. (Note 7) The second receiving unit is, Based on the first pulse, a second output signal A is output as the second output signal. Based on the second pulse, a second output signal B is output as the second output signal. A communication system as described in any one of the appendices 3 to 6. (Note 8) The second receiving unit is, A receiving circuit that receives the first pulse and the second pulse and generates the second output signal, A first monitoring timer that measures the time elapsed since the receiving circuit received the first pulse, The receiving circuit includes a second monitoring timer that measures the time elapsed since the receiving circuit received the second pulse, The receiving circuit is, When the first pulse is received, the second output signal A is changed from the fourth level to the third level. When the measurement time of the first monitoring timer exceeds the monitoring cycle, the second output signal A is changed from the third level to the fourth level. When the second pulse is received, the second output signal B is changed from the sixth level to the fifth level. If the measurement time of the second monitoring timer exceeds the monitoring cycle, the second output signal B is changed from the fifth level to the sixth level. The communication system described in Appendix 7. (Note 9) The first transmitting unit transmits pulses at regular time intervals when the first input signal remains at the first level or the second level. The monitoring period is longer than the fixed time interval. The communication system described in Appendix 8. (Note 10) The aforementioned isolated transmission unit is A first insulating element that transmits the first transmission signal in isolation from the primary chip to the secondary chip, The system includes a second insulating element that transmits the second transmission signal in isolation from the secondary chip to the primary chip. A communication system as described in any one of the appendices 1 through 9. (Note 11) The aforementioned insulated transmission unit has one insulating element, The insulating element transmits the first transmission signal in isolation from the primary chip to the secondary chip, and transmits the second transmission signal in isolation from the secondary chip to the primary chip. A communication system as described in any one of the appendices 1 through 9.

[0090] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0091] 1,101…Communication system, 10…Primary chip, 11…First transmitter, 12…First receiver, 20…Secondary chip, 21…Second transmitter, 22…Second receiver, 22a…First monitoring timer, 22b…Second monitoring timer, 30,130…Isolated transmission unit, 40…Control logic circuit, 131…Isolating element, So2…Second output signal, So2A Second output signal A, So2B…Second output signal B, Si2…Second input signal, Si2A… Second input signal A, Si2B…Second input signal B, P1…First pulse, P2…Second pulse, Sb, VSb…Transmission start signals, SbA…First transmission start signal, SbB…Second transmission start signal, Si1…First input signal, So1…First output signal, So2A…Second output signal A, So2B…Second output signal B, St1…First transmission signal, St2…Second transmission signal, T1…First isolated transmission circuit, T2…Second isolated transmission circuit, tb…Monitoring cycle

Claims

1. A communication system that performs isolated transmission between a primary chip and a secondary chip, A first isolated transmission circuit that transmits a first input signal isolatedly from the primary chip to the secondary chip, A second isolated transmission circuit that transmits a second input signal isolatedly from the secondary chip to the primary chip, The secondary chip includes a control logic circuit that connects the first isolated transmission circuit and the second isolated transmission circuit, The first isolated transmission circuit is, The primary chip includes a first transmitting unit that receives the first input signal and converts it into a first transmission signal, An isolated transmission unit that transmits the first transmission signal isolatedly from the primary chip to the secondary chip, The secondary chip includes a first receiving unit that receives and demodulates the first transmission signal and outputs a first output signal, The second isolated transmission circuit is, The secondary chip includes a second transmitting unit that receives the second input signal and converts it into a second transmission signal, The isolated transmission unit transmits the second transmission signal isolatedly from the secondary chip to the primary chip, The primary chip includes a second receiving unit that receives and demodulates the second transmission signal and outputs a second output signal. The control logic circuit detects the reception of the first transmission signal in the first receiving unit and transmits a transmission start signal to the second transmitting unit. The second transmitting unit transmits the second transmission signal based on the transmission start signal. Communication system.

2. The first transmission signal includes a first pulse and a second pulse having different signal modes from each other. The first input signal changes between a first level and a second level, which have different voltage levels. The first transmitting unit is, When the first input signal changes from the second level to the first level, and when the first input signal remains at the first level, the first pulse is transmitted at regular time intervals. When the first input signal changes from a first level to a second level, and when the first input signal remains at the second level, the second pulse is transmitted at regular time intervals. The communication system according to claim 1.

3. The aforementioned second input signal includes second input signal A and second input signal B, The second input signal A changes between a third level and a fourth level, which have different voltage levels. The second input signal B changes between a fifth level and a sixth level, which have different voltage levels. The second transmission signal includes a first pulse and a second pulse having different signal modes from each other. The second transmitting unit is, When the transmission start signal is received and the second input signal A is at the third level, the first pulse is transmitted. When the transmission start signal is received, if the second input signal B is at the fifth level, the second pulse is transmitted. The communication system according to claim 1.

4. The aforementioned transmission start signal is The first transmission start signal and The system includes a second transmission start signal that is generated with a delay relative to the first transmission start signal, The second transmitting unit is, When the first transmission start signal is received and the second input signal A is at the third level, the first pulse is transmitted. When the second transmission start signal is received, if the second input signal B is at the fifth level, the second pulse is transmitted. The communication system according to claim 3.

5. The second transmitting unit is, When the second input signal A changes from the fourth level to the third level, the first pulse is transmitted. The second pulse is transmitted when the second input signal B changes from the sixth level to the fifth level. The communication system according to claim 3.

6. The second transmitting unit is, A detection circuit that transmits a detection signal when the level of the second input signal changes, The system includes a transmission circuit that transmits the second transmission signal to the isolated transmission unit based on the detection signal and the transmission start signal, The transmission circuit, when the processing for receiving the detection signal and the processing for receiving the transmission start signal overlap, prioritizes the processing for receiving the transmission start signal. The communication system according to claim 5.

7. The second receiving unit is, Based on the first pulse, a second output signal A is output as the second output signal. Based on the second pulse, a second output signal B is output as the second output signal. A communication system according to any one of claims 3 to 6.

8. The second receiving unit is, A receiving circuit that receives the first pulse and the second pulse and generates the second output signal, A first monitoring timer that measures the time elapsed since the receiving circuit received the first pulse, The receiving circuit includes a second monitoring timer that measures the time elapsed since the receiving circuit received the second pulse, The receiving circuit is, When the first pulse is received, the second output signal A is changed from the fourth level to the third level. When the measurement time of the first monitoring timer exceeds the monitoring cycle, the second output signal A is changed from the third level to the fourth level. When the second pulse is received, the second output signal B is changed from the sixth level to the fifth level. When the measurement time of the second monitoring timer exceeds the monitoring cycle, the second output signal B is changed from the fifth level to the sixth level. The communication system according to claim 7.

9. The first transmitting unit transmits pulses at regular time intervals when the first input signal remains at the first level or the second level. The monitoring period is longer than the fixed time interval. The communication system according to claim 8.

10. The aforementioned isolated transmission unit is A first insulating element that transmits the first transmission signal in isolation from the primary chip to the secondary chip, The system includes a second insulating element that transmits the second transmission signal in isolation from the secondary chip to the primary chip. The communication system according to claim 1.

11. The aforementioned insulated transmission unit has one insulating element, The insulating element transmits the first transmission signal in isolation from the primary chip to the secondary chip, and transmits the second transmission signal in isolation from the secondary chip to the primary chip. The communication system according to claim 1.

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