Manufacturing method of wiring boards

Abstract

To improve the transmission characteristics of high-frequency signals. [Solution] A method for manufacturing a wiring board having conductive layers having a wiring pattern of the present disclosure, wherein an interlayer insulating layer made of thermosetting resin is provided between conductive layers, comprises: a first conductive layer forming step in which a conductive layer below the interlayer insulating layer is formed; a pre-bake step in which the interlayer insulating layer is coated or laminated onto the lower conductive layer and then heated to a semi-cured state; a second conductive layer forming step in which an upper conductive layer is formed on the semi-cured interlayer insulating layer; and a post-bake step in which the upper conductive layer is formed and then heated to a thermo-cured state, wherein in the post-bake step, the dielectric loss tangent and relative permittivity of the interlayer insulating layer are made smaller on the upper side than on the lower side.

Description

Technical Field

[0005]

[0001] The present disclosure relates to a method for manufacturing a wiring board in which an interlayer insulating layer made of a thermosetting resin is provided between conductive layers.

Background Art

[0002] In this type of method for manufacturing a wiring board, an interlayer insulating layer made of a thermosetting resin is laminated or the like on a lower conductive layer, heated and cured, and then an upper conductive layer is formed thereon (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0017] and FIGS. 1 and 2)

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the present application, the method for manufacturing a wiring board is reviewed, and a technique for improving the transmission characteristics of high-frequency signals of the wiring board is disclosed.

Means for Solving the Problems

[0005] A first aspect of the invention according to the present disclosure made in view of the above problems is a method for manufacturing a wiring board in which an interlayer insulating layer made of a thermosetting resin is provided between conductive layers having wiring patterns, the method including: a first conductive layer forming step of forming a conductive layer below the interlayer insulating layer; a pre-bake step of coating or laminating the interlayer insulating layer on the lower conductive layer and then heating it to a semi-cured state; a second conductive layer forming step of forming an upper conductive layer on the semi-cured interlayer insulating layer; and a post-bake step of heating the interlayer insulating layer to a thermoset state after the upper conductive layer is formed. In the post-bake step, the dissipation factor and relative permittivity of the interlayer insulating layer are made smaller on the upper surface side than on the lower surface side of the interlayer insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] Side cross-sectional view of a wiring board according to one embodiment of the present disclosure [Figure 2] Figures 2A and 2B are side cross-sectional views illustrating the manufacturing method of a wiring board. [Figure 3] Figures 3A to 3C are side cross-sectional views illustrating the manufacturing method of a wiring board. [Figure 4] Figures 4A to 4C are side cross-sectional views illustrating the manufacturing method of a wiring board.

[0007] The following describes a method for manufacturing a wiring board 10 according to one embodiment of the present disclosure with reference to Figures 1 to 4. Figure 1 shows a side cross-sectional view of the wiring board 10, showing only the front side from the core substrate 11. As shown in the figure, the wiring board 10 of this embodiment comprises a plurality of conductive layers 20 and a plurality of interlayer insulating layers 21 alternately laminated on both the front and back surfaces of the core substrate 11, and a solder resist layer (not shown) as the outermost layer. The following description will focus on the front side of the wiring board 10. When distinguishing between the conductive layers 20 in the wiring board 10, each conductive layer 20 will be referred to as "first conductive layer 20A," "second conductive layer 20B," and "third conductive layer 20C" in order from the side closest to the core substrate 11, and when distinguishing between the interlayer insulating layers 21, each interlayer insulating layer 21 will be referred to as "first interlayer insulating layer 21A," "second interlayer insulating layer 21B," and so on, from the side closest to the core substrate 11.

[0008] The core substrate 11 has an insulating substrate 11K and a first conductive layer 20A laminated on both its front and back surfaces. The insulating substrate 11K has a structure in which multiple prepregs (B-stage films made by impregnating a core material made of fibers such as glass cloth with resin) are laminated. Multiple through-holes 15H are formed in the insulating substrate 11K, and through-hole conductors 15 are filled inside them. The first conductive layers 20A on the front and back surfaces of the core substrate 11 are connected to each other by multiple through-hole conductors 15. The insulating substrate 11K may also have a structure in which multiple resin films are laminated.

[0009] Multiple conductive layers 20 have predetermined electrical circuits formed on them, including a wiring pattern 30Z in which multiple pads 16 and multiple wirings 31 extend in parallel.

[0010] The wiring pattern 30Z of the second conductive layer 20B includes high wiring density sections 30A and 30B where the spacing between wirings 31 is narrow. In this embodiment, the minimum wiring width in the high wiring density sections 30A and 30B is 2 μm or less, and the minimum wiring spacing between adjacent wirings 31 is 2 μm or less.

[0011] The pads 16 of the third conductive layer 20C are exposed through openings formed in a solder resist layer (not shown), to which, for example, electrical components are connected. The solder resist layer is, for example, an ultraviolet-curable photosensitive film made of epoxy resin. Alternatively, the solder resist layer may be formed by curing a liquid material.

[0012] Furthermore, the multiple conductive layers 20 are connected to each other by multiple via conductors 12 formed in the multiple interlayer insulating layers 21, with adjacent conductive layers 20 in the stacking direction being connected. Each via conductor 12 is formed by filling multiple vias 12H that penetrate each interlayer insulating layer 21 with plating.

[0013] The multiple interlayer insulating layers 21 are composed of a resin film containing a thermosetting resin material. Specific examples of thermosetting resins include epoxy resin, phenolic resin, polyimide resin, polyester resin, bismaleimide resin, polyolefin resin, polyphenylene ether resin, etc., and two or more of these may be combined.

[0014] Furthermore, the resin film of this embodiment contains an inorganic filler as a reinforcing material, with a content of, for example, 30 wt% to 80 wt%. Specific examples of inorganic fillers include silica, barium sulfate, talc, silicon dioxide, and boron nitride.

[0015] Hereinafter, an example of a manufacturing method for the wiring board 10 of this embodiment will be described with reference to Figures 2 to 4. (1) First, as shown in Figure 2A, a laminate 11S is prepared in which metal foil 11D is laminated on both sides of an insulating substrate 11K. Then, a through-hole formation process is carried out, in which multiple through-holes 15H are formed in the laminate 11S by drilling or laser irradiation, and the smear inside the through-holes 15H is removed by desmear treatment.

[0016] (2) Next, a conductive layer formation step is performed in which the first conductive layer 20A is formed. The first conductive layer 20A is formed, for example, by a known subtractive method, and as shown in Figure 2B, the first conductive layer 20A is laminated on both the front and back surfaces of the insulating substrate 11K, and through-hole conductors 15 are filled into the through-holes 15H. This forms the core substrate 11. This "conductive layer formation step" corresponds to the "first conductive layer formation step" in the claims.

[0017] (3) Next, a pre-bake process is performed, in which a resin film is laminated onto the conductive layer 20 and then heated and pressed, as shown in Figure 3A. This forms the first interlayer insulating layer 21A. The resin film contains a thermosetting resin material in a semi-cured or dry state, and in the pre-bake process, the heating temperature is set so that the interlayer insulating layer 21 reaches a semi-cured state that does not reach a fully cured state.

[0018] (4) Next, a via formation process is performed, in which a laser is irradiated onto predetermined locations on the first interlayer insulating layer 21A to form a plurality of vias 12H, and then the smear inside the vias 12H is removed by desmear treatment.

[0019] (5) Next, an electroless plating preparation step is performed, in which the surface of the semi-cured first interlayer insulating layer 21A and the interior of the vias 12H are roughened by a known method (not shown in the figure).

[0020] (6) Next, an electroless plating process is performed. As shown in FIG. 3C, a seed layer 22 is formed on the first interlayer insulating layer 21A and the inner surface of the via 12H by an electroless plating process.

[0021] (7) Next, an electrolytic plating preparation process is performed. As shown in FIG. 4A, a plating resist 50 with a predetermined pattern is formed on the seed layer 22 laminated on the first interlayer insulating layer 21A.

[0022] (8) Next, an electrolytic plating process is performed. As shown in FIG. 4B, electrolytic plating is filled into the plurality of vias 12H by an electrolytic plating process to form via conductors 12, and an electrolytic plating film 23 is formed on the portion of the seed layer 22 exposed from the plating resist 50.

[0023] (9) Next, a resist stripping process is performed. As shown in FIG. 4C, the plating resist 50 is stripped, and the seed layer 22 below the plating resist 50 is removed. The remaining electrolytic plating film 23 and seed layer 22 form a second conductive layer 20B on the first interlayer insulating layer 21A. The processes of (6) to (9) are conductive layer forming processes for forming the second conductive layer 20B, and correspond to the "first conductive layer forming process" and "second conductive layer forming process" in the claims.

[0024] (10) Next, a post-bake process is performed. In this process, for example, it is heated in an inert gas atmosphere such as argon or nitrogen, and the semi-cured first interlayer insulating layer 21A is fully cured. Specifically, the substrate on which the second conductive layer 20B is formed is placed in a sealed firing furnace, and in a state where the inside of the furnace is an inert gas atmosphere, it is heat-treated at a heating temperature corresponding to the curing temperature of the thermosetting resin contained in the resin film for a predetermined time. As a result, the interlayer insulating layer 21 is formed such that the dielectric tangent and relative dielectric constant gradually decrease as it approaches the side on which the second conductive layer 20B is laminated in the thickness direction.

[0025] (11) Next, steps (3) to (10) described above are repeated until the second interlayer insulating layer 21B and the third conductive layer 20C are laminated in order, and then the solder resist layer (not shown) is laminated. With this, the wiring board 10 is completed.

[0026] This concludes the description of the structure of the wiring board 10 of this embodiment and its manufacturing method. Next, the effects of the wiring board 10 will be described. In the wiring board 10 of this disclosure, as described above, the post-bake process is carried out in an inert gas atmosphere, so that the interlayer insulating layer 21 is formed such that, in its thickness direction, the dielectric loss tangent and relative permittivity gradually decrease as it approaches the side on which the conductive layer 20 is laminated. For example, at a frequency of 5.8 [GHz], the dielectric loss tangent of the interlayer insulating layer 21 on the upper side on which the conductive layer 20 is laminated is 0.007 or less, and the relative permittivity is 3.3 or less, while the dielectric loss tangent on the lower side is 0.01 or less, and the relative permittivity is 3.4 or less. Thus, in the manufacturing method of the wiring board 10 of this embodiment, the dielectric loss tangent and relative permittivity of the interlayer insulating layer 21 are low in the part close to the laminated conductive layer 20, so that the inter-wiring capacitance between the wirings 31 of the conductive layer 20 is suppressed, and the transmission characteristics at high frequencies can be improved.

[0027] The reason why the dielectric loss tangent and relative permittivity are suppressed when the post-bake process is carried out in an inert gas atmosphere, as described above, is presumed to be as follows. For example, if the post-bake process is carried out in an atmospheric atmosphere as in the conventional method, oxygen and water vapor in the atmosphere will enter the interlayer insulating layer 21, or dissolved oxygen inside the interlayer insulating layer 21 will diffuse, making it easier for the thermosetting resin material inside the interlayer insulating layer 21 to react with oxygen and generate polar groups, causing an increase in the dielectric constant of the entire interlayer insulating layer 21. On the other hand, if the post-bake process is carried out in an inert gas atmosphere as in this embodiment, the oxygen concentration on the surface side of the interlayer insulating layer 21 that is in contact with the inert gas is reduced, so it is presumed that reactions with oxygen are less likely to occur near the surface of the interlayer insulating layer 21, and an interlayer insulating layer 21 is formed in which the dielectric loss tangent and relative permittivity gradually decrease toward the surface.

[0028] Furthermore, in the manufacturing method of the wiring board 10 of this embodiment, as described above, the post-baking process is carried out under an inert gas atmosphere, making it possible to manufacture an interlayer insulating layer 21 in a single layer using a single resin film, in which the dielectric loss tangent and relative permittivity gradually decrease toward one side in the thickness direction.

[0029] Furthermore, in the manufacturing method of this embodiment, the interlayer insulating layer 21 is formed in a pre-bake step and a post-bake step, but only the post-bake step is performed under an inert gas atmosphere. Since the surface of the interlayer insulating layer 21 formed in the pre-bake step is scraped on the side closer to the conductive layer 20 in the subsequent electroless plating preparation step and electroless plating step, the dielectric loss tangent and relative permittivity on the side closer to the conductive layer 20 can be efficiently reduced by performing only the post-bake step under an inert gas atmosphere.

[0030] Furthermore, since the interlayer insulating layer 21 preferably has a low dielectric loss tangent and a low relative permittivity, it is preferable that the thermosetting resin used has few polar groups. Examples of resins with few polar groups include resins that do not have acryloyl groups or methacryloyl groups, or functional groups derived from acryloyl groups or methacryloyl groups. Epoxy resins or phenolic resins are preferred as thermosetting resins that do not have acryloyl groups or methacryloyl groups, and epoxy resins are particularly preferred. Specific examples of epoxy resins include bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac type epoxy resins such as phenol novolac type and alkylphenol novolac type (cresol novolac type, etc.), alicyclic epoxy resins, biphenyl type epoxy resins, naphthalene type epoxy resins, dicyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having phenolic hydroxyl groups, triglycidyl isocyanurates, and the like.

[0031] Furthermore, it is preferable to use inorganic fillers that have a low dielectric loss tangent and a low relative permittivity, such as silicon dioxide or boron nitride.

[0032] [Other embodiments] In the above embodiment, a resin film containing a thermosetting resin is used as the material for the interlayer insulating layer 21, but a liquid or paste-like ink containing a thermosetting resin may also be used. In this case, the interlayer insulating layer 21 in a semi-cured state can be manufactured by coating the ink in the pre-bake process using a coating method such as screen printing, dip coating, or spin coating.

[0033] In the above embodiment, the interlayer insulating layer 21 was manufactured as a single layer using one resin film, resulting in a lower dielectric loss tangent and relative permittivity on the upper surface where the conductive layer 31 is laminated. However, the interlayer insulating layer 21 may also be manufactured using multiple resin films (not a single layer).

[0034] Specifically, for example, two resin films having half the thickness of the resin film of the above embodiment are prepared. First, the first resin film is laminated onto the first conductive layer 20A and then heat-pressed (pre-bake step). Then, before laminating the second conductive layer 20B, a post-bake step is performed to fully cure the first resin film layer. Then, the second resin film is laminated onto the fully cured first resin film layer and then heat-pressed (pre-bake step). After that, instead of performing the post-bake step immediately, the second conductive layer 20B is laminated in the same manner as in the above embodiment, and then the post-bake step is performed to fully cure the second resin film layer. In this way, the first interlayer insulating layer 21A is manufactured using two resin films. Since each of the two resin films undergoes a post-baking process under an inert gas atmosphere, the dielectric loss tangent and relative permittivity of the upper surface of each film become lower. Therefore, when these are combined into a single interlayer insulating layer 21A, the dielectric loss tangent and relative permittivity inside the interlayer insulating layer 21A can also be lowered. In other words, the more layers of interlayer insulating layer 21A there are, the lower the dielectric loss tangent and relative permittivity inside the interlayer insulating layer 21A can be.

[0035] In the above embodiment, the resin film for forming the interlayer insulating layer 21 does not contain a core material, but it may be impregnated with a core material made of fibers such as glass fibers.

[0036] In the above embodiment, the interlayer insulating layer 21 contained an inorganic filler, but it does not have to contain an inorganic filler.

[0037] In the above embodiment, the seed layer 22 was formed by an electroless plating process, but it may also be formed by sputtering.

[0038] In the above embodiment, the surface of the interlayer insulating layer 21 was roughened by an electroless plating preparation step after the pre-baking step, but roughening is not required.

[0039] The pre-bake process may be carried out under an inert gas atmosphere.

[0040] Although the wiring board 10 in the above embodiment included a core board 11, it may also be a coreless board that does not include a core board 11.

[0041] The wiring board 10 may have any number of conductive layers 20 and interlayer insulating layers 21. Furthermore, the number of conductive layers 20 and interlayer insulating layers 21, and the configuration of the electronic circuits of the conductive layers 20, may differ on the front and back sides of the core substrate 11.

[0042] While this specification and drawings disclose specific examples of the technology included in the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and changes to these examples, as well as parts of the examples taken individually. [Explanation of Symbols]

[0043] 10 Wiring board 20,20A,20B conductive layer 21, 21A, 21B Interlayer insulating layer 30A, 30B Wiring Pattern

Claims

1. In a method for manufacturing a wiring substrate in which an interlayer insulating layer made of thermosetting resin is provided between conductive layers having wiring patterns, A first conductive layer formation step in which a conductive layer below the interlayer insulating layer is formed, A pre-bake step in which the interlayer insulating layer is coated or laminated onto the lower conductive layer and then heated to a semi-cured state, A second conductive layer formation step is performed in which an upper conductive layer is formed on the semi-cured interlayer insulating layer, The process includes a post-baking step in which the upper conductive layer is formed and then heated so that the interlayer insulating layer becomes thermally cured, In the post-baking process, the dielectric loss tangent and relative permittivity of the interlayer insulating layer are made smaller on the upper surface than on the lower surface.

2. In the method for manufacturing a wiring board according to claim 1, The post-baking process involves the thermal curing of the interlayer insulating layer under an inert gas atmosphere.

3. In the method for manufacturing a wiring board according to claim 1, In the post-baking process, the dielectric loss tangent at a frequency of 5.8 GHz on the upper surface side of the interlayer insulating layer is made 0.007 or less and the relative permittivity is made 3.3 or less.

4. In the method for manufacturing a wiring board according to claim 1, In the second conductive layer formation step, the wiring pattern is formed with a wiring width of 2 μm or less and a minimum wiring spacing of 2 μm or less.

5. In the method for manufacturing a wiring board according to claim 1, The second conductive layer formation step includes an electroless plating step in which wiring seeds corresponding to the conductive layer are formed by electroless plating, and an electroplating step in which the conductive layer is formed by electroplating on top of the wiring seeds.

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