DC-DC converter circuit

Abstract

To provide a DC-DC converter circuit with high conversion efficiency. [Solution] The DC-DC converter circuit has a first state in which a first capacitor is connected between the input node and the first node, a second capacitor and a first coil are connected in series between the first node and the output node, a third capacitor and a second coil are connected in series between the first node and the output node, and the second node to which the second capacitor and the first coil are connected is connected to the first reference potential node; and a second state in which a second capacitor and a first coil are connected in series between the third node and the output node, a first capacitor, a third capacitor, and a second coil are connected in series between the third node and the output node, the fourth node to which the second capacitor and the first coil are connected is connected to the node to which the first capacitor and the third capacitor are connected, and the fifth node to which the third capacitor and the second coil are connected is connected to the second reference potential node.

Description

Technical Field

[0001] Embodiments of the present invention relate to a DC-DC converter circuit.

Background Art

[0002] A DC-DC converter circuit that converts a direct current (DC) voltage into a DC voltage of another magnitude is known. The DC-DC converter circuit is required to have high conversion efficiency, that is, to suppress power loss.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a DC-DC converter circuit having high conversion efficiency.

Means for Solving the Problems

[0005] A DC-DC converter circuit according to one embodiment includes a first capacitor, a second capacitor, a third capacitor, a first coil, a second coil, and a plurality of switches. The DC-DC converter circuit has a first state in which, by turning the above-mentioned multiple switches on and off, the first capacitor is connected between the input node and the first node, the second capacitor and the first coil are connected in series between the first node and the output node, the third capacitor and the second coil are connected in series between the first node and the output node, and the second node to which the second capacitor and the first coil are connected is connected to the first reference potential node; and a second state in which, by turning the above-mentioned multiple switches on and off, the first capacitor is connected between the input node and the first node, the second capacitor and the first coil are connected in series between the third node and the output node, the fourth node to which the second capacitor and the first coil are connected is connected to the node to which the first capacitor and the third capacitor are connected, and the fifth node to which the third capacitor and the second coil are connected is connected to the second reference potential node. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram of a system including a DC-DC converter circuit according to the first embodiment. [Figure 2] Figure 2 is a block diagram of a voltage conversion circuit including a DC-DC converter circuit according to the first embodiment. [Figure 3] Figure 3 is a circuit diagram of the DC-DC converter circuit of the first embodiment. [Figure 4] Figure 4 shows the change in the level of the control signal supplied to the DC-DC converter circuit of the first embodiment over time. [Figure 5] Figure 5 shows one state during the operation of the DC-DC converter circuit of the first embodiment. [Figure 6] Figure 6 shows one state during the operation of the DC-DC converter circuit of the first embodiment. [Figure 7] Figure 7 shows one state during the operation of the DC-DC converter circuit of the first embodiment. [Figure 8] Figure 8 shows the sequential states during the operation of the DC-DC converter circuit of the first embodiment. [Figure 9] Figure 9 is a circuit diagram of a DC-DC converter circuit for reference. [Figure 10] Figure 10 is a circuit diagram of a DC-DC converter circuit according to the second embodiment. [Figure 11] Figure 11 shows the sequential states during the operation of the DC-DC converter circuit of the second embodiment. [Figure 12] Figure 12 is a circuit diagram of a DC-DC converter circuit according to the second embodiment. [Figure 13] Figure 13 shows the sequential states during the operation of the DC-DC converter circuit of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may have additional numbers or letters appended to the end of their reference numerals to distinguish them from one another. Embodiments following a previously described embodiment primarily describe the differences from the previously described embodiment. All descriptions of an embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded.

[0008] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0009] 1. First Embodiment Figure 1 is a block diagram of a system including a DC-DC converter circuit according to the first embodiment. As shown in Figure 1, the voltage conversion circuit 10 is a circuit that supplies voltage to circuit 20. The voltage conversion circuit 10 and circuit 20 may be contained in separate individual devices or in a single device.

[0010] The voltage conversion circuit 10 is a circuit that outputs a voltage different from the voltage it receives. The voltage conversion circuit 10 includes a DC-DC converter circuit according to the first embodiment. The voltage conversion circuit 10 receives an input voltage Vin. The input voltage Vin may be supplied from a power supply or from commercial power. The voltage conversion circuit 10 generates an output voltage Vout from the input voltage Vin and outputs the output voltage Vout. The output voltage Vout has a magnitude different from the input voltage Vin, and is smaller than the input voltage Vin. The voltage conversion circuit 10 receives the output voltage Vout and uses the output voltage Vout to control the magnitude of the output voltage Vout.

[0011] Figure 2 is a block diagram of a voltage conversion circuit including a DC-DC converter circuit of the first embodiment. As shown in Figure 2, the voltage conversion circuit 10 includes a DC-DC converter circuit 1 and a control circuit 2. The DC-DC converter circuit 1 receives an input voltage Vin, generates an output voltage Vout from the input voltage Vin, and outputs the output voltage Vout. The DC-DC converter circuit 1 receives the input voltage Vin at the input node Nin. The DC-DC converter circuit 1 outputs the output voltage Vout at the output node Nout. The DC-DC converter circuit 1 receives control signals φ1, φ1, φ2, and φ2. The DC-DC converter circuit 1 operates based on the control signals φ1, φ1, φ2, and φ2.

[0012] Control circuit 2 is a circuit that controls DC-DC converter circuit 1 based on the received voltage. Control circuit 2 receives the output voltage Vout and generates control signals φ1, φ1, φ2, and φ2 based on the output voltage Vout. Control circuit 2 adjusts the control signals φ1, φ1, φ2, and φ2 so that the output voltage Vout is of a preset magnitude. Specifically, the control signals φ1, φ1, φ2, and φ2 define the duty cycle of DC-DC converter circuit 1. The duty cycle is the proportion of the period during which the transistor in control circuit 2 is on relative to the period in which the transistor is on. Control circuit 2 adjusts the on and off periods of the control signals φ1, φ1, φ2, and φ2 so that the transistor operates to output an output voltage Vout of a preset magnitude. If the output voltage Vout is below a preset magnitude, control circuit 2 lengthens the on period of the control signals φ1, φ1, φ2, and φ2. When the output voltage Vout falls below or above a preset value, control circuit 2 shortens the on-period of the control signals φ1, φ1, φ2, and φ2.

[0013] FIG. 3 is a circuit diagram of the DC-DC converter circuit according to the first embodiment. As shown in FIG. 3, the DC-DC converter circuit 1 includes switches SW1, SW2, SW3, SW4, SW5, and SW6, capacitors C1, C2, C3, and coils L1 and L2. Each of the switches SW1, SW2, SW3, SW4, SW5, and SW6 remains in an on state or an off state based on the voltage at the control terminal. While each of the switches SW1, SW2, SW3, SW4, SW5, and SW6 is on, it maintains a state where both ends thereof are electrically connected. While each of the switches SW1, SW2, SW3, SW4, SW5, and SW6 is off, it maintains a state where both ends thereof are electrically disconnected. Examples of the switches SW1, SW2, SW3, SW4, SW5, and SW6 include n-type or p-type metal oxide semiconductor field effect transistors (MOSFETs). In this example, the control terminals of the switches SW1, SW2, SW3, SW4, SW5, and SW6 are gate electrodes. FIG. 3 and subsequent figures are based on an example where each of the switches SW1, SW2, SW3, SW4, SW5, and SW6 is an n-type MOSFET.

[0014] Switch SW1 is connected between the input node Nin and the node N1. Switch SW1 receives a control signal φ1 at the control terminal.

[0015] Switch SW2 is connected between the node N1 and the node N2. Switch SW2 receives a control signal φ2 at the control terminal.

[0016] Capacitor C1 is connected between the node N1 and the node N3.

[0017] Switch SW3 is connected between the node N2 and the node N3. Switch SW3 receives a control signal φ1 at the control terminal.

[0018] Capacitor C2 is connected between the node N2 and the node N4. [[ID=二十一]] [[ID=二十二]]

[0019] [[ID=二十三]] Switch SW4 is connected between node N4 and node N3. Switch SW4 receives the control signal φ2 at its control terminal.

[0020] Switch SW5 is connected between node N4 and the node receiving the ground voltage (or reference voltage) Vss. Switch SW5 receives the control signal φ2 at its control terminal. Hereinafter, the node receiving the reference voltage Vss may be referred to as the reference potential node Nss.

[0021] Capacitor C3 is connected between node N3 and node N5.

[0022] Switch SW6 is connected between node N5 and reference potential node Nss. Switch SW6 receives the control signal φ1 at its control terminal.

[0023] Coil L1 is connected between node N4 and output node Nout.

[0024] Coil L2 is connected between node N5 and output node Nout.

[0025] Figure 4 shows the change in the level of the control signals supplied to the DC-DC converter circuit of the first embodiment over time. The following description is based on an example in which switches SW1, SW2, SW3, SW4, SW5, and SW6 are turned on and off by the control signals φ1, φ1, φ2, and φ2 of the levels described below.

[0026] Switches SW1 and SW3 are on when receiving a high-level or "H" level control signal φ1, and off when receiving a low-level or "L" level control signal φ1.

[0027] Switches SW2 and SW4 are on when receiving a high-level or "H" level control signal φ2, and off when receiving a low-level or "L" level control signal φ2.

[0028] Switch SW5 is on when it receives a high-level or "H" level control signal φ2, and off when it receives a low-level or "L" level control signal φ2.

[0029] Switch SW6 is on when it receives a high-level or "H" level control signal φ1, and off when it receives a low-level or "L" level control signal φ1.

[0030] As shown in Figure 4, the combination of levels of the control signals φ1, φ1, φ2, and φ2 changes periodically. One period consists of states ST1, ST2, ST3, and ST4. State ST1 continues to state ST2. State ST2 continues to state ST3. State ST3 is followed by state ST4. State ST4 continues to state ST1.

[0031] The control signal φ1 maintains a high level during state ST1 and a low level during states ST2, ST3, and ST4.

[0032] The control signal φ1 maintains a low level during state ST1, and maintains a high level during states ST2, ST3, and ST4.

[0033] The control signal φ2 maintains a high level during state ST3 and a low level during states ST1, ST2, and ST4.

[0034] The control signal φ2 maintains a low level during state ST3 and a high level during states ST1, ST2, and ST4.

[0035] The duty cycle D of the control signals φ1, φ1, φ2, and φ2 is equal to the duration of state ST1 or ST3 relative to the sum of the durations of states ST1, ST2, ST3, and ST4.

[0036] The duration of state ST2 and the duration of state ST4 are substantially the same. In this specification and in the claims, two elements being “substantially the same” and “substantially equal” means that the two elements are intended to be the same, but are not exactly the same based on the limitations of the art of manufacture and measurement.

[0037] Figure 5 shows one state during the operation of the DC-DC converter circuit of the first embodiment. Figure 5 shows state ST1. As described above with reference to Figure 4, during state ST1, control signals φ1 and φ2 are at a high level, and control signals φ1 and φ2 are at a low level. Therefore, as shown in Figure 5, switches SW1, SW3, and SW5 are on, and switches SW2, SW4, and SW6 are off. Switches that are off are indicated by dashed lines. Therefore, node N1 is connected to input node Nin, node N2 and node N1 are disconnected, node N4 is disconnected from node N3 and connected to the common potential node, and node N5 is not connected to the common potential node.

[0038] Figure 6 shows one state during the operation of the DC-DC converter circuit of the first embodiment. Figure 6 shows states ST2 and ST4. As described above with reference to Figure 4, during states ST2 and ST4, control signals φ1 and φ2 are at a low level, and control signals φ1 and φ2 are at a high level. Therefore, as shown in Figure 6, switches SW1, SW2, SW3, and SW4 are off, and switches SW5 and SW6 are on. Therefore, nodes N4 and N5 are connected to the common potential node and disconnected from the other nodes, respectively.

[0039] Figure 7 shows one state during the operation of the DC-DC converter circuit of the first embodiment. Figure 7 shows state ST3. As described above with reference to Figure 4, during state ST3, control signals φ1 and φ2 have low levels, and control signals φ1 and φ2 have high levels. Therefore, as shown in Figure 7, switches SW1, SW3, and SW5 are off, and switches SW2, SW4, and SW6 are on. Therefore, node N1 is disconnected from the input node, node N2 and node N3 are disconnected, node N4 is connected to node N3 but not to the common potential node, and node N5 is connected to the common potential node.

[0040] Figure 8 sequentially shows the states during operation of the DC-DC converter circuit of the first embodiment. Figure 8 shows the equivalent circuits of Figures 5, 6, and 7. In the upper left portion of Figure 8, the equivalent circuit of state ST1 is shown. In the upper right portion of Figure 8, the equivalent circuit of state ST2 is shown. In the lower right portion of Figure 8, the equivalent circuit of state ST3 is shown. In the lower left portion of Figure 8, the equivalent circuit of state ST4 is shown.

[0041] As shown in the upper left of Figure 8, in state ST1, capacitors C1 and C3 are charged by the input voltage Vin. That is, each of capacitors C1 and C3 carries a positive charge at the terminal closest to the input node Nin. Also, current flows through capacitors C1 and C3 to coil L2 due to the input voltage Vin. The current flowing through coil L2 causes coil L2 to store magnetic energy.

[0042] Since capacitor C2 is connected to a common potential node at the terminal opposite the input voltage Vin, negative charge continues to flow out from the terminal opposite the input voltage Vin, meaning that capacitor C2 discharges.

[0043] As described later, in state ST3, which precedes state ST1, current flows through coil L1 from input node Nin to output node Nout, and magnetic energy is stored in coil L1 by this current. Then, in state ST1, when the supply of current to coil L1 is stopped, the magnetic energy flows from coil L1 to output node Nout as a current.

[0044] As shown in the upper right portion of Figure 8, in state ST2, the supply of current due to the magnetic energy stored in coil L1 continues. Also, when the supply of current to coil L2 stops, the magnetic energy that was stored in coil L2 flows as a current from coil L2 towards the output node Nout.

[0045] As shown in the lower right portion of Figure 8, in state ST3, the supply of current due to the magnetic energy stored in coil L2 continues. Also, when capacitor C1 discharges, that is, when the charge stored in capacitor C1 flows out of capacitor C1, current flows through capacitor C2 to coil L1. Furthermore, when capacitor C3 discharges, that is, when the charge stored in capacitor C3 flows out of capacitor C3, current flows through coil L1. Due to the current flowing through coil L1, coil L1 stores magnetic energy.

[0046] As shown in the lower left of Figure 8, in state ST4, the supply of current due to the magnetic energy stored in coil L2 continues. Also, when the supply of current to coil L1 stops, the magnetic energy stored in coil L1 flows as a current from coil L1 towards the output node Nout. State ST4 continues into state ST1.

[0047] According to the first embodiment, a DC-DC converter circuit 1 having high conversion efficiency is provided, as described below.

[0048] For reference and comparison, a basic DC-DC converter circuit is briefly described. Figure 9 is a schematic of a reference DC-DC converter circuit. Switch SW11 and coil L11 are connected in series between the input node Nin and the output node Nout. Switch SW12 is connected between the node to which switch SW11 and coil L11 are connected and the common potential node. Capacitor C11 is connected between the output node Nout and the common potential node.

[0049] Switches SW11 and SW12 are turned on alternately. While switch SW11 is on and switch SW12 is off, the input voltage Vin causes a voltage to appear at output node Nout via coil L11, and magnetic energy is stored in coil L11. While switch SW11 is off and switch SW12 is on, the magnetic energy stored in coil L11 causes a current to flow from coil L11 to output node Nout, and this current causes an output voltage Vout to appear at output node Nout.

[0050] If the duty cycle of switch SW1 is Da, then Vout = Vin × Da holds true. That is, Da = Vout / Vin. This equation means that in order to obtain a smaller output voltage Vout, a smaller duty cycle is necessary. A smaller duty cycle means that the time switch SW1 is on is shorter, resulting in greater power loss due to switch SW1. In other words, the greater the voltage reduction, the greater the power loss.

[0051] In the DC-DC converter circuit 1 of the first embodiment, the following relationships hold. As shown in Figure 8, let Va be the potential at node N3, Vc be the potential at node N5, Vb be the potential at node N2, and Vd be the potential at node N4. Then, in the steady state, the following equations (1), (2), and (3) hold for the terminal voltages of capacitors C1, C2, and C3 between state ST1 and state ST3, according to the law of conservation of charge. That is, equation (1) holds for the terminal voltage of capacitor C1. Equation (2) holds for the terminal voltage of capacitor C2. Equation (3) holds for the terminal voltage of capacitor C3. The left side of each equation is the terminal voltage of capacitor C1, C2, or C3 during state ST1. The right side of each equation is the terminal voltage of capacitor C1, C2, or C3 during state ST3. Vin - Va = Vb - Vd (1) Va = Vb - Vd (2) Va - Vc = Vd (3) Between state ST3 and other periods, the following equation (4) holds true for coil L1 according to the voltage-second balance law. The left side shows the case for state ST3, and the right side shows the case for states other than state ST3. D(Vd-Vout)=(1-D)Vout (4) Equation (4) is transformed into equation (5). DVd=Vout (5) Between state ST1 and other periods, the following equation (6) holds for coil L2 according to the voltage-time balance law. The left side shows the equation for state ST1, and the right side shows the equation for states other than state ST1. D(Vc-Vout)=(1-D)Vout (6) Equation (6) is transformed into equation (7). DVc=Vout (7) From equations (5) and (7), the following equation (8) is obtained. Vd=Vc (8) From equations (1), (2), (3), and (8), the following equation (9) is obtained. Vin = 4Vd (9) From equations (5) and (9), the following equation (10) is obtained.

[0052] D = 4 × (Vout / Vin) (10) Equation (10) shows that if DC-DC converter circuit 1 attempts to achieve the same conversion rate (i.e., Vout / Vin) as the reference DC-DC converter circuit, the duty cycle D can be set to four times the duty cycle Da. This means that by suppressing the time when switches SW1, SW2, SW3, SW4, SW5, and SW6 are off, it is possible to achieve the same conversion rate as the reference DC-DC converter circuit while reducing switching losses compared to the reference DC-DC converter circuit, and consequently, to realize a highly efficient DC-DC converter circuit.

[0053] 2. Second Embodiment Figure 10 is a circuit diagram of a DC-DC converter circuit according to the second embodiment. As shown in Figure 10, the DC-DC converter circuit 1 of the second embodiment includes a further set of switches SW3 and SW4 and capacitors C2 and C3, in addition to the set of switches SW3 and SW4 and capacitors C2 and C3 of the first embodiment. The set of switches SW3 and SW4 and capacitors C2 and C3 of the first embodiment may be referred to as switch-capacitor set SC_1. The switches SW3 and SW4 and capacitors C2 and C3 of switch-capacitor set SC_1 may be referred to as switches SW3_1 and SW4_1 and capacitors C2_1 and C3_1, respectively. The second set of switches SW3 and SW4 and capacitors C2 and C3 may be referred to as switch-capacitor set SC_2. The switches SW3 and SW4 and capacitors C2 and C3 of switch-capacitor set SC_2 may be referred to as switches SW3_2 and SW4 and capacitors C2_2 and C3_2, respectively.

[0054] Switch-capacitor sets SC_1 and SC_2 are connected in series between nodes N2 and N4, and between nodes 3 and N5. The connections of the components in the two switch-capacitor sets SC are identical. The same switches in the two switch-capacitor sets SC receive the same signal at their respective control terminals. Specifically, this is as follows:

[0055] The node to which capacitor C2_1 and switch SW3_1 are connected is sometimes referred to as node N2_1. Node N2_1 is connected to node N2 and is the same node as node N2.

[0056] The node to which capacitor C1 and switch SW3_1 are connected is sometimes referred to as node N3_1. Node N3_1 is connected to node N3 and is the same node as node N3.

[0057] The node to which capacitor C2_1 and switch SW4_1 are connected is sometimes referred to as node N4_1. The node opposite node N3_1 to capacitor C3_1 is sometimes referred to as node N5_1.

[0058] Switch SW3_2 is connected between node N2_2 and node N3_2. Switch SW3_2 receives control signal φ1 at its control terminal. Node N2_2 is connected to node N4_1 and is the same node as node N4_1. Node N3_2 is connected to node N5_1 and is the same node as node N5_1.

[0059] Capacitor C2_2 is connected between node N2_2 and node N4_2. Node 4_2 is connected to node N4 and is the same node as node N4.

[0060] Switch SW4_2 is connected between node N2_2 and node N3_2. Switch SW4 receives the control signal φ2 at its control terminal.

[0061] Capacitor C3_2 is connected between node N3_2 and node N5_2. Node 5_2 is connected to node N5 and is the same node as node N5.

[0062] Figure 11 shows the states during operation of the DC-DC converter circuit of the second embodiment in sequence. Figure 8 shows the equivalent circuits between states ST1, ST2, ST3, and ST4. In the upper left portion of Figure 11, the equivalent circuit of state ST1 is shown. In the lower right portion of Figure 11, the equivalent circuit of state ST3 is shown. The equivalent circuits of states ST2 and ST4 are the same as in the first embodiment (Figure 8).

[0063] As shown in Figure 11, in state ST1, capacitors C2_1, C2_2, and coil L1 are connected in series in that order between the input node Nin and the output node Nout. In state ST1, capacitors C3_1, C3_2, and coil L2 are connected in series in that order between the node to which capacitors C1 and C2_2 are connected (i.e., node N3) and the output node Nout. In state ST1, the node to which capacitors C2_1 and C2_2 are connected (i.e., node N2_2) is connected to the node to which capacitors C3_1 and C3_2 are connected (i.e., node N3_2). In state ST1, the node to which capacitor C2_2 and coil L1 are connected (i.e., node N4) is connected to the reference potential node Nss.

[0064] In state ST3, capacitors C2_1, C2_2, and coil L1 are connected in series in this order between the node to which capacitors C2_1 and C1 are connected (i.e., node N2) and the output node Nout. In state ST3, capacitors C1, C3_1, C3_2, and coil L2 are connected in series in this order between the node to which capacitors C2_1 and C1 are connected (i.e., node N2_2) and the output node Nout. In state ST3, the node to which capacitor C2_2 and coil L1 are connected (i.e., node N4_2) is connected to the node to which capacitors C3_1 and C3_2 are connected (i.e., node N3_2). In state ST3, the node to which capacitor C3_2 and coil L2 are connected (i.e., node N5) is connected to the reference potential node Nss.

[0065] In the DC-DC converter circuit 1b of the second embodiment, the following relationships hold. Let the potential at node N3_2 be Ve, the potential at node N5 be Vf, the potential at node N2_2 be Vg, and the potential at node N4_2 be Vh. Then, in a steady state, between state ST1 and state ST3, the following equations (11), (12), (13), (14), and (15) hold for the terminal voltages of capacitors C1, C2_1, C3_1, C2_2, and C3_2, according to the law of conservation of charge. That is, equation (11) holds for the terminal voltage of capacitor C1. Equation (12) holds for the terminal voltage of capacitor C2_1. Equation (13) holds for the terminal voltage of capacitor C3_1. Equation (14) holds for the terminal voltage of capacitor C2_2. Equation (15) holds true for the terminal voltage of capacitor C3_2. The left side of each equation is the terminal voltage of capacitors C1, C2_1, C3_1, C2_2, or C3_2 during state ST1. The right side of each equation is the terminal voltage of capacitors C1, C2_1, C3_1, C2_2, or C3_2 during state ST3. Vin - Va = Vb - Vg (11) Va - Ve = Vb - Vg (12) Va - Ve = Vg - Vh (13) Ve = Vg - Vh (14) Ve - Vf = Vh (15) Between state ST3 and other periods, the following equation (16) holds true for coil L1 according to the voltage-time balance law. The left side shows the case for state ST3, and the right side shows the case for states other than state ST3. D(Vh-Vout)=(1-D)Vout (16) Equation (16) is transformed into equation (17). DVh=Vout (17) Between state ST1 and other periods, the following equation (18) holds true for coil L2 according to the voltage-time balance law. The left side shows the case for state ST1, and the right side shows the case for states other than state ST3. D(Vf-Vout)=(1-D)Vout (18) Equation (18) is transformed into equation (19). DVf=Vout (19) From equations (17) and (19), the following equation (8) is obtained. Vf=Vh (20) From equations (11), (12), (13), (14), (15), (16), and (20), the following equation (21) is obtained. Vin=6Vh (21) From equations (17) and (21), the following equation (22) is obtained.

[0066] D = 6 × (Vout / Vin) (22) Equation (22) shows that if the DC-DC converter circuit 1 is to achieve the same conversion rate (i.e., Vout / Vin) as the reference DC-DC converter circuit, the duty cycle D can be set to six times the duty cycle Da of the reference DC-DC converter circuit. In other words, the duty cycle D can be made even larger than in the first embodiment.

[0067] As shown in Figure 12, three or more switch-capacitor sets SC may be provided. In this case, the multiple switch-capacitor sets SC are connected in series between nodes N2 and N4 and between nodes N3 and N5, as described above with reference to Figure 10. A generalized description including the case of two switch-capacitor sets SC is as follows:

[0068] Let p be an integer between 1 and P. For each case where p is between 1 and P, the switch-capacitor set SC_p includes switches SW3_p and SW4_p, and capacitors C2_p and C3_p. For each case where p is between 1 and P, switch SW3_p is connected between node N2_p and node N3_p. For each case where p is between 1 and P, switch SW3_p receives control signal φ1 at its control terminal. For each case where p is between 1 and P, switch SW4_p is connected between node N4_p and node N3_p. For each case where p is between 1 and P, switch SW4_p receives control signal φ2 at its control terminal.

[0069] Node N2_1 of switch-capacitor set SC_1 is connected to node N2. Node N3_1 of switch-capacitor set SC_1 is connected to node N3.

[0070] For each case where p is between 1 and P, node N4_p of switch-capacitor set SC_p is connected to node N2_p+1 of switch-capacitor set SC_p+1. For each case where p is between 1 and P, node N5_p of switch-capacitor set SC_p is connected to node N3_p+1 of switch-capacitor set SC_p+1.

[0071] Node N4_P of switch-capacitor set SC_P is connected to node N4. Node N5_P of switch-capacitor set SC_P is connected to node N5.

[0072] Figure 13 shows the states of the DC-DC converter circuit in the second embodiment in sequence. From top to bottom, Figure 13 shows the equivalent circuits between states ST1, ST2, ST3, and ST4. The equivalent circuits for states ST2 and ST4 are the same as those in the first embodiment (Figure 8).

[0073] As shown in Figure 13, in state ST1, the capacitors C2 (C2_1, C2_2, ..., C2_p, C2_p+1, ..., C2_P) and coil L1 of the P switch-capacitor sets SC are connected in series in this order between the input node Nin and the output node Nout. In state ST1, the capacitors C3 (C3_1, C3_2, ..., C3_p, C3_p+1, ..., C3_P) and coil L2 of the P switch-capacitor sets SC are connected in series in this order between the node to which capacitors C1 and C2_2 are connected (i.e., node N3) and the output node Nout. In state ST1, for each case where p is between 1 and P-1, the node to which capacitors C2_p and C2_p+1 are connected (i.e., node N2_p+1) is connected to the node to which capacitors C3_p and C3_p+1 are connected (i.e., node N3_p+1). In state ST1, the node to which capacitor C2_P and coil L1 are connected (i.e., node N4) is connected to the reference potential node Nss.

[0074] In state ST3, capacitors C2 (C2_1, C2_2, ..., C2_p, C2_p+1, ..., C2_P) and coil L1 of P switch-capacitor sets SC are connected in series in this order between the node to which capacitors C2_1 and C1 are connected (i.e., node N2) and the output node Nout. In state ST3, capacitor C1, capacitors C3 (C3_1, C3_2, ..., C3_p, C3_p+1, ..., C3_P) of P switch-capacitor sets SC, and coil L2 are connected in series in this order between the node to which capacitors C2_1 and C1 are connected (i.e., node N2) and the output node Nout. In state ST3, the node to which capacitors C2_1 and C2_2 are connected (i.e., node N4_1) is connected to the node to which capacitors C1 and C3_1 are connected (i.e., node N3). In state ST3, for each case where p is between 2 and P-1, the node to which capacitor C2_p and capacitor C2_p+1 are connected (i.e., node N2_p+1) is connected to the node to which capacitor C3_p-1 and capacitor C3_p are connected (i.e., node N3_p). In state ST3, the node to which capacitor C2_P and coil L1 are connected (i.e., node N4_P) is connected to the node to which capacitor C3_P-1 and capacitor C3_P are connected (i.e., node N3_P). In state ST3, the node to which capacitor C3_P and coil L2 are connected (i.e., node N5) is connected to the reference potential node Nss.

[0075] For the duty cycle D in a DC-DC converter circuit 1b containing P switch-capacitor sets SC, the following equation (23) holds true. In equation (23), x is the total number of capacitors C1, C2, and C3 in the DC-DC converter circuit 1, that is, if P switch-capacitor sets SC are included, x = 1 + 2 × P. D = (x + 1) × (Vout / Vin) (23) While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0076] 10...Voltage conversion circuit, 20... circuits, 1…DC-DC converter circuit, 2...control circuit, Vin...input voltage, Vout...Output voltage, Nin... Input node, Nout... Output node, SW1, SW2, SW3, SW4, SW5, SW6... Switches, C1, C2, C3... Capacitors, L1, L2... coils

Claims

1. It comprises a first capacitor, a second capacitor, a third capacitor, a first coil, a second coil, and multiple switches. By turning the aforementioned multiple switches on and off, In a first state, the first capacitor is connected between the input node and the first node, the second capacitor and the first coil are connected in series between the first node and the output node, the third capacitor and the second coil are connected in series between the first node and the output node, and the second node to which the second capacitor and the first coil are connected is connected to the first reference potential node. In the second state, the second capacitor and the first coil are connected in series between the third node and the output node, the first capacitor, the third capacitor, and the second coil are connected in series between the third node and the output node, the fourth node to which the second capacitor and the first coil are connected is connected to the node to which the first capacitor and the third capacitor are connected, and the fifth node to which the third capacitor and the second coil are connected is connected to the second reference potential node. A DC-DC converter circuit having the following features.

2. The on and off of the plurality of switches results in a third state in which the first coil is connected between the first reference potential node and the output node, and the second coil is connected between the second reference potential node and the output node. The DC-DC converter circuit according to claim 1.

3. By turning the multiple switches on and off, the system proceeds from the first state to the third state, from the third state to the second state, from the second state to the third state, and from the third state to the first state. The DC-DC converter circuit according to claim 2.

4. The aforementioned multiple switches are A first switch between the input node and the first capacitor, A second switch between the first switch and the third node, A third switch between the third node and the first node, A fourth switch between the second node and the first node, A fifth switch between the second node and the first reference potential node, A sixth switch between the fifth node and the second reference potential node, A DC-DC converter circuit according to any one of claims 1 to 3, including the above.

5. First capacitor and, A set of first to P (where P is an integer of 2 or more) capacitors, each comprising a second capacitor and a third capacitor, The first coil and The second coil and Multiple switches, Equipped with, By turning the aforementioned multiple switches on and off, In the first state, the first capacitor is connected between the input node and the first node, the second capacitor and the first coil of each of the first to P capacitor sets are connected in series between the first node and the output node, the third capacitor and the second coil of each of the first to P capacitor sets are connected in series between the first node and the output node, and in each case where p is 1 or greater and P-1 or less, the second node to which the second capacitor of the p capacitor set and the second capacitor of the p+1 capacitor set are connected is connected to the node to which the third capacitor of the p capacitor set and the third capacitor of the p+1 capacitor set are connected, and the third node to which the second capacitor and the first coil of the P capacitor set are connected is connected to the first reference potential node. The second capacitor and first coil of each of the first to P capacitor sets are connected in series between the fourth node and the output node, the first capacitor, each of the third capacitors of the first to P capacitor sets, and the second coil are connected in series between the fourth node and the output node, the node to which the second capacitor of the first capacitor set and the second capacitor of the second capacitor set are connected is connected to the first node, for each case where p is 2 or greater and less than or equal to P-1, the node to which the second capacitor of the p capacitor set and the second capacitor of the p+1 capacitor set are connected is connected to the fifth node to which the third capacitor of the p-1 capacitor set and the third capacitor of the p capacitor set are connected, the node to which the second capacitor of the P capacitor set and the first coil are connected is connected to the node to which the third capacitor of the P-1 capacitor set and the third capacitor of the P capacitor set are connected, and the sixth node to which the third capacitor of the P capacitor set and the second coil are connected is connected to the second reference potential node, in a second state, A DC-DC converter circuit having the following features.

6. The on and off of the plurality of switches results in a third state in which the first coil is connected between the first reference potential node and the output node, and the second coil is connected between the second reference potential node and the output node. The DC-DC converter circuit according to claim 5.

7. By turning the multiple switches on and off, the system proceeds from the first state to the third state, from the third state to the second state, from the second state to the third state, and from the third state to the first state. The DC-DC converter circuit according to claim 6.

8. The aforementioned multiple switches are A first switch between the input node and the first capacitor, A second switch between the first switch and the fourth node, For each case where p is between 1 and P, the third switch is between the second capacitor of the p capacitor set and the fifth node of the p capacitor set, For each case where p is between 1 and P, the fourth switch is located between the second node of the p capacitor set and the fifth node of the p capacitor set, A fifth switch between the third node and the first reference potential node, A sixth switch between the sixth node and the second reference potential node, A DC-DC converter circuit according to any one of claims 5 to 7, including the above.

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