Motor driver device and transmission circuit

Abstract

To provide a technology that can prevent current from flowing backward from the motor driver side to the control unit side. [Solution] The motor driver device according to this technology comprises a control unit, a motor driver, and a first transmission circuit. The control unit has a first output terminal that outputs a first signal and is driven by a first voltage value. The motor driver has an internal power supply having a second voltage value higher than the first voltage value, and a first input terminal connected to the internal power supply to which the first signal is input, and drives the motor by switching the motor drive mode based on the first signal input from the first input terminal. The first transmission circuit has a first reverse current prevention element for preventing reverse current flow from the first input terminal side to the first output terminal side, is interposed between the control unit and the motor driver, and transmits the first signal from the first output terminal to the first input terminal.

Description

Technical Field

[0001] This technology relates to technologies such as motor driver devices for driving motors.

Background Art

[0002] Conventionally, motor driver devices capable of driving a motor in different modes have been widely known (for example, see Patent Document 1 below).

[0003] For example, Patent Document 1 below discloses a stepping motor driving device including a driver IC (integrated circuit) for driving a stepping motor and a control unit for controlling the driving of the driver IC. In this stepping motor driving device, the driver IC switches the driving mode to either the 1-2 phase excitation method or the 2-phase excitation method based on a switching signal output from the control unit, and drives the motor in the selected driving mode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The switching signal for switching the mode is transmitted from the control unit side to the motor driver side, but there may be a case where current flows backward from the motor driver side to the control unit side.

[0006] In view of the above circumstances, it is an object to provide a technology capable of preventing current from flowing backward from the motor driver side to the control unit side.

Means for Solving the Problems

[0007] The motor driver device according to this technology comprises a control unit, a motor driver, and a first transmission circuit. The control unit has a first output terminal that outputs a first signal and is driven by a first voltage value. The motor driver has an internal power supply having a second voltage value higher than the first voltage value, and a first input terminal connected to the internal power supply to which the first signal is input, and drives the motor by switching the motor drive mode based on the first signal input from the first input terminal. The first transmission circuit has a first reverse current prevention element for preventing reverse current flow from the first input terminal to the first output terminal, is interposed between the control unit and the motor driver, and transmits the first signal from the first output terminal to the first input terminal.

[0008] In this motor driver device, the internal voltage of the motor driver that receives the signal is higher than the drive voltage of the control unit that outputs the signal. However, the first reverse current prevention element prevents current from flowing in reverse from the motor driver side to the control unit side.

[0009] The transmission circuit related to this technology is A control unit having an output terminal that outputs a signal and driven by a first voltage value, An internal power supply having a second voltage value higher than the first voltage value, and a motor driver having an input terminal connected to the internal power supply and into which the signal is input, which switches the motor drive mode and drives the motor based on the signal input from the input terminal. A transmission circuit interposed between the output terminal and the input terminal for transmitting the signal from the output terminal to the input terminal, It has a reverse current prevention element to prevent current from flowing back from the input terminal to the output terminal. [Effects of the Invention]

[0010] As described above, this technology provides a method to prevent current from flowing backward from the motor driver side to the control unit side. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows the circuit configuration near the M0 terminal of the motor driver in the motor driver device according to the first embodiment of this technology. [Figure 2] This figure shows the circuit configuration near the M1 terminal of the motor driver in the motor driver device according to the first embodiment of this technology. [Figure 3] This figure shows a status table illustrating the relationship between the combination of the states of the M0 and M1 terminals and the motor's drive mode. [Modes for carrying out the invention]

[0012] The embodiments of this technology will be described below with reference to the drawings.

[0013] <Overall structure and structure of each part>

[0014] Figure 1 shows the circuit configuration near the M0 terminal 21 of the motor driver 20 in the motor driver device 100 according to the first embodiment of this technology. Figure 2 shows the circuit configuration near the M1 terminal 26 of the motor driver 20 in the motor driver device 100 according to the first embodiment of this technology.

[0015] As shown in Figures 1 and 2, the motor driver device 100 comprises a CPU 10 (Central Processing Unit) (control unit) and a motor driver 20 (driver IC) that switches the drive mode of the (stepping) motor according to a mode switching signal input from the CPU 10. Note that in Figures 1 and 2, the CPU 10 and the motor driver 20 are the same component.

[0016] Referring to FIG. 1, the motor driver device 100 further includes a first transmission circuit 30 interposed between the CPU 10 and the motor driver 20 for transmitting a first mode switching signal (first signal) from the CPU 10 to the motor driver 20.

[0017] Also, referring to FIG. 2, the motor driver device 100 further includes a second transmission circuit 40 interposed between the control unit and the motor driver 20 for transmitting a second mode switching signal (second signal) from the CPU 10 to the motor driver 20.

[0018] The CPU 10 comprehensively controls the entire motor driver device 100. This CPU 10 generates a first mode switching signal and a second mode switching signal, outputs them to the motor driver 20, and drives the motor in an arbitrary drive mode.

[0019] In this motor driver device 100, a first mode switching signal is output from the CPU 10 to the M0 terminal 21 of the motor driver 20 (FIG. 1), and a second mode switching signal is output from the CPU 10 to the M1 terminal 26 of the motor driver 20 (FIG. 2).

[0020] The motor driver 20 sets the drive mode of the motor based on the combination of the first mode switching signal input via the M0 terminal 21 and the second mode switching signal input via the M1 terminal 26, and drives the motor in the currently set drive mode (see FIG. 3 described later).

[0021] [First Transmission Circuit 30] First, referring to FIG. 1, the configurations of the CPU 10, the motor driver 20, and the first transmission circuit 30 will be described.

[0022] The CPU 10 is entirely connected to ground and is driven by a 3.3V operating voltage. This CPU 10 includes a first GPIO terminal 11 (GPIO: General-purpose input / output) (first output terminal: first terminal) and a second GPIO terminal 12 (first output terminal: second terminal). The first GPIO terminal 11 and the second GPIO terminal 12 are configured to output a first mode switching signal.

[0023] Specifically, the voltage level of the first GPIO pin 11 of the CPU 10 is set to either a low level or a high level according to the control of the CPU 10. Similarly, the voltage level of the second GPIO pin 12 of the CPU 10 is also set to either a low level or a high level according to the control of the CPU 10.

[0024] At this time, there are four possible combinations of high-level and low-level voltage levels for the first GPIO terminal 11 and the second GPIO terminal 12, as shown in (1) to (4) below (2 x 2). (1) The first GPIO pin 11 is low level, and the second GPIO pin 12 is low level. (2) The first GPIO pin 11 is low level, and the second GPIO pin 12 is high level. (3) The first GPIO pin 11 is high level, and the second GPIO pin 12 is low level. (4) The first GPIO pin 11 is high level, and the second GPIO pin 12 is high level.

[0025] When the voltage level combination of the first GPIO terminal 11 and the second GPIO terminal 12 is set to one of (1) to (4), the M0 terminal 21 of the motor driver 20 is set to one of three states, including high level, low level, and high impedance (Hi-Z).

[0026] In this way, the first mode switching signal (a signal consisting of a combination of voltage levels) from the first GPIO terminal 11 and the second GPIO terminal 12 of the CPU 10 is transmitted to the motor driver 20 via the M0 terminal 21.

[0027] The motor driver 20 is configured to set the motor drive mode based on the combination of the state set at terminal M0 21 and the state set at terminal M1 26 (see Figure 3 below).

[0028] The motor driver 20 is entirely connected to ground. This motor driver 20 includes an M0 terminal 21 (first input terminal) to which a first mode switching signal from the CPU 10 is input, and a digital power terminal 22 (DVDD terminal).

[0029] The motor driver 20 also includes an internal power supply 23 located inside the motor driver 20. In this embodiment, the voltage value of the internal power supply 23 is set to 5V (the voltage value of the digital power terminal 22 is also set to 5V). The internal power supply 23 is connected to ground via an adjustment current source 24 (e.g., 10μA) and a resistor 25 (e.g., 200kΩ). The internal power supply 23 is also connected to the M0 terminal 21 via the adjustment current source 24.

[0030] The M0 terminal 21 is connected to the internal power supply 23 via an adjustment current source 24 within the motor driver 20. This M0 terminal 21 is configured to accept a first mode switching signal input from the CPU 10 via a first transmission circuit 30. In this embodiment, the M0 terminal 21 is set to one of three states, including high level, low level, and high impedance (Hi-Z), in response to the first mode switching signal.

[0031] In this embodiment, the voltage of the internal power supply 23 of the motor driver 20 is 5V, while the drive voltage of the CPU 10 is 3.3V. Therefore, without any countermeasures, there is a problem in the first transmission circuit 30 where current flows in reverse from the motor driver 20 to the CPU 10.

[0032] Therefore, in this embodiment, a first reverse current prevention element 1 is provided in the first transmission circuit 30 to prevent reverse current flow from the motor driver 20 to the CPU 10. Similarly, in this embodiment, a second reverse current prevention element 4 is provided in the second transmission circuit 40 to prevent reverse current flow from the motor driver 20 to the CPU 10.

[0033] The first transmission circuit 30 has a first reverse current prevention element 1. This first reverse current prevention element 1 is configured to appropriately transmit the first mode switching signal from the CPU 10 side to the motor driver 20 side, while preventing reverse current flow from the M0 terminal 21 (and digital power terminal 22) side to the first GPIO terminal 11 and the second GPIO terminal 12 side.

[0034] The first reverse current prevention element 1 includes three transistors: a first NPN type transistor 1a, a second NPN type transistor 1b, and a first PNP type transistor 1c. These transistors are bipolar transistors.

[0035] The base of the first NPN transistor 1a is connected to the first GPIO terminal 11 of the CPU 10 via a base resistor 1a', and this base is further connected to ground via a pull-down resistor 1a''. The collector of the first NPN transistor 1a is connected to the M0 terminal 21 of the motor driver 20 via a resistor 2, and this collector is further connected to the collector of the first PNP transistor 1c via a resistor 2. The emitter of the first NPN transistor 1a is connected to ground.

[0036] The base of the second NPN transistor 1b is connected to the second GPIO terminal 12 of the CPU 10 via a base resistor 1b', and this base is further connected to ground via a pull-down resistor 1b''. The collector of the second NPN transistor 1b is connected to the base of the first PNP transistor 1c, and its emitter is connected to ground.

[0037] The base of the first PNP transistor 1c is connected to the collector of the second NPN transistor 1b via a base resistor 1c', and this base is connected to the digital power terminal 22 of the motor driver 20 via a pull-up resistor 1c''. The emitter of the first PNP transistor 1c is also connected to the digital power terminal 22 of the motor driver 20. The collector of the first PNP transistor 1c is connected to the collector of the first NPN transistor 1a via a resistor 2, and this collector is connected to the M0 terminal 21 of the motor driver 20.

[0038] Furthermore, the first GPIO pin 11 of the CPU 10 is connected to the base side of the first npn transistor 1a. Also, the second GPIO pin 12 of the CPU 10 is connected to the base side of the second npn transistor 1b.

[0039] Furthermore, the M0 terminal 21 of the motor driver 20 is connected to the collector side of the first npn transistor 1a via resistor 2, and further connected to the collector side of the first pnp transistor 1c. In addition, the digital power supply terminal 22 of the motor driver 20 is connected to the emitter side of the first pnp transistor 1c, and further connected to ground via capacitor 3 (for example, 4μF).

[0040] [Second transmission circuit 40] Next, with reference to Figure 2, the configurations of the CPU 10, motor driver 20, and second transmission circuit 40 will be described.

[0041] The CPU 10 further includes a third GPIO terminal 13 (second output terminal: third terminal) and a fourth GPIO terminal 14 (second output terminal: fourth terminal). The second GPIO terminal 12 and the third GPIO terminal 13 are configured to output a second mode switching signal.

[0042] Specifically, the voltage level of the third GPIO pin 13 of the CPU 10 is set to either a low level or a high level according to the control of the CPU 10. Similarly, the voltage level of the fourth GPIO pin 14 of the CPU 10 is also set to either a low level or a high level according to the control of the CPU 10.

[0043] At this time, the combinations of high-level and low-level voltage levels at the third GPIO terminal 13 and the fourth GPIO terminal 14 are the following four types (2 × 2): (1)' to (4)'. (1)' The third GPIO pin 13 is low level, and the fourth GPIO pin 14 is low level. (2)' The third GPIO pin 13 is low level, and the fourth GPIO pin 14 is high level. (3)' The third GPIO pin 13 is high level, and the fourth GPIO pin 14 is low level. (4)' The third GPIO pin 13 is high level, and the fourth GPIO pin 14 is high level.

[0044] When the voltage level combination at the third GPIO terminal 13 and the fourth GPIO terminal 14 is set to one of (1)' to (4)', the M1 terminal 26 of the motor driver 20 is set to one of three states, including high level, low level, and ground connection via resistor 7 (e.g., 330kΩ).

[0045] In this way, the second mode switching signal (a signal consisting of a combination of voltage levels) from the third GPIO terminal 13 and the fourth GPIO terminal 14 of the CPU 10 is transmitted to the motor driver 20 via the M1 terminal 26.

[0046] The motor driver 20 is configured to set the motor drive mode based on the combination of the state set at terminal M0 21 and the state set at terminal M1 26 (see Figure 3 below).

[0047] The motor driver 20 includes an M1 terminal 26 (second input terminal) to which a second mode switching signal from the CPU 10 is input, and a digital power terminal 27 (DVDD terminal). The motor driver 20 also includes an internal power supply 23 located inside the motor driver 20. The internal power supply 23 is connected to ground via an adjustment current source 28 (e.g., 10 μA) and a resistor 29 (e.g., 200 kΩ). The internal power supply 23 is also connected to the M1 terminal 26 via the adjustment current source 28.

[0048] The M1 terminal 26 is connected to the internal power supply 23 via an adjustment current source 28 within the motor driver 20. This M1 terminal 26 is configured to accept a second mode switching signal input from the CPU 10 via a second transmission circuit 40. In this embodiment, the M1 terminal 26 is set to one of three states, including high level, low level, and ground connection via resistor 7 (e.g., 330kΩ), depending on the second mode switching signal.

[0049] The second transmission circuit 40 has a second reverse current prevention element 4. This second reverse current prevention element 4 is configured to appropriately transmit the second mode switching signal from the CPU 10 to the motor driver 20, while preventing reverse current flow from the M1 terminal 26 (and digital power terminal 22) to the third GPIO terminal 13 and the fourth GPIO terminal 14.

[0050] The second reverse current prevention element 4 includes three transistors: a third NPN type transistor 4a, a fourth NPN type transistor 4b, and a second PNP type transistor 4c. These transistors are bipolar transistors.

[0051] The base of the third NPN transistor 4a is connected to the third GPIO terminal 13 of the CPU 10 via a base resistor 4a', and this base is further connected to ground via a pull-down resistor 4a''. The collector of the third NPN transistor 4a is connected to the M1 terminal 26 of the motor driver 20 via a resistor 5, and this collector is further connected to the collector of the second PNP transistor 4c via a resistor 5. Furthermore, the collector of the third NPN transistor 4a is connected to ground via resistors 5 and 7 (e.g., 330kΩ). The emitter of the third NPN transistor 4a is also connected to ground.

[0052] The base of the fourth NPN transistor 4b is connected to the fourth GPIO pin 14 of the CPU 10 via a base resistor 4b', and this base is further connected to ground via a pull-down resistor 4b''. The collector of the fourth NPN transistor 4b is connected to the base of the second PNP transistor 4c, and its emitter is connected to ground.

[0053] The base of the second PNP transistor 4c is connected to the collector of the fourth NPN transistor 4b via a base resistor 4c', and this base is connected to the digital power terminal 27 of the motor driver 20 via a pull-up resistor 4c''. The emitter of the second PNP transistor 4c is also connected to the digital power terminal 27 of the motor driver 20. The collector of the second PNP transistor 4c is connected to the collector of the third NPN transistor 4a via a resistor 5, and this collector is connected to the M1 terminal 26 of the motor driver 20. Furthermore, the collector of the third NPN transistor 4a is connected to ground via a resistor 7 (for example, 330kΩ).

[0054] Furthermore, the first third GPIO pin 13 of the CPU 10 is connected to the base side of the third npn transistor 4a. Also, the fourth GPIO pin 14 of the CPU 10 is connected to the base side of the fourth npn transistor 4b.

[0055] Furthermore, the M1 terminal 26 of the motor driver 20 is connected to the collector side of the third npn transistor 4a via a resistor 5, and further connected to the collector side of the fourth npn transistor 4c. In addition, the M1 terminal 26 of the motor driver 20 is connected to ground via a resistor (e.g., 330kΩ). Furthermore, the digital power supply terminal 22 of the motor driver 20 is connected to ground via a capacitor (e.g., 4μF), and further connected to the emitter side of the second pnp transistor 4c.

[0056] [Operation in the first transmission circuit 30] Next, the operation of the first transmission circuit 30 will be described with reference to Figure 1.

[0057] {(1) The first GPIO pin 11 is low level, and the second GPIO pin 12 is low level} When the output voltage of the first GPIO terminal 11 is low level, the voltage value between the base and emitter of the first npn transistor 1a is less than a predetermined threshold, and in this case, the first npn transistor 1a is OFF.

[0058] Furthermore, when the output voltage of the second GPIO terminal 12 is low, the voltage between the base and emitter of the second npn transistor 1b is less than a predetermined threshold, and in this case, the second npn transistor 1b is OFF. When the second npn transistor 1b is OFF, the voltage between the emitter and base of the first pnp transistor 1c is less than a predetermined threshold, and therefore, the first pnp transistor 1c is also OFF.

[0059] When the output voltage of the first GPIO terminal 11 is low level and the second GPIO terminal 12 is also low level, the M0 terminal 21 of the motor driver 20 is in a high impedance state.

[0060] {(2) The first GPIO pin 11 is low level, and the second GPIO pin 12 is high level} When the output voltage of the first GPIO terminal 11 is low level, the first npn transistor 1a is OFF.

[0061] When the output voltage of the second GPIO terminal 12 is high, the voltage between the base and emitter of the second NPN transistor 1b becomes greater than or equal to a predetermined threshold, and the second NPN transistor 1b turns ON. As a result, the voltage between the emitter and base of the first PNP transistor 1c becomes greater than or equal to a predetermined threshold, and the first PNP transistor 1c turns ON.

[0062] When the second npn transistor 1b is ON and the first pnp transistor 1c is ON, current from the digital power supply terminal 22 flows from the emitter and collector of the first pnp transistor 1c, through the M0 terminal 21 and resistor 25 to ground. At this time, the M0 terminal 21 is at a high level.

[0063] Furthermore, at this time, current from the digital power terminal 22 flows to ground via the emitter and base of the first PNP transistor 1c and the collector and emitter of the second NPN transistor 1b. At this time, no current flows from the base side of the second NPN transistor 1b towards the second GPIO terminal 12, thus preventing reverse current flow from the motor driver 20 to the CPU 10.

[0064] When the output voltage of the first GPIO terminal 11 is low and the output voltage of the second GPIO terminal 12 is high, the M0 terminal 21 becomes high.

[0065] {(3) The first GPIO pin 11 is high level, and the second GPIO pin 12 is low level} When the output voltage of the second GPIO terminal 12 is low, the second npn transistor 1b and the first pnp transistor 1c are both OFF.

[0066] When the output voltage of the first GPIO terminal 11 is at a high level, the voltage value between the base and emitter of the first npn transistor 1a is greater than or equal to a predetermined threshold, and in this case, the first npn transistor 1a is ON.

[0067] When the first NPN transistor 1a is turned ON, current from the internal power supply 23 flows to ground through the adjustment current source 24, the M0 terminal 21, the resistor 2, and the collector and emitter junction of the first NPN transistor 1a. At this time, the M0 terminal 21 is at a low level. At this time, no current flows from the base side of the first NPN transistor 1a to the first GPIO terminal 11 side, thus preventing reverse current flow from the motor driver 20 side to the CPU 10 side.

[0068] When the output voltage of the first GPIO terminal 11 is high and the output voltage of the second GPIO terminal 12 is low-high, the M0 terminal 21 becomes low.

[0069] {(4) The first GPIO pin 11 is high level, and the second GPIO pin 12 is high level} When the output voltage of the first GPIO terminal 11 is at a high level, the first npn transistor 1a is turned ON.

[0070] When the first NPN transistor 1a is turned ON, current from the internal power supply 23 flows to ground through the adjustment current source 24, the M0 terminal 21, the resistor 2, and the collector and emitter junction of the first NPN transistor 1a. At this time, the M0 terminal 21 is at a low level. At this time, no current flows from the base side of the first NPN transistor 1a to the first GPIO terminal 11 side, thus preventing reverse current flow from the motor driver 20 side to the CPU 10 side.

[0071] Furthermore, when the output voltage of the second GPIO terminal 12 is at a high level, the second NPN transistor 1b and the first NPN transistor 1a are both turned ON.

[0072] When the second NPN transistor 1b and the first PNP transistor 1c are turned ON, current from the digital power supply terminal 22 flows to ground through the emitter and collector of the first PNP transistor 1c, resistor 2, and the collector and emitter of the first NPN transistor 1a.

[0073] Furthermore, at this time, the current from the digital power terminal 22 flows to ground via the emitter and base of the first PNP transistor 1c and the collector and emitter of the second NPN transistor 1b. At this time, no current flows from the base side of the second NPN transistor 1b towards the second GPIO terminal 12, thus preventing reverse current flow from the motor driver 20 to the CPU 10.

[0074] When the output voltage of the first GPIO terminal 11 is high and the output voltage of the second GPIO terminal 12 is high, the M0 terminal 21 becomes low.

[0075] [Operation in the second transmission circuit 40] Next, the operation of the second transmission circuit 40 will be explained with reference to Figure 2.

[0076] {(1)'The third GPIO pin 13 is low level, and the fourth GPIO pin 14 is low level} When the output voltage of the third GPIO terminal 13 is low, the voltage between the base and emitter of the third NPN transistor 4a is below a predetermined threshold, and therefore the third NPN transistor 4a is OFF.

[0077] Furthermore, when the output voltage of the fourth GPIO terminal 14 is low, the voltage between the base and emitter of the fourth npn transistor 4b is below a predetermined threshold, and therefore the fourth npn transistor 4b is OFF. When the fourth npn transistor 4b is OFF, the voltage between the emitter and base of the second pnp transistor 4c is below a predetermined threshold, and therefore the second pnp transistor 4c is also OFF.

[0078] When the output voltage of the third GPIO terminal 13 is low and the fourth GPIO terminal 14 is low, the M1 terminal 26 of the motor driver 20 is connected to ground via the resistor 7 (for example, 330kΩ).

[0079] {(2)'The third GPIO pin 13 is low level, and the fourth GPIO pin 14 is high level} When the output voltage of the third GPIO terminal 13 is low, the third NPN transistor 4a is OFF.

[0080] When the output voltage of the fourth GPIO terminal 14 is high, the voltage between the base and emitter of the fourth NPN transistor 4b becomes greater than or equal to a predetermined threshold, and the fourth NPN transistor 4b turns ON. As a result, the voltage between the emitter and base of the second PNP transistor 4c becomes greater than or equal to a predetermined threshold, and the second PNP transistor 4c turns ON.

[0081] When the fourth NPN transistor 4b is ON and the second PNP transistor 4c is ON, current from the digital power supply terminal 27 flows from the emitter and collector of the second PNP transistor 4c, through the M1 terminal 26 and resistor 29 to ground. At this time, the M1 terminal 26 is at a high level.

[0082] At this time, the current from the digital power supply terminal 27 flows through the emitter and collector of the second PNP transistor 4c, and through the resistor 7 to ground.

[0083] Furthermore, at this time, current from the digital power terminal 27 flows to ground via the emitter and base of the second PNP transistor 4c and the collector and emitter of the fourth NPN transistor 4b. At this time, no current flows from the base side of the fourth NPN transistor 4b towards the fourth GPIO terminal 14, thus preventing reverse current flow from the motor driver 20 to the CPU 10.

[0084] When the output voltage of the third GPIO terminal 13 is low and the output voltage of the fourth GPIO terminal 14 is high, the M1 terminal 26 becomes high.

[0085] {(3)'The third GPIO pin 13 is high level, and the fourth GPIO pin 14 is low level} When the output voltage of the fourth GPIO terminal 14 is low, the fourth NPN transistor 4b and the second PNP transistor 4c are both OFF.

[0086] When the output voltage of the third GPIO terminal 13 is high, the voltage value between the base and emitter of the third npn transistor 4a is greater than or equal to a predetermined threshold, and therefore the third npn transistor 4a is ON.

[0087] When the third NPN transistor 4a is turned ON, current from the internal power supply 23 flows to ground through the adjustment current source 28, M1 terminal 26, resistor 5, and the collector and emitter junction of the third NPN transistor 4a. At this time, M1 terminal 26 is at a low level. In addition, at this time, no current flows from the base side of the third NPN transistor 4a to the third GPIO terminal 13 side, thus preventing reverse current flow from the motor driver 20 side to the CPU 10 side.

[0088] At this time, the current from the internal power supply 23 flows to ground via the regulating current source 28, the M1 terminal 26, and the resistor 7.

[0089] When the output voltage of the third GPIO pin 13 is high and the output voltage of the fourth GPIO pin 14 is low, the M1 pin 26 will be low.

[0090] {(4)'The third GPIO pin 13 is high level, and the fourth GPIO pin 14 is high level} When the output voltage of the third GPIO terminal 13 is high, the third NPN transistor 4a turns ON.

[0091] When the third NPN transistor 4a is turned ON, current from the internal power supply 23 flows to ground through the adjustment current source 28, M1 terminal 26, resistor 5, and the collector and emitter junction of the third NPN transistor 4a. At this time, M1 terminal 26 is at a low level. In addition, at this time, no current flows from the base side of the third NPN transistor 4a to the third GPIO terminal 13 side, thus preventing reverse current flow from the motor driver 20 side to the CPU 10 side.

[0092] Furthermore, when the output voltage of the fourth GPIO terminal 14 is high, the fourth NPN transistor 4b and the second PNP transistor 4c are both turned ON.

[0093] When the fourth NPN transistor 4b and the second PNP transistor 4c are turned ON, current from the digital power terminal 27 flows to ground through the emitter and collector of the second PNP transistor 4c, resistor 5, and the collector and emitter of the third NPN transistor 4a. At this time, current from the digital power terminal 27 also flows to ground through the emitter and collector of the second PNP transistor 4c and resistor 7.

[0094] Furthermore, at this time, the current from the digital power terminal 27 flows to ground via the emitter and base of the second PNP transistor 4c and the collector and emitter of the fourth NPN transistor 4b. At this time, no current flows from the base side of the fourth NPN transistor 4b towards the fourth GPIO terminal 14, thus preventing reverse current flow from the motor driver 20 to the CPU 10.

[0095] When the output voltage of the third GPIO pin 13 is high and the output voltage of the fourth GPIO pin 14 is high, the M1 pin 26 becomes low.

[0096] <Motor drive modes> Next, we will explain the relationship between the combination of the states of terminal M0 21 and terminal M1 26 and the motor's drive mode (step mode).

[0097] Figure 3 is a status table showing the relationship between the combination of the states of terminal M0 21 and terminal M1 26 and the motor drive mode.

[0098] In the example shown in Figure 3, seven different drive modes, from drive mode (A) to drive mode (G), are set for each combination of the state of terminal M0 21 (low level, high level, high impedance state) and the state of terminal M1 26 (low level, high level, ground connection state via resistor 7 (330kΩ)).

[0099] In this embodiment, there are three states for the M0 terminal 21 and three states for the M1 terminal 26, so there are a maximum of 3 x 3 = 9 possible combinations. However, in this embodiment, 7 of the 9 possible combinations are used. It is also possible to assign all 9 possible combinations to each drive mode.

[0100] The motor drive modes (A) to (G) are pre-set according to various types, such as 2-phase excitation mode, 1-2 phase excitation mode, circular step mode, non-circular step mode, full step mode, 1 / 2 step mode, 1 / 4 step mode, 1 / 8 step mode, 1 / 16 step mode, etc.

[0101] <Effect, etc.> As described above, in this embodiment, a first reverse current prevention element 1 is provided in the first transmission circuit 30 interposed between the CPU 10 and the motor driver 20 to prevent reverse current flow from the motor driver 20 side to the CPU 10 side. Similarly, a second reverse current prevention element 4 is provided in the second transmission circuit 40 interposed between the CPU 10 and the motor driver 20 to prevent reverse current flow from the motor driver 20 side to the CPU 10 side.

[0102] In this embodiment, the first reverse current prevention element 1 and the second reverse current prevention element can appropriately transmit the mode switching signal to the M0 terminal 21 and the M1 terminal 26 (appropriately setting the state of the M0 terminal 21 and the M1 terminal 26) while preventing reverse current flow from the motor driver 20 to the CPU 10.

[0103] Furthermore, by using the circuit configuration in this embodiment, the motor drive mode can be easily changed by the control of the CPU 10. For example, consider a case where the motor is used as a paper feed motor for a printer. In this case, the CPU 10 drives the motor in full-step mode when the printer is driven in normal mode, and drives the motor in a low-speed 1 / 2-step mode when the printer is driven in silent mode.

[0104] The motor drive device according to this embodiment can be mounted on various electronic devices that include a motor (for example, a multifunction printer). [Explanation of Symbols]

[0105] 1...First backflow prevention element 1a...First NPN transistor 1b...Second NPN transistor 1c...First PNP type transistor 4…Fourth reverse current prevention element 4a...Third NPN transistor 4b...Fourth NPN transistor 4c... Second type of PNP transistor 10…CPU 11…First GPIO pin 12…Second GPIO pin 20…Motor Driver 21…M0 terminal 23…Internal power supply 26…M1 terminal 30...First transmission circuit 40...Second transmission circuit

Claims

1. A control unit having a first output terminal that outputs a first signal and driven by a first voltage value, A motor driver having an internal power supply having a second voltage value higher than the first voltage value, and a first input terminal connected to the internal power supply and to which the first signal is input, and which switches the motor drive mode and drives the motor based on the first signal input from the first input terminal, The control unit and the motor driver are interposed, and the motor driver has a first reverse current prevention element for preventing current from flowing backward from the first input terminal to the first output terminal, and a first transmission circuit for transmitting the first signal from the first output terminal to the first input terminal. A motor driver device comprising the following:

2. A motor driver device according to claim 1, The control unit further has a second output terminal that outputs a second signal, The motor driver further has a second input terminal connected to an internal power supply to which the second signal is input, and drives the motor by switching the drive mode of the motor based on the first signal input to the first input terminal and the second signal input to the second input terminal. The motor driver device is The control unit further comprises a second reverse current prevention element for preventing reverse current flow from the second input terminal to the second output terminal, and a second transmission circuit interposed between the control unit and the motor driver for transmitting the second signal from the second output terminal to the second input terminal. Motor driver device.

3. A motor driver device according to claim 2, The first signal is a signal for setting the first input terminal to one of a plurality of states, including at least a high level and a low level. The second signal is a signal for setting the second input terminal to one of a plurality of states, including at least a high level and a low level. The motor driver switches the motor's drive mode based on a combination of the state at the first input terminal and the state at the second input terminal. Motor driver device.

4. A motor driver device according to claim 3, The first reverse current prevention element transmits the first signal for setting the state while preventing the reverse flow of the current. Motor driver device.

5. A motor driver device according to claim 3, The second reverse current prevention element transmits the second signal for setting the state while preventing the reverse flow of the current. Motor driver device.

6. A motor driver device according to claim 1, The first output terminal includes the first terminal, The first reverse current prevention element includes a first NPN transistor whose base is connected to the first terminal and whose collector is connected to the first input terminal. Motor driver device.

7. A motor driver device according to claim 6, The first output terminal includes a second terminal, The motor driver includes power terminals, The first reverse current prevention element includes a second NPN transistor whose base is connected to the second terminal, and a first PNP transistor whose base is connected to the collector of the second NPN transistor, whose emitter is connected to the power supply terminal, and whose collector is connected to the first input terminal and the collector of the first NPN transistor. Motor driver device.

8. A motor driver device according to claim 2, The second output terminal includes a third terminal, The second reverse current prevention element includes a third NPN transistor whose base is connected to the third terminal and whose collector is connected to the input terminal 2. Motor driver device.

9. A motor driver device according to claim 8, The second output terminal includes a fourth terminal, The motor driver includes power terminals, The second reverse current prevention element includes a third NPN transistor whose base is connected to the fourth terminal, and a second PNP transistor whose base is connected to the collector of the third NPN transistor, whose emitter is connected to the power supply terminal, and whose collector is connected to the second input terminal and the collector of the third NPN transistor. Motor driver device.

10. A control unit having an output terminal that outputs a signal and driven by a first voltage value, An internal power supply having a second voltage value higher than the first voltage value, and a motor driver having an input terminal connected to the internal power supply and into which the signal is input, which drives the motor by switching the motor drive mode based on the signal input from the input terminal. A transmission circuit interposed between the output terminal and the input terminal for transmitting the signal from the output terminal to the input terminal, It has a reverse current prevention element to prevent reverse current flow from the input terminal side to the output terminal side. Transmission circuit.

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