Liquid crystal display device and method for driving a liquid crystal display device

Abstract

To provide a liquid crystal display device that can reduce the circuit size of the pixel circuit. [Solution] The subframe memory 15 has first memories provided at each intersection of multiple first column data lines and multiple first row scan lines. The image display unit 25 has pixel circuits 256 corresponding to pixels including a liquid crystal layer at each intersection of multiple second column data lines and multiple second row scan lines. Subframe voltage data corresponding to each pixel of the subframe data read from the subframe memory 15 is written to each pixel circuit 256 of the image display unit 25. Each pixel circuit 256 has a single second memory that holds the subframe voltage data of each pixel.

Description

Technical Field

[0001] The present invention relates to a liquid crystal display device and a method for driving the liquid crystal display device.

Background Art

[0002] Patent Document 1 describes a digital drive type liquid crystal display device including a pixel circuit including one static random access memory (SRAM) and one dynamic random access memory (DRAM).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the liquid crystal display device described in Patent Document 1 includes an SRAM that operates at a voltage boosted to, for example, 3.3V by a level shifter in order to drive the liquid crystal layer, the circuit scale of the pixel circuit becomes large.

[0005] An object of the present invention is to provide a liquid crystal display device and a method for driving the liquid crystal display device capable of reducing the circuit scale of a pixel circuit.

Means for Solving the Problems

[0006] The present invention provides a subframe memory in which a first memory is provided at each intersection of a plurality of first column data lines and a plurality of first row scan lines; a first horizontal driver that supplies subframe data, in which each pixel data is 1 bit and generated when each frame of a video signal is divided, to the plurality of first column data lines one line at a time in parallel; a first vertical shift register that selects the first row scan line corresponding to each line from the plurality of first row scan lines in order to write and read the data of each line of the subframe data output from the first horizontal driver to the first memory of the line corresponding to each line in the subframe memory; a plurality of second column data lines in the same number as the first column data lines; and the first row scan lines The present invention provides a liquid crystal display device comprising: an image display unit in which a pixel circuit is provided corresponding to a pixel including a liquid crystal layer at each intersection with a plurality of second row scan lines of the same number; a second horizontal driver that supplies subframe voltage data corresponding to the subframe data of each line read from the subframe memory in parallel to the plurality of second column data lines, one line at a time; and a second vertical shift register that selects the second row scan line corresponding to each line from the plurality of second row scan lines in order to write the subframe voltage data corresponding to each line output from the second horizontal driver to the pixels of each line in the image display unit, wherein the pixel circuit has a single second memory that holds the subframe voltage data of each pixel.

[0007] The present invention provides a method for driving a liquid crystal display device, which involves dividing each frame of a video signal to constitute subframe data in which each pixel data is 1 bit, writing the subframe data to a subframe memory having a plurality of first memories, and writing the subframe voltage data corresponding to each pixel of the subframe data read from the subframe memory to a pixel circuit having a single second memory provided in the image display unit, corresponding to a pixel including a liquid crystal layer. [Effects of the Invention]

[0008] According to the liquid crystal display device and the driving method for the liquid crystal display device of the present invention, the circuit size of the pixel circuit can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing a liquid crystal display device according to one embodiment. [Figure 2] Figure 2 is a block diagram showing a specific configuration example of the subframe memory 15 in Figure 1. [Figure 3] Figure 3 is a block diagram showing a specific configuration example of the image display unit 25 in Figure 1. [Figure 4] Figure 4 is a block diagram showing a specific configuration example of the subframe data conversion device 10 shown in Figure 1. [Figure 5] Figure 5 shows an example of a subframe grayscale table held in the subframe grayscale table holding unit 103 of Figure 4. [Figure 6] Figure 6 is a conceptual diagram illustrating an example where one frame of a video signal is converted into 15 subframes. [Figure 7] Figure 7 shows a specific configuration of pixels in a liquid crystal display device according to one embodiment. [Figure 8] Figure 8 is a characteristic diagram showing the relationship between the liquid crystal voltage applied to the liquid crystal layer of a pixel and the displayed grayscale. [Figure 9] Figure 9 is a diagram illustrating how the voltages V0 and V1 supplied to the voltage selection circuit 244 in Figure 1, and the common electrode voltage Vcom supplied to the common electrode 252 are determined. [Figure 10] Figure 10 is a timing chart showing the operation of a liquid crystal display device according to one embodiment. [Figure 11] Figure 11 is a timing chart showing the operation of a liquid crystal display device according to one embodiment, which prevents a period of time during which the image is not displayed correctly when switching between the positive and negative electrode modes. [Modes for carrying out the invention]

[0010] Hereinafter, a liquid crystal display device and a method for driving the liquid crystal display device according to one embodiment will be described with reference to the attached drawings. As shown in Figure 1, the liquid crystal display device 100 according to one embodiment includes a subframe data conversion device 10, a timing generator 11, a data latch circuit 12, a first vertical driver 13, a first horizontal driver 14, and a subframe memory 15. The first vertical driver 13 has a first vertical shift register 131, and the first horizontal driver 14 has a horizontal shift register 141, a first latch circuit 142, and a first switch circuit 143.

[0011] Furthermore, the liquid crystal display device 100 includes a voltage control circuit 17, a second vertical driver 23, a second horizontal driver 24, an image display unit 25, and a common electrode 252. The second vertical driver 23 has a second vertical shift register 231 and an inverter 232. The second horizontal driver 24 has a second switch circuit 241, a second latch circuit 242, a level shifter 243, and a voltage selection circuit 244. The subframe data conversion device 10 may be an external component of the liquid crystal display device 100. The liquid crystal display device 100 is a digitally driven liquid crystal display device.

[0012] As shown in Figure 2, if n and m are natural numbers greater than or equal to 2, the first horizontal driver 14 is connected to n column data lines D1 to Dn (first column data lines), and the first vertical driver 13 is connected to m row scan lines G1 to Gm (first row data lines). The subframe memory 15 has (n × m) SRAMs 151 arranged in a two-dimensional matrix. Each SRAM 151 is provided at each intersection where the n column data lines D1 to Dn and the m-th row scan line G1 to Gm intersect. Any row scan line among the row scan lines G1 to Gm may be referred to as row scan line G. DRAM may be provided instead of SRAMs 151. The subframe memory 15 may have (n × m) first memories arranged in a two-dimensional matrix.

[0013] As shown in FIG. 3, the second horizontal driver 24 is connected to n column data lines d1 to dn (second column data lines), and the second vertical driver 23 is connected to m row scanning lines g1 to gm (second row data lines). The column data lines d1 to dn are a plurality of lines having the same number as the column data lines D1 to Dn, and the row scanning lines g1 to gm are a plurality of lines having the same number as the row scanning lines G1 to Gm. The image display unit 25 has (n×m) pixels 251 arranged in a two-dimensional matrix. Each pixel 251 is provided at each intersection where n column data lines d1 to dn and the m-th row scanning line g1 to gm intersect. Any column data line in the column data lines d1 to dn may be referred to as a column data line d, and any row scanning line in the row scanning lines g1 to gm may be referred to as a row scanning line g.

[0014] In FIGS. 1 and 3, the common electrode 252 is shown separated from the image display unit 25. However, as will be described later, the common electrode 252 is provided as a part of the configuration of all pixels 251 in common.

[0015] As shown in FIG. 4, the sub-frame data conversion device 10 includes a dithering processing unit 101, a sub-frame gradation conversion unit 102, a sub-frame gradation table holding unit 103, a data buffer 104, and a sub-frame driving unit 105. A video signal displayed by the liquid crystal display device 100 is input to the sub-frame data conversion device 10. Assume that the video signal has 8-bit 256 gradations. Each frame input to the sub-frame data conversion device 10 is data of n columns × m rows × 8 bits.

[0016] The dithering processing unit 101 reduces the number of bits of the input 8-bit video signal to 4 bits. The dithering processing unit 101 can reduce the number of bits by error diffusion that spreads the information of each pixel data within the frame to surrounding pixels to reduce the number of gradations. Also, the dithering processing unit 101 can reduce the number of bits by using the frame rate control (FRC) technology that spreads the information of each pixel data in the frame direction using a predetermined dither pattern.

[0017] The sub-frame gradation table holding unit 103 holds the sub-frame gradation table shown in FIG. 5. The sub-frame gradation conversion unit 102 converts the 4-bit video signal supplied from the dither processing unit 101 into a 15-bit bit string according to the sub-frame gradation table. For example, the 4-bit 0000 corresponding to gradation 0 is converted into the 15-bit 000000000000000, and the 4-bit 0100 corresponding to gradation 4 is converted into the 15-bit 111100000000000.

[0018] The 15-bit bit string converted by the sub-frame gradation conversion unit 102 is supplied to the data buffer 104 and held as sub-frame data of 15 sub-frames of sub-frames SF0 to SF14 shown in FIG. 6. Each sub-frame is data of n columns × m rows × 1 bit. That is, each frame of the video signal is divided into a plurality of sub-frames, for example 15, and each sub-frame is composed of sub-frame data in which each pixel data is 1 bit.

[0019] The sub-frame driving unit 105 transfers the sub-frame data to the data latch circuit 12 of FIG. 1 in the order of sub-frames SF0 to SF14. The sub-frame driving unit 105 supplies the vertical synchronization signal SFVS, the horizontal synchronization signal SFHS of the sub-frame data, and the basic clock CLK to the timing generator 11 of FIG. 1. The sub-frame driving unit 105 supplies the threshold voltage Vtt and the saturation voltage Vsat for driving the image display unit 25 to the voltage control circuit 17 shown in FIGS. 1 and 3. Further, the sub-frame driving unit 105 supplies the sub-frame end pulse SFEND and the trigger pulse TRIG indicating the timing of the end of each sub-frame data to the timing generator 11. The trigger pulse TRIG is a pulse signal for determining the timing of the polarity inversion of the polarity inversion signal POL described later.

[0020] In Figure 1, the timing generator 11 generates the following internal signals based on the input basic clock CLK, vertical synchronization signal SFVS, horizontal synchronization signal SFHS, subframe end pulse SFEND, and trigger pulse TRIG. The timing generator 11 generates two types of start pulses VST1 and shift pulse VSH1, which indicate the start timing of writing subframe data to the subframe memory 15 and the start timing of reading subframe data from the subframe memory 15, respectively, and supplies them to the first vertical shift register 131. The timing generator 11 generates a clock signal HCK and a start pulse HST and supplies them to the horizontal shift register 141.

[0021] The timing generator 11 generates a first latch pulse LT1 and supplies it to the first latch circuit 142. The timing generator 11 generates a first switch signal SW1 and supplies it to the first switch circuit 143.

[0022] The timing generator 11 generates two types of start pulses VST2 and shift pulses VSH2, which individually indicate the start timing for writing the black voltage (described later) to each pixel 251 of each line of the image display unit 25, and the start timing for writing the voltage corresponding to each pixel to each pixel 251 of each line, and supplies them to the second vertical shift register 231. The timing generator 11 generates an inversion pulse INV and supplies it to the inverter 232.

[0023] The timing generator 11 generates a second switch signal SW2 and supplies it to the second switch circuit 241. The timing generator 11 generates a second latch pulse LT2 and a latch clear pulse LT2_CLR and supplies them to the second latch circuit 242. The timing generator 11 generates a polarity inversion signal POL, which inverts every subframe, and supplies it to the voltage control circuit 17.

[0024] The data latch circuit 12 latches the subframe data supplied from the subframe data converter 10 in 32-bit increments (data D0 to D31) based on the basic clock CLK, and supplies it to the horizontal shift register 141 in synchronization with the basic clock CLK. The horizontal shift register 141 starts shifting horizontally based on the start pulse HST supplied from the timing generator 11, which indicates the start timing of one line, and shifts 32 bits of data in synchronization with the clock signal HCK. By shifting the data in 32-bit increments, the horizontal shift register 141 shifts the data for one line in the subframe memory 15.

[0025] The first latch circuit 142 is supplied with a first latch pulse LT1 from the timing generator 11 when the horizontal shift register 141 has completed shifting one line of data. The first latch circuit 142 latches one line of data from the horizontal shift register 141 according to the input first latch pulse LT1 and supplies it to the first switch circuit 143. Once the data transfer from the horizontal shift register 141 to the first latch circuit 142 is complete, the horizontal shift register 141 is supplied with a start pulse HST from the timing generator 11. This causes the horizontal shift register 141 to resume shifting 32 bits of data from the data latch circuit 12 based on the base clock CLK.

[0026] When the first switch signal SW1 supplied to the first switch circuit 143 is high (H) and the second switch signal SW2 supplied to the second switch circuit 241 is low (L), the subframe memory 15 enters write mode. When the subframe memory 15 is in write mode, one line of data supplied to the first switch circuit 143 is transferred to the subframe memory 15 and written to one line of SRAM 151.

[0027] The first vertical shift register 131 selects the topmost line, row scan line G1, by a start pulse VST1 indicating the start timing for writing subframe data to the subframe memory 15, and then shifts the selected row scan lines sequentially by a shift pulse VSH1. As a result, the first vertical shift register 131 supplies row scan signals to row scan lines G1 to Gm sequentially, one line at a time, from the topmost line, row scan line G1, to the lowest line, row scan line Gm. Therefore, row scan lines G1 to Gm in the subframe memory 15 are selected sequentially from row scan line G1 to row scan line Gm for each line of each subframe. Consequently, the data for each line of each subframe is sequentially written to the corresponding line's SRAM 151 in the subframe memory 15.

[0028] When the first switch signal SW1 supplied to the first switch circuit 143 is low (L) and the second switch signal SW2 supplied to the second switch circuit 241 is high (H), the subframe memory 15 enters read mode.

[0029] The first vertical shift register 131 selects the topmost line, row scan line G1, by a start pulse VST1 indicating the start timing for reading subframe data from the subframe memory 15, and shifts the selected row scan lines G sequentially by a shift pulse VSH1. As a result, the first vertical shift register 131 supplies row scan signals to row scan lines G1 to Gm sequentially, one line at a time, from the topmost line, row scan line G1, to the lowest line, row scan line Gm. Therefore, row scan lines G1 to Gm in the subframe memory 15 are selected sequentially from row scan line G1 to row scan line Gm for each line of each subframe. Consequently, the subframe data written to the subframe memory 15 is read sequentially line by line and transferred to the second latch circuit 242 via the second switch circuit 241.

[0030] Furthermore, the pulse intervals of the multiple pulses in the shift pulse VSH1 used to sequentially shift the row scan lines G differ when writing subframe data to the subframe memory 15 and when reading subframe data from the subframe memory 15. As described above, the horizontal shift register 141 shifts the data for one line in the subframe memory 15 by shifting the data horizontally in 32-bit increments, so the time required for the first horizontal driver 14 to transfer the data for each line to the subframe memory 15 is relatively long. On the other hand, the time required to read the data for each line of the subframe data written to the subframe memory 15 and transfer it to the second horizontal driver 24 is relatively short.

[0031] Therefore, when writing subframe data to the subframe memory 15, the pulse interval between multiple pulses in the shift pulse VSH1 is long, while when reading subframe data from the subframe memory 15, the pulse interval between multiple pulses in the shift pulse VSH1 is short.

[0032] The second latch circuit 242 latches one line of data read from the subframe memory 15 according to the second latch pulse LT2 and transfers it to the level shifter 243. When the latch clear pulse LT2_CLR is input to the second latch circuit 242, the second latch circuit 242 is cleared. The reason for clearing the second latch circuit 242 will be explained later.

[0033] The level shifter 243 shifts the signal level of one line of input data up to the operating voltage of the subsequent voltage selection circuit 244. The level shifter 243 supplies the level-shifted data of one line to the voltage selection circuit 244. Note that if the signal level of the subframe data output from the second latch circuit 242 is equal to or greater than the operating voltage of the voltage selection circuit 244, the level shifter 243 does not need to be provided. Therefore, providing the level shifter 243 is not mandatory and should be done as needed.

[0034] The voltage control circuit 17 generates voltage V0 (first voltage) and voltage V1 (second voltage) based on the threshold voltage Vtt and saturation voltage Vsat supplied from the subframe data conversion device 10 and the polarity inversion signal POL supplied from the timing generator 11, and supplies them to the voltage selection circuit 244. As will be described later, the voltages V0 and V1 have different values ​​depending on whether the polarity inversion signal POL is L or H. The voltage control circuit 17 also generates a common electrode voltage Vcom, which will be described later, and supplies it to the common electrode 252.

[0035] The voltage selection circuit 244 outputs n subframe voltage data corresponding to n pixels in one line in parallel to n column data lines d1 to dn, based on n subframe data that have been level-shifted by the level shifter 243. If the subframe data is 0, the voltage selection circuit 244 outputs voltage V0 as subframe voltage data to column data line d, and if the subframe data is 1, it outputs voltage V1 as subframe voltage data to column data line d.

[0036] Since the second horizontal driver 24 performs each of the above operations for each line, the voltage selection circuit 244 simultaneously outputs n subframe voltage data points in parallel to the column data lines d1 to dn for each line. The n subframe voltage data points for one line supplied to the column data lines d1 to dn are written to the n pixels 251 of the row selected by the row scanning signal supplied from the second vertical driver 23. The operation of the second vertical driver 23 in more detail will be described later.

[0037] Figure 7 illustrates the specific circuit configuration of pixel 251. Pixel 251 includes a liquid crystal layer 254 sealed between a common electrode 252 and a pixel electrode 253. The common electrode 252 is a transparent electrode made of indium tin oxide (ITO). When the image display unit 25 is a reflective liquid crystal display element, the pixel electrode 253 is a reflective electrode provided for each pixel 251. Light from a light source (not shown) passes through the common electrode 252 and enters the liquid crystal layer 254, where it is modulated. The pixel electrode 253 reflects the light modulated by the liquid crystal layer 254. The light reflected by the pixel electrode 253 passes through the liquid crystal layer 254 and the common electrode 252 and is emitted from the common electrode 252.

[0038] A pixel circuit 256 formed on a silicon substrate 255 is connected to the pixel electrode 253. The pixel circuit 256 includes a DRAM that includes a switch 257 and a signal holding unit 258 connected to the switch 257. The signal holding unit 258 is grounded. The switch 257 can be made up of a field-effect transistor (FET). The signal holding unit 258 can be made up of a capacitor that functions as a holding capacitance. The gate of the switch 257 is connected to the row scan line g, the source is connected to the column data line d, and the drain is connected to the signal holding unit 258.

[0039] Each pixel circuit 256 of each pixel 251 does not have SRAM, but only a single DRAM, which allows for a smaller circuit size for the pixel circuit 256. If the pixel circuit 256 were to have SRAM, the SRAM would need to operate at a voltage boosted to, for example, 3.3V by the level shifter 243, thus increasing the circuit size. The liquid crystal display device 100 has a subframe memory 15 with (n × m) SRAMs 151 outside the image display unit 25. Since the SRAMs 151 only need to operate at a voltage of about 1.2V, the circuit size does not increase significantly. The memory provided by the pixel circuit 256 is not limited to DRAM; it only needs to have a single second memory. The pixel circuit 256 does not have any memory other than the second memory.

[0040] Figure 8 shows the relationship between the liquid crystal voltage applied to the liquid crystal layer 254 and the displayed grayscale. If the voltage applied to the liquid crystal layer 254 is the threshold voltage Vtt, black is displayed on the image display unit 25, and if the voltage applied to the liquid crystal layer 254 is the saturation voltage Vsat, white is displayed on the image display unit 25.

[0041] Using Figure 9, we will explain how the voltages V0 and V1 supplied to the voltage selection circuit 244 and the common electrode voltage Vcom supplied to the common electrode 252 are determined. When the polarity inversion signal POL is L, voltages V0 and V1 become positive mode voltages, with voltage V0 being the ground voltage GND (i.e., voltage 0) and voltage V1 being the voltage (Vsat-Vtt). As a result, positive mode subframe voltage data is written to the signal holding unit 258. When the polarity inversion signal POL is L, the common electrode voltage Vcom becomes the positive mode voltage (-Vtt).

[0042] When the subframe voltage data is 0, the liquid crystal layer 254 is subjected to a voltage of (GND - (-Vtt)) = voltage Vtt, calculated as voltage V0 - common electrode voltage Vcom. When the subframe voltage data is 1, the liquid crystal layer 254 is subjected to a voltage of ((Vsat - Vtt) - (-Vtt)) = voltage Vsat, calculated as voltage V1 - common electrode voltage Vcom.

[0043] When the polarity inversion signal POL is high, voltages V0 and V1 become negative mode voltages, with voltage V0 being the ground voltage (Vsat-Vtt) and voltage V1 being GND (i.e., voltage 0). As a result, negative mode subframe voltage data is written to the signal holding unit 258. When the polarity inversion signal POL is high, the common electrode voltage Vcom becomes the negative mode voltage (Vsat).

[0044] When the subframe voltage data is 0, the liquid crystal layer 254 is subjected to a voltage of ((Vsat-Vtt)-Vsat) = (-Vtt) from the voltage V0 minus the common electrode voltage Vcom. When the subframe voltage data is 1, the liquid crystal layer 254 is subjected to a voltage of (GND-Vsat) = (-Vsat) from the voltage V1 minus the common electrode voltage Vcom.

[0045] When the polarity inversion signal POL is low, the voltage control circuit 17 supplies the voltage selection circuit 244 with a set of voltages: voltage V0 as the positive mode voltage 0 and voltage V1 as the difference voltage between the positive mode saturation voltage Vsat and the threshold voltage Vtt. When the polarity inversion signal POL is high, the voltage control circuit 17 supplies the voltage selection circuit 244 with a set of voltages: voltage V0 as the difference voltage between the negative mode saturation voltage Vsat and the threshold voltage Vtt, and voltage V1 as the negative mode voltage 0. The voltage control circuit 17 switches between the set of voltages V0 and V1 when the polarity inversion signal POL is low and the set of voltages V0 and V1 when the polarity inversion signal POL is high, supplying them to the voltage selection circuit 244 every subframe.

[0046] When the polarity reversal signal POL is high, the voltage control circuit 17 supplies the saturation voltage Vsat of the negative mode to the common electrode 252 as the common electrode voltage Vcom. When the polarity reversal signal POL is low, the voltage control circuit 17 supplies the voltage obtained by reversing the polarity of the threshold voltage Vtt of the positive mode to the common electrode 252 as the common electrode voltage Vcom. The voltage control circuit 17 switches between supplying the saturation voltage Vsat of the negative mode when the polarity reversal signal POL is high and the voltage obtained by reversing the polarity of the threshold voltage Vtt of the positive mode when the polarity reversal signal POL is low to the common electrode 252 every subframe.

[0047] The operation of the liquid crystal display device 100 will be further explained using the timing chart shown in Figure 10. In Figure 10, (a) shows the subframe data written to the subframe memory 15 (SARAM 151). Here, the subframe data of consecutive subframes SF0 to SF3 is shown. The upper end of subframes SF0 to SF3 is the highest line, and the lower end is the lowest line. The reason why the highest and lowest lines are offset in the time direction is that data transfer takes time. The difference between the start timing of the highest line and the start timing of the lowest line is the data transfer period to the subframe memory 15.

[0048] In Figure 10, (b) shows the trigger pulse TRIG supplied from the subframe data converter 10 to the timing generator 11. The trigger pulse TRIG is output from the subframe data converter 10 at the subframe time interval. (c) shows the polarity inversion signal POL, in which L and H are reversed at the subframe time interval. The timing at which the polarity inversion signal POL reverses polarity is determined by the trigger pulse TRIG.

[0049] The voltage control circuit 17 generates two types of voltages V0 and V1 synchronized with the polarity inversion signal POL, based on a threshold voltage Vtt for displaying black and a saturation voltage Vsat for displaying white. In Figure 10, (d) shows voltage V0 and (e) shows voltage V1. Voltage V0 is the voltage applied to the pixel electrode 253 for displaying black. Voltage V1 is the voltage applied to the pixel electrode 253 for displaying white.

[0050] In the period from time t0 to time t1 shown in Figure 10, the polarity reversal signal POL is H, in negative mode, so voltage V0 is voltage (Vsat-Vtt) and voltage V1 is voltage GND. In the period from time t1 to time t2, the polarity reversal signal POL is L, in positive mode, so voltage V0 is voltage GND and voltage V1 is voltage (Vsat-Vtt). Voltage V0 reverses in sync with the reversal of the polarity reversal signal POL. Voltage V1, inverted from voltage V0, reverses in sync with the reversal of the polarity reversal signal POL.

[0051] In positive electrode mode, a voltage is applied to the liquid crystal layer 254 such that the pixel electrode 253 is at a positive potential compared to the potential of the common electrode 252. In negative electrode mode, a voltage is applied to the liquid crystal layer 254 such that the pixel electrode 253 is at a negative potential compared to the potential of the common electrode 252.

[0052] In Figure 10, (f) shows the common electrode voltage Vcom. In Figure 10(f), during the period from time t0 to time t1, the polarity reversal signal POL is H, and the common electrode voltage Vcom is in negative mode, so the common electrode voltage Vcom is voltage Vsat. During the period from time t1 to time t2, the polarity reversal signal POL is L, and the common electrode voltage Vcom is in positive mode, so the common electrode voltage Vcom is voltage (-Vtt). Similarly, during the periods from time t2 to time t3, from time t3 to time t4, and from time t4 to time t5, the common electrode voltage Vcom is voltage Vsat, (-Vtt), and Vsat, respectively.

[0053] In Figure 10, (g) shows the subframe voltage data written to the pixel circuit 256. The subframe data of subframe SF0 written to the subframe memory 15 during the period from time t0 to time t1 is written to the pixel circuit 256 as positive mode subframe voltage data (SF0+) during the period from time t1 to time t2. The subframe data of subframe SF1 written to the subframe memory 15 during the period from time t1 to time t2 is written to the pixel circuit 256 as negative mode subframe voltage data (SF1-) during the period from time t2 to time t3.

[0054] Similarly, during the period from time t3 to time t4, positive mode subframe voltage data (SF2+) is written to the pixel circuit 256, and during the period from time t4 to time t5, negative mode subframe voltage data (SF3-) is written to the pixel circuit 256.

[0055] In Figure 10, (h) represents the voltage state applied to the liquid crystal layer 254. In Figure 10 (h), during the period from time t1 to time t2, the pixel electrode 253 is subjected to positive mode subframe voltage data, and the common electrode voltage Vcom is subjected to positive mode voltage (-Vtt). Therefore, when the subframe voltage data is 0, the voltage Vtt is applied to the liquid crystal layer 254, and when the subframe voltage data is 1, the voltage Vsat is applied.

[0056] During the period from time t2 to time t3, the pixel electrode 253 is subjected to subframe voltage data in negative mode, and the common electrode voltage Vcom is subjected to the voltage Vsat in negative mode. Therefore, when the subframe voltage data is 0, the liquid crystal layer 254 is subjected to a voltage (-Vtt), and when the subframe voltage data is 1, it is subjected to a voltage (-Vsat).

[0057] Similarly, during the period from time t3 to time t4, the liquid crystal layer 254 is subjected to a voltage Vtt when the subframe voltage data is 0, and a voltage Vsat when the subframe voltage data is 1. During the period from time t4 to time t5, the liquid crystal layer 254 is subjected to a voltage (-Vtt) when the subframe voltage data is 0, and a voltage (-Vsat) when the subframe voltage data is 1.

[0058] By the way, since subframe voltage data for each line is written to the image display unit 25, it takes a predetermined amount of time for the subframe voltage data for the entire subframe to be written to all pixels 251 of the image display unit 25. On the other hand, the positive and negative modes of the image display unit 25 switch at a certain timing for each subframe. Therefore, at the timing when the subframe voltage data of the subframe written to the image display unit 25 switches, the correct voltage shown in Figure 10(h) is not applied, and there is a period of time when the image is not displayed correctly.

[0059] The operation of the liquid crystal display device 100 to prevent a period of time during which the image is not displayed correctly when switching between the positive and negative modes will be further explained using the timing chart shown in Figure 11. In Figure 11, (a) shows the subframe data written to the subframe memory 15 (SARAM 151). Here again, the subframe data for consecutive subframes SF0 to SF3 is shown. (b) shows the vertical synchronization signal SFVS for the subframe data, and (c) shows the subframe end pulse SFEND. (d) shows the trigger pulse TRIG. The trigger pulse TRIG is located midway between the vertical synchronization signal SFVS, which is the beginning of each subframe, and the subframe end pulse SFEND, which is the end of the subframe immediately preceding each subframe.

[0060] In Figure 11, (e) shows the first switch signal SW1 supplied to the first switch circuit 143, and (h) shows the second switch signal SW2 supplied to the second switch circuit 241. The first switch signal SW1 switches from H to L with the trigger pulse TRIG and from L to H with the vertical synchronization signal SFVS. The second switch signal SW2 switches from L to H with the trigger pulse TRIG and from H to L with the vertical synchronization signal SFVS. When the first switch signal SW1 is H and the second switch signal SW2 is L at time t0a, the subframe memory 15 enters write mode.

[0061] As shown in Figure 11(f), the timing generator 11 generates a start pulse VST1 at the timing of the trigger pulse TRIG (times t0, t1, ...) to indicate the start timing for reading subframe data from the subframe memory 15. The timing generator 11 also generates a start pulse VST1 at the timing of the vertical synchronization signal SFVS (times t0a, t1a, ...) to indicate the start timing for writing subframe data to the subframe memory 15. The subframe memory 15, which is in write mode, starts writing subframe data in response to the start pulse VST1 at time t0a.

[0062] Figure 11(g) shows a pulse that switches between H and L generated inside the timing generator 11, and represents the pulse interval switching pulse VSH1_PI, which indicates the timing for lengthening and shortening the pulse interval of multiple pulses in the shift pulse VSH1. The timing generator 11 generates a shift pulse VSH1 with a shorter pulse interval for multiple pulses during the period when the pulse interval switching pulse VSH1_PI is H from time t0 to time t0a and from time t1 to time t1a. The same applies to subsequent periods when the pulse interval switching pulse VSH1_PI is H.

[0063] The timing generator 11 generates a shift pulse VSH1 with a long pulse interval for multiple pulses during the period when the pulse interval switching pulse VSH1_PI is L, from time t0a to time t1 and from time t1a to time t2. The same applies to subsequent periods when the pulse interval switching pulse VSH1_PI is L.

[0064] The subframe memory 15 starts writing subframe data in response to the start pulse VST1 at time t0a, and writes the subframe data by sequentially shifting the lines of the SRAM 151 to which the data for each line is written using the shift pulse VSH1. The subframe memory 15 writes all subframe data during the period from time t0a to time t0b.

[0065] As shown in Figure 11(i), at time t0b, the timing generator 11 supplies a latch clear pulse LT2_CLR to the second latch circuit 242. As shown in Figure 11(j), at time t0b, the timing generator 11 supplies a start pulse VST2 to the second vertical shift register 231, indicating the start timing for writing the black voltage to the pixels 251 of each line of the image display unit 25. Since the second latch circuit 242 is cleared, the output of the voltage selection circuit 244 becomes the black voltage V0, and the voltage V0 is sequentially written to the pixel circuits 256 (DRAM) of each line of the image display unit 25. The voltage V0 is written to the image display unit 25 line by line during the period from time t0b to time t1.

[0066] At this time, the image display unit 25 can write the voltage V0 as subframe voltage data for one line to the pixel circuit 256 every clock cycle, so it can write the black voltage to all lines of the pixel circuit 256 at high speed.

[0067] As shown in Figure 11(m), when the polarity reversal signal POL shown in Figure 11(d) becomes L at time t1, the voltage control circuit 17 sets voltages V0 and V1 to positive mode voltages, and the common electrode voltage Vcom to positive mode voltage. As shown in Figure 11(i), the timing generator 11 also supplies a latch clear pulse LT2_CLR to the second latch circuit 242 at time t1. As shown in Figure 11(k), the timing generator 11 supplies an inversion pulse INV to the inverter 232 at time t1. The timing generator 11 generates the latch clear pulse LT2_CLR and the inversion pulse INV in response to the trigger pulse TRIG that occurs at time t1, so strictly speaking, the latch clear pulse LT2_CLR and the inversion pulse INV occur immediately after time t1.

[0068] When the second latch circuit 242 is cleared and an inverting pulse INV is input to the inverter 232, all outputs of the inverter 232 become high, and all row scan lines g1 to gm are selected. Therefore, at time t1 (more precisely, immediately after time t1), the voltage V0, which is the voltage for black, is written to all pixel circuits 256 of the image display unit 25 all at once.

[0069] Furthermore, the timing generator 11 does not need to supply the latch clear pulse LT2_CLR to the second latch circuit 242 at times t1, t2, ... which are the timings for writing the voltage V0 to all pixel circuits 256 of the image display unit 25 at once. The timing generator 11 may simply supply the latch clear pulse LT2_CLR to the second latch circuit 242 only at time t0b, which is the start timing for writing the black voltage to each line, and at similar timings thereafter.

[0070] During the period from time t1 to time t1a, the first switch signal SW1 is low and the second switch signal SW2 is high. Therefore, the subframe memory 15 enters read mode, and the subframe data read from the subframe memory 15 is supplied to the second horizontal driver 24. Subframe voltage data is written to the image display unit 25 line by line.

[0071] As described above, the liquid crystal display device 100 clears the second latch circuit 242 at the timing of the end of the subframe data for each subframe written to the subframe memory 15. The liquid crystal display device 100 is configured to sequentially write black voltages to the pixel circuits 256 corresponding to each line of the image display unit 25 during the period from the first time (time t0b in Figure 11) when the second time (time t1 in Figure 11) when the positive and negative modes are switched for the next subframe data. Furthermore, the liquid crystal display device 100 is configured to invert the output of the second vertical shift register 231 by the inverter 232 at the second time, and to write black voltages to the pixel circuits 256 corresponding to each line of the image display unit 25 all at once.

[0072] According to the liquid crystal display device 100, the timing of the switch between positive and negative polarity modes is avoided, so users viewing the image displayed on the image display unit 25 will not experience any discomfort.

[0073] The present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]

[0074] 10 Subframe data conversion device 11 Timing Generator 12. Data latch circuit 13. First Vertical Driver 14. First horizontal driver 15 Subframe Memory 17 Voltage control circuit 23 Second Vertical Driver 24 Second horizontal driver 25 Image display section 100 LCD display device 131 First Vertical Shift Register 231 Second vertical shift register 232 Inverter 241 Second Switch Circuit 242 Second latch circuit 243 Level Shifter 244 Voltage Selection Circuit 251 pixels 252 Common electrode 253 Pixel Electrodes 254 liquid crystal layers 255 silicon substrate 256-pixel circuit 257 switches 258 Signal holding section

Claims

1. A subframe memory is provided, in which a first memory is located at each intersection of multiple first column data lines and multiple first row scan lines, A first horizontal driver supplies subframe data, where each pixel data is 1 bit and generated by dividing each frame of the video signal, to the plurality of first column data lines one line at a time in parallel. A first vertical shift register selects the first row scan line corresponding to each line from among the plurality of first row scan lines in order to write and read the data of each line of the subframe data output from the first horizontal driver to the first memory of the subframe memory corresponding to each line, An image display unit is provided with a pixel circuit corresponding to a pixel containing a liquid crystal layer at each intersection of a plurality of second column data lines, the same number as the first column data lines, and a plurality of second row scan lines, the same number as the first row scan lines. A second horizontal driver that supplies subframe voltage data corresponding to the subframe data of each line read from the subframe memory to the plurality of second column data lines one line at a time in parallel, In order to write the subframe voltage data corresponding to each line output from the second horizontal driver to the pixels of each line in the image display unit, a second vertical shift register selects the second row scan line corresponding to each line from among the plurality of second row scan lines, Equipped with, The pixel circuit has a single second memory that holds the subframe voltage data of each pixel. LCD display device.

2. The liquid crystal display device according to claim 1, wherein the pixel circuit has a dynamic random access memory as the second memory and does not have any memory other than the second memory.

3. The second horizontal driver described above is A latch circuit that latches the subframe data of each line read from the subframe memory, A voltage selection circuit that selects a first voltage and a second voltage as subframe voltage data according to the value of one bit of the subframe data and outputs them to the plurality of second column data lines, thereby writing the first voltage or the second voltage to the second memory, It has, An inverter for inverting the output of the second vertical shift register, A voltage control circuit supplies the voltage selection circuit with the first and second voltage sets for positive mode and the first and second voltage sets for negative mode, switching between them for each subframe, as the subframe voltage data. Furthermore, The latch circuit is cleared at the timing of the end of the subframe data of each subframe written to the subframe memory, and during the period from the first time when the latch circuit is cleared to the second time when the positive mode and the negative mode are switched for the next subframe data, a black voltage is sequentially written to the pixel circuit corresponding to each line of the image display unit. At the second time, the inverter inverts the output of the second vertical shift register, and the black voltage is written all at once to the pixel circuits corresponding to each line of the image display unit. The liquid crystal display device according to claim 1 or 2.

4. The video signal is divided into frames, and subframe data is constructed where each pixel data is 1 bit. The subframe data is written to a subframe memory having a plurality of first memories. The subframe voltage data corresponding to each pixel of the subframe data read from the subframe memory is written to a pixel circuit in the image display unit, which has a single second memory provided for each pixel including the liquid crystal layer. A method for driving a liquid crystal display device.

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