Optical scanning apparatus and image forming apparatus

Abstract

Compared to a system without a waste current control means for controlling the waste current generated by the waste current generation means, this system suppresses fluctuations in light intensity caused by fluctuations in the drive voltage. [Solution] The scanning means comprises a plurality of groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned and arranged along the main scanning direction, and scanning by causing each of the light-emitting elements to emit light based on image information; a driving means for driving each of the light-emitting elements of the scanning means for each scanning period; and a waste current generation means that generates a waste current from the driving means to supply power to elements other than each of the light-emitting elements during non-scanning periods set between the scanning periods, and is capable of controlling the waste current.

Description

Technical Field

[0001] This invention relates to an optical scanning device and an image forming apparatus.

Background Art

[0002] Conventionally, as technologies related to optical scanning devices, for example, those disclosed in Patent Documents 1 to 4 and the like have already been proposed.

[0003] Patent Document 1 is configured to have power consumption means that is executed during a non-writing period that occurs between scans repeatedly performed in a light emitting element group, and consumes power corresponding to the light emission power consumption of the light emitting element group.

[0004] Patent Document 2 is configured to include correction means for correcting the light amount of a light emitting element targeted for light emission among a plurality of light emitting elements according to correction information stored in storage means when usage conditions corresponding to different usage conditions are satisfied.

[0005] Patent Document 3 is configured to have setting means for setting the operation time of transfer signal generation means so that a transfer signal is transmitted to a self-scanning type LED chip for a predetermined time and the temperature of an image recording head falls within a predetermined range.

[0006] Patent Document 4 includes a plurality of light emitting element array members in which a plurality of light emitting elements are arranged in a row, and drive means for sequentially lighting each of the plurality of light emitting elements arranged in each of the plurality of light emitting element array members at a predetermined transfer period in the arrangement direction. The drive means is configured such that the transfer period when transferring a signal can be changed.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

[0008] The objective of this invention is to suppress fluctuations in light intensity caused by fluctuations in the driving voltage, compared to a case where there is no waste current generation means for generating and controlling waste current. [Means for solving the problem]

[0009] The invention described in claim 1 comprises a scanning means for scanning by arranging multiple groups of light-emitting elements, each of which is arranged along the main scanning direction, facing the object to be scanned along the main scanning direction, and causing each of the light-emitting elements to emit light based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, During the non-scanning period set within the scanning period, the drive means generates a waste current to supply current to all light-emitting elements except those in the respective light-emitting element groups, and the waste current generation means is capable of controlling the waste current. It is an optical scanning device equipped with [a specific feature].

[0010] The invention described in claim 2 is an optical scanning device according to claim 1, wherein the waste current generation means has a switching unit that switches whether or not the waste current is generated.

[0011] The invention described in claim 3 is an optical scanning apparatus according to claim 2, wherein the switching unit switches whether or not to generate the waste current over the scanning period located before and after the non-scanning period.

[0012] The invention described in claim 4 is an optical scanning apparatus according to claim 3, wherein the switching unit changes the timing of switching whether or not to generate the discard current in accordance with the image information in the scanning period immediately preceding the non-scanning period.

[0013] The invention described in claim 5 is an optical scanning device according to claim 4, wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

[0014] The invention described in claim 6 is an optical scanning device according to claim 5, wherein the switching unit calculates the time for energizing the discarded current by multiplying the basic ON time of the discarded current by a required coefficient.

[0015] The invention described in claim 7 is an optical scanning device according to claim 1, wherein the waste current generation means has a setting unit for setting the value of the waste current.

[0016] The invention described in claim 8 is an optical scanning apparatus according to claim 7, wherein the setting unit sets the value of the discarded current according to the image information in the scanning period immediately preceding the non-scanning period.

[0017] The invention described in claim 9 is an optical scanning device according to claim 8, wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

[0018] The invention described in claim 10 is an optical scanning device according to claim 9, wherein the setting unit changes the value of the discard current according to at least one integrated value of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

[0019] The invention described in claim 11 comprises an image holder and An exposure means for exposing the image holder based on image information, Equipped with, The image forming apparatus uses the optical scanning apparatus described in any one of claims 1 to 10 as the exposure means. [Effects of the Invention]

[0020] According to the invention described in claim 1, compared with the case where there is no waste current generation means for generating and controlling the waste current, it is possible to suppress fluctuations in the amount of light caused by fluctuations in the drive voltage.

[0021] According to the invention described in claim 2, the waste current generation means can cope with a delay in the timing when the waste current is energized, compared with the case where it does not provided with a switching unit for switching the presence or absence of waste current generation.

[0022] According to the invention described in claim 3, the switching unit can energize the required waste current over the entire non-scanning period, compared with the case where the switching unit does not switch the presence or absence of waste current generation over the scanning periods located before and after the non-scanning period.

[0023] According to the invention described in claim 4, the switching unit can further reduce the influence of fluctuations in the power supply voltage, compared with the case where the switching unit does not change the timing for switching the presence or absence of waste current generation according to the image information in the scanning period immediately after the non-scanning period.

[0024] According to the invention described in claim 5, the image information can further reduce the influence of fluctuations in the power supply voltage caused by the image information, compared with the case where the image information does not include the amount of light and the luminous efficiency in the light-emitting elements of each light-emitting element group.

[0025] According to the invention described in claim 6, the switching unit can further reduce the influence of fluctuations in the power supply voltage caused by the image information, compared with the case where the timing for switching the presence or absence of waste current generation is fixed.

[0026] According to the invention described in claim 7, the waste current generation means can surely reduce fluctuations in the power supply voltage, compared with the case where the value of the waste current is fixed.

[0027] According to the invention described in claim 8, the setting unit can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the value of the discarded current is kept constant regardless of the image information in the scanning period immediately preceding the non-scanning period.

[0028] According to the invention described in claim 9, the image information can further reduce the influence of power supply voltage fluctuations caused by the image information compared to the case where the light intensity and luminescence of the light-emitting elements of each light-emitting element group are not included.

[0029] According to the invention described in claim 10, the setting unit can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the value of the discard current is kept constant regardless of the light intensity or luminescence of the light-emitting elements in each group of light-emitting elements. According to the invention described in claim 11, compared to a case where there is no waste current generation means that generates and controls waste current, fluctuations in light intensity caused by fluctuations in the drive voltage are suppressed. [Brief explanation of the drawing]

[0030] [Figure 1] This is an overall configuration diagram showing an image forming apparatus to which an example of an optical scanning apparatus according to Embodiment 1 of this invention is applied. [Figure 2] This is a cross-sectional view showing an LED print head as an example of an optical scanning device according to Embodiment 1 of this invention. [Figure 3] This is a diagram showing an LED circuit board according to Embodiment 1 of the present invention. [Figure 4] This is a diagram showing the arrangement of LEDs in an SLED chip. [Figure 5] This is an explanatory diagram showing the scanning exposure state of the photosensitive drum by an LED print head. [Figure 6] This is an equivalent circuit diagram showing an SLED chip. [Figure 7] This is a circuit diagram showing a transfer thyristor. [Figure 8] This is a timing chart showing the operating status of the SLED chip. [Figure 9] This is a timing chart showing the operating status of the SLED chip. [Figure 10] This is a block diagram of a signal generation circuit. [Figure 11] This is a wiring diagram showing the connection of the SLED chip to the signal generation circuit. [Figure 12] This graph shows the control of exposure levels in an SLED chip. [Figure 13] This is an explanatory diagram illustrating image defects in conventional LED print heads. [Figure 14] This is a schematic diagram illustrating an example of an image defect. [Figure 15] This is a block diagram showing the essential parts of a signal generation circuit. [Figure 16] This is a timing chart showing the waste current. [Figure 17] This is a circuit diagram showing a waste current control circuit. [Figure 18] This is a diagram showing the parameters for controlling the waste current. [Figure 19] This graph shows the results of an experimental example. [Modes for carrying out the invention]

[0031] Embodiments of this invention will be described below with reference to the drawings.

[0032] [Embodiment 1] Figure 1 is a schematic diagram showing the overall configuration of an image forming apparatus to which the optical scanning device according to Embodiment 1 of this invention is applied. In the figure, the reference numeral X indicates the horizontal direction of the image forming apparatus, Y indicates the depth direction of the image forming apparatus, and Z indicates the vertical direction of the image forming apparatus.

[0033] <Overall configuration of the image forming apparatus> The image forming apparatus 1 according to Embodiment 1 is configured, for example, as a so-called tandem-type color printer. As shown in Figure 1, this image forming apparatus 1 is broadly composed of an image processing unit 2, an image forming unit 3, and a control unit 4. The image forming apparatus 1 is connected to, for example, an external device such as an image reader 5 or a personal computer (PC) 6. The image forming apparatus 1 may also have the image reader 5 integrated into the top of the main body of the apparatus. The image processing unit 2 performs predetermined image processing on image data (image information) input from the image reader 5 or personal computer (PC) 6. The image forming unit 3 performs image formation corresponding to the image data of each color that has been processed by the image processing unit 2. The control unit 4 acquires various information indicating the operating status of the image forming apparatus 1 and comprehensively controls the operation of the image forming apparatus 1.

[0034] The image forming unit 3 comprises a plurality of image forming units 10, an intermediate transfer device 20, a paper transport device 50, a fixing device 40, etc. The plurality of image forming units 10 form toner images that are developed with toner constituting the developer. The intermediate transfer device 20 holds the toner images formed by each image forming unit 10 and transports them to a secondary transfer position where they are ultimately transferred to recording paper 7, which is an example of a recording medium. The paper transport device 50 transports the required amount of recording paper 7 to be transported to the secondary transfer position of the intermediate transfer device 20. The recording paper 7 is supplied from a paper feed device (not shown). The fixing device 40 fixes the toner images on the recording paper 7.

[0035] The image forming unit 10 consists of four image forming units 10Y, 10M, 10C, and 10K, each dedicated to forming toner images of four colors: yellow (Y), magenta (M), cyan (C), and black (K). These four image forming units 10 (Y, M, C, K) are arranged along the horizontal direction X in the internal space of the image forming apparatus 1.

[0036] Each image forming unit 10 (Y, M, C, K) includes a photoreceptor drum 11 as an example of an image holder, a charging device 12, an exposure device 13 as an example of an exposure means, a developing device 14, a primary transfer device 15, a drum cleaning device 16, etc. The charging device 12 charges the image-forming surface (image-holding surface) of the photoreceptor drum 11 to the required potential. The exposure device 13 irradiates the charged surface of the photoreceptor drum 11 with light based on image data to form electrostatic latent images for each color with potential differences. The developing device 14 develops the electrostatic latent images with toners of the corresponding color (Y, M, C, K) to form toner images. The primary transfer device 15 transfers each toner image to the intermediate transfer device 20 at the primary transfer position. The drum cleaning device 16 cleans the image-holding surface of the photoreceptor drum 11 by removing any toner or other deposits that remain after the primary transfer.

[0037] As shown in Figure 1, the intermediate transfer device 20 is positioned below each image forming unit 10 (Y, M, C, K) along the vertical Z direction. This intermediate transfer device 20 mainly consists of an intermediate transfer belt 21, a plurality of belt support rolls 22-24, a secondary transfer device 30, and a belt cleaning device (not shown).

[0038] The paper transport device 50 transports the recording paper 7 supplied from a paper feeder (not shown) to the secondary transfer position. The paper transport device 50 also transports the recording paper 7, on which the toner images of each color have been transferred at the secondary transfer position, to the fuser device 40. In the illustrated example, the paper transport device 50 is shown as a belt-type device equipped with a paper transport belt 51, but the paper transport device 50 may also be equipped with multiple pairs of paper transport rolls or the like.

[0039] The fixing device 40 is composed of a heating rotating body 41 and a pressurizing rotating body 42, among other components. In the fixing device 40, the contact area where the heating rotating body 41 and the pressurizing rotating body 42 come into contact becomes the fixing processing unit where the required fixing process (heating and pressurizing) is performed.

[0040] <Operation of the image forming apparatus> The following describes the basic image forming operation of the image forming apparatus 1.

[0041] This section describes the operation in full-color mode, in which a full-color image is formed by combining four toner images (Y, M, C, K) using the four image forming units 10 (Y, M, C, K).

[0042] The image forming apparatus 1 receives image data and command information requesting full-color image forming operations (printing) from the image reading device 5, personal computer 6, etc. Then, the control unit 4 starts the four image forming units 10 (Y, M, C, K), intermediate transfer device 20, secondary transfer device 30, fixing device 40, etc.

[0043] In each image forming unit 10 (Y, M, C, K), as shown in Figure 1, first each photoreceptor drum 11 rotates in the direction indicated by the arrow. Then, each charging device 12 charges the surface of each photoreceptor drum 11 to the required polarity and potential. Subsequently, the exposure device 13 irradiates the charged surface of the photoreceptor drum 11 with light emitted based on image data obtained by converting it into each color component (Y, M, C, K). Then, electrostatic latent images of each color component, composed of the required potential difference, are formed on the surface of each photoreceptor drum 11.

[0044] Next, the developing device 14 for each image forming unit 10 (Y, M, C, K) performs development. Development is performed by supplying toner of the corresponding color (Y, M, C, K), charged with the required polarity, from the developing roll 141 to electrostatically adhere to the electrostatic latent images of each color component formed on the photoreceptor drum 11. Through this development, the electrostatic latent images of each color component formed on each photoreceptor drum 11 are revealed as four toner images of the corresponding colors (Y, M, C, K), which have been developed with the toner of their respective colors.

[0045] Next, the toner images of each color formed on the photoreceptor drum 11 of each image forming unit 10 (Y, M, C, K) are transported to the primary transfer position. Then, the primary transfer device 15 performs a primary transfer, sequentially overlapping the toner images of each color onto the intermediate transfer belt 21 of the intermediate transfer device 20, which rotates in the direction indicated by the arrow.

[0046] Furthermore, in each image forming unit 10 (Y, M, C, K) after the primary transfer is completed, the drum cleaning device 16 cleans the surface of the photoreceptor drum 11 by scraping off any attached material. This prepares each image forming unit 10 (Y, M, C, K) for the next image formation operation.

[0047] Next, the intermediate transfer device 20 holds the toner image transferred in the first stage by the rotation of the intermediate transfer belt 21 and transports it to the secondary transfer position. Meanwhile, the paper transport device 50 feeds and supplies the required recording paper 7 to the secondary transfer position in accordance with the image formation operation and the transfer timing.

[0048] At the secondary transfer position, the secondary transfer device 30 transfers the toner image on the intermediate transfer belt 21 onto the recording paper 7 in one go. After the secondary transfer is complete, the intermediate transfer device 20 uses a belt cleaning device (not shown) to remove any toner or other deposits remaining on the surface of the intermediate transfer belt 21 after the secondary transfer.

[0049] Next, the recording paper 7 on which the toner image has been secondarily transferred is transported to the fuser unit 40 by the paper transport belt 51. In the fuser unit 40, the necessary fixing process (heating and pressurizing) is performed by the heating rotating body 41 and the pressurizing rotating body 42 to fix the unfixed toner image to the recording paper 7. Finally, the recording paper 7 on which fixing is complete is discharged to a paper discharge unit (not shown).

[0050] Through the above operations, a recording sheet 7 is output, on which a full-color image composed of four toner images is formed.

[0051] <Configuration of the exposure system> As shown in Figure 2, the image forming apparatus 1 according to this embodiment 1 includes an exposure apparatus 13 as an example of an optical scanning apparatus.

[0052] The exposure apparatus 13 is positioned across an image forming area along the axial direction (perpendicular to the drawing) of the photoreceptor drum 11, which is an example of an object to be scanned, so as to face the photoreceptor drum 11. The exposure apparatus 13 consists of an LED print head 60, which is an example of a scanning means, in which a plurality of LEDs (Light Emitting Diodes) as light-emitting elements are arranged along the main scanning direction, which is the axial direction of the photoreceptor drum 11. The LED print head 60 scans and exposes the surface of the photoreceptor drum 11, which is charged to a required potential by the charging device 12 and rotated at a required rotational speed (peripheral speed), with light corresponding to the image information to form an electrostatic latent image.

[0053] The LED print head 60 comprises a housing 61 as a support, an LED circuit board 62, a rod lens array 64, etc. As shown in Figure 3, the LED circuit board 62 is equipped with an LED array 63 in which a plurality of LEDs are arranged along the main scanning direction, and a signal generation circuit 100 as an example of a driving means for driving the LED array 63.

[0054] The LED print head 60 uses a self-scanning light-emitting device (SLED) 65 as the LED array 63.

[0055] The rod lens array 64 is an optical component that projects light from the SLED 65 onto the surface of the photoreceptor drum 11. The housing 61 holds the rod lens array 64 and shields and protects the SLED 65 from the outside.

[0056] The housing 61 is formed from a metal such as aluminum or stainless steel, or a heat-resistant synthetic resin, and is a long, frame-like or block-like structure extending in a direction intersecting the drawing. An LED circuit board 62 is positioned on the end face of the housing 61 facing the photosensitive drum 11. The housing 61 holds the LED circuit board 62 and the rod lens array 64. In this configuration, the housing 61 aligns the light-emitting point of the SLED 65 provided on the LED circuit board 62 with the focal point of one end of the rod lens array 64 along the optical axis direction (vertical direction in the drawing).

[0057] The LED print head 60 configured in this way is movable along the optical axis direction of the rod lens array 64 by an adjustment screw (not shown). The LED print head 60 is set so that the imaging position (focal plane) of the other end of the rod lens array 64 along the optical axis direction is located on the surface of the photoreceptor drum 11.

[0058] As shown in Figure 3, the LED circuit board 62 has SLED chips 67-1 to 67-40 arranged in a straight line with precision parallel to the axis direction of the photoreceptor drum 11, as an example of a group of multiple (e.g., 40) light-emitting elements that make up the SLED 65. Each SLED chip 67-1 to 67-40 has LEDs arranged on it as an example of a group of multiple (e.g., 256) light-emitting elements. The SLED chips 67-1 to 67-40 are arranged alternately in a staggered pattern. In this case, as shown in Figure 4, the LEDs of each SLED chip 67-1 to 67-40 are arranged to be continuous at equal intervals at adjacent ends.

[0059] Furthermore, as shown in Figure 3, the LED circuit board 62 includes a signal generation circuit 100, a power supply circuit 101, an EEPROM 102 as an example of a storage means, and a harness 103 at one end along the longitudinal direction of the SLED chips 67-1 to 67-40. The signal generation circuit 100 generates a signal (lighting signal) to drive each of the SLED chips 67-1 to 67-40. The power supply circuit 101 consists of a constant voltage power supply such as a three-terminal regulator that outputs a predetermined voltage to each of the SLED chips 67-1 to 67-40. The EEPROM 102 stores the light intensity unevenness correction value for each of the SLED chips 67-1 to 67-40, and parameters for controlling the discard current as described later. The harness 103 transmits and receives various signals between the signal generation circuit 100 and the control unit 4 and the image processing unit 2.

[0060] As shown in Figures 5(a) and 5(b), when the LED print head 60 performs image exposure on the surface of the photoreceptor drum 11 based on image data, each SLED chip 67-1 to 67-40 is driven simultaneously for each line. When scanning exposure of one line is completed, each SLED chip 67-1 to 67-40 starts scanning exposure of the next line after a required pause period. In Figure 5(b), the dashed arrows indicate the state in which the scanning exposure position moves with the pause period in between.

[0061] In the illustrated example, as shown in Figure 5(b), the case where each SLED chip 67-1 to 67-40 scans in the same direction, that is, from the left end to the right end in the figure. However, it is not limited to this, and each SLED chip 67-1 to 67-40 may be configured so that adjacent SLED chips 67-1 to 67-40 scan in opposite directions, for example, the first SLED chip 67-1 scans from the left end to the right end in the figure, and the second SLED chip 67-2 scans from the right end to the left end in the figure.

[0062] <SLEDチップ> Figure 6 is an equivalent circuit diagram showing the circuit configuration of an SLED chip mounted on an LED print head according to this embodiment 1. As shown in Figure 6, the SLED chip 67 has multiple (four in the illustrated example) terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) on the substrate 68. In addition, a Vsub terminal is provided on the back surface of the substrate 68. Here, the first SLED chip 67-1 will be used as an example to explain its relationship with the signal generation circuit 100. The other SLED chips 67-2 to 67-40 are configured similarly to SLED chip 67-1.

[0063] As shown in Figure 6, the SLED chip 67-1 is broadly divided into a light-emitting section 201 and a transfer section 202. The light-emitting section 201 of the SLED chip 67-1 includes a plurality of light-emitting thyristors L1, L2, L3, ... as an example of a plurality of light-emitting elements arranged linearly on the substrate 68. The transfer section 202 of the SLED chip 67-1 includes a plurality of transfer thyristors T1, T2, T3, ... arranged linearly on the substrate 68 corresponding to the plurality of light-emitting thyristors L1, L2, L3, ...

[0064] Multiple light-emitting thyristors L1, L2, L3... and multiple transfer thyristors T1, T2, T3... are formed on a substrate 68 made of a Si substrate or the like as semiconductor elements, each having a second gate Gts on the anode side in addition to the usual first gates Glf and Gtf on the cathode side. Figure 7 is a circuit diagram in which the transfer thyristor T1 is replaced with a transistor. Note that the second gates Gls of the light-emitting thyristors L1, L2, L3... are not connected to other elements and are therefore not shown.

[0065] Multiple light-emitting thyristors L1, L2, L3... and multiple transfer thyristors T1, T2, T3... are connected to Vsub terminals, each with an anode wired to the back surface of the substrate 68, as shown in Figure 6. The Vsub terminals are connected to the power supply circuit 101 of the LED circuit board 62 via power line 200. In this embodiment 1, the power supply circuit 101 is set to "H" (3.3V). Therefore, the potential of the Vsub terminals is "H" (3.3V). From the power supply circuit 101, a lighting current flows to the Vsub terminal of the SLED chip 67-1 via power line 200. The ignition current for the multiple light-emitting thyristors L1, L2, L3, etc. flows from the Vsub terminal to the anode of each light-emitting thyristor L1, L2, L3, etc., and then flows from the cathode through each light-emitting thyristor L1, L2, L3, etc., through the ignition signal line 70 and the ignition time control / drive units 118-1 to 118-40 of the signal generation circuit 100 to the reference potential supply unit 69 which serves as a return power supply. Here, the potential of the Vsub terminal is assumed to be "H" (3.3V) and the potential of the Vga terminal is assumed to be "L" (0V). However, in order to explain the operation of the SLED chip 67-1, the potential of the Vsub terminal may be assumed to be "H" (0V) and the potential of the Vga terminal may be assumed to be "L" (-3.3V).

[0066] The cathodes of multiple light-emitting thyristors L1, L2, L3, etc. are connected to the illumination signal line 70. The illumination signal line 70 is connected to the φI1 terminal of the SLED chip 67-1. The φI1 terminal of the SLED chip 67-1 is connected to the illumination time control / drive unit 118 of the signal generation circuit 100 via a current limiting resistor RI. The illumination time control / drive unit 118 transmits an illumination signal φI1 that controls whether each light-emitting thyristor L1, L2, L3, etc. is illuminated and the illumination time. The illumination signal φI1 supplies current to the light-emitting thyristors L1, L2, L3, etc. for illumination. For convenience, terminals and signals, or terminals and the voltage applied to those terminals, etc., will be indicated by the same symbol here.

[0067] The first gates Glfn of the multiple light-emitting thyristors L1, L2, L3, etc., are connected to the power line 71 via resistors Rgn, as shown in Figure 6. The power line 71 is connected to the Vga terminal of the SLED chip 67-1. The Vga terminal is connected to the reference potential supply unit 69, which serves as a return power supply, via the reference potential line 206. The reference voltage Vga of the reference potential supply unit 69 is set to, for example, -3.3V.

[0068] Meanwhile, among the multiple transfer thyristors T1, T2, T3, etc., the cathodes of the odd-numbered transfer thyristors T1, T3, T5, etc. are connected to the first transfer signal line 72 to which the first transfer signal φ1 is transmitted. The first transfer signal line 72 is connected to the φ1 terminal of the SLED chip 67 via a current limiting resistor R1 to prevent excessive current from flowing. The first transfer signal φ1 is transmitted to the φ1 terminal of the SLED chip 67 from the timing signal generation unit 114 of the signal generation circuit 100.

[0069] Furthermore, among the multiple transfer thyristors T1, T2, T3..., the cathodes of the even-numbered transfer thyristors T2, T4, T6... are connected to the second transfer signal line 73 to which the second transfer signal φ2 is transmitted. The second transfer signal line 73 is connected to the φ2 terminal of the SLED chip 67 via a current limiting resistor R2 to prevent excessive current flow. The second transfer signal φ2 is transmitted to the φ2 terminal of the SLED chip 67 from the timing signal generation unit 114 of the signal generation circuit 100.

[0070] The SLED chip 67-1 has coupling transistors Q1, Q2, Q3... positioned between two adjacent transfer thyristors Tn and Tn+1. The base of each coupling transistor Q1, Q2, Q3... is connected to the second gate Gtsn of the preceding transfer thyristor Tn. The collector terminals of each coupling transistor Q1, Q2, Q3... are connected to the first gate Gtfn+1 of the subsequent transfer thyristor Tn+1 via a resistor Rcn. The bases of each coupling transistor Q1, Q2, Q3... are connected to the Vsub terminal wired on the back of the circuit board 68.

[0071] Furthermore, for the first transfer thyristor T1, its first gate Gtf1 is connected to a second transfer signal line 73 located downstream of the current limiting resistor R2 via the start resistor Rs.

[0072] <Operation of SLED Chip> FIG. 8 is a timing chart showing the operation of the SLED chip 67 of the LED print head 60 according to the first embodiment.

[0073] In FIG. 8, a timing chart for controlling the lighting or non-lighting of the first to fifth of a plurality (for example, 256) of light-emitting thyristors L1 to L256 of the SLED chip 67 is shown. In FIG. 8, the light-emitting thyristors L1, L2, L3, and L5 of the SLED chip 67 are lit, and the light-emitting thyristor L4 is not lit.

[0074] Among the plurality of SLED chips 67-1 to 67-40 arranged on the LED circuit board 62, the other SLED chips 67-2 to 67-40 are driven in parallel simultaneously with the SLED chip 67-1 as shown in FIG. 5. Here, the operation of the first SLED chip 67-1 will be described.

[0075] First, when starting image exposure by the LED print head 60, the line sync signal Lsync is transmitted from the control unit 4 to the timing signal generation unit 114 of the signal generation circuit 100. The line sync signal Lsync is composed of a signal that rises from the "L" state to the "H" state and then falls from the "H" state to the "L" state for each line, for example, when scanning and exposing the surface of the photoreceptor drum 11. In the state before the line sync signal Lsync falls, as shown at time a in FIG. 8, the first and second transfer signals φ1, φ2 and the lighting signal φI1 are both "H" (0V).

[0076] At this time, as shown in Figure 6, the transfer section 202 of the SLED chip 67 is connected to the first transfer signal line 72, where the cathodes of the odd-numbered transfer thyristors T1, T3, T5, etc. are set to "H". Similarly, the cathodes of the even-numbered transfer thyristors T2, T4, T6, etc. are connected to the second transfer signal line 73, which is set to "H". Therefore, the transfer thyristors T1, T3, T5, etc. and the transfer thyristors T2, T4, T6, etc. are in the off state because both their anodes and cathodes are "H".

[0077] On the other hand, the cathodes of the light-emitting thyristors L1, L2, L3, etc. are connected to the illumination signal line 70, which is set to "H". Therefore, the light-emitting thyristors L1, L2, L3, etc. are also in the off state because both their anode and cathode are set to "H".

[0078] In this case, the first transfer thyristor T1 in the transfer unit 202 has its first gate Gtf1 connected to the "L" (-3.3V) power line 71 via resistor Rg1, as shown in Figure 6. Furthermore, the first transfer thyristor T1 has its first gate Gtf1 connected to the "H" (0V) second transfer signal line 73 via start resistor Rs.

[0079] Therefore, the potential of the first gate Gtf1 of the first transfer thyristor T1 is the potential obtained by dividing the potential difference between the "L" (-3.3V) of the power line 71 and the "H" (0V) of the second transfer signal line 73 by resistor Rg1, start resistor Rs, and current limiting resistor R2. If we set resistor Rg1 to 10kΩ, start resistor Rs to 2kΩ, and current limiting resistor R2 to 300Ω, the potential of the first gate Gtf1 will be -0.62V. The threshold voltage of the first transfer thyristor T1 is Vgtf-Vd, so it is -0.62-1.5=-2.12V. Here, Vd is the diffusion potential of the first transfer thyristor T1 (for example, 1.5V). The potential of the first gate Gtf1 of the first transfer thyristor T1 is set, as described above, by the voltage of "L" (-3.3V) on the power line 71 and the resistance values ​​of resistor Rg1, start resistor Rs, and current limiting resistor R2. Also, the first light-emitting thyristor L1 has a threshold voltage of -2.12V because its first gate Glf1 is connected to the first gate Vgtf1 of the first transfer thyristor T1.

[0080] At this time, the first transfer thyristor T1 is in the off state, so the coupling transistor Q1 is also in the off state. Therefore, the first gate Gtf2 of the second transfer thyristor T2 is connected to the potential of the power line 71, "L" (-3.3V), via resistor Rg2. Thus, the threshold voltage for the second transfer thyristor T2 is -3.3V - 1.5 = -4.8V. Similarly, the threshold voltages for the third and subsequent transfer thyristors T3, T4, and T5 are also -4.8V.

[0081] Next, as shown at time b in Figure 8, when the line sync signal Lsync falls to the "L" state, the first transfer signal φ1 output from the timing signal generator 114 of the signal generation circuit 100 changes from "H" to "L" in synchronization with the SLED chip 67. Then, the first transfer thyristor T1, whose threshold voltage is -2.12V, turns on as shown in Figure 6, because the first transfer signal line 72, i.e., the cathode, becomes "L" (-3.3V). However, the odd-numbered transfer thyristors T from the third onward have their cathodes connected to the first transfer signal line 72, but as mentioned above, their threshold voltage is -4.8V, so they do not turn on and remain in the off state. On the other hand, the even-numbered transfer thyristors T2, T4, T6, etc. do not turn on because the second transfer signal line 73 remains "H" (0V).

[0082] In the first transfer thyristor T1, which is in the ON state, the first gate Gtf1 becomes the saturation potential Vc of transistor Tr1, as shown in Figure 7. Here, the saturation potential Vc is assumed to be -0.2V as an example. Therefore, in the first transfer thyristor T1, the first gate Gtf1 becomes -0.2V, and the second gate Gts1 becomes the potential obtained by subtracting the diffusion potential Vd (1.5V) from the anode A1 ("H" (0V)) (-1.5V).

[0083] Furthermore, in the first transfer thyristor T1 when it is ON, current flows from the anode A1 ("H" (0V)) towards the terminal φ1 ("L" (-3.3V)) to which the cathode K1 is connected. Therefore, the potential Vk of the cathode K1 of the first transfer thyristor T1 when it is ON is expressed by the following equation (1), using the internal resistance rk (let the resistance value be rk), current limiting resistor R1 (let the resistance value be R1), and diffusion potential Vd of the first transfer thyristor T1 when it is ON.

[0084] Vk=(Vga+Vd)×{rk / (R1+rk)}-Vd (1)

[0085] For example, if the current limiting resistor R1 is 300Ω and the internal resistance rk is 60Ω, the potential Vk of cathode K1 will be -1.8V. Note that the potential Vk of cathode K1 is the potential of the first transfer signal line 72.

[0086] Then, as mentioned above, the first transfer thyristor T1 has a first gate Gtf1 of -0.2V. The first light-emitting thyristor L1 has a first gate Glf1 connected to the first gate Gtf1 (0.2V) of the transfer thyristor T1, so the threshold voltage is -0.2 - 1.5 = -1.7V.

[0087] On the other hand, when the first transfer thyristor T1 turns on, the coupling transistor Q1 transitions from the off state to the on state. As a result, the first gate Gtf2 of the second transfer thyristor T2 transitions to -0.72V, and the threshold voltage for the second transfer thyristor T2 and the second light-emitting thyristor L2 becomes -2.22V. However, since the second transfer signal line 73 is "H" (0V), the second transfer thyristor T2 does not turn on. Also, since the illumination signal line 70 is "H" (0V), the second light-emitting thyristor L2 does not turn on either.

[0088] Since the second transfer thyristor T2 is in the off state, the coupling transistor Q2 is also in the off state. Therefore, the first gate Gtf3 of the third transfer thyristor T3 is "L" (-3.3V), and the threshold voltage for the third transfer thyristor T3 and the third light-emitting thyristor L3 is -4.8V. Similarly, the threshold voltage for transfer thyristors T and light-emitting thyristors L numbered 4 or higher is also -4.8V.

[0089] Immediately after time b (here, this refers to the time when a steady state is reached after changes in thyristors, etc., have occurred due to the change in signal potential at time b), the first transfer thyristor T1 and coupling transistor Q1 are in the ON state, while the other transfer thyristors T and coupling transistor Q, and all light-emitting thyristors L are in the OFF state.

[0090] Subsequently, as shown in Figure 8, at time c, the illumination signal φI1 transitions from "H" to "L". Then, as shown in Figure 6, the illumination signal line 70 transitions from "H" (0V) to "L" (-3.3V) via the current limiting resistor RI and the φI terminal. At this point, the first light-emitting thyristor L1, which has a threshold voltage of -1.7V, turns on and lights up (emits light). As a result, the illumination signal line 70 becomes -1.86V.

[0091] As mentioned above, the second light-emitting thyristor L2 has a threshold voltage of -2.22V, but the first light-emitting thyristor L1, which has a higher threshold voltage of -1.7V, turns on and raises the illumination signal line 70 to -1.86V, so the second light-emitting thyristor L2 does not turn on.

[0092] Immediately after time c, the first transfer thyristor T1 and the first coupling transistor Q1 are ON, and the first light-emitting thyristor L1 is ON and illuminated.

[0093] Next, at time d, the illumination signal φI1 transitions from "L" to "H". Then, via the current limiting resistor RI and the φI terminal, the illumination signal line 70 transitions from -1.86V to "H" (0V). As a result, the first light-emitting thyristor L1 turns off as both its anode and cathode become "H". The illumination period t1 of the first light-emitting thyristor L1 is the period from time c, when the illumination signal φI1 transitions from "H" to "L", to time d, when the illumination signal φI1 transitions from "L" to "H". Therefore, the illumination period t1 of the first light-emitting thyristor L1 is controlled by the time the illumination signal φI1 remains in the "L" state, based on image data, etc. Immediately after time d, the first transfer thyristor T1 and the first coupling transistor Q1 are in the ON state.

[0094] Furthermore, at time e, the second transfer signal φ2 transitions from "H" to "L". At this point, the period T(1) for controlling the illumination of the first light-emitting thyristor L1 ends, and the period T(2) for controlling the illumination of the second light-emitting thyristor L2 begins. Then, the φ2 terminal transitions from "H" to "L" (-3.3V). Since the first transfer thyristor T1 is in the ON state, the first gate Gtf1 of the first transfer thyristor T1 is -0.2V. Therefore, the second transfer signal line 73 is the value obtained by dividing the potential difference between "L" (-3.3V) and -0.2V by the start resistor Rs (2kΩ) and the current limiting resistor R2 (300Ω). That is, the second transfer signal line 73 becomes -2.9V.

[0095] At time b, the second transfer thyristor T2 turns on because its threshold voltage is -2.22V. As a result, the first gate Gtf2 (first gate Glf2) of the second transfer thyristor T2 becomes -0.2V, and the threshold voltage of the second light-emitting thyristor L2 becomes -1.7V. When the second transfer thyristor T2 turns on, the second transfer signal line 73 becomes -1.8V.

[0096] Furthermore, when the second transfer thyristor T2 turns on, the second coupling transistor Q2 transitions from the off state to the on state, and the first gate Gtf3 of the third transfer thyristor T3 becomes -0.72V. Therefore, the threshold voltage for the third transfer thyristor T3 and the third light-emitting thyristor L3 becomes -2.22V. Transfer thyristors T and light-emitting thyristors L numbered 4 or higher maintain a threshold voltage of -4.8V. Note that the lighting signal φI1 is "H" (0V), so none of the light-emitting thyristors L turn on. Immediately after time e, the first and second transfer thyristors T1, T2 and the first and second coupling transistors Q1, Q2 are in the on state.

[0097] Subsequently, at time f, the first transfer signal φ1 transitions from "L" to "H". Then, the potential of the first transfer signal line 72 via terminal φ1 transitions from "L" to "H". As a result, the ON transfer thyristor T1 turns off, with both its anode and cathode becoming "H".

[0098] The first gate Gtf1 (first gate Glf1) is connected to the power line 71 ("L" (-3.3V)) via resistor Rg1, and also to the second transfer signal line 73, which is "L" (-3.3V), via start resistor Rs. Therefore, the first transfer thyristor T1 is turned on when the first gate Gtf1 (first gate Glf1) changes from -0.2V to "L" (-3.3V), and the threshold voltage between the first transfer thyristor T1 and the first light-emitting thyristor L1 becomes -4.8V. Immediately after time f, the second transfer thyristor T2 is turned on.

[0099] Subsequently, at time g, when the illumination signal φI1 changes from "H" to "L", the second light-emitting thyristor L2 turns on and lights up, similar to the first light-emitting thyristor L1 at time c. Then, at time h, when the illumination signal φI1 changes from "L" to "H", the second light-emitting thyristor L2 turns off and turns off, similar to the light-emitting thyristor L1 at time d.

[0100] Furthermore, at time i, when the first transfer signal φ1 transitions from "H" to "L", the third transfer thyristor T3, with a threshold voltage of -2.22V, turns on, similar to the first transfer thyristor T1 at time b or the second transfer thyristor T2 at time e. At this time, the first transfer thyristor T1 does not turn on because its threshold voltage is -4.8V. At time i, the period T(2) for controlling the illumination of the second light-emitting thyristor L2 ends, and the period T(3) for controlling the illumination of the third light-emitting thyristor L3 begins.

[0101] Furthermore, if you want to keep the light-emitting thyristor L off-light, you can simply keep the lighting signal φI1 at "H" (0V) as shown in Figure 8, during the lighting control period T(4) for light-emitting thyristor L4. In this way, the fourth light-emitting thyristor L4 will remain off-light even if the threshold voltage remains at -1.7V.

[0102] From this point onward, the process repeats as described above until the illuminating / deactivating of the 256th light-emitting thyristor, L256, is controlled. Once the illuminating / deactivating control of the 256th light-emitting thyristor, L256, is complete, the first and second transfer signals φ1, φ2, and the illumination signal φI1 all become "H" (0V), and the process transitions to a pause period.

[0103] At this time, as shown in Figure 6, Vga (-3.3V) is applied to the Vga terminal of each SLED 67 via the reference potential line 206 by the reference potential supply unit 69, which acts as a return power supply. Meanwhile, at the Vsub terminal, a lighting current flows from the anode, which is "H" (0V), through the cathode of the light-emitting thyristors L1, L2, L3, etc., which light up when the lighting signal φI1 of each SLED 67 transitions to "L" via the power line 200, to the lighting signal line 70.

[0104] The ignition current flowing to these light-emitting thyristors L1, L2, L3... varies depending on the number of light-emitting thyristors L1, L2, L3... among the SLED chips 67-1 to 67-40 that are lit simultaneously, the lighting time, and the lighting intensity. For the sake of simplicity, the lighting intensity of light-emitting thyristors L1, L2, L3... is assumed to be constant in this explanation.

[0105] Therefore, in the SLED chips 67-1 to 67-40 of the LED print head 60, depending on the lighting state of the light-emitting thyristor L located immediately before the rest period, a large lighting current may flow to the Vsub terminal via the power line 200 through the power supply circuit 101 consisting of a constant voltage power supply. This large lighting current is then cut off simultaneously with the start of the rest period.

[0106] Figure 10 is a block diagram showing the configuration of the signal generation circuit.

[0107] As shown in Figure 10, the signal generation circuit 100 includes an image data unpacking unit 110 that receives image data from the image processing unit 2. The image data unpacking unit 110 unpacks the image data input from the image processing unit 2 into image data of 256 pixels each, corresponding to each SLED chip 67-1 to 67-40, for each line. The image data unpacked by the image data unpacking unit 110 is transmitted to the lighting time control and driving units 118-1 to 118-40, which are provided corresponding to each SLED chip 67-1 to 67-40.

[0108] Furthermore, the signal generation circuit 100 includes a correction value calculation unit 112 that receives a correction value for light intensity unevenness from the EEPROM 102 on the LED circuit board 62. Image data is input to the correction value calculation unit 112 from the image processing unit 2. The correction value for light intensity unevenness is determined in advance, for example, by actually lighting each SLED chip 67-1 to 67-40 and measuring the light intensity unevenness at the time of shipment. The correction value calculation unit 112 calculates the correction value for light intensity unevenness and transmits the light intensity unevenness correction value to the lighting time control / drive units 118-1 to 118-40 that drive the corresponding SLED chips 67-1 to 67-40.

[0109] Furthermore, the signal generation circuit 100 includes a timing signal generation unit 114 and a reference clock generation unit 116. The timing signal generation unit 114 receives a line sync signal Lsync, thyristor transfer period setting data, and light intensity adjustment data from the control unit 4. The thyristor transfer period setting data is data for appropriately setting the thyristor transfer period according to the print speed, etc. The timing signal generation unit 114 outputs a data readout signal to the image data development unit 110 and the correction value calculation unit 112. The timing signal generation unit 114 also outputs a trigger signal TRG to the lighting time control / drive units 118-1 to 118-40 for synchronization. Furthermore, the timing signal generation unit 114 outputs first and second transfer signals φ1 and φ2 to each SLED chip 67-1 to 67-40. The lighting time control and drive units 118-1 to 118-40 output lighting signals φI1 to φI40 to each SLED chip 67-1 to 67-40 according to the image data and light intensity unevenness correction value data.

[0110] The reference clock generation unit 116 outputs a reference clock signal to the timing signal generation unit 114 and the lighting time control / drive unit 118.

[0111] Figure 11 is a circuit diagram showing the wiring between the signal generation circuit 100 and each of the SLED chips 67-1 to 67-40.

[0112] Each SLED chip 67-1 to 67-40 has a φI terminal connected to the corresponding lighting time control / drive unit 118-1 to 118-40 of the signal generation circuit 100 via a current limiting resistor RI through a lighting signal line 203-1 to 203-40. In addition, the φ1 and φ2 terminals of each SLED chip 67-1 to 67-40 are connected to the timing signal generation unit 114 of the signal generation circuit 100 via first and second transfer signal lines 204 and 205, respectively. Furthermore, each SLED chip 67-1 to 67-40 has a Vga terminal connected to the power supply circuit 101 via a power supply line 200, and a Vsub terminal connected to the reference potential supply unit 69 via a reference potential line 206.

[0113] Incidentally, in the image forming apparatus 1 to which the LED print head 60 configured as described above is applied, high speed is required in order to increase the number of prints per unit time and achieve high productivity. To meet the demand for high speed in the image forming apparatus 1, it is necessary to increase the process speed, which is defined by the rotation speed of the photoreceptor drum 11 in each image forming unit 10 (Y, M, C, K). Furthermore, the LED print head 60 that exposes the surface of the photoreceptor drum 11 to images is required to meet the demand for high speed by increasing the number of lights illuminated per unit time.

[0114] As shown in Figure 12, the LED print head 60 adjusts the exposure amount when exposing the surface of the photoreceptor drum 11 according to the image data, by adjusting at least one of the maximum light output determined by the drive voltage applied to each LED of the LED print head 60 and the light emission time of each LED. In order to meet the demand for higher speed in the LED print head 60, it is desirable to increase the drive voltage applied to each LED and to shorten the scanning time required to expose one line of the photoreceptor drum 11.

[0115] As shown in Figure 12, with increasing speed, the LED print head 60 requires reducing the idle period, which is the non-scanning period set between scanning periods, in order to shorten the scanning time required to expose one line of the photoreceptor drum 11.

[0116] As a result, the LED print head 60 increases the relative current flowing through each LED as the driving voltage to each LED is increased. In addition, during the pause period set between scanning periods, the relatively large current flowing through each LED is instantaneously cut off.

[0117] As shown in Figure 10, the LED print head 60 has inductance, including capacitance, in the power supply line 200 that applies the drive voltage to each LED from the power supply circuit 101, which consists of a DC-DC converter, etc. Therefore, in the LED print head 60, as shown in Figure 13(b), due to the inductance of the power supply line 200, even if the relatively large current flowing to each LED is instantaneously interrupted, the supply current decreases gradually, causing the voltage of the power supply circuit 101 to rise sharply due to excessive current. As a result, when the rest period ends and the next line exposure starts in the LED print head 60, the voltage of the power supply circuit 101 is high, then drops sharply, and then returns to the normal voltage.

[0118] In conventional LED print heads 60, the drive voltage fluctuates at the start of the scanning period immediately after the end of the rest period, causing the light output of the LEDs in the LED print head 60 to fluctuate. Therefore, at the start of scanning by the exposure device 13, there was a technical problem in that density unevenness, such as white streaks of low density and black streaks of high density, may occur in the halftone image, as shown in Figure 14.

[0119] To address these technical challenges, a configuration has already been proposed that includes a power consumption means for consuming power corresponding to the light emission power consumption of the light-emitting element group, as disclosed in Patent Document 1, etc.

[0120] However, the unevenness in image density caused by fluctuations in the drive voltage varies depending on the total light output of the LEDs in the LED print head 60 during the scanning period immediately preceding the pause time. Therefore, simply consuming power corresponding to the light-emitting power consumption of the light-emitting element group is not sufficient to adequately suppress the unevenness in image density caused by the amount of light emitted due to fluctuations in the drive voltage, which remains a technical challenge.

[0121] Therefore, the optical scanning apparatus according to this embodiment is configured to include a waste current generation means that generates a waste current from the driving means to supply current to elements other than each group of light-emitting elements during a non-scanning period set during the scanning period, and a waste current control means that controls the waste current generated by the waste current generation means.

[0122] In other words, the LED print head 60, as an example of an optical scanning device according to this embodiment 1, as shown in Figure 10, has a signal generation circuit 100 mounted on an LED circuit board 62, which includes a waste current amount control means 301 as an example of a control unit for the waste current generation means, and a waste current ON / OFF means 302 as an example of a switching unit for the waste current generation means. The waste current amount control means 301 controls the current value of the waste current Iab that is energized during the idle period, as shown in Figure 15. The waste current ON / OFF means 302 switches whether or not waste current is generated, including the timing of energization of the waste current Iab. The waste current amount control means 301 is controlled by a waste current amount control unit 303. The waste current ON / OFF means 302 is controlled by a waste current ON time control unit 304. The waste current amount control means 301 and the waste current ON / OFF means 302 are connected in series with a power supply circuit 101 that outputs the power supply Vsub for the SLED and a reference potential supply unit 69 which is the return power supply for the SLED. The Vga terminal of the SLED is connected to the reference potential supply unit 69, which is the return power supply for the SLED, and the return current of the SLED flows into it.

[0123] As the waste current amount control means 301, for example, as shown in Figure 17, a first transistor Q11 is used that controls the waste current by a PWM signal flowing to its base via a filter circuit 305. The PWM signal is output from the waste current amount control unit 303 to control the current value of the waste current Iab to a required value. As the waste current ON / OFF means 302, a second transistor Q12 is used, to which Vsub is applied to the collector via a resistor. Signals controlling the ON timing and OFF timing of the waste current Iab are output from the waste current ON time control unit 304 to the base terminal of the second transistor Q12.

[0124] As shown in Figure 15, the waste current control unit 303 receives image data and density unevenness correction data from the signal generation circuit 100. The waste current control unit 303 also receives three parameters from the control unit 4: the calculation start transfer number A, the waste current coefficient B, and the waste current fixed value C. Of these parameters, the calculation start transfer number A determines which of the 256 light-emitting thyristors L1 to L256 on each SLED chip 67 the lighting signal from which the calculation of image data, etc., will begin in order to determine the waste current. For example, if the calculation start transfer number A is 245, it means that the calculation of image data, etc., will begin from the lighting signal of the 246th light-emitting thyristor L, i.e., the 245th transfer. The waste current coefficient B is a coefficient multiplied by the integrated value of the lighting signals from the calculation start transfer number A to the last 256th light-emitting thyristor to determine the value of the waste current. The waste current fixed value C indicates a predetermined fixed value for the waste current.

[0125] To explain further, assuming that the initial transfer count A is 245, if the image data is ON after the initial transfer count A is 245, the light intensity unevenness correction value data (on-time of light-emitting thyristor L) t is acquired and accumulated up to the last light-emitting thyristor L256, as shown in equation (2) below. Note that if the light-emitting thyristor L is off, t=0 and no accumulation is performed. Here, the on-time t of the light-emitting thyristor L is an example of the on-time ratio of the light-emitting thyristor L. If the on-time t of the light-emitting thyristor L is zero, the on-time ratio is zero, and if the on-time t of the light-emitting thyristor L is at its maximum value, the on-time ratio is 100. Σt=t246+t247+...t254+t255 (2)

[0126] Then, the waste current control unit 303 calculates the current value Iab of the waste current based on the following equation (3). Iab={(Σt1+Σt2+···Σt 40 ) / tmax) × B + C (3)

[0127] Here, the number of transfers to start the calculation A, the discard current coefficient B, and the fixed discard current value C are set for each model of the image forming apparatus 1 and are pre-stored in the EEPROM 102 as an example of a storage means. Note that Σt1 is the integrated value of the lighting time t of the SLED chip 67-1, Σt 40 The values ​​shown are the cumulative values ​​of the illumination time t for SLED chips 67-40. Furthermore, tmax represents the maximum value of the cumulative illumination time t for SLED chips 67-1 to 67-40.

[0128] Furthermore, the waste current ON / OFF means 302 is controlled by the waste current ON time control unit 304, which switches the ON / OFF timing of the waste current.

[0129] The discard current ON time control unit 304 receives the ON time coefficient D, the fixed ON time value E, the ON time correction value F, and the OFF time correction value G from the control unit 4. The discard current ON time control unit 304 also receives a trigger signal TRG from the timing signal generation unit 114 of the signal generation circuit 100 to synchronize the timing of supplying the discard current. Of these parameters, the ON time coefficient D is a coefficient to be multiplied by the basic ON time of the discard current, and is a value set for each model of the image forming apparatus 1. The fixed ON time value E is a predetermined fixed value for the ON time. The ON time correction value F and the OFF time correction value G are correction values ​​to correct the ON / OFF time of the discard current.

[0130] The ON time for the discard current is calculated using the following equation (4) in relation to the basic ON time for the discard current. Discarded current ON time = (Basic ON time × D) + E (4)

[0131] The ON / OFF timing of the discard current is calculated using equations (5) and (6) below, based on the circuit characteristics of the discard current, with the end time of the 255th transfer period of the final transfer as the reference. Note that the ON time correction value F is basically a negative value. ON timing = end time of transfer period + F (5) OFF timing = Transfer period end time + Discard current ON time + G (6)

[0132] As shown in Figure 16, the ON timing and OFF timing controlled and switched by the waste current ON time control unit 304 can be set before and after the pause period. Furthermore, when determining the ON timing of the waste current, for example, the ON time correction value F may be configured to change its magnitude according to the magnitude of the waste current value Iab.

[0133] In other words, the waste current ON time control unit 304 is capable of starting the supply of waste current before the start of the pause period. Furthermore, the waste current ON time control unit 304 is capable of ending the supply of waste current after the end of the pause period.

[0134] Thus, the waste current ON time control unit 304 can supply the required waste current throughout the entire rest period, compared to not switching the presence or absence of waste current generation across scanning periods located before and after the rest period. Due to circuit configuration and operational reasons, the waste current amount control means 301 cannot necessarily supply the required waste current at the same time as the start of the rest period. Therefore, by starting the supply of waste current before the start of the rest period, the waste current ON time control unit 304 can ensure that the required waste current is supplied throughout the rest period. Furthermore, even if the waste current amount control means 301 stops supplying the required waste current at the same time as the end of the rest period, it is not possible to reduce the excessive drive current. Therefore, by continuing to supply waste current even after the end of the rest period, the waste current ON time control unit 304 can quickly reduce the excessive drive current.

[0135] Here, the discard current coefficient B and the ON time coefficient D vary depending on the hardware such as the capacitance of the LED circuit board 62, so it is desirable that they be adjusted for each model of the image forming apparatus 1. However, they may also be configured to be adjustable depending on the operating conditions within the same model.

[0136] As an example of adjustments based on usage conditions, some image forming apparatuses 1 allow the print speed to be adjusted depending on the type of recording paper 7. Generally, when the recording paper 7 is thick paper or coated paper, the print speed is set slower than when using plain paper. When the print speed is slowed down in the image forming apparatus 1, the transfer time of each SLED chip 67 increases, but the illumination time of the light-emitting thyristor L does not fundamentally change.

[0137] As a result, the average current consumption of the LED print head 60 decreases. Therefore, the voltage fluctuation of the LED circuit board 62 during the idle period of each SLED chip 67 becomes smaller. Accordingly, the voltage fluctuation of the LED circuit board 62 can be reduced by reducing the amount of waste current in the waste current control unit 303 and by shortening the waste current ON time in the waste current ON time in the waste current ON time control unit 304. In other words, when the printing speed of the image forming apparatus 1 slows down, it is effective to set the waste current coefficient B and the ON time coefficient D to be smaller.

[0138] In this embodiment 1, when the print speed of the image forming apparatus 1 is reduced, that is, when the scanning exposure speed of the LED print head 60 is slowed down, as shown in Figure 18, for example, the waste current coefficient B is reduced to "70" and "40", and the ON time coefficient D is reduced to "80" and "60". These values ​​of the waste current coefficient B and ON time coefficient D corresponding to the print speed are stored in advance in the EEPROM 102, as described above.

[0139] <Operation of the exposure device> In the above configuration, the image forming apparatus to which the LED print head according to this embodiment 1 is applied can suppress fluctuations in light intensity caused by fluctuations in the drive voltage, compared to the case in which there is no waste current control means for controlling the waste current generated by the waste current generation means, as follows.

[0140] In other words, in the image forming apparatus 1 according to this embodiment 1, as shown in Figure 1, it receives image data and command information requesting a full-color image forming operation (print) from an image reading device 5, a personal computer 6, etc. Then, the control unit 4 drives the photoreceptor drum 11 of each image forming unit 10 (Y, M, C, K) and charges the surface of each photoreceptor drum 11 with a charging device 12. After that, the surface of each photoreceptor drum 11 is irradiated with light emitted based on image data obtained by converting each color component (Y, M, C, K) by the LED print head 60.

[0141] In this process, as shown in Figure 10, each SLED chip 67-1 to 67-40 of the LED print head 60 is driven by the signal generation circuit 100. Based on the image data, the signal generation circuit 100 controls the illumination / de-illumination and illumination time of the 256 light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 according to the illumination signal φI flowing through the illumination signal lines 203-1 to 203-40.

[0142] As shown in Figure 6, in the light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40, a lighting current flows from the Vsub power supply (SLED power supply voltage) supplied from the power supply circuit 101 to the reference potential supply unit 69, which is the return power supply, in accordance with the lighting signal φI flowing through the lighting signal line 70.

[0143] At this time, the reference potential supply unit 69, which is the return power supply, is common to each SLED chip 67-1 to 67-40. The lighting current flowing from the power supply circuit 101 to the light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 varies depending on whether the light-emitting thyristors L1 to L256 are lit or not.

[0144] The LED print head 60 is equipped with multiple SLED chips 67-1 to 67-40. The power lines 200 that apply the drive voltage to each SLED chip 67-1 to 67-40 consist of long linear conductors wired on the LED circuit board 62 along the axial direction of the photoreceptor drum 11 and have a relatively large capacitance via the board 68.

[0145] Furthermore, as shown in Figure 9, the LED print head 60 has a pause period set for each scan exposure of one line of the photosensitive drum 11. Therefore, during each pause period, the ignition current flowing to the light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 is interrupted. Moreover, the ignition current flowing to the light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 before and after the pause period changes individually according to the image data.

[0146] Therefore, in the LED print head 60, if no countermeasures are taken, the ignition current flowing to the light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 will be instantaneously interrupted. However, due to the inductance caused by the capacitance of the power supply path, the ignition current will gradually decrease. As a result, the power supply voltage of the power supply circuit 101 will rise sharply due to excessive current. Consequently, the LED print head 60 had a technical problem in that when the rest period ended and the next line exposure started, the voltage of the power supply circuit 101 was high, then it dropped sharply before returning to the normal voltage, causing streaks of light and dark to appear in the image.

[0147] Incidentally, the LED print head 60 according to this embodiment 1, as shown in Figure 10, is equipped with a waste current amount control means 301 and a waste current ON / OFF means 302 connected to the power line 200 of the power supply circuit 101. Furthermore, in the LED print head 60 according to this embodiment 1, as shown in Figure 16, the current value of the waste current Iab and the timing of energizing the waste current Iab are controlled by a waste current amount control unit 303 and a waste current ON time control unit 304.

[0148] To explain further, in the LED print head 60, as shown in Figure 15, the waste current control unit 303 calculates the waste current value Iab based on equation (3) according to the integrated value of the illumination time of the light-emitting thyristor L after the transfer count reaches 245. The waste current control means 301 then controls the waste current value Iab to be the value calculated by the waste current control unit 303.

[0149] Furthermore, the waste current ON time control unit 304 calculates the ON timing for supplying the waste current and the OFF timing for cutting off the waste current. The waste current ON time control unit 304 then controls the timing for supplying the waste current through its own control.

[0150] Therefore, in the LED print head 60 according to this embodiment 1, if the number of lit light-emitting thyristors L immediately before the pause time is relatively small, or if the lighting time of the light-emitting thyristors is relatively short, resulting in a relatively small lighting current, the discard current is set to a small value, and the energizing time is controlled to be relatively short.

[0151] Furthermore, in the LED print head 60 according to this embodiment 1, if the number of lit light-emitting thyristors L immediately before the pause time is relatively large, or if the lighting time of the light-emitting thyristors L is relatively long, resulting in a relatively large lighting current, the discard current is set to a large value, and the energizing time is controlled to be relatively long.

[0152] Therefore, the LED print head 60 according to this embodiment 1 makes it possible to suppress fluctuations in light output caused by fluctuations in the drive voltage during a pause period, compared to a case where there is no waste current control means for controlling the waste current generated by the waste current generation means.

[0153] Experimental example The inventors fabricated an LED print head 60 having SLED chips 67-1 to 67-40 driven by a signal generation circuit 100 as shown in Figure 10, and conducted experiments to confirm the effect of suppressing fluctuations in light intensity caused by fluctuations in the drive voltage.

[0154] In this experiment, the difference in the power supply voltage of the power supply circuit 101 immediately after the pause period was measured for the LED print head 60, when the illumination time of the light-emitting thyristor with image data Cin at 100% was at its maximum, and when the illumination time of the light-emitting thyristor with image data Cin at 50% was at half the maximum.

[0155] Figure 19 shows the measured values ​​of the power supply voltage fluctuations, illustrating the results of this experimental example.

[0156] As is clear from Figure 19, when the value of the discard current is controlled according to the image data Cin, the power supply voltage fluctuation is 10mV, whereas when the value of the discard current is kept constant regardless of the image data Cin, the power supply voltage fluctuation is 14mV, demonstrating a significantly larger effect.

[0157] Although the above embodiment described the case where the method is applied to a full-color image forming apparatus, it goes without saying that the same method can be applied to a monochrome image forming apparatus as well.

[0158] Furthermore, although the above embodiment described the case in which an optical scanning device is applied to an image forming apparatus, the apparatus to which the optical scanning device is applied is not limited to an image forming apparatus.

[0159] Furthermore, although the above embodiment described the case in which the light-emitting thyristor of the SLED chip is driven with the anode set to H (0V) and the cathode set to L (-3.3V) as the optical scanning device, it is of course also possible to drive the light-emitting thyristor of the SLED chip with the anode set to H (a positive electrode of approximately +3.3V) and the cathode set to L (0V).

[0160] (Note) (((1))) A scanning means that arranges multiple groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned along the main scanning direction, and scans by emitting light from each of the light-emitting elements based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, During the non-scanning period set within the scanning period, the drive means generates a waste current to supply current to all light-emitting elements except those in the respective light-emitting element groups, and the waste current generation means is capable of controlling the waste current. An optical scanning device equipped with the following features. (((2))) The optical scanning apparatus according to (((1))), wherein the waste current generation means has a switching unit that switches whether or not the waste current is generated. (((3))) The optical scanning apparatus according to (((2))), wherein the switching unit switches whether or not to generate the waste current over the scanning period located before and after the non-scanning period. (((4))) The optical scanning apparatus according to (((3))), wherein the switching unit changes the timing of switching whether or not to generate the discard current in accordance with the image information in the scanning period immediately preceding the non-scanning period. (((5))) The optical scanning apparatus according to (((4))), wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements. (((6))) The switching unit calculates the time for supplying the discard current by multiplying the basic ON time of the discard current by a required coefficient, as described in (((5))) (((5))) (((7))) The optical scanning apparatus according to (((1))), wherein the waste current generation means has a setting unit for setting the value of the waste current. (((8))) The optical scanning apparatus according to (((7))), wherein the setting unit sets the value of the discard current according to the image information in the scanning period immediately preceding the non-scanning period. (((9))) The optical scanning apparatus according to ((8)), wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements. (((10))) The optical scanning apparatus according to (((9))), wherein the setting unit changes the value of the discard current according to at least one integrated value of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements. (((11))) Image holder and, An exposure means for exposing the image holder based on image information, Equipped with, An image forming apparatus using an optical scanning device as described in any of (((1))) to (((10))) as the exposure means.

[0161] According to the optical scanning device described in (((1))), fluctuations in the amount of light caused by fluctuations in the drive voltage can be suppressed compared to a device that does not have a waste current generation means for generating and controlling a waste current. According to the optical scanning device described in (((2))), the waste current generation means can accommodate the timing delay of the supply of waste current compared to a device that does not have a switching unit for switching between generating waste current and not generating waste current. According to the optical scanning device described in (((3))), the switching unit can supply the required waste current over the entire non-scanning period, compared to not switching whether or not to generate waste current over the scanning period located before and after the non-scanning period. According to the optical scanning device described in (((4))), the switching unit can further reduce the impact of power supply voltage fluctuations compared to a device in which the timing of switching whether or not to generate a discard current according to the image information in the scanning period immediately following the non-scanning period is not changed. According to the optical scanning device described in (((5))), the image information can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the light intensity and luminescence of the light-emitting elements of each light-emitting element group are not included. According to the optical scanning device described in (((6))), the switching unit can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the timing of switching whether or not to generate a waste current is kept constant. According to the optical scanning device described in (((7))), the waste current generation means can reliably reduce fluctuations in the power supply voltage compared to the case where the value of the waste current is kept constant. According to the optical scanning device described in (((8))), the setting unit can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the value of the discarded current is kept constant regardless of the image information in the scanning period immediately preceding the non-scanning period. According to the optical scanning device described in (((9))), the image information can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the light intensity and luminescence of the light-emitting elements of each light-emitting element group are not included. According to the optical scanning device described in (((10))), the setting unit can further reduce the influence of power supply voltage fluctuations caused by image information compared to the case where the value of the discard current is kept constant regardless of the light intensity or luminescence of the light-emitting elements of each group of light-emitting elements. According to the image forming apparatus described in (((11))), fluctuations in light intensity caused by fluctuations in the drive voltage are suppressed compared to a case in which there is no waste current generation means that generates and controls waste current. [Explanation of symbols]

[0162] 1…Image forming apparatus 13… Exposure equipment 60…LED print head 100...Signal generation circuit

Claims

1. A scanning means that arranges multiple groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned along the main scanning direction, and scans by emitting light from each of the light-emitting elements based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, During the non-scanning period set within the scanning period, the drive means generates a waste current that supplies current to everything except the respective light-emitting element groups, and the waste current generation means is capable of controlling the waste current. An optical scanning device equipped with the following features.

2. The optical scanning apparatus according to claim 1, wherein the waste current generation means has a switching unit that switches whether or not the waste current is generated.

3. The optical scanning apparatus according to claim 2, wherein the switching unit switches whether or not to generate the waste current over the scanning period located before and after the non-scanning period.

4. The optical scanning apparatus according to claim 3, wherein the switching unit changes the timing of switching whether or not to generate the discard current in accordance with the image information in the scanning period immediately preceding the non-scanning period.

5. The optical scanning apparatus according to claim 4, wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

6. The optical scanning apparatus according to claim 5, wherein the switching unit calculates the time for energizing the discarded current by multiplying the basic ON time of the discarded current by a required coefficient.

7. The optical scanning apparatus according to claim 1, wherein the waste current generation means has a setting unit for setting the value of the waste current.

8. The optical scanning apparatus according to claim 7, wherein the setting unit sets the value of the discarded current according to the image information in the scanning period immediately preceding the non-scanning period.

9. The optical scanning apparatus according to claim 8, wherein the image information includes at least one of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

10. The optical scanning apparatus according to claim 9, wherein the setting unit changes the value of the discard current according to at least one integrated value of the light intensity and luminescence of the light-emitting elements of each group of light-emitting elements.

11. Image holder and, An exposure means for exposing the image holder based on image information, Equipped with, An image forming apparatus using the optical scanning apparatus described in any one of claims 1 to 10 as the exposure means.

Images