Liquid dispensing device and head unit

Abstract

To provide a liquid dispensing device that can reduce the risk of the drive signal voltage becoming higher than the power supply voltage supplied to the head when multiple drive circuits are started. [Solution] A liquid dispensing device comprising: a head having a first dispensing section and a second dispensing section; a first drive circuit that outputs a first drive signal; a second drive circuit that outputs a second drive signal; and a start control circuit that controls the start of the first drive circuit and the second drive circuit, wherein the first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage; the second drive circuit outputs a signal to stop the output of the drive circuit power signal from the power supply circuit when the drive circuit power signal falls below a predetermined voltage; and the start control circuit starts the start sequence of the first drive circuit and then starts the start sequence of the second drive circuit.

Description

Technical Field

[0001] The present invention relates to a liquid ejection device and a head unit.

Background Art

[0002] In liquid ejection devices such as inkjet printers that eject ink to print images and documents, for example, those using piezoelectric elements such as piezo elements are known. The piezoelectric elements are provided corresponding to each of a plurality of nozzles in the head, and each is driven according to a drive signal. As a result, a predetermined amount of liquid is ejected from the nozzles formed in the head at a predetermined timing, and dots are formed on the print medium.

[0003] In such a liquid ejection device, in order to control the supply of the drive signal to the piezoelectric element, for example, a high voltage of 42V is supplied to the head as the power supply voltage. If an abnormality such as an overvoltage or an overcurrent occurs in the path through which such a power supply voltage propagates, the liquid ejection device may malfunction. In contrast, in Patent Document 1, a liquid ejection device has been proposed in which a plurality of drive circuits monitor the power supply voltage supplied to the head and a fuse is provided on the wiring path through which the power supply voltage propagates.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the voltage of the drive signal becomes higher than the high voltage supplied to the head, an excessive current flows from the drive signal wiring to the head power supply wiring due to the parasitic diode existing in the head, and the head may malfunction. In particular, such a situation is likely to occur when a plurality of drive circuits are started up. [Means for solving the problem]

[0006] One embodiment of the liquid dispensing device according to the present invention is: It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A transport unit for transporting the aforementioned medium, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit that controls the startup of the first drive circuit and the second drive circuit, A liquid dispensing device comprising, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then the second drive Start the startup sequence of the power circuit.

[0007] One embodiment of the head unit according to the present invention is: It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit that controls the startup of the first drive circuit and the second drive circuit, A head unit equipped with, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then starts the startup sequence of the second drive circuit. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing the schematic configuration of a liquid dispensing device. [Figure 2] This is a block diagram showing the electrical configuration of a liquid dispensing device. [Figure 3] This figure shows an example of a drive signal COM. [Figure 4] Block diagram showing the electrical configuration of the drive signal selection circuit. [Figure 5] This is a circuit diagram showing the electrical configuration of the selection circuit. [Figure 6] This diagram shows the decoded content in the decoder. [Figure 7] This is a diagram illustrating the operation of the drive signal selection circuit. [Figure 8] This is a cross-sectional view showing the schematic configuration of the discharge section. [Figure 9] This is a block diagram showing the circuit configuration of the drive circuit board in the first embodiment. [Figure 10] This figure shows an example of the configuration of an overcurrent protection circuit. [Figure 11]It is a block diagram showing the configuration of the drive circuit. [Figure 12] It is a diagram showing an example of the startup sequence of the drive circuit. [Figure 13] It is a block diagram showing the circuit configuration of the drive circuit board in the second embodiment. [Figure 14] It is a block diagram showing the circuit configuration of the drive circuit board in the third embodiment. [Figure 15] It is a block diagram showing the circuit configuration of the drive circuit board in the fourth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0010] 1. First Embodiment 1-1. Configuration of the Liquid Discharge Device As an example of the liquid discharge device according to this embodiment, a printing device is an inkjet printer that forms dots on a printing medium such as paper by discharging ink according to image data input from an external host computer, and prints an image including characters, graphics, etc. according to the image data.

[0011] FIG. 1 is a perspective view showing the schematic configuration of the liquid discharge device 1. In FIG. 1, the direction X in which the medium P is conveyed, the direction Y in which the moving body 2 reciprocates intersecting the direction X, and the direction Z in which the ink is discharged are illustrated. In this embodiment, the directions X, Y, and Z are described as axes orthogonal to each other, but the various configurations of the liquid discharge device 1 are not limited to being arranged orthogonal to each other. Also, in the following description, the direction Y in which the moving body 2 moves may be referred to as the main scanning direction.

[0012] As shown in Figure 1, the liquid dispensing device 1 comprises a movable body 2 and a moving mechanism 3 that reciprocates the movable body 2 along direction Y. The moving mechanism 3 includes a carriage motor 31 that serves as the driving source for the movable body 2, a carriage guide shaft 32 fixed at both ends, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0013] The carriage 24 included in the mobile body 2 is supported so as to be able to reciprocate on the carriage guide shaft 32 and is also fixed to a part of the timing belt 33. The carriage motor 31 drives the timing belt 33, causing the carriage 24 to reciprocate along the direction Y, guided by the carriage guide shaft 32. A head unit 20 with numerous nozzles is provided in the part of the mobile body 2 that faces the medium P. Control signals and the like are input to the head unit 20 via the cable 190. Based on the input control signals, the head unit 20 ejects ink as an example of a liquid from the nozzles.

[0014] The liquid dispensing device 1 includes a conveying mechanism 4 that transports the medium P on a platen 40 along direction X. The conveying mechanism 4 includes a conveying motor 41 which is the drive source, and conveying rollers 42 which are rotated by the conveying motor 41 to transport the medium P along direction X.

[0015] In the liquid dispensing device 1 configured as described above, the head unit 20 dispenses ink at the time the medium P is transported by the transport mechanism 4, thereby forming an image on the surface of the medium P.

[0016] 1-2. Electrical Configuration of Liquid Dispensing Device Figure 2 is a block diagram showing the electrical configuration of the liquid dispensing device 1. As shown in Figure 2, the liquid dispensing device 1 includes a control unit 10 and a head unit 20. The control unit 10 and the head unit 20 are electrically connected by a cable 190 such as a flexible flat cable (FFC).

[0017] The control unit 10 includes a control circuit 100, a power supply circuit 90, and an oscillator circuit 91. The control circuit 100 generates multiple control signals, etc., for controlling various configurations based on image data input from the host computer and outputs them to the head unit 20.

[0018] Specifically, the control circuit 100 outputs a clock signal SCK, print data signals SIa, SIb, SIc, SId, latch signals LATa, LATb, LATc, LATd, change signals CHa, CHb, CHc, CHd, and drive data signals DATAa, DATAb, DATAc, DATAd to the head unit 20.

[0019] Although not shown in the diagram, the control circuit 100 controls the carriage motor 31 and the transport motor 41. This controls the movement of the carriage 24 in direction Y as shown in Figure 1, and the movement of the medium P in direction X as shown in Figure 1.

[0020] The power supply circuit 90, for example, uses DC 42V voltages VHV_H, VHV_A1, VHV_A2 The power supply circuit 90 then generates the voltages VHV_H, VHV_A1, and VHV_A2 and supplies them to the head unit 20.

[0021] The oscillator circuit 91 outputs a clock signal MCK. The clock signal MCK output from the oscillator circuit 91 is input to the head unit 20. The oscillator circuit 91 may be configured independently of the control circuit 100, as shown in Figure 2, or it may be configured inside the control circuit 100.

[0022] The head unit 20 comprises a print head 22 and a drive circuit board 50. The drive circuit board 50 is connected to the print head 22.

[0023] The drive circuit board 50 includes drive circuits 51a, 51b, 51c, and 51d. The drive circuits 51a, 51b, 51c, and 51d each drive the liquid ejection modules 21a, 21b, 21c, and 21d included in the print head 22.

[0024] The drive circuit 51a generates a drive signal COMa and a reference voltage signal VBSa based on the voltage VHV_A1, drive data signal DATAa, and clock signal MCK, and outputs them to the liquid discharge module 21a. The drive circuit 51b generates a drive signal COMb and a reference voltage signal VBSb based on the voltage VHV_A1, drive data signal DATAb, and clock signal MCK, and outputs them to the liquid discharge module 21b. The drive circuit 51c generates a drive signal COMc and a reference voltage signal VBSc based on the voltage VHV_A2, drive data signal DATAc, and clock signal MCK, and outputs them to the liquid discharge module 21c. The drive circuit 51d generates a drive signal COMd ​​and a reference voltage signal VBSd based on the voltage VHV_A2, drive data signal DATAd, and clock signal MCK, and outputs them to the liquid discharge module 21d. Here, the reference voltage signals VBSa, VBSb, VBSc, and VBSd are signals of constant voltage, such as ground potential, DC 5V, DC 6V, etc.

[0025] Although not shown in Figure 2 due to its complexity, the drive circuit board 50 also includes circuits other than the drive circuits 51a, 51b, 51c, and 51d. Details of the circuit configuration and operation of the drive circuit board 50 will be described later.

[0026] The print head 22 includes liquid ejection modules 21a, 21b, 21c, and 21d. Liquid ejection module 21a has a drive signal selection circuit 200a and a plurality of ejection units 600a. Each ejection unit 600a also includes a piezoelectric element 60a. The drive signal selection circuit 200a receives a clock signal SCK, a print data signal SIa, a latch signal LATa, a change signal CHa, a drive signal COMa, and a voltage VHV_H as inputs. Based on the clock signal SCK, print data signal SIa, latch signal LATa, change signal CHa, and voltage VHV_H, the drive signal selection circuit 200a generates a drive signal VOUTa by selecting or deselecting the drive signal COMa.

[0027] The drive signal VOUTa is supplied to one end of the piezoelectric element 60a included in each of the multiple ejection units 600a. A reference voltage signal VBSa is supplied to the other end of the piezoelectric element 60a. The piezoelectric element 60a is then driven by the potential difference between the drive signal VOUTa and the reference voltage signal VBSa, causing ink to be ejected from the ejection unit 600a. In other words, the liquid ejection module 21a has a piezoelectric element 60a driven by a drive signal COMa, and a drive signal selection circuit 200a that controls the supply of the drive signal COMa to the piezoelectric element 60a.

[0028] The liquid dispensing module 21b has a drive signal selection circuit 200b and a plurality of dispensing units 600b. Each dispensing unit 600b also includes a piezoelectric element 60b. The following signals are input to this circuit: clock signal SCK, print data signal SIb, latch signal LATb, change signal CHb, drive signal COMb, and voltage VHV_H. The drive signal selection circuit 200b then generates the drive signal VOUTb by selecting or deselecting the drive signal COMb based on the clock signal SCK, print data signal SIb, latch signal LATb, change signal CHb, and voltage VHV_H.

[0029] The drive signal VOUTb is supplied to one end of the piezoelectric element 60b included in each of the multiple ejection units 600b. A reference voltage signal VBSb is supplied to the other end of the piezoelectric element 60b. The piezoelectric element 60b is driven by the potential difference between the drive signal VOUTb and the reference voltage signal VBSb, causing ink to be ejected from the ejection unit 600b. In other words, the liquid ejection module 21b has a piezoelectric element 60b driven by a drive signal COMb and a drive signal selection circuit 200b that controls the supply of the drive signal COMb to the piezoelectric element 60b.

[0030] The liquid dispensing module 21c has a drive signal selection circuit 200c and a plurality of dispensing units 600c. Each dispensing unit 600c also includes a piezoelectric element 60c. The drive signal selection circuit 200c receives a clock signal SCK, a print data signal SIc, a latch signal LATc, a change signal CHc, a drive signal COMc, and a voltage VHV_H as inputs. Based on the clock signal SCK, print data signal SIc, latch signal LATc, change signal CHc, and voltage VHV_H, the drive signal selection circuit 200c generates a drive signal VOUTc by selecting or deselecting the drive signal COMc.

[0031] The drive signal VOUTc is supplied to one end of the piezoelectric element 60c included in each of the multiple ejection units 600c. A reference voltage signal VBSc is supplied to the other end of the piezoelectric element 60c. The piezoelectric element 60c is then driven by the potential difference between the drive signal VOUTc and the reference voltage signal VBSc, causing ink to be ejected from the ejection unit 600c. In other words, the liquid ejection module 21c has a piezoelectric element 60c driven by a drive signal COMc and a drive signal selection circuit 200c that controls the supply of the drive signal COMc to the piezoelectric element 60c.

[0032] The liquid dispensing module 21d has a drive signal selection circuit 200d and a plurality of dispensing units 600d. Each dispensing unit 600d also includes a piezoelectric element 60d. The drive signal selection circuit 200d receives a clock signal SCK, a print data signal SId, a latch signal LATd, a change signal CHd, a drive signal COMd, and a voltage VHV_H as inputs. Based on the clock signal SCK, print data signal SId, latch signal LATd, change signal CHd, and voltage VHV_H, the drive signal selection circuit 200d generates a drive signal VOUTd by selecting or deselecting the drive signal COMd.

[0033] The drive signal VOUTd is supplied to one end of the piezoelectric element 60d included in each of the multiple ejection units 600d. A reference voltage signal VBSd is supplied to the other end of the piezoelectric element 60d. The piezoelectric element 60d is driven by the potential difference between the drive signal VOUTd and the reference voltage signal VBSd, causing ink to be ejected from the ejection unit 600d. In other words, the liquid ejection module 21d has a piezoelectric element 60d driven by a drive signal COMd, and a drive signal selection circuit 200d that controls the supply of the drive signal COMd ​​to the piezoelectric element 60d.

[0034] In the following explanation, drive circuits 51a, 51b, 51c, and 51d have similar configurations and may be referred to as drive circuit 51 unless otherwise specified. The various signals input to drive circuit 51 are referred to as voltage VHV, drive data signal DATA, and clock signal MCK. The various signals output from drive circuit 51 are referred to as drive signal COM and reference voltage signal VBS.

[0035] Furthermore, the liquid discharge modules 21a, 21b, 21c, and 21d have a similar configuration, in particular When there is no need to distinguish, it will be referred to as the liquid discharge module 21. Furthermore, the liquid discharge module 21 will be described as having a drive signal selection circuit 200 and a plurality of discharge units 600, the plurality of discharge units 600 including a piezoelectric element 60. In this case, the various signals input to the liquid discharge module 21 will be referred to as the clock signal SCK, the print data signal SI, the latch signal LAT, the change signal CH, the drive signal COM, the reference voltage signal VBS, and the voltage VHV_H. The signal supplied to the piezoelectric element 60 will be referred to as the drive signal VOUT.

[0036] 1-3. Configuration and Operation of the Liquid Dispensing Module Next, the configuration and operation of the drive signal selection circuit 200 will be described. To explain the configuration and operation of the drive signal selection circuit 200, first, an example of the drive signal COM input to the drive signal selection circuit 200 will be described using Figure 3. Then, the configuration and operation of the drive signal selection circuit 200 will be described using Figures 4 to 7.

[0037] Figure 3 shows an example of the drive signal COM. Figure 3 shows the period T1 from when the latch signal LAT rises until the change signal CH rises, the period T2 from period T1 until the next rise of the change signal CH, and the period T3 from period T2 until the latch signal LAT rises. The period consisting of these periods T1, T2, and T3 is the period Ta for forming a new dot on the medium P. In other words, as shown in Figure 3, the latch signal LAT is a signal that defines the period for forming a new dot on the medium P, and the change signal CH is a signal that defines the switching timing of the waveform included in the drive signal COM.

[0038] As shown in Figure 3, the drive circuit 51 generates a trapezoidal waveform Adp during period T1. When the trapezoidal waveform Adp is supplied to the piezoelectric element 60, a predetermined amount, specifically a moderate amount of ink, is ejected from the corresponding ejection unit 600. The drive circuit 51 also generates a trapezoidal waveform Bdp during period T2. When the trapezoidal waveform Bdp is supplied to the piezoelectric element 60, a small amount of ink, less than the predetermined amount, is ejected from the corresponding ejection unit 600. The drive circuit 51 also generates a trapezoidal waveform Cdp during period T3. When the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, the piezoelectric element 60 is driven to the extent that no ink is ejected from the corresponding ejection unit 600. Therefore, when the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, no dots are formed on the medium P. This trapezoidal waveform Cdp is a waveform that prevents the ink near the nozzle opening of the ejection unit 600 from vibrating slightly and thus prevents an increase in ink viscosity. In the following explanation, driving the piezoelectric element 60 to the extent that ink is not ejected from the ejection section 600 in order to prevent an increase in ink viscosity is referred to as "micro-vibration."

[0039] Here, the voltage values ​​at the start and end timings of the trapezoidal waveforms Adp, Bdp, and Cdp are all the same at voltage Vc. That is, the trapezoidal waveforms Adp, Bdp, and Cdp are waveforms that start and end at voltage Vc. Therefore, the drive circuit 51 outputs a drive signal COM with a continuous waveform of trapezoidal waveforms Adp, Bdp, and Cdp over period Ta. Note that the waveform of the drive signal COM shown in Figure 3 is just an example, and the waveform of the drive signal COM may be different. Also, drive circuit 51a and drive circuit 51b may generate and output drive signals COM with different waveforms.

[0040] Figure 4 is a block diagram showing the electrical configuration of the drive signal selection circuit 200. The drive signal selection circuit 200 generates and outputs a drive signal VOUT supplied to the piezoelectric element 60 during period Ta by switching whether or not to select the trapezoidal waveforms Adp, Bdp, and Cdp included in the drive signal COM during periods T1, T2, and T3, respectively. As shown in Figure 4, the drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230.

[0041] The selection control circuit 210 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, and a voltage VHV_H. The selection control circuit 210 is supplied with a shift signal. A set of shift register 212 (S / R), latch circuit 214, and decoder 216 is provided corresponding to each of the output units 600. In other words, the head unit 20 is provided with the same number of sets of shift register 212, latch circuit 214, and decoder 216 as the total number n of output units 600.

[0042] The shift register 212 temporarily holds the 2 bits of print data [SIH, SIL] contained in the print data signal SI for each corresponding ejector unit 600. Specifically, the number of shift registers 212 corresponding to the number of ejector units 600 are connected in cascaded order, and the serially supplied print data signal SI is sequentially transferred to the subsequent stages according to the clock signal SCK. In Figure 4, the shift registers 212 are labeled as 1st stage, 2nd stage, ..., nth stage in order from the upstream side to which the print data signal SI is supplied, in order to distinguish them.

[0043] Each of the n latch circuits 214 latches the print data [SIH,SIL] held in the corresponding shift register 212 on the rising edge of the latch signal LAT. Each of the n decoders 216 decodes the 2-bit print data [SIH,SIL] latched by the corresponding latch circuit 214 to generate a selection signal S, which is supplied to the selection circuit 230.

[0044] A selection circuit 230 is provided corresponding to each of the output units 600. That is, the number of selection circuits 230 in one head unit 20 is the same as the total number n of output units 600 included in the head unit 20. Based on the selection signal S supplied from the decoder 216, the selection circuit 230 controls the supply of the drive signal COM to the piezoelectric element 60.

[0045] Figure 5 is a circuit diagram showing the electrical configuration of the selection circuit 230 corresponding to one discharge unit 600. As shown in Figure 5, the selection circuit 230 has an inverter 232 and a transfer gate 234. The transfer gate 234 also includes transistor 235, which is an NMOS transistor, and transistor 236, which is a PMOS transistor.

[0046] The selection signal S is supplied from the decoder 216 to the gate terminal of transistor 235. The selection signal S is also logically inverted by the inverter 232 and supplied to the gate terminal of transistor 236. The drain terminal of transistor 235 and the source terminal of transistor 236 are connected to terminal TG-In, which is one end of the circuit. The drive signal COM is input from terminal TG-In. When transistors 235 and 236 are controlled to be on or off according to the selection signal S, the drive signal VOUT is output from terminal TG-Out, which is the other end to which the source terminal of transistor 235 and the drain terminal of transistor 236 are commonly connected. Terminal TG-Out is electrically connected to electrode 611 of piezoelectric element 60, which will be described later. In the following description, when transistors 235 and 236 are controlled to be conductive, they are referred to as "on," and when transistors 235 and 236 are controlled to be non-conductive, they are referred to as "off."

[0047] Next, the decoding process of decoder 216 will be explained using Figure 6. Figure 6 shows the decoding process in decoder 216. Decoder 216 receives 2-bit print data [SIH,SIL], a latch signal LAT, and a change signal CH as inputs. Decoder 216 then outputs a selection signal S that is at H,L,L levels for periods T1, T2, and T3, for example, when the print data [SIH,SIL] is [1,0] which defines a "middle dot". Here, the logic level of the selection signal S is level-shifted to a high-amplitude logic based on the voltage VHV_H by a level shifter (not shown).

[0048] Figure 7 is a diagram illustrating the operation of the drive signal selection circuit 200. As shown in Figure 7, the print data signal SI is supplied serially to the drive signal selection circuit 200 in synchronization with the clock signal SCK, and is sequentially transferred in the shift register 212 corresponding to the ejection unit 600. When the supply of the clock signal SCK stops, each of the shift registers 212 holds the print data [SIH, SIL] corresponding to the ejection unit 600. The print data signal SI is supplied in the order corresponding to the last n stages, ..., 2nd stage, 1st stage of the ejection unit 600 in the shift register 212.

[0049] Here, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the corresponding shift register 212. LT1, LT2, ..., LTn shown in Figure 7 represent the print data [SIH,SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stage shift registers 212.

[0050] The decoder 216 outputs a logic level selection signal S in each of the periods T1, T2, and T3, according to the content shown in Figure 6, depending on the size of the dots defined in the latched print data [SIH, SIL].

[0051] When the print data [SIH,SIL] is [1,1], the selection circuit 230 selects trapezoidal waveform Adp during period T1, trapezoidal waveform Bdp during period T2, and does not select trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, a drive signal VOUT corresponding to the large dot shown in Figure 7 is generated. Therefore, a medium amount of ink and a small amount of ink are ejected from the ejection unit 600. Thus, a large dot is formed on the medium P by the adhesion of this ink. Also, when the print data [SIH,SIL] is [1,0], the selection circuit 230 selects trapezoidal waveform Adp during period T1, does not select trapezoidal waveform Bdp during period T2, and does not select trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, a drive signal VOUT corresponding to the medium dot shown in Figure 7 is generated. Therefore, a medium amount of ink is ejected from the ejection unit 600. Thus, a medium dot is formed on the medium P. Furthermore, when the print data [SIH,SIL] is [0,1], the selection circuit 230, according to the selection signal S, does not select trapezoidal waveform Adp during period T1, selects trapezoidal waveform Bdp during period T2, and does not select trapezoidal waveform Cdp during period T3. As a result, a drive signal VOUT corresponding to the small dots shown in Figure 7 is generated. Therefore, a small amount of ink is ejected from the ejection unit 600. Thus, small dots are formed on the medium P. Also, when the print data [SIH,SIL] is [0,0], the selection circuit 230, according to the selection signal S, does not select trapezoidal waveform Adp during period T1, does not select trapezoidal waveform Bdp during period T2, and selects trapezoidal waveform Cdp during period T3. As a result, a drive signal VOUT corresponding to the micro-vibrations shown in Figure 7 is generated. Therefore, no ink is ejected from the ejection unit 600, and micro-vibrations occur.

[0052] Here, the configuration and operation of the discharge section 600, including the piezoelectric element 60, will be explained using Figure 8. Figure 8 is a cross-sectional view showing the schematic configuration of the discharge section 600 when the liquid discharge module 21 is cut to include the discharge section 600.

[0053] As shown in Figure 8, the liquid dispensing module 21 includes a dispensing unit 600 and a reservoir 641. Ink is introduced into the reservoir 641 from the supply port 661. Furthermore, a separate reservoir 641 is provided for each ink color.

[0054] The discharge section 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651. The diaphragm 621 is provided between the cavity 631 and the piezoelectric element 60. The diaphragm 621 is displaced by the movement of the piezoelectric element 60, which is provided on its upper surface. The diaphragm 621 functions as a diaphragm that expands / contracts the internal volume of the cavity 631 by displacing. The cavity 631 is filled with ink. The cavity 631 also functions as a pressure chamber whose internal volume changes when driven by the piezoelectric element 60. The nozzle 651 is provided on the nozzle plate 632 and is an opening that communicates with the cavity 631.

[0055] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. A drive signal VOUT is supplied to electrode 611, and a reference voltage signal VBS is supplied to electrode 612. A piezoelectric element 60 with this structure is driven according to the potential difference between electrode 611 and electrode 612. As the piezoelectric element 60 is driven, the electrodes 611 and 612 and the central part of the diaphragm 621 are displaced vertically relative to the ends. As the diaphragm 621 is displaced, the internal volume of the cavity 631 changes, and the ink filled inside the cavity 631 is ejected from the nozzle 651.

[0056] Here, as described above, the drive signal VOUTa is a signal in which at least a portion of the waveform of the drive signal COMa is selected, the piezoelectric element 60a is driven by the drive signal COMa, and the ejection unit 600a ejects ink to the medium P in response to the drive of the piezoelectric element 60a. Similarly, the drive signal VOUTb is a signal in which at least a portion of the waveform of the drive signal COMb is selected, the piezoelectric element 60b is driven by the drive signal COMb, and the ejection unit 600b ejects ink to the medium P in response to the drive of the piezoelectric element 60b. Similarly, the drive signal VOUTc is a signal in which at least a portion of the waveform of the drive signal COMc is selected, the piezoelectric element 60c is driven by the drive signal COMc, and the ejection unit 600c ejects ink to the medium P in response to the drive of the piezoelectric element 60c. Similarly, the drive signal VOUTd is a selected signal in which at least a portion of the waveform of the drive signal COMd ​​is selected, the piezoelectric element 60d is driven by the drive signal COMd, and the ejection unit 600d ejects ink to the medium P in response to the drive of the piezoelectric element 60d.

[0057] 1-4. Circuit configuration and operation of the drive circuit board Next, the circuit configuration and operation of the drive circuit board 50 will be described. Figure 9 is a block diagram showing the circuit configuration of the drive circuit board 50. As shown in Figure 9, the drive circuit board 50 includes overcurrent protection circuits 70a, 70b, 70c, logic circuits 71a, 71b, 71c, 71d, resistors 72, 73, 74, power supply wiring 75a, 75b, 75c, capacitors 76a, 76b, 76c, and a start control circuit 80.

[0058] Power supply wiring 75a connects the power supply circuit 90 shown in Figure 2 to the print head 22, and voltage VHV_H is supplied to the print head 22 via power supply wiring 75a. Power supply wiring 75b connects the power supply circuit 90 to the drive circuits 51a and 51b, and voltage VHV_A1 is supplied to the drive circuits 51a and 51b via power supply wiring 75b. Power supply wiring 75c connects the power supply circuit 90 to the drive circuits 51c and 51d, and voltage VHV_A1 is supplied to the drive circuits 51c and 51d via power supply wiring 75c.

[0059] In this embodiment, the voltage VHV_A1 supplied to the drive circuits 51a and 51b is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22. Similarly, the voltage VHV_A2 supplied to the drive circuits 51c and 51d is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22.

[0060] Capacitor 76a is connected between power supply wiring 75a and ground. Capacitor 76b is connected between power supply wiring 75b and ground. Capacitor 76c is connected between power supply wiring 75c and ground. Capacitors 76a,7 6b and 76c are stabilizing capacitors. Since the drive circuits 51a, 51b, 51c, and 51d need to charge and discharge a large number of piezoelectric elements 60 simultaneously, the capacitance value of capacitor 76b connected to power wiring 75b through which the power supply voltage VHV_A1 of drive circuits 51a and 51b propagates, and the capacitance value of capacitor 76c connected to power wiring 75c through which the power supply voltage VHV_A2 of drive circuits 51c and 51d propagates, are greater than the capacitance value of capacitor 76a connected to power wiring 75a through which the power supply voltage VHV_H of the print head 22 propagates.

[0061] The overcurrent protection circuit 70a is provided on the power supply wiring 75a and has a conduction mode in which the power supply circuit 90 and the print head 22 are in a conductive state, and a non-conduction mode in which the power supply circuit 90 and the print head 22 are in a non-conduction state. The overcurrent protection circuit 70a outputs an operation mode signal MD_H that indicates whether the operating mode is the conduction mode or the non-conduction mode. In this embodiment, when the operation mode signal MD_H is at the H level, the operating mode is the conduction mode, and when the operation mode signal MD_H is at the L level, the operating mode is the non-conduction mode.

[0062] The overcurrent protection circuit 70a switches from conduction mode to non-conduction mode when the current flowing through the power supply wiring 75a exceeds a predetermined value while in conduction mode. When the current flowing through the power supply wiring 75a exceeds a predetermined value, the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, so the supply of voltage VHV_H from the power supply circuit 90 to the print head 22 stops, and the operation mode signal MD_H changes from H level to L level.

[0063] Furthermore, the overcurrent protection circuit 70a may also switch from conduction mode to non-conduction mode if the voltage VHV_H output from the power supply circuit 90 falls below a predetermined value when it is in conduction mode. When the voltage VHV_H falls below a predetermined value, the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, so the supply of voltage VHV_H from the power supply circuit 90 to the print head 22 stops, and the operation mode signal MD_H changes from H level to L level.

[0064] The overcurrent protection circuit 70b is provided on the power supply wiring 75b and has a conduction mode in which the power supply circuit 90 and the drive circuits 51a and 51b are in a conduction state, and a non-conduction mode in which the power supply circuit 90 and the drive circuits 51a and 51b are in a non-conduction state. The overcurrent protection circuit 70b outputs an operation mode signal MD_A1 that indicates whether the operating mode is the conduction mode or the non-conduction mode. In this embodiment, when the operation mode signal MD_A1 is at the H level, the operating mode is the conduction mode, and when the operation mode signal MD_A1 is at the L level, the operating mode is the non-conduction mode.

[0065] The overcurrent protection circuit 70b switches from conduction mode to non-conduction mode when the current flowing through the power supply wiring 75b exceeds a predetermined value while in conduction mode. When the current flowing through the power supply wiring 75b exceeds a predetermined value, the overcurrent protection circuit 70b switches from conduction mode to non-conduction mode, so the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b stops, and the operation mode signal MD_A1 changes from H level to L level.

[0066] Furthermore, the overcurrent protection circuit 70b may also switch from conduction mode to non-conduction mode if the voltage VHV_A1 output from the power supply circuit 90 falls below a predetermined value when it is in conduction mode. When the voltage VHV_A1 falls below a predetermined value, the overcurrent protection circuit 70b switches from conduction mode to non-conduction mode, so the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b stops, and the operation mode signal MD_A1 changes from H level to L level.

[0067] Logic circuit 71a receives the operating mode signal MD_H and the operating mode signal MD_A1 as inputs. The logic circuit 71a outputs a VHV abnormality signal VERa. Specifically, when the operation mode signal MD_H and the operation mode signal MD_A1 are at an H level, the logic circuit 71a outputs a L level VHV abnormality signal VERa indicating that both voltages VHV_H and VHV_A1 are normal, and when at least one of the operation mode signal MD_H and the operation mode signal MD_A1 is at an L level, it outputs an H level VHV abnormality signal VERa indicating that at least one of voltages VHV_H and VHV_A1 is abnormal. In other words, the logic circuit 71a is implemented with a 2-input NAND gate. The VHV abnormality signal VERa output from the logic circuit 71a is input to the drive circuit 51a as an error signal ERRa.

[0068] When the error signal ERRa is at a high level, the drive circuit 51a stops outputting the drive waveform of the drive signal COMa. Also, when the error signal ERRa is at a low level, the drive circuit 51a outputs an enable signal ENa to the overcurrent protection circuits 70a and 70b, and when the error signal ERRa is at a high level, it stops outputting the enable signal ENa to the overcurrent protection circuits 70a and 70b. Therefore, when the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, the drive circuit 51a stops outputting the enable signal ENa to the overcurrent protection circuit 70a and also stops outputting the enable signal ENa to the overcurrent protection circuit 70b. Also, when the overcurrent protection circuit 70b switches from conduction mode to non-conduction mode, the drive circuit 51a stops outputting the enable signal ENa to the overcurrent protection circuit 70b and also stops outputting the enable signal ENa to the overcurrent protection circuit 70a.

[0069] In this embodiment, the enable signal ENa is an H-level control signal VHV_CNTa output from the drive circuit 51a, and the drive circuit 51a stops the output of the enable signal ENa by outputting an L-level control signal VHV_CNTa. When the enable signal ENa is input, the overcurrent protection circuits 70a and 70b enter either a conduction mode or a non-conduction mode depending on the current flowing through the power supply wirings 75a and 75b, respectively, and enter a non-conduction mode when the enable signal ENa is not input. Therefore, the overcurrent protection circuit 70b also switches from conduction mode to non-conduction mode when the output of the enable signal ENa from the drive circuit 51a is stopped due to the overcurrent protection circuit 70a switching from conduction mode to non-conduction mode. Similarly, the overcurrent protection circuit 70a also switches from conduction mode to non-conduction mode when the output of the enable signal ENa from the drive circuit 51a is stopped due to the overcurrent protection circuit 70b switching from conduction mode to non-conduction mode. Furthermore, when the enable signal ENa is not input, the overcurrent protection circuits 70a and 70b will not enter conduction mode even if the current flowing through the power supply wirings 75a and 75b falls below a predetermined value.

[0070] Furthermore, the overcurrent protection circuit 70a is switchable from a non-conducting mode to a conduction mode. Specifically, the overcurrent protection circuit 70a switches from a non-conducting mode to a conduction mode when a predetermined signal is input. For example, the predetermined signal may be the enable signal ENa output from the drive circuit 51a. That is, the overcurrent protection circuit 70a may switch from a non-conducting mode to a conduction mode when the control signal VHV_CNTa output from the drive circuit 51a switches from an L level to an H level. Alternatively, after the drive circuit 51a switches the control signal VHV_CNTa from an H level to an L level, it may continue to output the L level control signal VHV_CNTa unless it is reset, and then switch the control signal VHV_CNTa from an L level to an H level when it is reset. In this case, the predetermined signal is a reset signal (not shown).

[0071] Logic circuit 71b receives the operating mode signal MD_A1 as input and outputs the VHV abnormality signal VERb. Specifically, when the operating mode signal MD_A1 is at a high level, logic circuit 71b outputs a low-level VHV abnormality signal VERa indicating that the voltage VHV_A1 is normal, and when the operating mode signal MD_A1 is at a low level, it outputs a low-level VHV abnormality signal VERa indicating that the voltage VHV_A1 is abnormal. It outputs a high-level VHV abnormal signal VERb indicating a certain condition. In other words, logic circuit 71b is implemented using a NOT gate. The VHV abnormal signal VERb output from logic circuit 71b is input to drive circuit 51b as an error signal ERRb.

[0072] The drive circuit 51b stops outputting the drive waveform of the drive signal COMb when the error signal ERRb is at a high level. Also, when the error signal ERRb is at a low level, the drive circuit 51b outputs an enable signal ENb to the overcurrent protection circuit 70b, and when the error signal ERRb is at a high level, it stops outputting the enable signal ENb to the overcurrent protection circuit 70b. Therefore, when the overcurrent protection circuit 70b switches from conduction mode to non-conduction mode, the drive circuit 51b stops outputting the enable signal ENb to the overcurrent protection circuit 70b.

[0073] In this embodiment, the enable signal ENb is an H-level control signal VHV_CNTb output from the drive circuit 51b, and the drive circuit 51b stops outputting the enable signal ENb by outputting an L-level control signal VHV_CNTb. When the enable signal ENb is input, the overcurrent protection circuit 70b enters either a conduction mode or a non-conduction mode depending on the current flowing through the power supply wiring 75b, and when the enable signal ENb is not input, it enters a non-conduction mode. Furthermore, when the enable signal ENb is not input, the overcurrent protection circuit 70b will not enter the conduction mode even if the current flowing through the power supply wiring 75b falls below a predetermined value.

[0074] Furthermore, the overcurrent protection circuit 70b is switchable from a non-conducting mode to a conduction mode. Specifically, the overcurrent protection circuit 70b switches from a non-conducting mode to a conduction mode when a predetermined signal is input. For example, the predetermined signal may be the enable signals ENa and ENb output from the drive circuits 51a and 51b. That is, the overcurrent protection circuit 70b may switch from a non-conducting mode to a conduction mode when the control signals VHV_CNTa and VHV_CNTb output from the drive circuits 51a and 51b both become high level. Alternatively, after switching the control signals VHV_CNTa and VHV_CNTb from high level to low level, the drive circuits 51a and 51b may continue to output the low-level control signals VHV_CNTa and VHV_CNTb until they are reset, and then switch the control signals VHV_CNTa and VHV_CNTb from low level to high level when they are reset. In this case, the specified signal is a reset signal, which is not shown in the diagram.

[0075] The overcurrent protection circuit 70c is provided on the power supply wiring 75c and has a conduction mode in which the power supply circuit 90 and the drive circuits 51c and 51d are in a conduction state, and a non-conduction mode in which the power supply circuit 90 and the drive circuits 51c and 51d are in a non-conduction state. The overcurrent protection circuit 70c outputs an operation mode signal MD_A2 that indicates whether the operating mode is the conduction mode or the non-conduction mode. In this embodiment, when the operation mode signal MD_A2 is at the H level, the operating mode is the conduction mode, and when the operation mode signal MD_A2 is at the L level, the operating mode is the non-conduction mode.

[0076] The overcurrent protection circuit 70c switches from conduction mode to non-conduction mode when the current flowing through the power supply wiring 75c exceeds a predetermined value while in conduction mode. When the current flowing through the power supply wiring 75c exceeds a predetermined value, the overcurrent protection circuit 70c switches from conduction mode to non-conduction mode, so the supply of voltage VHV_A2 from the power supply circuit 90 to the drive circuits 51c and 51d stops, and the operation mode signal MD_A2 changes from high level to low level.

[0077] Furthermore, the overcurrent protection circuit 70c may also switch from conduction mode to non-conduction mode if the voltage VHV_A2 output from the power supply circuit 90 falls below a predetermined value when it is in conduction mode. When the voltage VHV_A2 falls below a predetermined value, the overcurrent protection circuit 70c switches from conduction mode to non-conduction mode, so the voltage VHV_A2 from the power supply circuit 90 to the drive circuits 51c and 51d When the supply of V_A2 is cut off, the operating mode signal MD_A2 changes from a high level to a low level.

[0078] Logic circuit 71c receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERc. Specifically, when the operating mode signal MD_A2 is at a high level, logic circuit 71c outputs a low-level VHV abnormality signal VERc indicating that the voltage VHV_A2 is normal, and when the operating mode signal MD_A2 is at a low level, it outputs a high-level VHV abnormality signal VERc indicating that the voltage VHV_A2 is abnormal. In other words, logic circuit 71c is implemented using a NOT gate. The VHV abnormality signal VERc output from logic circuit 71c is input to the drive circuit 51c as an error signal ERRc.

[0079] The drive circuit 51c stops outputting the drive waveform of the drive signal COMc when the error signal ERRc is at a high level. Furthermore, when the error signal ERRc is at a low level, the drive circuit 51c outputs an enable signal ENc to the overcurrent protection circuit 70c, and when the error signal ERRc is at a high level, it stops outputting the enable signal ENc to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from conduction mode to non-conduction mode, the drive circuit 51c stops outputting the enable signal ENc to the overcurrent protection circuit 70c.

[0080] In this embodiment, the enable signal ENc is a high-level control signal VHV_CNTc output from the drive circuit 51c, and the drive circuit 51c stops outputting the enable signal ENc by outputting a low-level control signal VHV_CNTc. When the enable signal ENc is input, the overcurrent protection circuit 70c enters either a conduction mode or a non-conduction mode depending on the current flowing through the power supply wiring 75c, and when the enable signal ENc is not input, it enters a non-conduction mode. Furthermore, when the enable signal ENc is not input, the overcurrent protection circuit 70c will not enter the conduction mode even if the current flowing through the power supply wiring 75c falls below a predetermined value.

[0081] The logic circuit 71d receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERd. Specifically, when the operating mode signal MD_A2 is at a high level, the logic circuit 71d outputs a low-level VHV abnormality signal VERd indicating that the voltage VHV_A2 is normal, and when the operating mode signal MD_A2 is at a low level, it outputs a high-level VHV abnormality signal VERd indicating that the voltage VHV_A2 is abnormal. In other words, the logic circuit 71d is implemented using a NOT gate. The VHV abnormality signal VERd output from the logic circuit 71d is input to the drive circuit 51d as an error signal ERRd.

[0082] The drive circuit 51d stops outputting the drive waveform of the drive signal COMd ​​when the error signal ERRd is at a high level. Also, when the error signal ERRd is at a low level, the drive circuit 51d outputs an enable signal ENd to the overcurrent protection circuit 70c, and when the error signal ERRd is at a high level, it stops outputting the enable signal ENd to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from conduction mode to non-conduction mode, the drive circuit 51d stops outputting the enable signal ENd to the overcurrent protection circuit 70c.

[0083] In this embodiment, the enable signal ENd is a high-level control signal VHV_CNTd output from the drive circuit 51d, and the drive circuit 51d stops outputting the enable signal ENd by outputting a low-level control signal VHV_CNTd. When the enable signal ENd is input, the overcurrent protection circuit 70c enters either a conduction mode or a non-conduction mode depending on the current flowing through the power supply wiring 75c, and when the enable signal ENd is not input, it enters a non-conduction mode. Furthermore, when the enable signal ENd is not input, the overcurrent protection circuit 70c will not enter the conduction mode even if the current flowing through the power supply wiring 75c falls below a predetermined value.

[0084] Furthermore, the overcurrent protection circuit 70c is switchable from a non-conducting mode to a conduction mode. Specifically, the overcurrent protection circuit 70c switches from a non-conducting mode to a conduction mode when a predetermined signal is input. For example, the predetermined signal may be the enable signals ENc and ENd output from the drive circuits 51c and 51d. That is, the overcurrent protection circuit 70c may switch from a non-conducting mode to a conduction mode when both the control signal VHV_CNTc output from the drive circuit 51c and the control signal VHV_CNTd output from the drive circuit 51d become high level. Alternatively, after switching the control signals VHV_CNTc and VHV_CNTd from high level to low level, the drive circuits 51c and 51d may continue to output the low-level control signals VHV_CNTc and VHV_CNTd until they are reset, and then switch the control signals VHV_CNTc and VHV_CNTd from low level to high level once they are reset. In this case, the specified signal is a reset signal, which is not shown in the diagram.

[0085] As shown in Figure 9, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd are actually electrically connected to each other. Instead of outputting L-level control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd, the drive circuits 51a, 51b, 51c, and 51d set each of these terminals to high impedance (Hi-Z), and the pull-down resistors 72 make the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd L-level. Furthermore, if at least one of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd is H-level, a common enable signal is input to the overcurrent protection circuits 70a, 70b, and 70c. On the other hand, if all of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd reach the L level, the input of these enable signals to the overcurrent protection circuits 70a, 70b, and 70c is stopped.

[0086] Since the overcurrent protection circuits 70a, 70b, and 70c have similar configurations, they will be referred to as the overcurrent protection circuit 70, and an example of its configuration will be described. In the description of the example configuration of the overcurrent protection circuit 70, voltages VHV_H, VHV_A1, and VHV_A2 will be referred to as voltage VHV, operating mode signals MD_H, MD_A1, and MD_A2 will be referred to as operating mode signals MD, and control signals VHV_CNTa, HV_CNTb, HV_CNTc, and HV_CNTd will be referred to as control signals VHV_CNT.

[0087] Figure 10 shows an example configuration of the overcurrent protection circuit 70. As shown in Figure 10, the overcurrent protection circuit 70 includes an electronic fuse IC 700 and resistors 701 and 702. The electronic fuse IC 700 has a Vin terminal, a Vout terminal, a UVLO terminal, a P-Good terminal, and an EN terminal. The Vin terminal is a voltage input terminal, and the Vout terminal is a voltage output terminal. The UVLO terminal is a terminal for detecting a drop in input voltage, and the P-Good terminal is an output terminal that indicates the state of the input voltage. The EN terminal is an enable terminal.

[0088] The electronic fuse IC700 operates when the EN terminal is at a low level and the control signal VHV_CNT is at a high level. If the current flowing through the Vin terminal is greater than or equal to a predetermined value, the electronic fuse IC700 deconnects the Vin terminal and the Vout terminal and outputs a low-level signal from the P-Good terminal. Furthermore, if the voltage input to the UVLO terminal is less than or equal to a predetermined value, the electronic fuse IC700 deconnects the Vin terminal and the Vout terminal and outputs a low-level signal from the P-Good terminal. Additionally, if the current flowing through the Vin terminal is less than a predetermined value and the voltage input to the UVLO terminal is higher than a predetermined value, the electronic fuse IC700 connects the Vin terminal and the Vout terminal and outputs a high-level signal from the P-Good terminal.

[0089] The control signal VHV_CNT is input to the EN terminal. The Vin terminal is connected to the power supply circuit 90 by power supply wiring, and the Vout terminal is connected to the print head 22 or the drive circuit 51 by power supply wiring. The voltage VHV is input to the Vin terminal. Resistors 701 and 702 are connected in series between the Vin terminal and ground, and the connection node between resistors 701 and 702 is connected to the UVLO terminal. Therefore, the voltage VHV is divided by resistors 701 and 702 and input to the UVLO terminal. The overcurrent protection circuit 70 configured in this way realizes the aforementioned functions.

[0090] Returning to the explanation of Figure 9, the drive circuit 51a monitors the voltage VHV_H supplied to the print head 22 via the power supply wiring 75a. If the voltage VHV_H is higher than a predetermined voltage, the drive circuit 51a outputs an L-level error signal ERRa, and if the voltage VHV_H falls below the predetermined voltage, it outputs an H-level error signal ERRa and stops the output of the drive waveform of the drive signal COMa. The H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90, and the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is at the H level. For example, when the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, the voltage VHV_H monitored by the drive circuit 51a falls below the predetermined voltage, so the drive circuit 51a outputs an H-level error signal ERRa. The drive circuit 51a may output an H-level error signal ERRa and an L-level control signal VHV_CNTa when the voltage VHV_H falls below a predetermined voltage.

[0091] Furthermore, the drive circuit 51b monitors the voltage VHV_A1 supplied to the drive circuits 51a and 51b via the power supply wiring 75b. When the voltage VHV_A1 is higher than a predetermined voltage, the drive circuit 51b outputs an L-level error signal ERRb, and when the voltage VHV_A1 falls below the predetermined voltage, it outputs an H-level error signal ERRb and stops the output of the drive waveform of the drive signal COMb. The H-level error signal ERRb is a signal that stops the output of the voltage VHV_A1 from the power supply circuit 90, and the power supply circuit 90 stops the output of the voltage VHV_A1 when the error signal ERRb is at the H level. For example, when the overcurrent protection circuit 70b switches from conduction mode to non-conduction mode, the voltage VHV_A1 monitored by the drive circuit 51b falls below the predetermined voltage, so the drive circuit 51b outputs an H-level error signal ERRb. The drive circuit 51b may output an H-level error signal ERRb and an L-level control signal VHV_CNTb when the voltage VHV_A1 falls below a predetermined voltage.

[0092] Furthermore, the drive circuit 51c monitors the voltage VHV_A2 supplied to the drive circuits 51c and 51d via the power supply wiring 75c. If the voltage VHV_A2 is higher than a predetermined voltage, the drive circuit 51c outputs an L-level error signal ERRc, and if the voltage VHV_A2 falls below the predetermined voltage, it outputs an H-level error signal ERRc and stops outputting the drive waveform of the drive signal COMc. Similarly, the drive circuit 51d monitors the voltage VHV_A2 supplied to the drive circuits 51c and 51d via the power supply wiring 75c. If the voltage VHV_A2 is higher than a predetermined voltage, the drive circuit 51d outputs an L-level error signal ERRd, and if the voltage VHV_A2 falls below the predetermined voltage, it outputs an H-level error signal ERRd and stops outputting the drive waveform of the drive signal COMd. Furthermore, the H-level error signals ERRc and ERRd are signals that stop the output of the voltage VHV_A2 from the power supply circuit 90, and the power supply circuit 90 stops the output of the voltage VHV_A2 when at least one of the error signals ERRc and ERRd is at the H level. For example, when the overcurrent protection circuit 70c switches from conduction mode to non-conduction mode, the voltage VHV_A2 monitored by the drive circuits 51c and 51d falls below a predetermined voltage, so the drive circuits 51c and 51d output the H-level error signals ERRc and ERRd, respectively. If the voltage falls below a predetermined level, the system may output high-level error signals ERRc and ERRd, respectively, and low-level control signals VHV_CNTc and VHV_CNTd, respectively.

[0093] As shown in Figure 9, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output the error signals ERRa, ERRb, ERRc, and ERRd are actually electrically connected to each other. Instead of outputting L-level error signals ERRa, ERRb, ERRc, and ERRd, the drive circuits 51a, 51b, 51c, and 51d set each of these terminals to Hi-Z, and the pull-down resistors 73 make the error signals ERRa, ERRb, ERRc, and ERRd L-level. If all of the error signals ERRa, ERRb, ERRc, and ERRd are L-level, the error signal input to the power supply circuit 90 will be L-level. On the other hand, if at least one of the error signals ERRa, ERRb, ERRc, and ERRd is H-level, the error signal input to the power supply circuit 90 will be H-level, and the power supply circuit 90 will stop outputting voltages VHV_H, VHV_A1, and VHVA2.

[0094] Furthermore, the terminal on which drive circuit 51a outputs the error signal ERRa is also an input terminal. When the voltage at this terminal switches from L level to H level, drive circuit 51a stops outputting the drive waveform of drive signal COMa and outputs an L-level control signal VHV_CNTa. Similarly, the terminal on which drive circuit 51b outputs the error signal ERRb is also an input terminal. When the voltage at this terminal switches from L level to H level, drive circuit 51b stops outputting the drive waveform of drive signal COMb and outputs an L-level control signal VHV_CNTb. Similarly, the terminal on which drive circuit 51c outputs the error signal ERRc is also an input terminal. When the voltage at this terminal switches from L level to H level, drive circuit 51c stops outputting the drive waveform of drive signal COMc and outputs an L-level control signal VHV_CNTc. Similarly, the terminal on which the drive circuit 51d outputs the error signal ERRd is also an input terminal. When the voltage at this terminal switches from L level to H level, the drive circuit 51d stops outputting the drive waveform of the drive signal COMd ​​and outputs the L-level control signal VHV_CNTd. Therefore, when all error signals ERRa, ERRb, ERRc, and ERRd are at the L level, if at least one of the error signals ERRa, ERRb, ERRc, and ERRd switches from L level to H level, the output of the drive waveforms of the drive signals COMa, COMb, COMc, and COMd ​​to the print head 22 stops, and the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd all become L level. As a result, the overcurrent protection circuits 70a, 70b, and 70c all enter non-conducting mode.

[0095] Furthermore, drive circuit 51a outputs a status signal BUSYa indicating the operating state of drive circuit 51a. Similarly, drive circuit 51b outputs a status signal BUSYb indicating the operating state of drive circuit 51b. Similarly, drive circuit 51c outputs a status signal BUSYc indicating the operating state of drive circuit 51c. Similarly, drive circuit 51d outputs a status signal BUSYd indicating the operating state of drive circuit 51d. Drive circuits 51a, 51b, 51c, and 51d output H-level status signals BUSYa, BUSYb, BUSYc, and BUSYd respectively when in a predetermined state, and L-level status signals BUSYa, BUSYb, BUSYc, and BUSYd respectively when not in a predetermined state. The status signals BUSYa, BUSYb, BUSYc, and BUSYd are output to the control circuit 100 of the control unit 10, and the control circuit 100 determines the state of the drive circuits 51a, 51b, 51c, and 51d based on the status signals BUSYa, BUSYb, BUSYc, and BUSYd.

[0096] As shown in Figure 9, in reality, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output status signals BUSYa, BUSYb, BUSYc, and BUSYd are electrically connected to each other. Instead of outputting L-level status signals BUSYa, BUSYb, BUSYc, and BUSYd, the drive circuits 51a, 51b, 51c, and 51d each By setting the terminal to Hi-Z, the pull-down resistor 74 causes the status signals BUSYa, BUSYb, BUSYc, and BUSYd to be at a low level. Furthermore, if all of the status signals BUSYa, BUSYb, BUSYc, and BUSYd are at a low level, the status signal input to the control circuit 100 will be at a low level. On the other hand, if at least one of the status signals BUSYa, BUSYb, BUSYc, and BUSYd is at a high level, the status signal input to the control circuit 100 will be at a high level, and the control circuit 100 will determine the state of the drive circuits 51a, 51b, 51c, and 51d based on that status signal.

[0097] Here, if the drive signals COMa, COMb, COMc, and COMd ​​are being supplied to the print head 22, and the supply of voltage VHV_H to the print head 22 stops, or if the voltage VHV_H drops, then parasitic diodes between the drive signal wiring through which the drive signals COMa, COMb, COMc, and COMd ​​propagate and the power supply wiring through which the voltage VHV_H propagates may cause excessive current to flow from the drive signal wiring to the power supply wiring, potentially causing the print head 22 to malfunction.

[0098] While the drive circuit 51a is monitoring the voltage VHV_H, if the voltage VHV_H drops, it outputs an H-level error signal ERRa, which immediately stops the output of the drive waveforms COMa, COMb, COMc, and COMd ​​to the print head 22, making it unlikely that the print head 22 will fail. Conversely, if the voltage VHV_H drops before the drive circuit 51a starts monitoring the voltage VHV_H, and at least one of the drive waveforms COMa, COMb, COMc, and COMd ​​is output to the print head 22, the print head 22 may fail. Therefore, in this embodiment, the drive circuit board 50 includes a startup control circuit 80 that controls the startup of the drive circuits 51a, 51b, 51c, and 51d. When the head unit 20 starts up, the startup control circuit 80 starts the drive circuit 51a, which monitors the voltage VHV_H, first among the drive circuits 51a, 51b, 51c, and 51d. In other words, the startup control circuit 80 starts the startup sequence of the drive circuit 51a, and then starts the startup sequences of the drive circuits 51b, 51c, and 51d.

[0099] In this embodiment, the startup control circuit 80 receives the drive data signals DATAa, DATAb, DATAc, and DATAd output by the control circuit 100, and outputs data signals DATAXa, DATAXb, DATAXc, and DATAXd, which correspond to each of the drive data signals DATAa, DATAb, DATAc, and DATAd. That is, the startup control circuit 80 converts the drive data signals DATAa, DATAb, DATAc, and DATAd into data signals DATAXa, DATAXb, DATAXc, and DATAXd, respectively, in a format that matches the input specifications of the drive circuits 51a, 51b, 51c, and 51d, and outputs them. The data signals DATAXa, DATAXb, DATAXc, and DATAXd are input to the drive circuits 51a, 51b, 51c, and 51d, respectively. As mentioned above, the drive data signals DATAa, DATAb, DATAc, and DATAd are used to generate the drive signals COMa, COMb, COMc, and COMd. In practice, the drive circuits 51a, 51b, 51c, and 51d generate the drive signals COMa, COMb, COMc, and COMd ​​respectively based on the data signals DATAXa, DATAXb, DATAXc, and DATAXd.

[0100] Furthermore, the drive data signals DATAa, DATAb, DATAc, and DATAd are also used as commands to instruct the start of the drive circuits 51a, 51b, 51c, and 51d. For example, the control circuit 100 may output a command to instruct the start of drive circuit 51a as the drive data signal DATAa, and after a predetermined time has elapsed, output commands to instruct the start of drive circuits 51b, 51c, and 51d as the drive data signals DATAb, DATAc, and DATAd. In this case, the control circuit 100 can simply convert the format of the drive data signals DATAa, DATAb, DATAc, and DATAd to output data signals DATAXa, DATAXb, DATAXc, and DATAXd, thereby setting the start sequence of drive circuit 51a to drive cycle The startup sequence for circuits 51b, 51c, and 51d is initiated prior to the startup sequences for circuits 51b, 51c, and 51d. Alternatively, if at least one of the commands instructing the startup of drive circuits 51b, 51c, and 51d is input as drive data signals DATAb, DATAc, and DATAd before a command instructing the startup of drive circuit 51a as drive data signal DATAa is input to the control circuit 100, the control circuit 100 may wait to output data signals DATAXb, DATAXc, and DATAXd until a command instructing the startup of drive circuit 51a as drive data signal DATAa is input and data signal DATAXa is output. This ensures that the startup sequence for drive circuit 51a is initiated prior to the startup sequences for drive circuits 51b, 51c, and 51d.

[0101] Furthermore, if the format of the drive data signals DATAa, DATAb, DATAc, and DATAd matches the input specifications of the drive circuits 51a, 51b, 51c, and 51d, the startup control circuit 80 may output the data signals DATAXa, DATAXb, DATAXc, and DATAXd without format conversion, or the drive circuit board 50 may not include the startup control circuit 80, and the control circuit 100 may function as the startup control circuit 80.

[0102] 1-5. Drive Circuit Configuration Next, the configurations of the drive circuits 51a, 51b, 51c, and 51d will be described using Figure 11. In Figure 11, drive circuits 51a and 51b will not be distinguished and will be described as drive circuit 51. Figure 11 is a block diagram showing the configuration of drive circuit 51. Drive circuit 51 includes an integrated circuit 500, a drive signal amplification circuit 550, and resistors 555 and 556.

[0103] The integrated circuit 500 includes an amplification control signal generation circuit 502, a voltage generation circuit 400, an oscillation circuit 410, a clock selection circuit 420, an anomaly detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input / output circuit 480, and an error signal input / output circuit 490.

[0104] The voltage generation circuit 400 generates the voltage GVDD based on the voltage VHV. The voltage GVDD is, for example, a 7.5V DC voltage signal and is input to various components of the integrated circuit 500, including the gate drive unit 540, which will be described later.

[0105] The amplification control signal generation circuit 502 generates amplification control signals Hgd and Lgd based on a data signal that defines the waveform of the drive signal COM included in the drive data signal DATAX input from terminal DATA-In. The amplification control signal generation circuit 502 includes a DAC interface (DAC_I / F: Digital to Analog Converter Interface) 510, a DAC section 520, a modulation section 530, and a gate drive section 540.

[0106] The DAC interface 510 receives the drive data signal DATAX supplied from the DATA-In terminal and the clock signal MCK supplied from the MCK-In terminal. The DAC interface 510 integrates the drive data signal DATAX based on the clock signal MCK to generate, for example, 10-bit drive data dA that defines the waveform of the drive signal COM. The DAC unit 520 receives the drive data dA as input. The DAC unit 520 converts the input drive data dA into an analog base drive signal aA. This base drive signal aA is the target signal before amplification of the drive signal COM. The modulation unit 530 receives the base drive signal aA as input. The modulation unit 530 outputs a modulated signal Ms obtained by applying pulse width modulation to the base drive signal aA. The gate drive unit 540 receives the voltages VHV and GVDD and the modulated signal Ms as input. The gate drive unit 540 amplifies the input modulated signal Ms based on the voltage GVDD and generates an amplified control signal Hgd, which is level-shifted to a high-amplitude logic based on the voltage VHV, and an amplified control signal Lgd, which inverts the logic level of the input modulated signal Ms and amplifies it based on the voltage GVDD. That is, the amplified control signal Hgd and the amplified control signal Lgd are mutually exclusive to the high level. The amplified control signal Hgd is transmitted to the integrated circuit 5 via terminal Hg-Out. The signal is output from terminal 00 and input to the drive signal amplification circuit 550. Similarly, the amplification control signal Lgd is output from the integrated circuit 500 via terminal Lg-Out and input to the drive signal amplification circuit 550.

[0107] The drive signal amplification circuit 550 outputs a drive signal COM by operating based on the amplification control signals Hgd and Lgd. The drive signal amplification circuit 550 includes transistors 551 and 552, a coil 553, and a capacitor 554. Note that transistors 551 and 552 are, for example, N-channel type FETs (Field Effect Transistors).

[0108] A voltage VHV is supplied to the drain terminal of transistor 551. An amplification control signal Hgd is supplied to the gate terminal of transistor 551 via terminal Hg-Out. The source terminal of transistor 551 is electrically connected to the drain terminal of transistor 552. In addition, an amplification control signal Lgd is supplied to the gate terminal of transistor 552 via terminal Lg-Out. The source electrode of transistor 552 is connected to ground. Transistor 551, connected in this manner, operates according to the amplification control signal Hgd, and transistor 552 operates according to the amplification control signal Lgd. That is, transistors 551 and 552 are exclusively turned on. As a result, an amplified modulated signal is generated at the connection point between the source terminal of transistor 551 and the drain terminal of transistor 552, which is obtained by amplifying the modulation signal Ms based on the voltage VHV.

[0109] One end of coil 553 is connected to the source terminal of transistor 551 and the drain terminal of transistor 552. The other end of coil 553 is connected to one end of capacitor 554. The other end of capacitor 554 is connected to ground. In other words, coil 553 and capacitor 554 constitute a low-pass filter. When an amplified and modulated signal is supplied to this low-pass filter, the amplified and modulated signal is demodulated, and a drive signal COM is generated. The drive circuit 51 then outputs the drive signal COM generated as described above.

[0110] In the following description, the configuration including the amplification control signal generation circuit 502 and the drive signal amplification circuit 550 included in the integrated circuit 500 may be referred to as the drive signal generation circuit 501, which generates a drive signal COM based on the drive data signal DATAX.

[0111] The oscillator circuit 410 generates and outputs a clock signal LCK that defines the operating timing of the integrated circuit 500. The clock signal LCK is input to the clock selection circuit 420 and the anomaly detection circuit 430.

[0112] The clock selection circuit 420 receives the clock signals MCK, LCK and the clock selection signal CSW as inputs. Based on the logic level of the clock selection signal CSW, the clock selection circuit 420 switches whether to output the clock signal MCK as the clock signal RCK to the register control circuit 440, or to output the clock signal LCK as the clock signal RCK to the register control circuit 440. In this embodiment, the clock selection circuit 420 outputs the clock signal MCK as the clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a high level, and outputs the clock signal LCK as the clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a low level.

[0113] The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431, an operation abnormality detection unit 432, and a power supply voltage abnormality detection unit 433.

[0114] The oscillation abnormality detection unit 431 receives the clock signal LCK output by the oscillation circuit 410. The oscillation anomaly detection unit 431 detects whether the input clock signal LCK is normal or not, and outputs a logic-level clock selection signal CSW and an error signal NES based on the detection result. For example, the oscillation anomaly detection unit 431 detects at least one of the frequency and voltage level of the clock signal LCK. If at least one of the frequency and voltage level of the clock signal LCK is abnormal, the oscillation anomaly detection unit 431 outputs a high-level clock selection signal CSW to the clock selection circuit 420 and a high-level error signal NES to the register control circuit 440. If both the frequency and voltage level of the clock signal LCK are normal, the oscillation anomaly detection unit 431 outputs a low-level clock selection signal CSW to the clock selection circuit 420 and a low-level error signal NES to the register control circuit 440.

[0115] The malfunction detection unit 432 receives an operation status signal ASS indicating the operating status of various components of the drive circuit 51. Based on the logic level of the input operation status signal ASS, the malfunction detection unit 432 detects whether or not the various components of the drive circuit 51 are operating normally. In this embodiment, if any of the various components of the drive circuit 51 are abnormal, an H-level operation status signal ASS is input to the malfunction detection unit 432. When an H-level operation status signal ASS is input, the malfunction detection unit 432 outputs an H-level error signal NES to the register control circuit 440.

[0116] The power supply voltage abnormality detection unit 433 receives the voltage VHV as input. The power supply voltage abnormality detection unit 433 then detects the voltage value of the voltage VHV. Based on the voltage value of the voltage VHV, the power supply voltage abnormality detection unit 433 detects whether the voltage level of the voltage VHV supplied to the liquid discharge module 21 is normal or not. In this embodiment, if the power supply voltage abnormality detection unit 433 determines that the voltage level of the voltage VHV supplied to the liquid discharge module 21 is abnormal, it outputs an H-level error signal FES to the register control circuit 440.

[0117] The register control circuit 440 includes a sequence register 441, a state register 442, and a register control unit 443. The sequence register 441 and the state register 442 hold operation information that is input as a drive data signal DATAX in synchronization with the clock signal MCK. The register control unit 443 then generates and outputs control signals CNT1 to CNT6 in synchronization with the clock signal RCK, based on the information held in the sequence register 441 and the state register 442. This controls the operation of the drive circuit 51.

[0118] The control signal CNT1 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 controls the output of the drive signal COM output from the drive circuit 51. When an L-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 discharges the charge stored at terminal Com-Dis. On the other hand, when an H-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 does not discharge the charge stored at terminal Com-Dis.

[0119] The control signal CNT2 is input to the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS that is supplied to the piezoelectric element 60. The reference voltage signal VBS is a signal with a constant voltage value based on the voltage GVDD. When an H-level control signal CNT2 is input to the reference voltage signal output circuit 460, a reference voltage signal VBS with a constant voltage value is output from terminal VBS-Out. On the other hand, when an L-level control signal CNT2 is input to the reference voltage signal output circuit 460, a reference voltage signal VBS at ground potential is output. In other words, when an L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the output of the reference voltage signal VBS stops.

[0120] The control signal CNT3 is input to the VHV control signal output circuit 470. The VHV control signal output circuit 470 outputs the control signal VHV_CNT. When a low-level control signal CNT3 is input to the VHV control signal output circuit 470, the voltage GVDD is supplied to the terminal VHV_CNT-Out. That is, a high-level control signal VHV_CNT is output. On the other hand, when a high-level control signal CNT3 is input to the VHV control signal output circuit 470, the terminal VHV_CNT-Out becomes Hi-Z.

[0121] The control signal CNT4 is input to the status signal input / output circuit 480. The status signal input / output circuit 480 outputs a status signal BUSY indicating the operating status of the drive circuit 51. Based on the control signal CNT4 output from the register control circuit 440, the status signal input / output circuit 480 outputs a status signal BUSY from the terminal BUSY-Out and also inputs the signal input to terminal BUSY-Out to the register control circuit 440. When a low-level control signal CNT4 is input to the status signal input / output circuit 480, the voltage GVDD is supplied to terminal BUSY-Out. That is, a high-level status signal BUSY is output. On the other hand, when a high-level control signal CNT4 is input to the status signal input / output circuit 480, terminal BUSY-Out becomes Hi-Z.

[0122] The control signal CNT5 is input to the error signal input / output circuit 490. The error signal input / output circuit 490 outputs an error signal ERR indicating whether or not there is an abnormality in the drive circuit 51. Based on the control signal CNT5 output from the register control circuit 440, the error signal input / output circuit 490 outputs the error signal ERR from terminal ERR-Out and also inputs the signal input to terminal ERR-Out to the register control circuit 440. When a low-level control signal CNT5 is input to the error signal input / output circuit 490, the voltage GVDD is supplied to terminal ERR-Out. That is, a high-level error signal ERR is output. On the other hand, when a high-level control signal CNT5 is input to the error signal input / output circuit 490, terminal ERR-Out becomes Hi-Z.

[0123] The control signal CNT6 is input to the amplification control signal generation circuit 502. When the control signal CNT6 is input to the amplification control signal generation circuit 502, the waveform of the drive signal COM generated by the drive signal generation circuit 501 is determined by the control signal CNT6, not by the drive data signal DATAX. Specifically, the drive signal generation circuit 501 generates a drive signal COM that is constant at a predetermined voltage value based on the control signal CNT6. Alternatively, the drive signal generation circuit 501 may generate a drive signal COM that is constant at ground potential based on the control signal CNT6.

[0124] In the drive circuit 51 configured as described above, operation information input as a drive data signal DATAX in synchronization with the clock signal MCK is held in the sequence register 441. This operation information includes information corresponding to a command that instructs the start of the drive circuit 51. The register control unit 443 then executes sequence control of the drive circuit 51 based on the operation information held in the sequence register 441. As various sequence controls, including the aforementioned start sequence control, are executed, information indicating the operation mode associated with the execution of the sequence control is held in the state register 442. The register control circuit 440 controls the outputs of control signals CNT1 to CNT6 based on the information indicating the operation mode held in the state register 442. This controls the various signals output from the drive circuit 51. For example, the register control circuit 440 may control the outputs of control signals CNT1, CNT2, CNT3, and CNT5 based on an error signal FES or a signal input to the terminal ERR-Out.

[0125] 1-6. Startup sequence of the drive circuit Next, using Figure 12, the startup sequence of the drive circuits 51a, 51b, 51c, and 51d is shown in detail. Let me explain in detail. Figure 12 shows an example of the startup sequence of drive circuits 51a, 51b, 51c, and 51d. As shown in Figure 12, of the drive circuits 51a, 51b, 51c, and 51d, drive circuit 51a is the first to execute the startup sequence.

[0126] Immediately before starting the startup sequence, the drive circuit 51a sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMa. First, at time t1, the drive circuit 51a receives a startup command as a data signal DATAXa from the startup control circuit 80 and starts the startup sequence (step S11). Next, the drive circuit 51a outputs a high-level control signal VHV_CNTa and starts outputting a constant voltage as the drive signal COMa (step S12). Next, the drive circuit 51a waits for charging to be completed until the voltage VHV_H reaches the desired voltage (step S13), and at time t2, starts monitoring the voltage VHV_H (step S14). Next, the drive circuit 51a stops outputting the constant voltage as the drive signal COMa (step S15). Finally, the drive circuit 51a starts outputting the drive waveform of the drive signal COMa and ends the startup sequence (step S16).

[0127] Immediately before starting the startup sequence, the drive circuit 51b sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMb. First, at time t3, after time t2, the drive circuit 51b receives a startup command as a data signal DATAXb from the startup control circuit 80 and starts the startup sequence (step S21). Next, the drive circuit 51b outputs a high-level control signal VHV_CNTb and starts outputting a constant voltage as the drive signal COMb (step S22). Next, the drive circuit 51b starts monitoring the voltage VHV_A1 (step S24). Next, the drive circuit 51b stops outputting the constant voltage as the drive signal COMb (step S25). Finally, the drive circuit 51b starts outputting the drive waveform of the drive signal COMb and ends the startup sequence (step S26).

[0128] Immediately before starting the startup sequence, the drive circuit 51c sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMc. First, at time t4 after time t3, the drive circuit 51c receives a startup command as a data signal DATAXc from the startup control circuit 80 and starts the startup sequence (step S31). Next, the drive circuit 51c outputs a high-level control signal VHV_CNTc and starts outputting a constant voltage as the drive signal COMc (step S32). Next, the drive circuit 51c starts monitoring the voltage VHV_A2 (step S34). Next, the drive circuit 51c stops outputting the constant voltage as the drive signal COMc (step S35). Finally, the drive circuit 51c starts outputting the drive waveform of the drive signal COMc and ends the startup sequence (step S36).

[0129] Immediately before starting the startup sequence, the drive circuit 51d sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMd. First, at time t5, after time t4, the drive circuit 51d receives a startup command as a data signal DATAXd from the startup control circuit 80 and starts the startup sequence (step S41). Next, the drive circuit 51d outputs a high-level control signal VHV_CNTd and starts outputting a constant voltage as the drive signal COMd ​​(step S42). Next, the drive circuit 51d starts monitoring the voltage VHV_A2 (step S44). Next, the drive circuit 51d stops outputting the constant voltage as the drive signal COMd ​​(step S45). Finally, the drive circuit 51d starts outputting the drive waveform of the drive signal COMd ​​and ends the startup sequence (step S46).

[0130] Note that the start sequence of the drive circuits 51b, 51c, and 51d begins at times t3, t4, Time t5 should be after time t1, when the drive circuit 51a starts its startup sequence, but it is preferable that it be after time t2, when the drive circuit 51a starts monitoring the voltage VHV_H.

[0131] Note that the transport mechanism 4 is an example of a "transport unit". Also, the print head 22 is an example of a "head". Furthermore, voltage VHV_H is an example of a "head power signal", and voltage VHV_A1 is an example of a "drive circuit power signal". Furthermore, drive circuit 51a is an example of a "first drive circuit", drive circuit 51b is an example of a "second drive circuit", and drive circuit 51c is an example of a "third drive circuit". Furthermore, drive signal COMa is an example of a "first drive signal", drive signal COMb is an example of a "second drive signal", and drive signal COMc is an example of a "third drive signal". Furthermore, ejection unit 600a is an example of a "first ejection unit", ejection unit 600b is an example of a "second ejection unit", and ejection unit 600c is an example of a "third ejection unit". Furthermore, piezoelectric element 60a is an example of a "first drive unit," piezoelectric element 60b is an example of a "second drive unit," and piezoelectric element 60c is an example of a "third drive unit."

[0132] 1-7. Effects As described above, in the liquid ejection device 1 of the first embodiment, the drive circuit 51a, which monitors the voltage VHV_H supplied to the print head 22, starts its startup sequence before the drive circuit 51b, which monitors the voltage VHV_A1 supplied to the drive circuits 51a and 51b, and before the drive circuits 51c and 51d, which monitor the voltage VHV_A2 supplied to the drive circuits 51c and 51d. Therefore, the drive circuit 51a starts monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting the drive signals COMb, COMc, and COMd ​​to the print head 22, respectively. Also, the drive circuit 51a starts monitoring the voltage VHV_H before starting to output the drive signal COMa to the print head 22. When the drive circuit 51a detects a decrease in the voltage VHV_H, the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting the drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid dispensing device 1 of the first embodiment, the risk of the drive signals COMa, COMb, COMc, COMd ​​becoming higher than the voltage VHV_H can be reduced not only during steady operation of the drive circuits 51a, 51b, 51c, 51d, but also when the drive circuits 51a, 51b, 51c, 51d are started, thus reducing the risk of head failure.

[0133] However, if the supply of voltages VHV_H, VHV_A1, and VHV_A2 to the print head 22 is interrupted, the capacitance values ​​of the stabilizing capacitors 76b and 76c are greater than that of capacitor 76a. As a result, voltage VHV_H may drop faster than voltages VHV_A1 and VHV_A2, and the voltages of the drive signals COMa, COMb, COMc, and COMd ​​may become higher than voltage VHV_H. In addition, overshoot may occur in the drive signals COMa, COMb, COMc, and COMd ​​due to the inductance in the propagation path, and their voltages may also become higher than voltage VHV_H. Consequently, there is a non-zero possibility that the parasitic diodes inside the print head 22 may cause excessive current to flow from each drive signal wiring through which the drive signals COMa, COMb, COMc, and COMd ​​propagate to the power supply wiring 75a through which voltage VHV_H propagates, potentially causing the print head 22 to fail.

[0134] If the print head 22 malfunctions and the current flowing through the power wiring 75a exceeds a predetermined value, the overcurrent protection circuits 70a, 70b, and 70c switch from conduction mode to non-conduction mode, thereby protecting various circuits and electronic components such as the drive circuits 51a, 51b, 51c, and 51d included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that melt under high current, and are reusable because they can be switched from non-conduction mode to conduction mode. Therefore, according to the liquid ejection device 1 of the first embodiment, if the print head 22 malfunctions in the head unit 20, it is unnecessary to replace the drive circuit board 50, thus reducing the effort and cost of repairs.

[0135] Furthermore, according to the liquid dispensing device 1 of the first embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop receiving the enable signal when they switch from the conduction mode to the non-conduction mode, thus maintaining the non-conduction mode. Since they do not switch from the non-conduction mode to the conduction mode unless a predetermined signal is input, the risk of unintentionally returning to the conduction mode is also reduced.

[0136] 2. Second Embodiment In the following description of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and descriptions that overlap with those in the first embodiment are omitted or simplified. The main points to be described are those that differ from the first embodiment.

[0137] The liquid dispensing device 1 of the second embodiment differs from the liquid dispensing device 1 of the first embodiment in the circuit configuration and operation of the drive circuit board 50. Figure 13 is a block diagram showing the circuit configuration of the drive circuit board 50 in the second embodiment.

[0138] As shown in Figure 13, in the second embodiment, the drive circuit 51c monitors the voltage VHV_H instead of the voltage VHV_A2. The drive circuit 51c outputs an L-level error signal ERRc when the voltage VHV_H is higher than a predetermined voltage, and outputs an H-level error signal ERRc when the voltage VHV_H falls below the predetermined voltage, and also stops the output of the drive waveform of the drive signal COMc. The H-level error signal ERRc is a signal that stops the output of the voltage VHV_H from the power supply circuit 90, and the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRc is at the H level. For example, when the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, the voltage VHV_H monitored by the drive circuit 51c falls below the predetermined voltage, so the drive circuit 51c outputs an H-level error signal ERRc. The drive circuit 51c may output an H-level error signal ERRc and an L-level control signal VHV_CNTc when the voltage VHV_H falls below a predetermined voltage. In this way, the drive circuit 51c operates in the same manner as the drive circuit 51a. That is, in the second embodiment, the two drive circuits 51a and 51c monitor the voltage VHV_H.

[0139] Then, when the head unit 20 is started, the startup control circuit 80 starts at least one of the drive circuits 51a, 51b, 51c, and 51d that monitor the voltage VHV_H, specifically drive circuits 51a and 51c. That is, the startup control circuit 80 starts the startup sequence of at least one of the drive circuits 51a and 51c, and then starts the startup sequences of drive circuits 51b and 51d. For example, the startup control circuit 80 may start the startup sequence of drive circuit 51a and then start the startup sequences of drive circuits 51b, 51c, and 51d, or it may start the startup sequence of drive circuit 51c and then start the startup sequences of drive circuits 51a, 51b, and 51d, or it may start the startup sequences of drive circuits 51a and 51c simultaneously and then start the startup sequences of drive circuits 51b and 51d. Furthermore, it is preferable that the time at which the drive circuits 51b and 51d start their startup sequence is after the time at least one of the drive circuits 51a and 51c starts monitoring the voltage VHV_H.

[0140] The other circuit configurations of the drive circuit board 50 in the second embodiment are the same as those of the drive circuit board 50 in the first embodiment shown in Figure 9, so their description is omitted. Furthermore, the other configurations and functions of the liquid dispensing device 1 in the second embodiment are the same as those of the liquid dispensing device 1 in the first embodiment, so their description is omitted.

[0141] In the liquid ejection device 1 of the second embodiment described above, at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H supplied to the print head 22 is drive circuit 51a The startup sequence is initiated before drive circuit 51b, which monitors the voltage VHV_A1 supplied to 51b, and before drive circuit 51d, which monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d. Therefore, at least one of drive circuits 51a and 51c starts monitoring the voltage VHV_H before drive circuits 51b and 51d start outputting drive signals COMb and COMd ​​to the print head 22, respectively. Also, drive circuits 51a and 51c start monitoring the voltage VHV_H before outputting drive signals COMa and COMc to the print head 22. If at least one of drive circuits 51a and 51b detects a decrease in the voltage VHV_H, drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid dispensing device 1 of the second embodiment, the risk of the drive signals COMa, COMb, COMc, COMd ​​becoming higher than the voltage VHV_H can be reduced not only during steady operation of the drive circuits 51a, 51b, 51c, 51d, but also when the drive circuits 51a, 51b, 51c, 51d are started, thus reducing the risk of head failure.

[0142] If the print head 22 malfunctions and the current flowing through the power wiring 75a exceeds a predetermined value, the overcurrent protection circuits 70a, 70b, and 70c switch from conduction mode to non-conduction mode, thereby protecting various circuits and electronic components such as the drive circuits 51a, 51b, 51c, and 51d included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that melt under high current, and are reusable because they can be switched from non-conduction mode to conduction mode. Therefore, according to the liquid ejection device 1 of the second embodiment, if the print head 22 malfunctions in the head unit 20, it is unnecessary to replace the drive circuit board 50, thus reducing the effort and cost of repairs.

[0143] Furthermore, according to the liquid dispensing device 1 of the second embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop receiving the enable signal when they switch from the conduction mode to the non-conduction mode, thus maintaining the non-conduction mode. Since they do not switch from the non-conduction mode to the conduction mode unless a predetermined signal is input, the risk of unintentionally returning to the conduction mode is also reduced.

[0144] 3. Third Embodiment In the following description of the third embodiment, the same reference numerals are used for components similar to those in the first or second embodiment, and descriptions that overlap with those in the first or second embodiment are omitted or simplified. The description will mainly focus on the differences from the first and second embodiments.

[0145] The liquid dispensing device 1 of the third embodiment differs from the liquid dispensing device 1 of the first or second embodiment in the circuit configuration and operation of the drive circuit board 50. Figure 14 is a block diagram showing the circuit configuration of the drive circuit board 50 in the third embodiment.

[0146] As shown in Figure 14, in the third embodiment, the drive circuit board 50 includes a fuse 77. The fuse 77 is located on the power supply wiring 75a that supplies voltage VHV_H to the print head 22. Specifically, one end of the fuse 77 is connected to the output terminal of the overcurrent protection circuit 70a, and the other end is connected to the print head 22. Therefore, voltage VHV_H is supplied to the print head 22 from the other end of the fuse 77.

[0147] The drive circuit 51a monitors the voltage VHV_H propagating through the section of the power supply wiring 75a between the fuse 77 and the print head 22. When the voltage VHV_H falls below a predetermined voltage, it outputs an H-level error signal ERRa and stops the output of the drive waveform of the drive signal COMa. The H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90, and the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is at an H level. For example, when the overcurrent protection circuit 70a changes from conduction mode to deconduction mode... When the system switches to normal mode, the voltage VHV_H monitored by the drive circuit 51a falls below a predetermined voltage, so the drive circuit 51a outputs an H-level error signal ERRa. If the voltage VHV_H is below a predetermined voltage, the drive circuit 51a may output an H-level error signal ERRa and an L-level control signal VHV_CNTa.

[0148] Then, when the head unit 20 is started, the startup control circuit 80 starts the drive circuit 51a, which monitors the voltage VHV_H, first among the drive circuits 51a, 51b, 51c, and 51d. That is, after starting drive circuit 51a, the startup control circuit 80 starts the startup sequence of drive circuits 51b, 51c, and 51d. It is preferable that the time at which drive circuits 51b, 51c, and 51d start their startup sequence is after the time at which drive circuit 51a starts monitoring the voltage VHV_H.

[0149] The other circuit configurations of the drive circuit board 50 in the third embodiment are the same as those of the drive circuit board 50 in the first embodiment shown in Figure 9, so their description is omitted. Furthermore, the other configurations and functions of the liquid dispensing device 1 in the third embodiment are the same as those of the liquid dispensing device 1 in the first embodiment, so their description is omitted.

[0150] In the third embodiment, similar to the drive circuit board 50 of the second embodiment shown in Figure 13, the drive circuits 51a and 51c may monitor the voltage VHV_H propagating in the portion of the power supply wiring 75a between the fuse 77 and the print head 22. In this case, when the head unit 20 is started, the startup control circuit 80 starts at least one of the drive circuits 51a and 51c that monitor the voltage VHV_H among the drive circuits 51a, 51b, 51c, and 51d. That is, the startup control circuit 80 starts the startup sequence of at least one of the drive circuits 51a and 51c, and then starts the startup sequence of the drive circuits 51b and 51d. For example, the startup control circuit 80 may start the startup sequence of drive circuits 51b, 51c, and 51d after starting the startup sequence of drive circuit 51a, or it may start the startup sequence of drive circuits 51a, 51b, and 51d after starting the startup sequence of drive circuit 51c, or it may start the startup sequences of drive circuits 51a and 51c simultaneously, and then start the startup sequences of drive circuits 51b and 51d. It is preferable that the time at which drive circuits 51b and 51d start their startup sequences is after the time at least one of drive circuits 51a and 51c starts monitoring the voltage VHV_H.

[0151] Furthermore, the drive circuit board 50 may include other elements such as ferrite beads instead of the fuse 77 as elements for electrically disconnecting the power supply circuit 90 and the print head 22.

[0152] In the liquid ejection device 1 of the third embodiment described above, similar to the liquid ejection device 1 of the first embodiment, the drive circuit 51a starts monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting the drive signals COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid ejection device 1 of the third embodiment, the risk of the drive signals COMa, COMb, COMc, and COMd ​​becoming higher than the voltage VHV_H can be reduced not only during the steady operation of the drive circuits 51a, 51b, 51c, and 51d, but also when the drive circuits 51a, 51b, 51c, and 51d are started, thus reducing the risk of head failure.

[0153] Furthermore, according to the liquid ejection device 1 of the third embodiment, if an overcurrent flows through the power supply wiring 75a that supplies voltage VHV_H to the print head 22, the fuse 77 blows, further reducing the risk of the print head 22 malfunctioning.

[0154] Furthermore, according to the liquid dispensing device 1 of the first embodiment, the overcurrent protection circuits 70a, 70b, 70 In case c, the input of the enable signal stops when switching from the conduction mode to the non-conduction mode, so the non-conduction mode can be maintained, and unless a predetermined signal is input, it will not switch from the non-conduction mode to the conduction mode, thus reducing the risk of unintentionally returning to the conduction mode.

[0155] 4. Fourth Embodiment In the following description of the fourth embodiment, components similar to those in the first to third embodiments are denoted by the same reference numerals, and descriptions that overlap with those in the first to third embodiments are omitted or simplified. The description will mainly focus on aspects that differ from any of the first to third embodiments.

[0156] The liquid dispensing device 1 of the fourth embodiment differs from the liquid dispensing device 1 of the first to third embodiments in the circuit configuration and operation of the drive circuit board 50. Figure 15 is a block diagram showing the circuit configuration of the drive circuit board 50 in the fourth embodiment.

[0157] As shown in Figure 15, in the fourth embodiment, the voltage VHV_H supplied to the print head 22 and the voltage VHV_A1 supplied to the drive circuits 51a and 51b are the same voltage.

[0158] The drive circuits 51a and 51b monitor the voltage VHV_H. If the voltage VHV_H is higher than a predetermined voltage, the drive circuits 51a and 51b output L-level error signals ERRa and ERRb, respectively. If the voltage VHV_H falls below the predetermined voltage, they output H-level error signals ERRa and ERRb, respectively, and stop outputting the drive waveforms of the drive signals COMa and COMb, respectively. The H-level error signals ERRa and ERRb are signals that stop the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops outputting the voltage VHV_H when at least one of the error signals ERRa and ERRb is at the H level. For example, when the overcurrent protection circuit 70a switches from conduction mode to non-conduction mode, the voltage VHV_H monitored by the drive circuits 51a and 51b falls below the predetermined voltage, so the drive circuits 51a and 51b output H-level error signals ERRa and ERRb, respectively. The drive circuits 51a and 51b may output H-level error signals ERRa and ERRb, respectively, and L-level control signals VHV_CNTa and VHV_CNTb, respectively, when the voltage VHV_H falls below a predetermined voltage.

[0159] Then, when the head unit 20 is started, the startup control circuit 80 starts at least one of the drive circuits 51a, 51b, 51c, and 51d that monitor the voltage VHV_H, specifically drive circuits 51a and 51b. That is, the startup control circuit 80 starts the startup sequence of at least one of the drive circuits 51a and 51b, and then starts the startup sequences of drive circuits 51c and 51d. For example, the startup control circuit 80 may start the startup sequence of drive circuit 51a and then start the startup sequences of drive circuits 51b, 51c, and 51d, or it may start the startup sequence of drive circuit 51b and then start the startup sequences of drive circuits 51a, 51c, and 51d, or it may start the startup sequences of drive circuits 51a and 51b simultaneously and then start the startup sequences of drive circuits 51c and 51d. Furthermore, it is preferable that the time at which the drive circuits 51c and 51d start their startup sequence is after the time at least one of the drive circuits 51a and 51b starts monitoring the voltage VHV_H.

[0160] The other circuit configurations of the drive circuit board 50 in the fourth embodiment are the same as those of the drive circuit board 50 in the first embodiment shown in Figure 9, so their description is omitted. Furthermore, the other configurations and functions of the liquid dispensing device 1 in the fourth embodiment are the same as those of the liquid dispensing device 1 in the first embodiment, so their description is omitted.

[0161] In the fourth embodiment, similar to the drive circuit board 50 of the third embodiment shown in Figure 14, the drive circuit board 50 is powered by a power supply wiring that supplies voltage VHV_H to the print head 22. The drive circuits 51a and 51b may include a fuse 77 provided on 75a and monitor the voltage VHV_H propagating through the portion of the power supply wiring 75a between the fuse 77 and the print head 22.

[0162] In the liquid ejection device 1 of the fourth embodiment described above, at least one of the drive circuits 51a and 51b, which monitor the voltage VHV_H (VHV_A1) supplied to the print head 22 and drive circuits 51a and 51b, starts its startup sequence before the drive circuits 51c and 51d, which monitor the voltage VHV_A2 supplied to them. Therefore, at least one of the drive circuits 51a and 51b starts monitoring the voltage VHV_H (VHV_A1) before the drive circuits 51c and 51d start outputting the drive signals COMc and COMd ​​to the print head 22, respectively. Also, the drive circuits 51a and 51b start monitoring the voltage VHV_H (VHV_A1) before they start outputting the drive signals COMa and COMb to the print head 22. Furthermore, if at least one of the drive circuits 51a and 51b detects a drop in voltage VHV_H (VHV_A1), the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting the drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid ejection device 1 of the fourth embodiment, the risk of the drive signals COMa, COMb, COMc, and COMd ​​becoming higher than the voltage VHV_H (VHV_A1) can be reduced not only during the steady operation of the drive circuits 51a, 51b, 51c, and 51d, but also when the drive circuits 51a, 51b, 51c, and 51d are started, thus reducing the risk of head failure.

[0163] If the print head 22 malfunctions and the current flowing through the power wiring 75a exceeds a predetermined value, the overcurrent protection circuits 70a, 70b, and 70c switch from conduction mode to non-conduction mode, thereby protecting various circuits and electronic components such as the drive circuits 51a, 51b, 51c, and 51d included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and are reusable because they can be switched from non-conduction mode to conduction mode. Therefore, according to the liquid ejection device 1 of the fourth embodiment, if the print head 22 malfunctions in the head unit 20, it is unnecessary to replace the drive circuit board 50, thus reducing the effort and cost of repairs.

[0164] Furthermore, according to the liquid dispensing device 1 of the fourth embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop receiving the enable signal when they switch from the conduction mode to the non-conduction mode, thus maintaining the non-conduction mode. Since they do not switch from the non-conduction mode to the conduction mode unless a predetermined signal is input, the risk of unintentionally returning to the conduction mode is also reduced.

[0165] 5. Variations The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0166] For example, in each of the above embodiments, the drive circuit board 50 includes four drive circuits 51, but the number of drive circuits 51 included in the drive circuit board 50 may be two, three, or five or more. Similarly, the drive circuit board 50 includes four overcurrent protection circuits 70, but the number of overcurrent protection circuits 70 included in the drive circuit board 50 may be two, three, or five or more.

[0167] Furthermore, in each of the above embodiments, the VHV abnormal signals VERa, VERb, VERc, VERd output from the logic circuits 71a, 71b, 71c, 71d are input to the drive circuits 51a, 51b, 51c, 51d as error signals ERRa, ERRb, ERRc, ERRd, respectively. The constant signal VERa may be input in common.

[0168] Furthermore, in each of the above embodiments, the liquid ejection device 1 was described as a so-called serial inkjet printer in which a liquid ejection module 21 that ejects ink is mounted on a carriage 24, and printing is performed by the carriage 24 reciprocating over the medium P. However, it may also be a so-called line inkjet printer in which the liquid ejection modules 21 are arranged in a line in the width direction of the medium P, and printing is performed by transporting the medium P.

[0169] Although embodiments have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its essence. For example, the above embodiments can be combined as appropriate.

[0170] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0171] The following conclusions can be drawn from the embodiments described above.

[0172] One embodiment of a liquid dispensing device is: It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A transport unit for transporting the aforementioned medium, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit that controls the startup of the first drive circuit and the second drive circuit, A liquid dispensing device comprising, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then starts the startup sequence of the second drive circuit.

[0173] In this liquid dispensing device, the first drive circuit, which monitors the voltage of the head power signal, starts its startup sequence before the second drive circuit, which monitors the voltage of the drive circuit power signal. Therefore, the first drive circuit starts monitoring the voltage of the head power signal before the second drive circuit starts outputting the second drive signal to the head. Consequently, this liquid dispensing device reduces the risk that the voltage of the second drive signal will be higher than the voltage of the head power signal when the first and second drive circuits start up, thereby reducing the risk of head failure.

[0174] One embodiment of the liquid dispensing device is: A third drive unit is driven by a third drive signal, and a third discharge unit discharges liquid into the medium in response to the drive of the third drive unit, A third drive circuit that outputs the third drive signal, Equipped with, The third drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The startup control circuit may start the startup sequence of the second drive circuit after starting the startup sequence of at least one of the first drive circuit and the third drive circuit.

[0175] In this liquid dispensing device, at least one of the first drive circuit and the third drive circuit, which monitor the voltage of the head power signal, starts its startup sequence before the second drive circuit, which monitors the voltage of the drive circuit power signal. Therefore, at least one of the first drive circuit and the third drive circuit starts monitoring the voltage of the drive circuit power signal before the second drive circuit starts outputting the second drive signal to the head. Consequently, this liquid dispensing device reduces the risk that the voltage of the second drive signal will be higher than the voltage of the head power signal when the first drive circuit, the second drive circuit, and the third drive circuit are started, thereby reducing the risk of head failure.

[0176] In one embodiment of the liquid dispensing device, The drive circuit power supply signal is a different signal from the head power supply signal and does not need to be supplied to the head.

[0177] One embodiment of the liquid dispensing device is: The head power signal is supplied to the head, and a fuse is provided on the power wiring that supplies the head power signal. The first drive circuit may output a signal to stop the output of the head power signal from the power circuit when the head power signal propagating through the portion of the power wiring between the fuse and the head falls below the predetermined voltage.

[0178] With this liquid dispensing device, if an overcurrent flows through the power wiring that supplies the head power signal to the head, the fuse will blow, further reducing the risk of head failure.

[0179] One form of a head unit is: It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit that controls the startup of the first drive circuit and the second drive circuit, A head unit equipped with, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then starts the startup sequence of the second drive circuit.

[0180] In this head unit, the first drive circuit monitors the voltage of the head power signal, Since the startup sequence begins before the second drive circuit, which monitors the voltage of the power supply signal, the first drive circuit begins monitoring the voltage of the head power supply signal before the second drive circuit begins outputting the second drive signal to the head. Therefore, with this head unit, the risk of the voltage of the second drive signal becoming higher than the voltage of the head power supply signal during the startup of the first and second drive circuits is reduced, thus reducing the risk of head failure.

[0181] One embodiment of the head unit is: A third drive unit is driven by a third drive signal, and a third discharge unit discharges liquid into the medium in response to the drive of the third drive unit, A third drive circuit that outputs the third drive signal, Equipped with, The third drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The startup control circuit may start the startup sequence of the second drive circuit after starting the startup sequence of at least one of the first drive circuit and the third drive circuit.

[0182] In this head unit, at least one of the first drive circuit and the third drive circuit, which monitor the voltage of the head power signal, starts its startup sequence before the second drive circuit, which monitors the voltage of the drive circuit power signal. Therefore, at least one of the first drive circuit and the third drive circuit starts monitoring the voltage of the drive circuit power signal before the second drive circuit starts outputting the second drive signal to the head. Consequently, this head unit reduces the risk that the voltage of the second drive signal will be higher than the voltage of the head power signal when the first drive circuit, the second drive circuit, and the third drive circuit start up, thereby reducing the risk of head failure.

[0183] In one embodiment of the head unit, The drive circuit power supply signal is a different signal from the head power supply signal and does not need to be supplied to the head.

[0184] One embodiment of the head unit is: The head power signal is supplied to the head, and a fuse is provided on the power wiring that supplies the head power signal. The first drive circuit may output a signal to stop the output of the head power signal from the power circuit when the head power signal propagating through the portion of the power wiring between the fuse and the head falls below the predetermined voltage.

[0185] With this head unit, if an overcurrent flows through the power wiring that supplies the head power signal to the head, the fuse will blow, further reducing the risk of head failure. [Explanation of Symbols]

[0186] 1...Liquid dispensing device, 2...Mobile body, 3...Moving mechanism, 4...Conveying mechanism, 10...Control unit, 20...Head unit, 21,21a,21b,21c,21d...Liquid dispensing module, 22...Print head, 24...Carriage, 31...Carriage motor, 32...Carriage guide shaft, 33...Timing belt, 35...Carriage motor driver, 40...Platen, 41...Conveyor motor, 42...Conveyor roller, 45...Conveyor motor driver, 5 0…Drive circuit board, 51, 51a, 51b, 51c, 51d…Drive circuit, 52, 53, 54…Resistors, 60, 60a, 60b, 60c, 60d…Piezoelectric element, 70, 70a, 70b, 70c…Overcurrent protection circuit, 71a, 71b, 71c, 71d…Logic circuit, 72, 73, 74…Resistors, 75a, 75b, 75c…Power supply wiring, 76a, 76b, 76c…Capacitors, 77…Fuse, 80…Startup control circuit, 90…Power supply circuit, 91…Oscillator circuit, 100 ...control circuit, 190...cable, 200, 200a, 200b, 200c, 200d...drive signal selection circuit, 210...selection control circuit, 212...shift register, 214...latch circuit, 216...decoder, 230...selection circuit, 232...inverter, 234...transfer gate, 235, 236...transistor, 400...voltage generation circuit, 410...oscillator circuit, 420...clock selection circuit, 430...anomaly detection circuit, 4 31...Oscillation abnormality detection unit, 432...Operation abnormality detection unit, 433...Power supply voltage abnormality detection unit, 440...Register control circuit, 441...Sequence register, 442...State register, 443...Register control unit, 450...Drive signal discharge circuit, 451...Resistor, 452...Transistor, 460...Reference voltage signal output circuit, 461...Comparator, 462,463...Transistor, 464,465,466...Resistor, 467...Inverter Transistor, 470...VHV control signal output circuit, 471...Transistor, 480...Status signal input / output circuit, 481...Transistor, 482...Inverter, 490...Error signal input / output circuit, 491...Transistor, 492...Inverter, 500...Integrated circuit, 501...Drive signal generation circuit, 502...Amplification control signal generation circuit, 510...DAC interface, 520...DAC section, 530...Modulation section, 540...Gate drive section, 5 50…Drive signal amplification circuit, 551, 552…Transistor, 553…Coil, 554…Capacitor, 555, 556, 576…Resistor, 600, 600a, 600b, 600c, 600d…Discharge section, 601…Piezoelectric element, 611, 612…Electrode, 621…Diaphragm, 631…Cavity, 632…Nozzle plate, 641…Reservoir, 651…Nozzle, 661…Supply port, 700…Electronic fuse IC, 701, 702…Resistor

Claims

1. It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A transport unit for transporting the aforementioned medium, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit for controlling the startup of the first drive circuit and the second drive circuit, A liquid dispensing device comprising, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then starts the startup sequence of the second drive circuit. A liquid dispensing device characterized by the following features.

2. A third drive unit is driven by a third drive signal, and a third discharge unit discharges liquid into the medium in response to the drive of the third drive unit, A third drive circuit that outputs the third drive signal, Equipped with, The third drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of at least one of the first drive circuit and the third drive circuit, and then starts the startup sequence of the second drive circuit. The liquid dispensing device according to feature 1.

3. The aforementioned drive circuit power supply signal is a different signal from the aforementioned head power supply signal and is not supplied to the head. The liquid dispensing device according to feature 1.

4. The head power signal is supplied to the head, and a fuse is provided on the power wiring that supplies the head power signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power circuit when the head power signal propagating through the portion of the power wiring between the fuse and the head falls below the predetermined voltage. The liquid dispensing device according to feature 1.

5. It includes a first drive unit driven by a first drive signal, and a first discharge unit that discharges liquid onto a medium in response to the drive of the first drive unit, A second drive unit is driven by a second drive signal, and a second discharge unit discharges liquid into the medium in response to the drive of the second drive unit, A head having, A first drive circuit that outputs the first drive signal, A second drive circuit that outputs the second drive signal, A startup control circuit for controlling the startup of the first drive circuit and the second drive circuit, A head unit equipped with, The head is supplied with a head power signal. The first drive circuit and the second drive circuit are supplied with a drive circuit power supply signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The second drive circuit outputs a signal to stop the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of the first drive circuit, and then starts the startup sequence of the second drive circuit. A head unit characterized by the following features.

6. A third drive unit is driven by a third drive signal, and a third discharge unit discharges liquid into the medium in response to the drive of the third drive unit, A third drive circuit that outputs the third drive signal, Equipped with, The third drive circuit outputs a signal to stop the output of the head power signal from the power supply circuit when the head power signal falls below a predetermined voltage. The startup control circuit starts the startup sequence of at least one of the first drive circuit and the third drive circuit, and then starts the startup sequence of the second drive circuit. The head unit according to feature 5.

7. The aforementioned drive circuit power supply signal is a different signal from the aforementioned head power supply signal and is not supplied to the head. The head unit according to feature 5.

8. The head power signal is supplied to the head, and a fuse is provided on the power wiring that supplies the head power signal. The first drive circuit outputs a signal to stop the output of the head power signal from the power circuit when the head power signal propagating through the portion of the power wiring between the fuse and the head falls below the predetermined voltage. The head unit according to feature 5.

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