Digital power amplifier with analog clipping method

Abstract

The present invention provides a system, method, and apparatus for a digital power amplifier equipped with an analog clipping scheme. [Solution] An analog clipping method for a switched-capacitor power amplifier comprising an array of unit cells shareable between in-phase (I) signal components and quadrature-phase (Q) signal components, wherein each unit cell is associated with a pair of control bits, which include a first control bit for selectively enabling the unit cell to use the I component and a second control bit for selectively enabling the unit cell to use the Q component. Truth tables are configured for first and second subsets of unit cells such that, in response to a double-enable state of the respective pair of control bits, the unit cells of the first subset are driven by the I component. The truth tables are configured such that, in response to a double-enable state, the unit cells of the second subset are driven by the Q component.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims the benefit of Australian Provisional Patent Application No. 2024903101, filed on September 26, 2024. This provisional patent application is hereby incorporated by reference in its entirety for all purposes.

[0002] This disclosure is mainly related to wireless communication. For example, aspects of this disclosure relate to a clipping scheme of a digital power amplifier and / or a switched - capacitor power amplifier. This clipping can be implemented locally on the output unit of the capacitor array included in the amplifier.

Background Art

[0003] A power amplifier (PA) is used in a radio - frequency (RF) transmitter to transmit electromagnetic energy. The efficiency of the PA significantly affects the power consumption in a wireless transceiver, and the PA may account for a significant portion of the overall power consumption of the wireless system. The PA receives a direct - current (DC) power input and supplies a radio - frequency power output. The power conversion efficiency from the DC power input to the RF power output directly corresponds to the overall efficiency of the PA. Therefore, by improving the power conversion efficiency from the DC input to the RF output, energy savings and an extended battery life of various mobile devices and / or wireless devices equipped with the PA can be achieved. The PA is usually designed to achieve maximum power efficiency when operating at the maximum output power, but when operating in various low - output regions below the maximum output power, its power efficiency may significantly decrease.

[0004] In recent years, digital power amplifiers (DPAs) have gained increasing attention because they can integrate multiple functions and / or features, such as digital-to-analog converters (DACs), frequency upconverters / mixers, and PAs. Using a DPA in an RF receiver improves the receiver's energy efficiency and reduces power consumption. It also reduces the chip area associated with the physical implementation of the RF receiver (e.g., based on the multiple functions integrated into the DPA). "High-power" DPAs are associated with relatively high power consumption and may employ various techniques to improve efficiency. However, efficiency optimizations used in existing high-power DPAs can also introduce distortion, especially when the input amplitude code driving the DAC (e.g., a DAC included in or integrated within the DPA) is large. The in-phase (I) and quadrature-phase (Q) components of the input signal may be separated and coupled to different sections of the DPA. Coding circuits within the DPA are used to map the amplitudes of the I and Q components to drive these separate DPA sections. The signals from each section are then summed (e.g., recombined) to produce the final output of the DPA. A switched-capacitor power amplifier (ScPa) is a type of DPA that uses capacitors in conjunction with transistors acting as switches to achieve high linearity and efficiency, particularly at high power levels. In an ScPa architecture, capacitors in an array can be turned on or off by selectively driving (or de-driving) them with an input clock signal. This selective driving of capacitors can be controlled by amplitude codes derived from the amplitudes of the I and Q components of the input signal. For example, the amplitudes of the I and Q components are coded into an amplitude code, which is used to control which capacitors are turned on within each capacitor array of the ScPa (this control can also be performed by a DAC included in or integrated within the DPA). [Overview of the Initiative]

[0005] The following is a simplified summary of one or more embodiments disclosed herein. Therefore, the following summary should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope relating to any particular embodiment. Accordingly, the following summary is intended solely to present, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed description provided below.

[0006] This specification discloses systems, methods, apparatus, and computer-readable media for digital power amplifiers with analog clipping schemes. An exemplary embodiment provides a switched-capacitor power amplifier (ScPa) apparatus. The apparatus is a switched-capacitor power amplifier (ScPa) apparatus comprising: a switched-capacitor ray including a plurality of unit cells shareable between the in-phase (I) and quadrature-phase (Q) components of an input radio frequency (RF) signal, wherein each of the plurality of unit cells comprises a capacitor and an inverter; a pair of control bits associated with each of the plurality of unit cells, wherein each pair of control bits includes a first control bit configured to selectively drive or dedrive the unit cell based on the I component and a second control bit configured to selectively drive or dedrive the unit cell based on the Q component; and truth table logic configured for the unit cells of a first subset and the unit cells of a second subset of the plurality of unit cells, wherein the truth table logic is configured to drive the unit cells of the first subset based on the I component in response to a double-enable state of each of the pair of control bits, and to drive the unit cells of the second subset based on the Q component in response to the double-enable state.

[0007] In some embodiments, the ScPa device implements an analog clipping scheme based on a set of unit cells having the double-enabled state of the switched capacitor ray configured with the truth table logic, wherein the set of unit cells having the double-enabled state comprises a plurality of unit cells.

[0008] In some embodiments, the analog clipping scheme implemented using the truth table logic drives the first half of the set of unit cells having the double-enabled state with an I clock corresponding to the I component, and drives the second half of the set of unit cells having the double-enabled state with a Q clock corresponding to the Q component.

[0009] In some embodiments, the set of unit cells having the double-enabled state is equal to the difference between the sum of the magnitudes of the I component and the Q component and the number of the plurality of unit cells included in the switched capacitor ray.

[0010] In some embodiments, the double-enable state corresponds to each bit of the respective control bit pair of the unit cell being set to high, indicating that the unit cell is drivable based on the I component and also drivable based on the Q component.

[0011] In some embodiments, the first subset of the unit cells comprises the first half of the plurality of unit cells, and the second subset of the unit cells comprises the second half of the plurality of unit cells.

[0012] In some embodiments, the number of unit cells in the first subset is equal to the number of unit cells in the second subset.

[0013] In some embodiments, a first subset of unit cells comprises unit cells with even indices of the switched capacitor ray, and a second subset of unit cells comprises unit cells with odd indices of the switched capacitor ray.

[0014] Alternatively, the first subset of unit cells comprises unit cells with odd indices in the switched-capacitor ray, and the second subset of unit cells comprises unit cells with even indices in the switched-capacitor ray.

[0015] In some embodiments, one of the first and second subsets of the unit cells comprises unit cells with even indices of the switched capacitor ray, and the other of the first and second subsets comprises unit cells with odd indices of the switched capacitor ray.

[0016] In some embodiments, the truth table logic drives the plurality of unit cells according to the respective pairs of control bits when the double-enable state is absent.

[0017] In some embodiments, the truth table logic encodes the priority so that the I component takes precedence over the Q component for the unit cells of the first subset, and the truth table logic maps the encoded priority so that the I component takes precedence over the Q component to a double-enable state in which the first and second control bits are set high, respectively, for each unit cell of the first subset.

[0018] In some embodiments, the truth table logic encodes a priority for the unit cells of the second subset such that the Q component takes precedence over the I component, and the truth table logic maps the encoded priority, which takes precedence over the I component, to each unit cell of the first subset, to the double-enable state in which the first and second control bits are set to high, respectively.

[0019] In some embodiments, each of the multiple unit cells of the switched capacitor ray is switchably coupled to the primary input of an inductive transformer or balun included in the ScPa device.

[0020] In some embodiments, the truth table logic causes the ScPa device to automatically implement an analog clipping scheme for IQ amplitude codes having a total magnitude greater than the number of unit cells included in the plurality of unit cells, the analog clipping scheme being implemented locally by each unit cell having a double-enabled state, according to the truth table logic configured for each unit cell having a double-enabled state.

[0021] In some embodiments, the ScPa device further comprises a voltage level shifter in an output switch unit, the output switch unit comprising an NMOS switch device gate, an NMOS cascode gate, a PMOS cascode gate, and a PMOS switch device gate.

[0022] In some embodiments, the NMOS switch device gate is driven by a core voltage inverter driven from a core voltage (VDDL) rail, the NMOS cascode gate is coupled to the VDDL rail, the PMOS cascode gate is biased to a fixed voltage lower than the IO voltage (VDDH) rail, and the PMOS switch device gate is charged to a voltage of (VDDH - VDDL) by a signal voltage shift using a capacitor between the NMOS switch device gate and the PMOS switch device gate.

[0023] In some embodiments, the IO voltage (VDDH) is set to a maximum of twice the core voltage (VDDL).

[0024] In some embodiments, the output switch unit further comprises a cross-coupled PMOS device for periodically replenishing the small amount of charge that leaks from the capacitor over time.

[0025] In some embodiments, the PMOS cascode gate is coupled to a charge pump driven by a clock input at the VDDL level, and the core supply voltage of the charge pump is DC-shifted via a series capacitor to generate a rail that is one core voltage lower than the VDDH rail.

[0026] As another example, a method of controlling a switched-capacitor power amplifier (ScPa) having adaptive clipping, the method comprising: obtaining in-phase (I) and quadrature-phase (Q) codes corresponding to an input radio frequency (RF) signal; comparing the sum of the absolute values of the I and Q codes with a threshold corresponding to the number of unit cells included in a plurality of unit cells of a switched-capacitor array of the ScPa; and determining, according to the I and Q codes, each output cell of an inverter and a capacitor array of the ScPa to be an I-clock enabled output cell, a Q-clock enabled output cell, a double-enabled output cell, or an off output cell, wherein the number of double-enabled output cells is equal to zero when the sum of the absolute values of the I and Q codes is less than or equal to the threshold, and the number of double-enabled output cells is equal to a value obtained by subtracting the threshold from the sum of the absolute values of the I and Q codes. controlling to drive half of the double-enabled output cells by an I clock and the other half of the double-enabled output cells by a Q clock; controlling to drive the I-clock enabled output cells of the inverter and the capacitor array by the I clock; and controlling to drive the Q-clock enabled output cells of the inverter and the capacitor array by the Q clock.

[0027] In some aspects, controlling the ScPa includes implementing an analog clipping scheme based on configuring a set of unit cells having the double-enabled state of the switch capacitor array into truth table logic, and the set of unit cells having the double-enabled state is included in the plurality of unit cells.

[0028] In some aspects, the truth table logic drives the first half of the set of unit cells having the double-enabled state with an I clock corresponding to the I code, and drives the second half of the set of unit cells having the double-enabled state with a Q clock corresponding to the Q code.

[0029] Other objects and advantages related to the aspects disclosed herein will be readily understood by those skilled in the art based on the accompanying drawings and the detailed description.

Brief Description of the Drawings

[0030] Exemplary aspects of the present application will be described in detail below with reference to the following drawings. [Figure 1] It is a block diagram showing an exemplary wireless communication network. [Figure 2A] It is a block diagram of a wireless communication device that can implement a station (STA) or an access point (AP) according to some embodiments. [Figure 2B] It is a schematic block diagram of the receiver data flow architecture of the wireless communication device of FIG. 2A according to some embodiments. [Figure 2C] It is a schematic block diagram of a transmitter data flow architecture that can be used to transmit a radio frequency (RF) signal via a wireless medium according to some embodiments. [Figure 3]An example of a digitally controlled switched-capacitor power amplifier (ScPa) architecture consisting of two arrays of CMOS inverters according to several embodiments is shown, where each array includes multiple capacitors that are driven or not driven by the corresponding inverters within the array. [Figure 4] This figure shows an example of a composite drive scheme for the ScPa architecture implemented using a non-Cartesian coordinate system according to several embodiments. [Figure 5] This figure shows an example of a composite drive scheme for an ScPa architecture implemented using a Cartesian coordinate system according to several embodiments. [Figure 6] This figure shows an example of a composite drive scheme for an ScPa architecture implemented using a Cartesian coordinate system and four inverters and a capacitor array branch according to several embodiments. [Figure 7] This is an IQ constellation diagram showing clipping diamonds corresponding to the performance degradation thresholds of several embodiments of digital power amplifiers. [Figure 8] This figure shows examples of capacitor array unit (e.g., output cell) allocation in an IQ shared cell ScPa where clipping is not required, and examples of capacitor array unit allocation in an IQ shared cell ScPa where clipping is required. [Figure 9] This is a schematic diagram of an exemplary ScPa output switch unit, including a stack of four core devices, two switch devices and two cascode devices, according to several embodiments. [Figure 10] The following are examples of circuits that achieve the required voltage for each device included in the stack of four core devices of the ScPa output unit in Figure 9, according to several embodiments. [Figure 11] Examples of circuits with charge pumps driven by a VDDL-level clock input according to several embodiments are shown. [Figure 12]This block diagram shows an example of a computing system for implementing a particular embodiment described herein according to several embodiments. [Modes for carrying out the invention]

[0031] Specific aspects of this disclosure are provided below. Some of these aspects can be applied independently, and some of them can be applied in combination as will be apparent to those skilled in the art.

[0032] The following description includes specific details to provide a complete understanding of the embodiments of the Application for illustrative purposes. However, it will be apparent that various embodiments may be implemented without these specific details. The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of exemplary embodiments will provide a useful explanation for those skilled in the art to implement the exemplary embodiments. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of the Application, as described in the attached claims. The figures and descriptions are not intended to be limiting.

[0033] Aspects of the present invention can be used to provide novel and effective techniques for power amplifier clipping to reduce and / or minimize distortion or other performance degradation that may be associated with driving the power amplifier beyond the configured output level or other operating range. In some embodiments, the systems and techniques described herein can be used to implement a PA of improved efficiency based on combining outputs from two or more separate PAs, where the separate PAs operate for different ranges or values ​​of the input signal or signal components. In one exemplary embodiment, a switched-capacitor power amplifier (ScPa) is used to solve problems and issues typically associated with the use of digital-to-analog converters (DACs), since the ScPa is a fully digital power amplifier. Aspects of the present disclosure include implementations in which the ScPa is provided in combination with a complementary metal-oxide-semiconductor (CMOS) system in which it is integrated.

[0034] Aspects and embodiments of the present invention correspond to providing a digitally controlled ScPa system for power amplification for improved power efficiency. For example, a digitally controlled ScPa system can combine the outputs of two separate ScPas, at least in part on the observation that the output impedance of the ScPas is constant at all gain settings. Advantageously, embodiments of the present disclosure can be implemented by configuring and / or reconfiguring components already present in the ScPa to obtain a combiner for combining the outputs of two separate PAs. Thus, the improved-efficiency digitally controlled ScPa systems described herein can be implemented without the need to add additional large and / or complex physical circuits, etc. In some embodiments, aspects of the present disclosure include the ability to configure amplifier control to combine a common-mode (I) signal and a quadrature-phase (Q) signal without experiencing the efficiency degradation typically associated with a combined mixer when operating in a Cartesian coordinate system. Furthermore, the system and technology can be used to provide changes to combiner configurations that can maximize power efficiency at multiple backoff levels, including efficiency maximization at 12 dB backoff and efficiency maximization at 6 dB backoff. [Examples]

[0035] Figure 1 is a block diagram illustrating an exemplary wireless communication network 100. In some embodiments, the wireless communication network 100 may be an example of a wireless local area network (WLAN). As used herein, a WLAN may be a Wi-Fi network. In some examples, the WLAN 100 may be a network implementing at least one of the IEEE 802.11 family of wireless communication protocol standards (e.g., defined by the IEEE 802.11-2020 specification or its modifications including but not limited to 802.11ah, 802.11ay, 802.11ax, 802.11az, 802.11ba, and 802.11be). The WLAN 100 may include at least one AP 102 and a plurality of associated STAs 104. For example, the STAs 104 may include a first STA 104a, a second STA 104b, a third STA 104c, a fourth STA 104d, and so on. Although only one AP 102 is shown, the WLAN network 100 can also contain multiple APs 102.

[0036] Each of STA 104a-104d may be referred to as a mobile station (MS), mobile device, mobile handset, wireless handset, access terminal (AT), user equipment (UE), subscriber station (SS), and / or subscriber unit. STA 104 can represent a variety of devices, including mobile phones, handheld devices, netbooks, computers, tablet computers, laptops, display devices (e.g., televisions, computer monitors, navigation systems, etc.), music or other audio or stereo devices, remote control devices ("remote controls"), printers, kitchen or other household appliances, and key fobs (e.g., for passive keyless entry and start (PKES) systems).

[0037] A single AP 102 and its associated set of STAs 104a-104d are sometimes referred to as a basic service set (BSS) managed by each AP 102. Figure 1 further illustrates an example of a coverage area 106 of AP 102, which may represent a basic service area (BSA) of WLAN 100. A BSS can be identified to users by its Service Set Identifier (SSID) and to other devices by its Basic Service Set Identifier (BSSID), which may be the Media Access Control (MAC) address of AP 102.

[0038] AP 102 periodically broadcasts beacon frames ("beacons") containing the BSSID so that any STAs within AP 102's wireless range (e.g., one or more, or all, of STAs 104a-104d) can associate with or reassociate with AP 102 and establish their respective communication links 108a-108d (e.g., also hereafter referred to as "Wi-Fi links"). For example, the first STA 104a can establish its respective communication link 108a with AP 102, the second STA 104b can establish its respective communication link 108b with AP 102, the third STA 104c can establish its respective communication link 108c with AP 102, and the fourth STA 104d can establish its respective communication link 108d with AP 102. STAs 104a to 104d can further utilize beacon frames broadcast by AP 102 to maintain their respective communication links 108a to 108d with AP 102. For example, the beacon may include identification of the primary channel used by each AP 102, as well as timing synchronization functionality to establish or maintain timing synchronization with AP 102. AP 102 can then provide access to the external network to various STAs within the WLAN via their respective communication links 108.

[0039] To establish communication links 108a–108d with AP 102, each STA 104a–104d can perform passive or active scan operations ("scan") on frequency channels in one or more frequency bands. For example, to perform a passive scan, each of the STAs 104a–104d listens for beacons transmitted by AP 102 at regular time intervals called the Target Beacon Transmission Time (TBTT). The TBTT can be measured in units of time (TU). In some examples, 1 TU may be equal to 1024 microseconds (μs). In some examples, the TBTT may have a default value of 102.4 milliseconds (ms). To perform an active scan, each of the STAs 104a–104d can generate and sequentially transmit probe requests on each channel being scanned and listen for probe responses from AP 102. Each of the STAs 104a to 104d may be configured to identify or select an AP 102 to associate with (for example, based on scan information obtained through passive or active scanning) and perform authentication and association operations to establish their respective communication links 108a to 108d with the selected AP 102. Upon completion of the association operation, AP 102 assigns an Association Identifier (AID) to each of the STAs 104a to 104d, which AP 102 uses to track the STAs 104a to 104d.

[0040] In some examples, one or more STAs 104a-104d may have the opportunity to select one of several BSSs within the STA's range, or to select from several APs 102 that form an Extended Service Set (ESS) containing multiple connected BSSs. The Extended Network Station associated with the WLAN 100 may be connected to a wired or wireless distribution system that enables multiple APs 102 to be connected in the ESS. In some examples, one or more STAs 104a-104d may be covered by multiple APs 102 and may be associated with different APs 102 at different times for transmission. After association with an AP 102, one or more STAs 104a-104d may be configured to periodically scan its vicinity to find and associate with a more suitable AP. For example, a particular STA 104a-104d that is far from its associated AP 102 may perform a “roaming” scan to find another AP with more favorable network characteristics (e.g., higher received signal strength indicator (RSSI), lower traffic load, etc.).

[0041] In some cases, STAs 104a-104d can form a network without any other equipment other than AP 102 or the STAs 104a-104d themselves. One example of such a network is an ad-hoc network. Some examples of ad-hoc networks are mesh networks and peer-to-peer (P2P) networks. In some cases, an ad-hoc network may be implemented within a larger wireless network. In such implementations, STAs 104a-104d can communicate with each other via AP 102 using their respective communication links 108a-108d, but STAs 104a-104d can also communicate directly with each other using wireless link 110. In some cases, two STAs can communicate directly via communication link 110 regardless of whether both STAs 104 are associated with and serviced by the same AP 102. In such ad-hoc systems, one or more STAs 104a-104d may take on the role that AP 102 plays in the BSS. Such STAs are called Group Owners (GOs) and may coordinate transmissions within an ad-hoc network. Examples of direct wireless links include one or more Wi-Fi Direct connections, connections established using Wi-Fi Tunnel Direct Link Setup (TDLS) links, and other P2P group connections.

[0042] AP 102 and STA 104a-104d can function and communicate using their respective communication links 108a-108d, in accordance with at least one of the IEEE 802.11 wireless communication protocol standards. These standards define the WLAN radio and baseband protocols for the physical (PHY) layer and media access control (MAC) layer. For example, AP 102 and STA 104a-104d transmit and receive radio communications from each other in the form of PHY protocol data units (PPDUs) or Physical Layer Convergence Protocol (PLCP) PDUs. AP 102 and STA 104a-104d of WLAN 100 can transmit PPDUs over licensed or unlicensed spectrum, which may be part of the spectrum including frequency bands traditionally used in Wi-Fi technology, such as the 2.4 GHz, 5 GHz, 60 GHz, 3.6 GHz, and sub-1 GHz bands. Some implementations of AP 102 and STA 104a-104d described herein can also communicate in other frequency bands, such as the 6 GHz band, which can support both licensed and unlicensed communications. AP 102 and STA 104a-104d can also be configured to communicate over other frequency bands, such as shared license frequency bands, which can have licenses operating in the same or overlapping frequency bands.

[0043] Each frequency band can contain multiple subbands or frequency channels. For example, a PPDU compliant with the IEEE 802.11 standard and specifications may be transmitted over a frequency band divided into multiple 20 MHz channels. In such an example, the PPDU is transmitted over a physical channel with a minimum bandwidth of 20 MHz, but other channel bandwidths are also available. In some examples, channel bonding can be used to combine multiple channels with the minimum bandwidth to form a channel with a larger bandwidth.

[0044] Each PPDU is a composite structure containing a PHY preamble and a payload in the form of a PHY Service Data Unit (PSDU). The information provided in the preamble can be used by the receiving device to decode subsequent data within the PSDU. When a PPDU is transmitted over a combined channel, the preamble fields are duplicated and may be transmitted on each of the multiple component channels. The PHY preamble may contain both a legacy portion (or "legacy preamble") and a non-legacy portion (or "non-legacy preamble"). The legacy preamble may be used for packet discovery, automatic gain control, channel estimation, etc. The legacy preamble may also be used to maintain compatibility with legacy devices in general. The format, coding, and information provided in the non-legacy portion of the preamble are based on the specific IEEE 802.11 protocol used to transmit the payload.

[0045] Figure 2A is a high-level block diagram of an exemplary wireless communication device 200 that can be used to implement an STA or AP in several examples. The wireless communication device 200 may include one or more MAC and PHY layers compliant with the IEEE 802.11 standard.

[0046] The wireless communication device 200 includes a radio frequency (RF) transmitter module 202, an RF receiver module 204, an antenna unit 206, one or more memory banks 208, input and output interfaces 210, and a communication bus 212. The RF transmitter module 202 and the RF receiver module 204 include a modem (modulator-demodulator device) that transmits data by modulating one or more carrier wave signals to encode digital information, and receives data by demodulating the signals to reconstruct the original digital information. As shown in the figure, the wireless communication device 200 further includes a MAC processor 214, a PHY processor 216, and a HOST processor 218. These processors can be any type of integrated circuit (IC), such as a general-purpose processing unit, an application-specific integrated circuit (ASIC), or a Reduced Instruction Set Computer-Five (RISC-V) based IC.

[0047] Memory 208 may be used to store software and / or computer-readable instructions, including software or instructions for implementing at least some functions of the MAC layer. For example, each processor included in the wireless communication device 200 (e.g., MAC processor 214, PHY processor 216, HOST processor 218, etc.) runs its respective software to implement the functions of its respective communication / application layer.

[0048] The PHY processor 216 includes a transmit signal processing unit and a receive signal processing unit (not shown) which can be used to manage the interface with the radio medium (WM). The PHY processor 216 operates the PPDU by exchanging digital samples with a radio module which includes an RF transmitter 202, an RF receiver 204, an analog-to-digital converter, and a digital filter.

[0049] The MAC processor 214 executes MAC-level instructions and manages the interface between the application software and the WM via the PHY processor 216. The MAC processor 214 is responsible for coordinating access to the WM so that access points (APs) and STAs within range can communicate effectively. The MAC processor 214 adds header and tail bytes to the data units provided from higher levels and sends them to the PHY layer for transmission. When data is received from the PHY layer, the reverse process is performed. If a frame is received with an error, the MAC processor 214 manages the retransmission of the frame.

[0050] The HOST processor 218 interfaces with the MAC layer and is responsible for performing higher-level functions of wireless communication devices.

[0051] The PHY processor 216, MAC processor 214, HOST processor 218, peripheral bus 220, memory 208, and I / O interface 210 communicate with each other via peripheral bus 212. Peripheral bus 220 connects to numerous peripherals supporting the core functions of the wireless communication device 200, including timers, interrupts, radio / filter / system registers, counters, UART, and GPIO interfaces. Memory 208 can further store the operating system and applications. In some examples, the memory can store recorded information about captured frames and packets. The I / O interface unit 210 enables the exchange of information with the user of the wireless communication device. The antenna unit 206 may include a single antenna and / or multiple antennas. For example, multiple antennas can be used to implement Multiple Input Multiple Output (MIMO) technology.

[0052] Figure 2B shows a schematic block diagram of a receiver dataflow architecture 250 that can be used to receive Wi-Fi packets over a network. In one exemplary embodiment, the receiver dataflow architecture 250 shown in Figure 2B may correspond to, or otherwise relate to, the wireless communication device 200 shown in Figure 2A. A wireless signal is received via a WM and converted into an electrical signal by a receiving antenna 252 (which may be the same as, or similar to, antenna 206, for example). The received signal is tuned using a series of analog filters 254 (which may be shown as analog RF receiving (Rx) filters, for example) and then converted into a digital signal equivalent using an analog-to-digital converter (ADC) 256. The sampled signal output of the ADC 256 is tuned again using a filter bank 258 which may include one or more digital RF filters and / or Faro filters before the samples are collected into an asynchronous receive First-In-First-Out (FIFO) data structure 260.

[0053] Samples of the FIFO structure 260 can be accessed by multiple modules. For example, samples can be accessed by a packet detection module and a subband module, which may be included in the lower-level PHY portion 262 shown in Figure 2B. In some embodiments, the lower-level PHY portion 262 itself is included in the PHY processor 216 shown in Figure 2A.

[0054] The packet detection module included in the lower-level PHY section 262 may implement hardware and / or algorithms that can be used to analyze the initial section of the PPDU in the time domain. Based on the analysis, the packet detection module can recognize the received frame and use it to synchronize the frequency and timing of the radio communication device with the packet being received. The subband module included in the lower-level PHY section 262 may include hardware and / or implementation algorithms that can be used to detect which subchannel of the allocated frequency band is being used for the received packet.

[0055] Once a packet is detected and the relevant subchannel is established, the sample may be forwarded to the upper-level PHY portion 264. The upper-level PHY portion 264 may be contained within the PHY processor 216 shown in Figure 2A. In some embodiments, the upper-level PHY portion 264 can be used to process and decode orthogonal division multiplexing (OFDM) symbols (with the support of a coprocessor module) to reconstruct a complete PPDU. The reconstructed PPDU is output by the upper-level PHY portion 264 and subsequently processed by the MAC layer processor 266. The MAC layer processor 266 can extract the data payload from the PPDU and provide the relevant information to the HOST layer 268 for consumption.

[0056] In some examples, the MAC layer processor 266 shown in Figure 2B may be the same as or similar to the MAC processor 214 shown in Figure 2A. In some examples, the HOST layer 268 shown in Figure 2B may include, or be the same as or similar to, the HOST processor 218 shown in Figure 2A.

[0057] Figure 2C is a schematic block diagram of a transmitter dataflow architecture 280 that can be used to transmit RF signals over a wireless medium according to several embodiments. More specifically, Figure 2C shows a simplified schematic block diagram of a transmitter dataflow architecture 280 used to transmit wireless signals over a WM. Data can be generated from the HOST or APP module 282 and packaged into MAC-Level Protocol Data Units (MPDUs) for routing over the wireless network by the MAC Management Module 284. The PHY module 286 interfaces with the WM and compiles the PPDU by adding a PHY preamble and tail to the MPDU. Typically, a modulation coding scheme (MCS) for packet transmission over the medium is established by the MAC module 284 or PHY module 286 using a rate control algorithm. The selected modulation scheme can define the modulation technique and coding rate used to transmit data over the WM. Based on the selected modulation scheme, e.g., quadrature amplitude modulation (QAM) 64, the PPDU is modulated for transmission over the WM. The encoder module 288 generates signals corresponding to points in a QAM constellation symbol (a group of bits in PPDU) that can be encoded using polar coordinates (r-θ) or Cartesian coordinates (QI). Modulation is performed by linking the encoder module 288 to a digital phase-locked loop (DPLL) 290. The modulated signal can be filtered by an analog filter 292 and transmitted using the transmitting antenna 294.

[0058] Many modern wireless systems use orthogonal frequency division multiplexing (OFDM) modulation schemes with relatively large peak-to-average power ratio (PAPR) values. For example, a larger PAPR value corresponds to a larger difference between the peak RF output power and the average RF output power of the wireless system. As mentioned above, wireless systems often include one or more power amplifiers (PAs) that achieve maximum power efficiency when the PA operates at its maximum output power, and the power efficiency of the PA decreases significantly as the output power decreases from its maximum. A higher PAPR value corresponds to a larger difference between the peak power level and the average power level, and generally, it is undesirable to allow the wireless system to tolerate the peak RF output power level exceeding the PA's maximum output power (e.g., to avoid distortion). Therefore, the peak power level is usually constrained to remain within the PA's maximum output capability, and the average power level is backed off to remain below the PA's maximum output. Thus, a high PAPR signal may correspond to the PA operating significantly below the peak output level, resulting in poor power efficiency.

[0059] There is a need for systems and technologies that can be used to improve the power efficiency of PAs when operating with relatively high or relatively large power backoff. For example, most Wi-Fi systems (an example of wireless systems using one or more PAs) operate with PAPRs between 8 decibels (dB) and 12 dB. The average power level of a Wi-Fi system with an 8-12 dB PAPR is about 10% of the peak power level, and therefore the power amplifiers of Wi-Fi systems operate in a suboptimal power efficiency regime for most of the time. One technique proposed to maximize PA efficiency with a 6 dB backoff is based on combining the outputs of two separate PAs, where one PA is capable of operating across the entire desired output power range, and the other PA is normally off and can act as a boost amplifier at high output levels. This combination allows both power amplifiers to operate near maximum efficiency for more of the power range and for more time. There is still a need for systems and technologies that can be used to apply the proposed technique to modern integrated PAs and / or DPAs.

[0060] For example, combining the outputs of two separate PAs, one operating within its configured power range and the other usable as a high-power boost amplifier, has traditionally been difficult to implement in modern integrated PAs due to the large size of the required combiner components and the difficulty of designing a combiner that can consistently match the output impedance of each of the two PAs. For instance, the output impedance of each PA often varies considerably depending on the total output power.

[0061] In some embodiments, the systems and techniques described herein can be used to implement an improved efficiency PA based on combining outputs from two or more separate PAs, as described above. In one exemplary example, a switched-capacitor power amplifier (ScPa) is used to solve problems and issues typically associated with the use of digital-to-analog converters (DACs), since the ScPa is a fully digital power amplifier. Embodiments of this disclosure include implementations in which the ScPa is provided in combination with a complementary metal-oxide-semiconductor (CMOS) system in which it is integrated.

[0062] The systems and techniques described herein can be used to provide a digitally controlled ScPa system for power amplification with improved power efficiency. For example, a digitally controlled ScPa system can combine the outputs of two separate ScPas, at least in part on the observation that the output impedance of the ScPas is constant at all gain settings. Advantageously, embodiments of the present disclosure can be implemented by configuring and / or reconfiguring components already present in the ScPa to obtain a combiner for combining the outputs of two separate PAs. Thus, the improved-efficiency digitally controlled ScPa systems described herein can be implemented without the need to add additional large and / or complex physical circuits, etc. In some embodiments, aspects of the present disclosure include the ability to configure amplifier control to combine a common-mode (I) signal and a quadrature-phase (Q) signal without experiencing the efficiency degradation typically associated with a combined mixer when operating in a Cartesian coordinate system. Furthermore, the systems and techniques can be used to provide changes in combiner placement that can maximize power efficiency at multiple backoff levels, such as maximizing efficiency at a 12 dB backoff or maximizing efficiency at a 6 dB backoff.

[0063] In some embodiments, a digitally controlled switched-capacitor power amplifier comprises two arrays of CMOS inverters, each inverter driving its own unit capacitor, and each complete array of capacitors is connected to the primary input of an inductive balun / transformer. For example, a balun may refer to a type of transformer or electrical device configured to provide an interface between balanced and unbalanced lines (e.g., balanced-unbalanced, or "balun").

[0064] Figure 3 shows an example of a digitally controlled switched-capacitor power amplifier (ScPa) architecture 300, comprising two arrays of CMOS inverters, each array containing multiple capacitors that are either driven or undriven by the corresponding inverters within the array. For example, the ScPa architecture 300 includes a first array of CMOS inverters 310 (also called the first section of the ScPa) and a second array of CMOS inverters 330 (also called the second section of the ScPa). One array of inverters is driven by a square wave, and the other array is driven by an inverse square wave, both of which are desired RF output frequencies for the ScPa architecture 300. For example, the first inverter array 310 may be driven by a square wave 315, and the second inverter array 330 may be driven by an inverse square wave 335. The square wave 315 and the inverse square wave 335 may be associated with desired (e.g., configured, etc.) RF output frequencies for the ScPa architecture 300, respectively.

[0065] The first array 310 and the second array 330 each include a plurality of inverters (e.g., CMOS inverters). In each array, some inverters are driven and some are kept stationary. For example, a first subset of the plurality of CMOS inverters in the first array 310 is driven, while a second subset of the plurality of CMOS inverters in the first array 310 is kept stationary. Similarly, a first subset of the plurality of CMOS inverters in the second array 330 is driven, while a second subset of the plurality of CMOS inverters in the second array 330 is kept stationary. The proportion of inverters driven or kept stationary within a given array (e.g., the first array 310 or the second array 330) of the ScPa architecture 300 can be configured according to a digital amplitude control signal, for example, an amplitude code provided as input to the first array 310 and the second array 330. Based on varying the number of active or static inverters within a given array, the arrays form a capacitive voltage divider in which the output voltage amplitude is proportional to the number of active inverters. The complete differential inverter-capacitor-inductor circuit forms a series resonant circuit tuned to the desired operating frequency of the ScPa architecture 300, resulting in a high current at the desired operating frequency and attenuation of RF harmonics generated by the square wave drive signals (315, 335). As described above, the first array 310 and the second array 330 can be connected to the primary input of a balun (e.g., related to the primary coil), which in the example in Figure 3 is shown to consist of a balun primary coil 342 and a balun secondary coil 346. The high current in the balun primary coil 342 is coupled to the balun secondary coil 346, where the current is impedance-converted and converted into a single-terminated signal that can be directly driven to the transmitting antenna.

[0066] Each inverter in the ScPa array is either driven or held stationary, as described above. Since the static inverters have exactly the same output impedance as the clock-driven inverters, the impedance and frequency of the resonant circuit (e.g., the resonant circuit formed by the complete differential inverter-capacitor-inductor circuit in the ScPa architecture 300) are not affected by the digital code or amplitude control signals used to determine the proportion of inverters driven in the array.

[0067] Static units (e.g., a subset of inverters in an array that are kept stationary) attenuate signals by creating capacitive loads on active units (e.g., a subset of inverters in an array that are driven). Therefore, the power lost by inactive units (e.g., each inverter kept stationary) can be determined according to P=fCV, where P is the power consumption, f is the RF output frequency or switching frequency of the inverter, C is the capacitance, and V is the voltage. Since inactive inverter units still consume power through their capacitive loads, the efficiency of the ScPa decreases proportionally to the number of inactive units in each array. For example, a larger proportion of inactive inverter units in the ScPa results in greater power consumption by the inactive inverter units, and consequently, a lower overall ScPa power efficiency. Based on the fact that each inactive inverter unit consumes power according to P=fCV, it can be seen that the ScPa efficiency is maximized when all inverter units are active (e.g., this eliminates the power consumption / losses associated with keeping inactive inverters stationary).

[0068] Existing ScPa designs drive the primary coil of a balun (e.g., primary coil 342) with differential signals of different amplitudes from two inverter and capacitor arrays (e.g., first array 310 and second array 330). Aspects and embodiments of the present disclosure can be used to implement and / or provide a balun / transformer with improved common-mode rejection that enables driving an ScPa without using a conventional differential drive approach. For example, using an improved common-mode rejection balun / transformer eliminates the need for differential drive of the balun's primary coil 342, and the same or similar performance can be achieved by applying two independent drive signals across the balun's primary coil 342.

[0069] In some embodiments, the two inverter and capacitor arrays within the ScPa can be treated as independent amplifiers, enabling an efficiency-enhancing scheme in which the first PA output operates within a desired power range and the second PA output acts as a boost amplifier at a higher power level. For example, the first inverter and capacitor array 310 can be used as an independent amplifier associated with applying a first independent drive signal to the first end of the balun primary coil 342, and the second inverter and capacitor array 330 can be used as a second independent amplifier associated with applying a second independent drive signal to the second end of the balun primary coil 342. In some embodiments, the balun primary coil 342 can be used to provide the combination of the two inverter and capacitor arrays 310 and 330 required for efficiency enhancement (for example, the balun primary coil 342 can be used as a combiner component for an efficiency-enhancing ScPa configuration based on combining the outputs of two independent PAs operating in different power ranges). The combination function provided by the balun primary coil 342 is constant regardless of amplitude code, and the different amplitude outputs from the two inverter and capacitor arrays 310 and 330 are added with good linearity.

[0070] For example, Figure 4 shows an example of a composite drive scheme 400 of an ScPa architecture implemented using a non-orthogonal coordinate system. The ScPa architecture shown in Figure 4 may be the same as, or similar to, the exemplary ScPa architecture 300 in Figure 3. JPEG2026059739000002.jpg18152

[0071] In some embodiments, the method shown in Figure 4 is implemented by applying the lower half of the amplitude code 402 to the first inverter and capacitor array 410 while the second inverter and capacitor array 430 are kept stationary. The first inverter and capacitor array 410 in Figure 4 may be the same as or similar to the first array 310 in Figure 3. Similarly, the second inverter and capacitor array 430 in Figure 4 is Until it operates at its maximum efficiency, the second array 430 remains stationary and is applied only to the first array 410. For example, the first array 410 is fully driven and operates at its maximum configured output power level, which corresponds to the first array 410 operating at its maximum power efficiency. Once the first array 410 is fully driven and operating at maximum efficiency, the upper half of the amplitude code 404 can begin to be applied to the second inverter and capacitor array 430 while the first inverter and capacitor array 410 remains fully driven. In some examples, the driving scheme for the non-orthogonal coordinate system 400 shown in Figure 4, also referred to herein as a “combined scheme”, is based, for example, on using a balun primary coil to provide a combination of outputs for the first array 410 and the second array 430, respectively.

[0072] As described above, the combined drive system 400 in Figure 4 corresponds to an example of ScPa implemented in a non-orthogonal coordinate system. Figure 5 shows an example of an ScPa combined drive system 500 implemented in an orthogonal coordinate system of an ScPa architecture including a first inverter and capacitor array 510 and a second inverter and capacitor array 530. For example, a non-orthogonal coordinate system (e.g., polar coordinate system) can represent an RF input signal using magnitude and phase information, while an orthogonal coordinate system can use orthogonal coordinates to represent a signal, for example, using an in-phase (I) signal component and an orthogonal-phase (Q) signal component. In some examples, an orthogonal coordinate system can use separate amplification paths for the I and Q signal components and then recombine the I and Q signals from their respective separate amplification paths.

[0073] In the exemplary Cartesian coordinate system composite drive scheme 500, the first inverter and capacitor array 510 in Figure 5 may be the same as or similar to one or more of the first array 310 in Figure 3 and / or the first inverter and capacitor array 410 in Figure 4. The second inverter and capacitor array 530 in Figure 5 may be the same as or similar to one or more of the second array 330 in Figure 3 and / or the first inverter and capacitor array 430 in Figure 4. The Cartesian coordinate system uses two clocks that are 90 degrees out of phase, also called I and Q clocks. The I and Q components are coupled via different capacitor arrays, which are controlled by coding circuits that map the amplitudes of the I and Q components to different capacitor arrays, in particular, the amplitudes of the I and Q components are encoded into amplitude codes configured to control which capacitors in each array (e.g., the first array 510 and the second array 530) are driven, so that these capacitors are driven rather than statically held.

[0074] In some embodiments, the systems and techniques described herein can achieve power amplifier efficiency improvements (e.g., improvements, increases, etc.) for Cartesian coordinate systems similar to those provided above for non-Cartesian coordinate systems. For example, the same or similar power efficiency improvements can be achieved by dividing the I-amplitude code and the Q-amplitude code into upper and lower halves, respectively, and distributing the upper and lower halves of the I and Q-amplitude code between the first and second inverters and capacitor arrays 510 and 530, respectively.

[0075] JPEG2026059739000004.jpg31151Q can be used for input 504 consisting of the lower half of the amplitude code. In this example, each of the two arrays 510 and 530 is used for the lower half of one code (e.g., either the lower half of the I code or the lower half of the Q code) and the upper half of the other code (e.g., either the upper half of the Q code or the upper half of the I code). Each code is divided across the two arrays 510 and 530, and neither array processes only the lower half or only the upper half.

[0076] In some embodiments, assigning digital IQ amplitude codes to different branches of the amplifier's inverter and capacitor arrays (for example, assigning each I and Q amplitude code between the first inverter and capacitor array 510 and the second inverter and capacitor array 530) can configure the switched-capacitor power amplifier to operate each branch (for example, the first branch corresponding to array 510 and the second branch corresponding to array 530) at the maximum possible power and therefore with the maximum power efficiency.

[0077] In some embodiments, further improvements may be achieved by further subdividing the branches of the first inverter and capacitor array 510 and the second inverter and capacitor array 530. For example, the subdivision in the example of Figure 5 corresponds to a subdivision between the first branch of the inverter and capacitor array 510 and the second branch of the inverter and capacitor array 530. In some embodiments, one or more subdivisions can be applied to divide the inverter and capacitor arrays within the same branch (e.g., 510 or 530) into two halves, four quarters, etc. These further subdivisions allow the ScPa system to be operated or driven using two or more separate inverter and capacitor array branches that can be coupled in various different combinations.

[0078] For example, each of the two branches shown in Figure 5 (e.g., 510 and 530) can be divided or split into two halves to allow for the combination of a total of four separate inverter and capacitor array branches. For example, Figure 6 shows an example of a composite drive scheme 600 of the ScPa architecture implemented using a Cartesian coordinate system and four inverter and capacitor array branches. The I and Q amplitude codes can be divided into quarters and distributed to the first inverter and capacitor array branch 610-1, the second inverter and capacitor array branch 610-2, the third inverter and capacitor array branch 630-1, and the fourth inverter and capacitor array branch 630-2.

[0079] JPEG2026059739000005.jpg58151

[0080] The balun primary side can be implemented as a series resonant balun primary side formed from two tightly coupled inductors 642-1 and 642-2. The balun secondary side 646 may be the same as, or similar to, the balun secondary side 346 in Figure 3. Inductor 642-1 may be connected to the output of the second branch 610-2 and the third branch 630-1 of the inverter and capacitor array. Inductor 642-2 may be connected to the output of the first branch 610-1 and the fourth branch 630-2 of the inverter and capacitor array. The balun topology becomes more complex, but the overall dimensions of the balun shown in Figure 6 do not increase significantly.

[0081] Embodiments of the present invention make the application of the system to a Cartesian coordinate system more feasible. The concept of the present invention can be extended to multiple branches using multiple coupled transformers (e.g., baluns) on the primary side. As long as the transformers are not perfectly balanced among their multiple inputs, the combination will exhibit only a small linear gain difference between each coupled amplifier, which is much easier to correct than the complex pre-distortion techniques required for other integrated amplifier architectures.

[0082] As described above, the systems and techniques described herein can be used to improve the efficiency of switched-capacitor power amplifiers and / or various other digital power amplifiers. Digital PAs not only improve the energy efficiency of RF receivers but also reduce the required chip area. In the case of an ScPa digital PA implementation using a Cartesian coordinate system, the I and Q components of a signal are coupled through different capacitor arrays of the ScPa by using coding circuits to map the amplitudes of the respective I and Q components to different combinations of capacitor arrays in the ScPa. The amplitudes of the I and Q components are coded into amplitude codes to control or configure which capacitors in each capacitor array are turned on (e.g., rather than being held in a quiescent state). Aspects of this disclosure can be used to address the limitations of existing digital power amplification techniques, including the fact that the performance of conventional digital PAs degrades (e.g., degrades, becomes inferior, etc.) when the absolute values ​​of the I samples and the corresponding Q samples are too large.

[0083] Specifically, the performance of a digital PA degrades below an acceptable level when the sum of the absolute values ​​(e.g., magnitude) of the I and Q components exceeds a certain threshold. The threshold for digital PA performance degradation may be a value based on the number of bits used to represent the I and Q samples, and / or a corresponding value. For example, in a 16-bit DAC used in an RF receiver, each I and Q sample is represented by a 15-bit amplitude code, with 1 bit representing the sign and 15 bits representing the amplitude. The threshold to prevent digital PA performance degradation can be determined as 2 to the power of the bit lengths of the I and Q samples. In the example of a 16-bit DAC where each I and Q sample is a 15-bit amplitude code, the threshold for digital PA performance degradation is 2 15 = 32768.

[0084] In other words, the performance of the digital PA degrades when |I|+|Q|>32768, where I represents a sample on the common-mode path and Q represents a sample on the quadrature-phase path. The threshold for digital PA performance degradation can be determined according to the bit width of the DAC or the number of bits used to represent the amplitude of the I / Q samples, as described in the example above. In some cases, digital PA performance degradation may be caused by undesirable mirror behavior exhibited by the digital PA when the sum of the absolute values ​​of I and Q exceeds a threshold. For example, mirror image distortion by ScPa occurs for I / Q samples where the sum of the absolute values ​​of I and Q exceeds the threshold. In some cases, these IQ samples whose sum exceeds the threshold may be indicated by clipping diamonds superimposed on the IQ constellation diagram. IQ samples inside (e.g., enclosed) the clipping diamond are IQ samples whose sum of magnitude is less than the digital PA performance degradation threshold. IQ samples outside the clipping diamond are I / Q samples whose sum of magnitude is greater than the digital PA performance degradation threshold. The IQ samples on the clipping rhombus are IQ samples whose total size is equal to the digital PA performance degradation threshold.

[0085] As an example, aspects and embodiments of the present invention can be used to correct mirror image distortion by analog circuit blocks in a digital PA. In a conventional orthogonal ScPa system, two sub-ScPas are provided, one sub-ScPa dedicated to the I signal and the other sub-ScPa dedicated to the Q signal. The number of capacitors switched between VDD (e.g., positive power supply voltage / high voltage rail) and Vground (e.g., low voltage rail / reference ground) in each sub-ScPa is between 0 and 1 / 2 of the total number of capacitors N. The total number of capacitors in the dedicated capacitor arrays for the I and Q signals shows a decrease in efficiency due to the division where each sub-ScPa uses only a portion of the total array, corresponding to the dedicated IQ array architecture having 3-6 dB lower output power and degraded drain efficiency compared to an equivalent polar coordinate ScPa. The orthogonal IQ shared cell ScPa employs coupled unit vectors with flexible vector assignments that increase output power.

[0086] Figure 7 is an IQ constellation figure 700 showing a clipping diamond 750 corresponding to the performance degradation threshold of a digital power amplifier. For example, the clipping diamond 750 can correspond to the digital PA performance degradation threshold discussed above, which has a value of num_bits equal to the number of bits used to represent the bit width of the DAC or the amplitude of the I / Q sample. num_bits It is given by raising it to a power. In some embodiments, the clipping rhombus 750 is a constructed threshold (for example, |I|+|Q|=2 num_bits Includes a set of IQ samples having a set of IQ samples having a set of IQ samples having a set of IQs num_bits Includes a set of IQ samples that have (a set of IQ samples that have [a certain characteristic]).

[0087] In the example in Figure 7, clipping is shown from a request point 730 corresponding to an IQ sample within the clipping region (e.g., outside the clipping rhombus 750) to a clip point 735 located on the clipping rhombus 750. Clipping from the request point 730 to the clip point 735 can be used to reduce or prevent performance degradation associated with exceeding a configured threshold of the clipping rhombus 750 and can be used to prevent or mitigate the undesirable mirroring behavior described above. As an example, clipping from the request point 730 to the clip point 735 can be performed according to an analog clipping scheme configured for DPA and / or ScPa systems, according to various embodiments of the present invention. For example, in some embodiments, the clipping scheme can be performed to clip from various request points consisting of I / Q samples within the clipping region (e.g., outside the clipping rhombus 750) to their respective clip points located on or inside the clipping rhombus 750. In some embodiments, each clip point includes an orthogonal projection of any request point within the clipping region onto the clipping profile provided by the clipping rhombus 750.

[0088] In some embodiments, the analog clipping scheme can be implemented by setting two control bits configured to control each output unit of the capacitor array in an IQ shared cell ScPa system, thereby providing prioritization and / or processing logic for any "double-enabled" units commanded simultaneously by both the I and Q signals.

[0089] In particular, the clipping diamond 750 can correspond to the boundary of the linear operating region of an amplifier where the total number of active units required for a combination of I and Q codes (e.g., IQ samples) does not exceed the available capacitance of the total number of capacitor units N in the capacitor array of the IQ shared cell ScPa. For example, the number of capacitor units required by the I code is |I| and the number of capacitor units required by the Q code is |Q|, which corresponds to the degradation condition described above where performance degradation of the digital PA is observed when |I|+|Q|>threshold. Thus, the clipping diamond 750 can be considered to represent a threshold given by the total number of capacitor units N in the shared cell ScPa array. The IQ samples within the clipping diamond 750 do not exceed the number of output units in the capacitor array and satisfy |I|+|Q|≦N. The IQ samples outside the clipping diamond 750 are combinations of I and Q amplitudes where the number of units exceeds the total number of capacitor units in the capacitor array, i.e., |I|+|Q|>N.

[0090] In an IQ shared cell ScPa, each output cell (N) of the capacitor array can be driven by either an I clock or a Q clock. The output cells of the capacitor array are also referred to herein as “output units,” “capacitor units,” and / or “capacitor cells.” As described above, there is a limit to the number of output cells driven by the I and Q clocks, and this limit depends on the number of output units N in the capacitor array. This limit arises when the sum of the number of output cells driven or requested by the I clock (e.g., |I|) and the number of output cells driven or requested by the Q clock (e.g., |Q|) is greater than the number of output units N in the shared capacitor array (e.g., |I| + |Q| > N).

[0091] In some embodiments of the IQ shared cell ScPa, each output unit of a plurality of output units (e.g., N) in a shared capacitor array may be implemented with two control bits to define the operating state of each output unit. For example, a first control bit may be used to enable and / or prioritize operation from the I clock, and a second control bit may be used to enable and / or prioritize operation from the Q clock. The first control bit may also be referred to herein as the “I control bit” or “I clock control bit”. The second control bit may also be referred to herein as the “Q control bit” or “Q clock control bit”. Each control bit can take a low value (e.g., “0”) or a high value (e.g., “1”).

[0092] For example, if both control bits of a given output unit in a capacitor array are set low (e.g., I control bit = 0, Q control bit = 0), the operating state of the output unit is set to "off". If one control bit is set high and the other control bit is low, the operating state of the output unit is driven by either the I clock or the Q clock, which has a higher control bit value. For example, setting I control bit = 1 and Q control bit = 0 corresponds to the output unit's operating state being driven by the I clock. Similarly, setting I control bit = 0 and Q control bit = 1 corresponds to the output unit's operating state being driven by the Q clock.

[0093] When ScPa enters the clipping region (e.g., the clipping region beyond clipping rhombus 750 in Figure 7), the number of output cells required by I and Q is greater than the number of output cells in the capacitor array, |I|+|Q|>N. Within the clipping region, some of the output cells of the capacitor array are "double enabled," with both the I control bit and the Q control bit set to high. For example, an output cell of a capacitor array is double enabled when I control bit=1 and Q control bit=1. In IQ shared cell ScPa, the shared cell design of the capacitor array allows the same capacitor array to be shared between the I clock and the Q clock, but individual cells / output units within the capacitor array are driven by either the I clock or the Q clock, but only one at a time (e.g., individual cells / output units themselves are not shared and cannot be driven by I and Q simultaneously). Therefore, a double-enable control bit state with both the I control bit and the Q control bit can cause contention in the double-enable output cells of the capacitor array. In a shared capacitor array, double-enable output cells are a subset of cells where both control bits are set high, i.e., output cells that receive the I and Q clocks for the ScPa to enter the clipping region. In some ScPa designs, double-enable output cells are simply deactivated, kept quiescent, or have their operating state set to "off" due to the incompatibility of the double-enable control bit state with the requirement that a given output cell in the capacitor array is driven by either the I clock or the Q clock or only one of the two.

[0094] In some embodiments, the number of double-enable cells when ScPa enters the clipping region is equal to |I|+|Q|-N, or the number of units required by I and Q exceeding the number of units N in the shared capacitor array. In the example shown in Figure 7, the “I code” 760 and the “Q code” 770 correspond to the required point 730 located within the clipping region beyond the clipping rhombus 750. The total number of output units in the capacitor array is N, and the clipping rhombus 750 intersects the I axis at (I=N, Q=0), and the clipping rhombus 750 intersects the Q axis at (I=0, Q=N).

[0095] I-code 760 is shown divided into a first I-code portion 762, a second I-code portion 764, and a third I-code portion 766. Similarly, Q-code 770 is shown divided into a first Q-code portion 772, a second Q-code portion 774, and a third Q-code portion 776.

[0096] The second and third I-code portions 764 and 766 are double-enabled with the second and third Q-code portions 774 and 776. The number of double-enabled cells is the same in I-code 760 and Q-code 770, i.e., the number of output cells for I-code portions 764 and 766 = the number of output cells for Q-code portions 774 and 776. The number of double-enabled output cells associated with request point 730 is equal to |I| + |Q| - N.

[0097] The first I code portion 762 corresponds to a set of output cells driven by I without being double-enabled (e.g., a set of output cells with I control bit = 1 and Q control bit = 0). The first Q code portion 772 corresponds to a set of output cells driven by Q without being double-enabled (e.g., a set of output cells with I control bit = 0 and Q control bit = 1).

[0098] Embodiments of the present invention can be used to provide an analog clipping scheme that controls the operating state behavior of one or more double-enabled output cells when both control bits are set high (e.g., I control bit = 1, Q control bit = 1). The analog clipping scheme can be implemented locally at each output unit of the shared capacitor array, thereby allowing each double-enabled output unit to determine its respective priority for selecting either the I or Q control bit when each output unit is double-enabled. By providing local prioritization logic at each output unit of the capacitor array, the double-enabled units still contribute to the coupled output signal of the IQ shared cell ScPa (rather than setting its operating state to "off" in response to being double-enabled, as may occur in existing ScPa designs). The analog clipping scheme can be implemented as local analog logic, circuitry, etc., associated with each output cell / unit of the shared capacitor array, thereby enabling request points outside the clipping diamond 750 (e.g., request point 730) to automatically clip around the clipping diamond 750 without requiring a central clipping module to globally detect the clipping state and reconfigure the ScPa accordingly.

[0099] In some embodiments, analog clipping logic can be implemented locally for each output cell / unit of the shared capacitor array to define the behavior of the output cell's operating state when both control bits are set high. Output cells with both control bits set high are also called double-enabled output cells. In some embodiments, the analog clipping scheme applied by the IQ shared cell ScPa results in a prioritization logic being applied to the first half of the double-enabled output cells to operate from the I clock, and a prioritization logic being applied to the second half of the double-enabled output cells to operate from the Q clock. For example, the analog clipping scheme can be implemented locally by assigning or configuring a priority to each output cell of each of the multiple output cells N of the shared capacitor array. Half of the output cells N may be configured to prioritize operation from the I clock when the cell is double-enabled, and the other half of the output cells N may be configured to prioritize operation from the Q clock when the cell is double-enabled.

[0100] In the example in Figure 7, the local prioritization logic of the analog clipping scheme results in an orthogonal projection of any request point 730 from outside the clipping rhombus 750 to a position on the clipping rhombus 750. The orthogonal projection is based on local prioritization logic that prioritizes half of the double-enabled bits to operate from the I clock and half of the double-enabled bits to operate from the Q clock.

[0101] For example, clip point 735 in Figure 7 corresponds to a valid I-code (e.g., a clipped I-code) corresponding to the first and second I-code sections 762 and 764 from which the third I-code section 766 has been removed (e.g., clipped). Similarly, clip point 735 corresponds to a valid Q-code (e.g., a clipped Q-code) corresponding to the first and second Q-code sections 772 and 774 from which the third Q-code section 776 has been removed (e.g., clipped).

[0102] I-code section 764 represents half of a double-enable cell that prioritizes operation from the I clock. I-code section 766 represents half of a double-enable cell that is clipped, with the I control bit set high, but is locally configured to prioritize the Q control bit and ignore the I control bit.

[0103] Similarly, Q code section 774 represents half of a double-enable cell that prioritizes operation from the Q clock. Q code section 776 represents half of a double-enable cell that is clipped, with the Q control bit set high, but is locally configured to prioritize the I control bit and ignore the Q control bit.

[0104] In some embodiments, the analog clipping scheme can be implemented according to different truth table configurations that can be applied to and / or defined for alternately interleaved output cells in a capacitor array. Half of the double-enabled output cells use the I clock when both the I clock and Q clock are enabled, and the other half of the double-enabled output cells use the Q clock when both the I clock and Q clock are enabled. In some embodiments, the divided priority between the I clock and Q clock of the double-enabled output cells can be implemented based on ScPa utilizing different truth tables for even-indexed and odd-indexed output cells (for example, based on half of the ScPa capacitor array output cells being even-indexed and half being odd-indexed): JPEG2026059739000006.jpg67148 Table 1 Example of truth table configuration for IQ shared cell ScPa. Here, the truth table is configured for the output cells of even and odd indices in the capacitor array. "EN_I" corresponds to the I control bit, and "EN_Q" corresponds to the Q control bit, with a value of "0" corresponding to low and a value of "1" corresponding to high. "State" represents the operating state of the output cell.

[0105] In the example in Table 1, the truth table for the even-indexed output cells is configured to prioritize operation where each even-indexed output cell in the capacitor array is driven by the I clock, so that the even-indexed output cells operate from the I clock when double-enabled. The truth table for the odd-indexed output cells is configured to prioritize operation where each odd-indexed output cell in the capacitor array is driven by the Q clock, so that the odd-indexed output cells operate from the Q clock when double-enabled.

[0106] As shown in Figure 7, instead of driving the output cell N of the capacitor array with the original Q code 770 and I code 760 corresponding to the request point 730, the output cell is driven by the active Q and I codes clipped to the boundary of the clipping diamond 750. The active Q code (e.g., consisting of Q code portions 772 and 774) is realized by assigning the number of output cells activated according to the original Q code to the double-enabled output cell, where both control bits (EN_I, EN_Q) of the double-enabled output cell are equal to 1. Similarly, the active I code (e.g., consisting of I code portions 762 and 764) is realized by assigning the number of output cells activated by the original I code to the double-enabled output cell. Based on the truth table in Table 1 above, the operating state of the even-indexed double-enabled output cell (1, 1) is the I clock, and the operating state of the odd-indexed double-enabled output cell (1, 1) is the Q clock.

[0107] For example, the I-code portion 764 can correspond to double-enabled output cells for even indices configured to prioritize I-codes by truth table. The clipped I-code portion 766 can correspond to double-enabled output cells for odd indices configured to prioritize Q-codes by truth table. Similarly, the Q-code portion 774 can correspond to double-enabled output cells for these odd indices configured to prioritize Q-codes by truth table (for example, the double-enabled output cells used for the valid Q-code and portion 774 may be the same as the double-enabled output cells clipped as portion 766 removed from I-code 760). The Q-code portion 776 can correspond to double-enabled output cells for even indices configured to prioritize I-codes by truth table (for example, the double-enabled output cells used for the valid I-code and portion 764 may be the same as the double-enabled output cells clipped as portion 776 removed from Q-code 770).

[0108] In another embodiment, even-indexed double-enabled output cells are Q-clock enabled, and odd-indexed double-enabled output cells are I-clock enabled. This reduces the number of I-clock enabled output cells by half the number of double-enabled output cells, and the number of Q-clock enabled output cells by half the number of double-enabled output cells, thereby achieving the desired clipping behavior from the requested point to the clipping point.

[0109] FIG. 8 shows, according to an embodiment of the present invention, an example of capacitor array unit (e.g., output cell) allocation 800 when clipping is not required in the IQ sharing cell ScPa, and an example of capacitor array unit allocation 850 when clipping is required in the IQ sharing cell ScPa. In the exemplary allocation 800, when the total number of I and Q valid output cells is less than the total number of output cells N (e.g., |I| + |Q| < N), clipping is not required. In the example of non-clipping allocation 800, a subset of the output cells has an "off" operating state, where the number of output cells having an "off" operating state = N - |I| - |Q|.

[0110] In the example of clipping allocation 850, when the sum of the absolute value of I and the absolute value of Q is greater than the number of output cells N (e.g., |I| + |Q| > N), the number of output cells equal to the difference between |I| + |Q| and N (e.g., |I| + |Q| - N) becomes double-enabled output cells. The operating states of these double-enabled output cells are determined according to the above local analog clipping logic and are locally implemented at each output cell of the capacitor array, for example, according to an exemplary truth table in Table 1. In some aspects, the double-enabled output cells have an operating state set to alternate I and Q clock enable such that half of the double-enabled output cells have an operating state with I clock valid and the other half have an operating state with Q clock valid.

[0111] In some examples, the capacitor array of an ScPa output unit is typically driven from a high-voltage rail (e.g., IO voltage) to maximize output power, while the clock tree and control code tree run from a low-voltage rail (e.g., core voltage) to maximize speed and minimize gate area and operating current. Therefore, the clock signal driving each output unit is voltage-level shifted to control the PMOS switch devices of the output units. Conventional logic-level voltage shifters are relatively large, slow, and current-consuming when used with the potentially and / or desirablely faster clock speeds used in ScPa output units. Systems and techniques that can vary the voltage of the high-voltage rail are beneficial because changing (e.g., altering) the voltage of the high-voltage rail can provide a simple and efficient way to change the peak output power of the ScPa. However, in many examples, conventional (e.g., existing) logic-level shifters rapidly degrade in performance as the voltage of the high-voltage rail decreases.

[0112] In some examples, the ScPa output unit is formed from a stack of four core devices, namely two switch devices and two cascode devices. Such a configuration allows for small, low-resistance switch devices while limiting the Vds and Vgs of the devices to safe levels. The Vds and Vgs of the core devices must be kept below the core voltage specified by the process.

[0113] Figure 9 shows an exemplary schematic diagram of an ScPa output switch unit 900 including a stack of the four core devices described above. For example, the ScPa output switch unit 900 includes two switch devices consisting of a PMOS switch 910 and an NMOS switch 940. The ScPa output switch unit 900 further includes two cascode devices comprising a PMOS cascode 920 and an NMOS cascode 930. In some examples, the cascode devices can correspond to a common-source transistor supplying a common-gate transistor, among various other configurations and / or implementations. In the exemplary schematic diagram of the ScPa output switch unit 900 shown in Figure 9, the IO voltage (VDDH) is set to up to twice the core voltage (VDDL). The IO voltage (VDDH) can correspond to a high-voltage rail driving the ScPa output switch unit 900, and the core voltage (VDDL) can correspond to a low-voltage rail of the ScPa output switch unit.

[0114] In some examples, the voltages required for each device gate within the ScPa output switch unit 900 are as follows: the NMOS switch device 940 gate is driven by a clock between 0 and VDDL; the NMOS cascode 930 gate is driven by VDDL; the PMOS cascode 920 gate is driven by the difference between the IO voltage and the core voltage (VDDH - VDDL); and the PMOS switch device 910 gate is driven by a clock between (VDDH - VDDL) and VDDH.

[0115] In an exemplary embodiment, Figure 10 shows a circuit 1000 that achieves the required voltage for each device included in the stack of four core devices of the ScPa output unit. The NMOS switch device 1040 ("Nsw" in Figure 10) may be the same as or similar to the NMOS switch device 940 in Figure 9 and can be driven directly from a core voltage inverter driven from the VDDL rail of circuit 1000. The NMOS cascode gate 1030 ("Ncas" in Figure 10) may be the same as or similar to the NMOS cascode gate 930 in Figure 9 and can be directly connected to the VDDL rail of circuit 1000.

[0116] The signal voltage shift required for the PMOS switch device 1010 (labeled "Psw" in Figure 10, where PMOS switch device 1010 may be the same as or similar to PMOS switch device 910 in Figure 9) can be achieved by using a capacitor 1005(C1) connected between the gate of NMOS switch 1040 and the gate of PMOS switch 1010, where capacitor 1005(C1) is charged to have a voltage of (VDDH - VDDL) across the entire capacitor. No current is required to maintain the voltage difference across this series capacitor, and this level shifter has the advantage that the power requirements are no more than those required to drive a simple core voltage inverter. By including a very small cross-coupled PMOS device 1007(P3) in the circuit 1000, the small amount of charge that leaks from the capacitor over time can be periodically replenished.

[0117] In some embodiments, a PMOS cascode gate (e.g., PMOS cascode 1020 in Figure 10, "Pcas" in Figure 10) is biased to a fixed voltage lower than the VDDH rail using a charge pump driven by a VDDL-level clock input, as shown in the exemplary circuit 1100 in Figure 11. In exemplary circuit 1100, the core supply voltage is DC-shifted through a series capacitor to create a rail one core voltage lower than the VDDH rail. The DC current consumed by the Vpcas rail across the entire ScPa array is small, due only to gate leakage. Embodiments of the charge pump are implemented with very small switches and consume only negligible current in operation.

[0118] The advantages of these circuits include decoupling the speed of I / O device performance from the circuit operating at core device speed. For example, the circuit described above and implemented according to aspects of the present invention does not limit speed by I / O device performance because the circuit operates at core device speed. No power is consumed from the VDDH rail for signal buffering and level shifting. Switch resistance does not increase because Vgs, which is present in all devices, remains unchanged even when VDDH is reduced. Therefore, efficiency does not decrease even if output power is reduced by lowering the rail voltage. In some embodiments, the disclosed circuit allows the PMOS switch gate and PMOS cascode gate to be dropped to a negative voltage lower than the ground rail, so that VDDH can be reduced to very low levels (for example, in at least some cases VDDH can be reduced to below VDDL) while maintaining high-speed operation, good switch resistance, and efficiency.

[0119] Figure 12 shows a computing device architecture 1200 of a computing device that can implement one or more of the technologies described herein. In some examples, the computing device may include a mobile device, a wearable device, an augmented reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a personal computer, a laptop computer, a video server, a vehicle (or a computing device in a vehicle), or other devices. The components of the computing device architecture 1200 are shown communicating electrically with each other using connections 1205 such as a bus. The computing device architecture 1200 includes a processing unit 1210 and computing device connections 1205 that connect various computing device components, including computing device memory 1215 such as read-only memory (ROM) 1220 and random access memory (RAM) 1225, to the processor 1210.

[0120] The computing device architecture 1200 may include a cache of high-speed memory that is directly connected to, adjacent to, or integrated as part of the processor 1210. The computing device architecture 1200 can copy data from memory 1215 and / or storage device 1230 to cache 1212 to enable rapid access by the processor 1210. In this way, the cache can provide a performance improvement that avoids delays while the processor 1210 is waiting for data. These and other engines may be configured to control the processor 1210 or to perform various actions. Other computing device memories 1215 may also be available. Memory 1215 may include multiple different types of memory with different performance characteristics. The processor 1210 may include any general-purpose processor and hardware or software services such as service 1 1232, service 2 1234, and service 3 1236 stored in storage device 1230, which are configured to control the processor 1210, and also dedicated processors in which software instructions are incorporated into the processor design. Processor 1210 may be a self-contained system including multiple cores or processors, a bus, a memory controller, a cache, etc. A multicore processor may be symmetric or asymmetric.

[0121] To enable user interaction with the computing device architecture 1200, the input device 1245 can represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphical input, a keyboard, a mouse, motion input, or voice. The output device 1235 may be one or more of the many output mechanisms known to those skilled in the art, such as a display, projector, television, or speaker device. In some examples, a multimodal computing device may allow the user to provide multiple types of inputs for communication with the computing device architecture 1200. The communication interface 1240 can generally manage and control user input and computing device output. Since there are no restrictions on operating with a specific hardware configuration, the basic functionality described here can be easily replaced with improved hardware or firmware configurations as they are developed.

[0122] The storage device 1230 is non-volatile memory and may be a computer-readable medium capable of storing computer-accessible data, such as a magnetic cassette, flash memory card, solid-state memory device, digital versatile disk, cartridge, RAM, ROM, and hybrids thereof. The storage device 1230 may include services 1232, 1234, and 1236 for controlling the processor 1210. Other hardware or software modules or engines are also contemplated. The storage device 1230 may be connected to the computing device connection 1205. In one embodiment, a hardware module performing a particular function may, in order to perform the function, connect to the necessary hardware components such as the processor 1210, connection 1205, and output device 1235, and may include software or processor-readable code stored on a computer-readable medium.

[0123] The term “device” is not limited to one or a specific number of physical objects (such as one smartphone, one controller, one processing system). As used herein, a device may be any electronic device having one or more components that may implement at least some parts of this disclosure.

[0124] Individual aspects may be described above as processes or methods depicted as flowcharts or data flow diagrams. While flowcharts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when its operations are complete, but it may have additional steps not shown in the diagram. A process may correspond to a method, function, procedure, subroutine, or subprogram. If a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0125] The technologies described herein may be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such technologies may be implemented in any of a variety of devices, such as general-purpose computers, wireless communication device handsets, or integrated circuit devices having multiple applications, including applications in wireless communication device handsets and other devices. Any functionality described as a module or component may be implemented together in an integrated logic device, or separately as individual interoperable logic devices. When implemented in software, the technology may be at least partially realized by a computer-readable data storage medium containing program code that includes instructions that perform one or more of the methods described above at runtime.

[0126] The program code may be executed by a processor that includes one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices.

Claims

1. A switched-capacitor power amplifier (ScPa) device, A switched capacitor ray comprising a plurality of unit cells that can be shared between the in-phase (I) component and the quadrature-phase (Q) component of an input radio frequency (RF) signal, wherein each of the plurality of unit cells comprises a capacitor and an inverter. A pair of control bits corresponding to each of the plurality of unit cells, wherein the pair of control bits includes a first control bit configured to selectively enable or disable the unit cell based on the I component, and a second control bit configured to selectively enable or disable the unit cell based on the Q component, Truth table logic configured for the unit cells of a first subset and the unit cells of a second subset of the plurality of unit cells, wherein the truth table logic is configured to drive the unit cells of the first subset based on the I component in response to the double-enable state of each pair of control bits, and to drive the unit cells of the second subset based on the Q component in response to the double-enable state, A device equipped with the following features.

2. The ScPa device according to claim 1, wherein the ScPa device implements an analog clipping scheme based on a set of unit cells having the double-enabled state of the switched capacitor ray configured with the truth table logic, and the set of unit cells having the double-enabled state includes the plurality of unit cells.

3. The ScPa device according to claim 2, wherein the analog clipping method implemented using the truth table logic drives the first half of the set of unit cells having a double-enabled state with an I clock corresponding to the I component, and drives the second half of the set of unit cells having a double-enabled state with a Q clock corresponding to the Q component.

4. The ScPa apparatus according to claim 3, wherein the set of unit cells having the double-enabled state is equal to the difference between the sum of the magnitudes of the I component and the Q component and the number of the plurality of unit cells included in the switched capacitor ray.

5. The ScPa device according to claim 1, wherein the double-enable state corresponds to each bit of each control bit pair of the unit cell being set to high, enabling the unit cell to be driven based on the I component and enabling the unit cell to be driven based on the Q component.

6. The ScPa apparatus according to claim 1, wherein a first subset of the unit cells comprises a first half of the plurality of unit cells, and a second subset of the unit cells comprises a second half of the plurality of unit cells.

7. The ScPa apparatus according to claim 1, wherein the number of unit cells included in the first subset is equal to the number of unit cells included in the second subset.

8. The ScPa device according to claim 1, wherein one of the first subset and the second subset of the unit cell comprises unit cells with even indices of the switched capacitor ray, and the other of the first subset and the second subset comprises unit cells with odd indices of the switched capacitor ray.

9. The ScPa device according to claim 1, wherein the truth table logic drives the plurality of unit cells according to each pair of control bits when the double-enable state is absent.

10. The truth table logic encodes a priority for the unit cells of the first subset such that the I component takes precedence over the Q component, and the truth table logic maps the encoded priority, which takes precedence over the Q component, to the double-enable state in which the first and second control bits are set to high, respectively, for each unit cell of the first subset. The ScPa device according to claim 1, wherein the truth table logic encodes a priority for the unit cells of the second subset such that the Q component takes precedence over the I component, and the truth table logic maps the priority encoded such that the Q component takes precedence over the I component to the double-enable state in which the first and second control bits are set to high, respectively, for each unit cell of the second subset.

11. The ScPa device according to claim 1, wherein each of the plurality of unit cells of the switched capacitor array is switchably coupled to the primary input of an inductive transformer or balun included in the ScPa device.

12. The truth table logic causes the ScPa device to automatically implement an analog clipping scheme for IQ amplitude codes whose total size is greater than the number of unit cells included in the plurality of unit cells. The ScPa device according to claim 1, wherein the analog clipping method is implemented locally by each unit cell having the double-enabled state, in accordance with the truth table logic configured for each unit cell having the double-enabled state.

13. Furthermore, the ScPa device according to claim 1, wherein the output switch unit is provided with a voltage level shifter, and the output switch unit comprises an NMOS switch device gate, an NMOS cascode gate, a PMOS cascode gate, and a PMOS switch device gate.

14. The ScPa apparatus according to claim 13, wherein the NMOS switch device gate is driven from a core voltage inverter driven from a core voltage (VDDL) rail, the NMOS cascode gate is coupled to the VDDL rail, the PMOS cascode gate is biased to a fixed voltage lower than the IO voltage (VDDH) rail, and the PMOS switch device gate is charged to a voltage of (VDDH - VDDL) by a signal voltage shift using a capacitor between the NMOS switch device gate and the PMOS switch device gate.

15. The ScPa device according to claim 14, wherein the IO voltage (VDDH) is set to a maximum of twice the core voltage (VDDL).

16. The ScPa apparatus according to claim 14, further comprising a cross-coupled PMOS device for periodically replenishing the small amount of charge that leaks from the capacitor over time.

17. The ScPa apparatus according to claim 14, wherein the PMOS cascode gate is coupled to a charge pump driven by a VDDL-level clock input, and the core supply voltage of the charge pump is DC-shifted via a series capacitor to generate a rail with a voltage one core lower than the VDDH rail.

18. A method for controlling a switched-capacitor power amplifier (ScPa) having adaptive clipping, The steps include obtaining common-mode (I) and quadrature-phase (Q) codes corresponding to the input radio frequency (RF) signal, The steps include comparing the sum of the absolute values ​​of the I and Q codes with a threshold corresponding to the number of unit cells included in the multiple unit cells of the switched capacitor ray of the ScPa, A step of determining, according to the I and Q codes, that each output cell of the inverter and capacitor array of the ScPa is an I-clock enabled output cell, a Q-clock enabled output cell, a double-enabled output cell, or an off output cell, wherein the number of double-enabled output cells is equal to zero if the sum of the absolute values ​​of the I and Q codes is less than or equal to the threshold, and the number of double-enabled output cells is equal to the sum of the absolute values ​​of the I and Q codes minus the threshold, The steps include controlling half of the double-enable output cell to be driven by the I clock and the other half of the double-enable output cell to be driven by the Q clock, The steps include controlling the I-clock enabled output cell of the inverter and capacitor array to be driven by the I-clock, The steps include controlling the Q-clock enabled output cells of the inverter and capacitor array to be driven by the Q-clock, A method that includes [a certain feature].

19. Controlling the ScPa includes implementing an analog clipping scheme based on configuring the set of unit cells having the double-enabled state of the switched capacitor ray with truth table logic, The method according to claim 18, wherein the set of unit cells having the double-enabled state is included in the plurality of unit cells.

20. The method according to claim 19, wherein the truth table logic drives the first half of the set of unit cells having the double-enabled state with an I clock corresponding to the I code, and drives the second half of the set of unit cells having the double-enabled state with a Q clock corresponding to the Q code.

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