Delta-sigma modulators and delta-sigma converters

Abstract

Delta-sigma modulators and converters with low power consumption and high resolution. [Solution] A delta-sigma modulator is provided, comprising: a first switched capacitor circuit provided between an input terminal and an analog amplifier and including a first capacitor; a feedback capacitor provided as a feedback circuit for the analog amplifier; and a second switched capacitor circuit provided in parallel with the feedback capacitor and including a second capacitor; a first operating mode for controlling the second switched capacitor circuit so that the second capacitor is connected in parallel with the feedback capacitor while the first switched capacitor circuit is in switching operation; and a second operating mode for synchronously controlling the first switched capacitor circuit and the second switched capacitor circuit.

Description

[Technical Field]

[0001] The present invention relates to a delta-sigma modulator and a delta-sigma converter. [Background technology]

[0002] Conventionally, switched-capacitor integrators have been known (see, for example, Patent Document 1). Also, delta-sigma modulators that amplify the input signal component using such a switched-capacitor integrator have been known. Furthermore, incremental delta-sigma AD converters that reset the charge accumulated in the integrating circuit at predetermined time intervals have been known (see, for example, Patent Document 2). In addition, delta-sigma modulators that control the analog amplifier section so that it operates as an integrator with a first-order feedback coefficient of 1 until a predetermined period has elapsed after the analog amplifier section has been reset, and then operates as an amplifier with a first-order feedback coefficient greater than 1 after the predetermined period has elapsed (see, for example, Patent Document 3). Patent Document 1: Japanese Unexamined Patent Publication No. 2013-101494 Patent Document 2: Japanese Unexamined Patent Publication No. 2016-131366 Patent Document 3: Japanese Unexamined Patent Publication No. 2019-118100 [Overview of the project] [Problems that the invention aims to solve]

[0003] Delta-sigma modulators and delta-sigma converters using delta-sigma modulators are required to have lower power consumption and higher resolution. [Means for solving the problem]

[0004] In a first aspect of the present invention, the present invention comprises an analog amplifier having at least a first-order feedback coefficient for amplifying an analog signal; a quantizer for quantizing the output signal of the analog amplifier; a DA converter that outputs a feedback signal for which the output of the quantizer is converted by DA conversion and fed back to the analog amplifier; an adder / subtractor that inputs an analog signal obtained by subtracting the feedback signal from the input analog signal to the analog amplifier; a reset circuit that resets the analog amplifier at predetermined intervals; and a control circuit for controlling the analog amplifier, wherein the analog amplifier comprises an analog amplifier provided between the input terminal and the output terminal of the analog amplifier, and a first-order feedback coefficient provided between the input terminal and the analog amplifier. A delta-sigma modulator is provided, comprising: a first switched-capacitor circuit including a capacitor; a feedback capacitor provided between the input and output terminals of the analog amplifier as a feedback circuit for the analog amplifier; and a second switched-capacitor circuit provided in parallel with the feedback capacitor and including a second capacitor, wherein the control circuit has a first operating mode that controls the second switched-capacitor circuit so as to maintain the state in which the second capacitor is connected in parallel with the feedback capacitor between the input and output terminals of the analog amplifier while the first switched-capacitor circuit is in switching operation; and a second operating mode that synchronously controls the first switched-capacitor circuit and the second switched-capacitor circuit.

[0005] In a second embodiment of the present invention, a delta-sigma converter is provided, comprising a delta-sigma modulator according to the first embodiment and a digital filter unit for filtering the modulated digital signal output by the delta-sigma modulator.

[0006] It should be noted that the above summary of the invention does not list all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0007] [Figure 1]An example of a discrete system configuration of integrator 10, as shown in the reference example, is presented. [Figure 2] This is an example showing the input / output characteristics of the integrator 10 in the Z-plane. [Figure 3] The following shows an example of the actual circuit configuration of the integrator 10 in the reference example. [Figure 4] Figure 3 shows an example of the operating characteristics of the integrator 10. [Figure 5] Figure 3 shows an example configuration of a delta-sigma converter 40 using the integrator 10 shown. [Figure 6] An example of a discrete system configuration of the analog amplification section 100 related to the reference example is shown. [Figure 7] Figure 6 shows an example of a configuration equivalent to the analog amplification unit 100. [Figure 8] This is an example showing the input / output characteristics of the analog amplifier section 100 in the Z-plane. [Figure 9] The following shows an example of the actual circuit configuration of the analog amplifier section 100 related to the reference example. [Figure 10] An example of the operating characteristics of the analog amplifier section 100 in the reference example is shown. [Figure 11] An example configuration of the delta-sigma modulator 200 is shown as a reference example. [Figure 12] An example configuration of the delta-sigma converter 300 is shown as a reference example. [Figure 13] A first modified example of the delta-sigma modulator 200 is shown. [Figure 14] A second modified example of the delta-sigma modulator 200 is shown. [Figure 15] A third modified example of the delta-sigma modulator 200 is shown. [Figure 16] The following shows an example of the actual circuit configuration of the analog amplifier section 100 as a reference example. [Figure 17] An example of the actual circuit configuration of the analog amplifier section 800 according to one embodiment is shown. [Figure 18] This is a timing chart showing an example of each control signal Φ. [Figure 19] An example configuration of a delta-sigma modulator 900 according to one embodiment is shown.

Best Mode for Carrying Out the Invention

[0008] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

[0009] FIG. 1 shows a configuration example of a discrete system of an integrator 10 according to a reference example. The integrator 10 integrates an input analog signal A OUT , , , ,

[0012] ,

[0010] , , , ,

[0011] , OUT , , IN , , , , , , , , , and outputs an integrated signal A OUT The integrator 10 includes an input terminal 2, an output terminal 4, a delay element 12, and an adder 14. The delay element 12 is provided between the input terminal 2 and the output terminal 4, and delays and outputs the input signal. The adder 14 adds the output signal A IN of the delay element 12 to the analog signal A OUT input to the input terminal 2, and the resulting signal A s IN +A OUT is input to the delay element 12.

[0010] Thus, since the integrator 10 outputs a signal obtained by delaying the signal A IN +A OUT input to the delay element 12, the output signal A OUT is expressed as follows.

Equation

[0011] From Equation (1), the input-output characteristics are expressed as follows.

Equation

[0012] Figure 2 shows an example of the input / output characteristics of an integrator 10 in the Z-plane. In Figure 2, the horizontal axis represents the real number axis, and the vertical axis represents the imaginary number axis. As shown in Figure 2, it can be seen that the pole appears at 1 on the unit circle. Such an integrator 10 can be constructed as a real circuit using a switched capacitor, etc., as follows.

[0013] Figure 3 shows an example of the actual circuit configuration of an integrator 10 according to a reference example. The integrator 10 comprises an input terminal 2, an output terminal 4, an amplifier 22, a feedback capacitor 24, and a switched capacitor circuit 26. The amplifier 22 and the switched capacitor circuit 26 are connected in series between the input terminal 2 and the output terminal 4. One input terminal of the amplifier 22 is connected to the output terminal of the switched capacitor circuit 26, and the other input terminal is connected to a reference potential. The reference potential can be a predetermined potential, for example, 0V (ground potential). The output terminal of the amplifier 22 is connected to the output terminal 4 of the integrator 10.

[0014] The feedback capacitor 24 is connected between one input terminal and one output terminal of the amplifier 22. The feedback capacitor 24 stores the signal input to one input terminal of the amplifier 22. The switched capacitor circuit 26 is provided between the input terminal 2 and one terminal of the amplifier 22, and repeatedly charges the analog signal input to the integrator 10 and discharges it to the amplifier 22.

[0015] The switched-capacitor circuit 26 has a first capacitor C1. In a period φ1, for example, the switched-capacitor circuit 26 connects one terminal of the first capacitor C1 to the input terminal 2 of the integrator 10 and the other terminal to a reference potential to charge the analog signal from the input terminal 2. In this case, in a period φ2, the switched-capacitor circuit 26 connects one terminal of the first capacitor C1 to the reference potential and the other terminal to one input terminal of the amplifier 22 to discharge the accumulated charge. The switched-capacitor circuit 26 repeats the charging and discharging of the first capacitor C1 by repeating periods φ1 and φ2.

[0016] Figure 4 shows an example of the operating characteristics of the integrator 10 shown in Figure 3. In Figure 4, the horizontal axis represents time and the vertical axis represents voltage. Figure 4 shows the output signal A from the output terminal 4 of the integrator 10. OUT The following shows an example of timing signals for periods φ1 and φ2. In this case, the timing signals for periods φ1 and φ2 can be signals synchronized with a substantially constant clock period. That is, periods φ1 and φ2 switch on and off at a predetermined period. Figure 4 also shows that the analog signal input to the integrator 10 is 0V until time 0, and then a substantially constant potential A from time 0 onwards. IN Here is an example.

[0017] Output signal A of such an integrator 10 OUT The following equation applies in response to n clock signals (i.e., n charge / discharge cycles): That is, the integrator 10 changes according to the input analog signal A. IN It operates to amplify by n times, where n corresponds to the number of input clocks. Delta-sigma modulators are known to use such an integrator 10.

number

[0018] Figure 5 shows an example configuration of a delta-sigma converter 40 using the integrator 10 shown in Figure 3. The delta-sigma converter 40 comprises an input terminal 6, an output terminal 8, a delta-sigma modulator 30, and a digital filter section 42. The delta-sigma modulator 30 and the digital filter section 42 are connected in series between the input terminal 6 and the output terminal 8.

[0019] Figure 5 shows an example where the delta-sigma modulator 30 operates as a first-order modulator with one integrator 10. The delta-sigma modulator 30 has an integrator 10, a quantizer 32, a DA converter 34, and an adder / subtractor 36. The quantizer 32 processes the output signal A of the integrator 10. OUT Quantized digital signal D OUT The DA converter 34 outputs the output D of the quantizer 32. OUT Feedback signal A is obtained by performing a D / A conversion and feeding it back to the integrator 10. FBThe adder / subtractor 36 outputs the analog signal A that is input to the delta-sigma modulator 30. SIG Feedback signal A FB Analog signal A obtained by subtracting IN This is input to integrator 10.

[0020] The integrator 10 of the delta-sigma modulator 30, which operates as a primary modulator, receives the input analog signal A SIG and feedback signal A FB In contrast, as explained in Figure 4, after n clock signals are input, the value is multiplied by n and then output. That is, the analog signal A input to the integrator 10 IN The analog signal A input to the delta-sigma modulator 30 is as shown in the following equation. SIG and feedback signal A FB It is shown as the difference. Also, the output signal A of integrator 10 OUT From equation (2), it can be shown as follows.

number

[0021] When the DA converter 34 operates ideally, the output D of the quantizer 32 is OUT and feedback signal A FB Since these can be taken as approximately the same value, equation (4) can be expressed as follows.

number

[0022] Here, the output signal A of the integrator 10. OUT The initial value is 0, and the analog signal A is input to the delta-sigma modulator 30. SIG If we assume that is a nearly constant value, the output of the i-th quantizer 32 is D OUT (i) Then, output signal A OUT The expression is given by the following equation, where n represents the number of input clocks.

number

[0023] By transforming equation (6), we obtain the following equation.

number

[0024] From equation (7), the analog signal A input to the delta-sigma modulator 30 is SIG This is the output D of quantizer 32. OUT It can be seen that it can be expressed using the digital output D of the delta-sigma modulator 30. OUT By performing the operation as shown in the first term on the right-hand side of equation (Equation 7) using this, the analog signal A SIG The digital signal D obtained by digital conversion SIG It is possible to calculate this.

[0025] The digital filter unit 42 performs such calculations, that is, digital calculations equivalent to the operation of the integrator 10 shown in the following equation.

number

[0026] Thus, the digital filter section 42 filters the analog signal A SIG The digital signal D obtained by digital conversion SIG Since it can output D, it can be seen that the delta-sigma converter 40 shown in Figure 5 is capable of AD conversion. Note that the output D of the delta-sigma converter 40 SIG This is approximately equal to equation (8). Therefore, by comparing equations (7) and (8), we can determine the quantization error E of the AD conversion. MOD1 This is expressed by the following equation.

number

[0027] Here, if the feedback loop of the delta-sigma modulator 30 is stabilized, the output signal A of the integrator 10 OUTThis can be kept within a value of approximately a constant voltage V. When stabilized in this way, the quantization error E of the delta-sigma modulator 30 MOD1 This is expressed by the following equation.

number

[0028] From equation (10), it can be seen that the delta-sigma converter 40 uses a first-order delta-sigma modulator 30, and by performing n integral operations from an initial value of 0 to the output of the integrator 10, the quantization error can be reduced to 1 / n. That is, the delta-sigma converter 40 can improve the resolution of the AD conversion by n times. In order to set the output of the integrator 10 to an initial value of 0, the delta-sigma converter 40 may reset the integrator 10 and the digital filter section 42 at a predetermined period. A delta-sigma converter 40 with such a reset operation is known as an incremental delta-sigma converter.

[0029] Such a delta-sigma converter 40 can further improve its resolution by increasing the number of integrators 10 in the delta-sigma modulator 30. That is, in Figure 5, multiple integrators 10 may be connected in series between the adder / subtractor 36 and the quantizer 32. For example, an example of a delta-sigma modulator 30 in which three integrators 10 are provided between the adder / subtractor 36 and the quantizer 32 will be described.

[0030] Of the three integrators 10, the output signal A of the final stage integrator 10. OUT3 This is shown by the following equation.

number

[0031] Here, the initial value of the output signals of the three integrators 10 is 0, and the analog signal A input to the delta-sigma modulator 30 is... SIG If we assume that is a nearly constant value, the output of the i-th quantizer 32 is D OUT (i) Then, output signal A OUT3 This is expressed by the following equation.

number

[0032] By rearranging equation (12), we obtain the following equation.

number

[0033] From equation (13), the analog signal A input to the delta-sigma modulator 30 is SIG This is the output D of quantizer 32. OUT It can be expressed using analog signal A SIG The digital signal D obtained by digital conversion SIG The quantization error E of the AD conversion when using such a third-order modulator can be calculated. MOD3 This is shown by the following equation, which is almost identical to the second term of equation (13).

number

[0034] In this case as well, by stabilizing the feedback loop of the delta-sigma modulator 30, the output signal A of the final stage integrator 10 is stabilized. OUT3 This can be kept within a value of approximately a constant voltage V. That is, the quantization error E of the third-order delta-sigma modulator 30. MOD3 This is expressed by the following equation.

number

[0035] From equation (15), the delta-sigma converter 40 uses a third-order delta-sigma modulator 30, and by performing n integral operations from an initial value of 0 on the output of the integrator 10, the quantization error can be reduced to 3! / {n·(n-1)·(n-2)} times. That is, the delta-sigma converter 40 can improve the resolution of the AD conversion by {n·(n-1)·(n-2)} / 3!} times. In this way, when an L-order delta-sigma modulator is used in an incremental delta-sigma converter, the resolution RL It is known that this can be expressed as shown in the following equation. Note that the DA converter 34 is assumed to be a 1-bit DA converter.

number

[0036] In the case of a delta-sigma converter using a first-order modulator, the resolution of the AD conversion can be improved by a factor of n by performing n integral operations, as shown in equation (10). For example, n=2 16 By performing a certain number of integration operations, a 16-bit resolution can be obtained. However, to obtain such a high resolution, if the clock frequency is f [Hz], the conversion speed is f / 2 16 The frequency becomes around [Hz], making it unsuitable for use as a high-speed AD converter.

[0037] Therefore, by using a delta-sigma converter with an L-order modulator (L>1), it is possible to realize an AD converter with a higher resolution and faster conversion speed. However, when using a higher-order L-order modulator, L integrators 10 are required, which increases power consumption and cost. Therefore, the delta-sigma modulator and delta-sigma converter in the reference example realize an AD converter with a higher resolution and faster conversion speed while preventing an increase in power consumption and cost.

[0038] Figure 6 shows an example of a discrete system configuration of the analog amplifier 100 according to the reference example. The delta-sigma modulator and delta-sigma converter according to the reference example use such an analog amplifier 100 instead of the integrator 10 to realize a high-speed and high-resolution AD converter. The analog amplifier 100 may be configured by providing an amplifier in the feedback loop of the integrator 10 shown in Figure 1. That is, the analog amplifier 100 includes an input terminal 102, an output terminal 104, a delay element 112, an amplifier 114, and an adder 116.

[0039] The delay element 112 is located between the input terminal 102 and the output terminal 104, and delays the input signal before outputting it. The amplifier 114 amplifies the output of the delay element 112 and supplies it to the adder 116. The amplifier 114 amplifies the output A of the delay element 112 at a multiplier x greater than 1. OUT The adder 116 amplifies the analog signal A input to input terminal 102. IN x·A is the output signal of amplifier 114. OUT Signal A with added signal A IN +x·A OUT This is input to the delay element 112.

[0040] Thus, the analog amplifier 100 receives the signal A input to the delay element 112. IN +x·A OUT Since it outputs a delayed signal, output signal A OUT This is expressed by the following equation.

number

[0041] From equation (17), the input / output characteristics are shown as follows:

number

[0042] Figure 7 shows an example of a configuration equivalent to the analog amplifier 100 shown in Figure 6. Figure 8 shows an example of the input / output characteristics of such an analog amplifier 100 in the Z-plane. In Figure 8, the horizontal axis represents the real number axis, and the vertical axis represents the imaginary number axis. As shown in Figure 8, it can be seen that the poles appear outside the unit circle. Although Figure 8 is explained using the Z-plane as a discrete system, it may also be represented using the S-plane as a continuous system. In this case, the poles of the analog amplifier 100 would be located in the right half-plane of the S-plane. Such an analog amplifier 100 can be constructed as a real circuit using switched capacitors, etc., as follows.

[0043] Figure 9 shows an example of the actual circuit configuration of the analog amplifier section 100 according to the reference example. The analog amplifier section 100 includes an input terminal 102, an output terminal 104, an analog amplifier 110, a feedback capacitor 120, a first switched capacitor circuit 130, and a second switched capacitor circuit 140.

[0044] The analog amplifier 110 is located between the input terminal 102 and the output terminal 104. The analog amplifier 110 may be an operational amplifier or the like. One input terminal of the analog amplifier 110 receives the signal from input terminal 102 via the first switched-capacitor circuit 130. The other input terminal of the analog amplifier 110 is connected to a reference potential. The reference potential may be a predetermined potential, for example, 0V (ground potential). The output terminal of the analog amplifier 110 is connected to output terminal 104.

[0045] The feedback capacitor 120 is located between one input terminal and one output terminal of the analog amplifier 110, forming part of the feedback circuit. Here, the capacitance of the feedback capacitor 120 is denoted as C0.

[0046] The first switched-capacitor circuit 130 is located between the input terminal 102 and the analog amplifier 110. The output of the first switched-capacitor circuit 130 is connected to one of the input terminals of the analog amplifier 110. That is, the first switched-capacitor circuit 130 and the analog amplifier 110 are connected in series between the input terminal 102 and the output terminal 104. The first switched-capacitor circuit 130 includes a first capacitor C1 that charges and discharges the input signal.

[0047] The first switched capacitor circuit 130, for example, in period φ1, connects one terminal of the first capacitor C1 to the input terminal 102 of the analog amplifier 100 and the other terminal to a reference potential, thereby charging the analog signal from the input terminal 102. In this case, in period φ2, the first switched capacitor circuit 130 connects one terminal of the first capacitor C1 to a reference potential and the other terminal to one input terminal of the analog amplifier 110, thereby discharging the accumulated charge. The first switched capacitor circuit 130 repeats the charging and discharging of the first capacitor C1 by repeating periods φ1 and φ2.

[0048] The second switched-capacitor circuit 140 is provided between one input terminal and one output terminal of the analog amplifier 110. That is, the second switched-capacitor circuit 140 and the feedback capacitor 120 are provided in parallel as a feedback circuit of the analog amplifier 110. The second switched-capacitor circuit 140 includes a second capacitor C2 that charges and discharges the input signal.

[0049] The second switched capacitor circuit 140 charges the input signal by connecting one terminal of the second capacitor C2 to the output terminal 104 of the analog amplifier 100 and the other terminal to a reference potential during period φ1. In this case, during period φ2, the second switched capacitor circuit 140 discharges the charged capacitor by connecting one terminal of the second capacitor C2 to a reference potential and the other terminal to one input terminal of the analog amplifier 110. The second switched capacitor circuit 140 repeats the charging and discharging of the second capacitor C2 by repeating periods φ1 and φ2.

[0050] The amplification factor x of such an analog amplifier 100 is determined based on the ratio of the second capacitor C2 and the feedback capacitor 120, as shown in the following equation.

number

[0051] In other words, in the case of the integrator 10 in Figure 3, the integration operation was performed by holding charge in the feedback capacitor 24. In contrast, the analog amplifier 100 in Figure 9 adds a charge corresponding to the capacitance ratio C2 / C0 to the charge in the feedback capacitor 120 and supplies it to one input of the analog amplifier 110, thereby achieving a calculation of an amplification factor greater than 1.

[0052] Figure 10 shows an example of the operating characteristics of the analog amplifier 100 in the reference example. In Figure 10, the horizontal axis represents time and the vertical axis represents voltage. Figure 10 shows the output signal A from the output terminal 104 of the analog amplifier 100. OUT The following shows examples of timing signals for periods φ1 and φ2. In this case, the timing signals for periods φ1 and φ2 can be signals synchronized with a substantially constant clock period. That is, periods φ1 and φ2 switch on and off at a predetermined period. Figure 10 also shows that the analog signal input to the analog amplifier 100 is 0V until time 0, and then a substantially constant potential A from time 0 onwards. IN An example of this is shown. Figure 10 also shows an example of the operating characteristics when C2=C0, that is, when the amplification factor x of the analog amplifier 100 is 2.

[0053] Output signal A of such analog amplifier 100 OUT The value changes according to n clock signals (i.e., n charge / discharge cycles) as follows (x>1):

number

[0054] Furthermore, the analog signal input to the analog amplifier 100 from time 0 is at a nearly constant potential A. IN Therefore, equation (20) can be expressed as follows: That is, the output signal A of the analog amplifier 100 OUT It can be seen that increases exponentially with increasing n. A delta-sigma modulator using such an analog amplifier 100 will be described next.

number

[0055] Figure 11 shows an example configuration of a delta-sigma modulator 200 for reference. The delta-sigma modulator 200 uses the analog amplifier 100 shown in Figure 9. Specifically, the delta-sigma modulator 200 comprises an input terminal 106, an output terminal 108, an analog amplifier 100, a quantizer 210, a DA converter 220, and an adder / subtractor 230.

[0056] The analog amplifier 100 amplifies the input analog signal as described in Figures 9 and 10. The quantizer 210 amplifies the output signal A of the analog amplifier 100. OUT Quantized digital signal D OUT The output is as follows: The analog amplifier 100 has at least a first-order feedback coefficient, and the feedback coefficient is greater than 1. For example, if the feedback circuit is ideal and the losses are almost negligible, the amplification factor of the analog amplifier 100 may be greater than 1, and this amplification factor may be approximately equal to the feedback coefficient.

[0057] The quantizer 210 adjusts the output signal A of the analog amplifier 100 according to the clock signal supplied from an external source. OUT The signal may be quantized. The quantizer 210 may function as a 1-bit quantizer and quantize it into a binary digital signal. Alternatively, the quantizer 210 may function as a multi-bit quantizer and quantize it into a multi-level digital signal.

[0058] The DA converter 220 receives the output D of the quantizer 210. OUT Feedback signal A is obtained by DA conversion and fed back to the analog amplifier section 100. FB The DA converter 220 outputs a digital signal D in synchronization with the clock signal, etc. OUT to analog signal A FB It may be converted to this. The adder / subtractor 230 inputs the analog signal obtained by subtracting the feedback signal from the analog signal to the analog amplifier 100.

[0059] Analog signal A input to the analog amplification unit 100 described above. INis the analog signal A input to the delta-sigma modulator 200 as shown by the following equation SIG and the feedback signal A FB is represented by the difference therebetween. Also, the output signal A OUT of the analog amplifier section 100 is represented as follows by (Equation 18). [Equation]

[0060] When the DA converter 220 operates ideally, since the output D OUT of the quantizer 210 and the feedback signal A FB can be made to have substantially the same value, (Equation 22) is represented as follows. [Equation]

[0061] Here, when the initial value of the output signal A OUT of the analog amplifier section 100 is 0 and the analog signal A SIG input to the delta-sigma modulator 200 is a substantially constant value, if the output of the quantizer 210 at the i-th time is D OUT (i), the output signal A OUT is represented as follows. Here, let x > 1. [Equation]

[0062] By transforming (Equation 24), the following equation is obtained. [Equation]

[0063] As described above, it can be seen that the analog signal A SIG input to the delta-sigma modulator 200 can be expressed using the output D OUT of the quantizer 210. Therefore, the digital output D OUTBy performing the operation as shown in the first term on the right-hand side of equation (25) using this, the analog signal A SIG The digital signal D obtained by digital conversion SIG It is possible to calculate this.

[0064] Figure 12 shows an example configuration of a delta-sigma converter 300 for reference. The delta-sigma converter 300 comprises a delta-sigma modulator 200, as described in Figure 11, and a digital filter section 310. The delta-sigma modulator 200 was described in Figure 11, so its description is omitted here.

[0065] The digital filter section 310 filters the modulated digital signal output by the delta-sigma modulator 200. The digital filter section 310 performs digital calculations equivalent to the amplification operation of the analog amplifier section 100. That is, the digital filter section 310 performs digital calculations that are approximately equivalent to the operation of the delta-sigma modulator 200, as shown in the following equation.

number

[0066] Thus, the digital filter section 310 processes the analog signal A SIG The digital signal D obtained by digital conversion SIG Since it can output this, it can be seen that the delta-sigma converter 300 shown in Figure 12 is capable of AD conversion. The quantization error E1 of the AD conversion of the delta-sigma converter 300 is given by the following equation.

number

[0067] Here, if the feedback loop of the delta-sigma modulator 200 is stabilized, the output signal A of the analog amplifier 100 OUT This can be kept within a value of approximately a constant voltage V. When stabilized in this way, the quantization error E1 of the delta-sigma modulator 200 is given by the following equation.

number

[0068] As described above, the delta-sigma modulator 200 according to the reference example can reduce the quantization error more than the delta-sigma modulator 30 using the integrator 10 by using the analog amplifier section 100. For example, when n = 10, from Equation (10), the delta-sigma modulator 30 using the integrator 10 has a quantization error E MOD1 less than V / 10. Also, from Equation (15), the quantization error E MOD3 of the third-order delta-sigma modulator 30 is less than V / 120. On the other hand, for the delta-sigma modulator 200 using the analog amplifier section 100, from Equation (28), when x = 2, the quantization error E1 is less than V / 1023.

[0069] That is, the delta-sigma modulator 200 according to the reference example can obtain a resolution 102.3 times that of the first-order delta-sigma modulator 30 and 8.525 times that of the third-order delta-sigma modulator 30. Also, since the analog amplifier section 100 does not connect a plurality of delay elements 112 in series, without reducing the conversion speed like the nth-order delta-sigma modulator 30, and while preventing an increase in power consumption due to multi-staging of the analog amplifier 110, a high resolution can be realized.

[0070] As a configuration example of the delta-sigma modulator 200 according to the above reference example, the example in FIG. 11 has been described, but it is not limited thereto. Various circuits may be added to the delta-sigma modulator 200. For example, an amplifier may be added to each part of the delta-sigma modulator 200. An example of such a delta-sigma modulator 200 will be described next.

[0071] FIG. 13 shows a first modification example of the delta-sigma modulator 200 according to the reference example. The delta-sigma modulator 200 of the first modification example further includes a first amplifier 410 and a second amplifier 420.

[0072] The first amplifier 410 is provided between the analog amplifier section 100 and the quantizer 210. The first amplifier 410 has an amplification factor a1ff The input signal may be amplified. The second amplifier 420 is provided between the DA converter 220 and the adder / subtractor 230. The second amplifier 420 has an amplification factor a 1fb The input signal may be amplified. The delta-sigma modulator 200 may improve the stability of the feedback loop by adjusting the amplification factor of such an amplifier.

[0073] For example, the output A of the analog amplification section 100 OUT From there, the signal passes through the first amplifier 410, quantizer 210, DA converter 220, second amplifier 420, adder / subtractor 230, and adder 116 to A SUM The transfer function TF1 of the feedback path leading to -a 1ff ·a 1fb This is the result. Also, inside the analog amplification section 100, A OUT From A SUM The transfer function TF2 of the feedback path corresponds to the amplification factor x. Therefore, A OUT From A SUM If we consider all the feedback paths leading up to the end point and denote the transfer function as TF, it can be expressed as follows:

number

[0074] Here, the output A of the analog amplifier section 100 OUT is, A SUM Since this is a delayed version, the following equation holds true.

number

[0075] That is, if equation (29) holds, the output A of the analog amplifier 100 OUT This is the A of the next clock. SUM It does not affect output A at one clock timing. OUT This is output A in the next clock cycle. OUT It does not affect the amplification factor a of the first amplifier 410. 1ffand the amplification factor a of the second amplifier 420 1fb When the product of these values ​​is approximately equal to the amplification factor x of the analog amplifier 100, which is the feedback coefficient, the output A of the analog amplifier 100 is OUT The likelihood of divergence and instability is reduced, allowing the analog amplifier 100 to operate stably.

[0076] The amplification factor x of the analog amplifier 100 may be variable. For example, the amplification factor of the analog amplifier 100 may change at predetermined timings. Here, the amplification factor of the analog amplifier 100 at the i-th clock timing is x. i Therefore, the input analog signal A of the delta-sigma modulator 200 SIG This corresponds to equation (25) and can be shown as follows:

number

[0077] In a delta-sigma converter 300 using such a delta-sigma modulator 200, the digital filter section 310 operates as shown in the first term on the right-hand side of equation (31), thereby achieving an amplification factor x i AD conversion can be performed in response to changes in x. Furthermore, when the amplification factor of the analog amplifier 100 is variable, the amplification factor x i Depending on the change in x, the amplification factors of the first amplifier 410 and the second amplifier 420 may also be variable. That is, the amplification factors of the first amplifier 410 and the second amplifier 420 are: amplification factor x i The analog amplifier 100 can be operated stably by changing in accordance with the change in (Equation 29) so that it satisfies.

[0078] The delta-sigma modulator 200 may further include a third amplifier 430, a fourth amplifier 440, and an adder 442. The third amplifier 430 receives the analog signal A input to the delta-sigma modulator 200. SIG The signal is amplified and supplied to the adder / subtractor 230. The third amplifier 430 may amplify the input signal at an amplification factor a1. The fourth amplifier 440 amplifies the analog signal A that is input to the delta-sigma modulator 200.SIG The signal is amplified and supplied to the adder 442. The fourth amplifier 440 has an amplification factor a off The input signal may be amplified. The adder 442 adds the signal amplified by the fourth amplifier 440 to the output of the first amplifier 410 and supplies it to the quantizer 210. The amplification factors of the third amplifier 430 and the fourth amplifier 440 may be variable.

[0079] Figure 14 shows a second modified example of the delta-sigma modulator 200 according to the reference example. The delta-sigma modulator 200 of the second modified example further includes an AD conversion unit 450. The quantization error E1 of the delta-sigma modulator 200 is given by the output A of the analog amplifier unit 100, as shown in equation (Equation 27). OUT The value is proportional to this. That is, the output A of the analog amplifier section 100 OUT By performing AD conversion, a digital value corresponding to the quantization error E1 can be calculated, and the resolution can be further improved. Therefore, in the second modified delta-sigma modulator 200, the output A of the analog amplifier 100 OUT Convert to a digital value.

[0080] The AD conversion unit 450 receives the output signal A from the analog amplification unit 100. OUT The signal is converted into a digital signal. The AD conversion unit 450 may output the converted digital signal from the output terminal 452. The AD conversion unit 450 may include successive approximation, flash, pipeline, and delta-sigma type AD converters. The AD conversion unit 450 may include an AD converter added to the delta-sigma modulator 200, or alternatively, an AD converter using a quantizer 210 may be used. The number of bits of the AD conversion unit 450 is m, and the full scale is A. FS , quantization error E ADC Therefore, the digital signal D output by the AD conversion unit 450 OUT2 This is expressed by the following equation.

number

[0081] (Equation 32) Digital signal D OUT2By substituting the equation relating to (Equation 25) into equation (Equation 25), we obtain the following equation.

number

[0082] Also, the quantization error E in equation (32) ADC By substituting the equation relating to (Equation 33) into equation (Equation 33), we obtain the following equation.

number

[0083] As described above, the delta-sigma modulator 200 of the second modified example uses the digital signal D output by the quantizer 210. OUT And the output A of the analog amplification section 100 OUT The digital signal obtained by A / D conversion D OUT2 It outputs the following. Therefore, the delta-sigma converter 300 having the delta-sigma modulator 200 of the second modified example outputs the digital signal D OUT and digital signal D OUT2 By performing digital operations using this method, the resolution can be further improved by m bits. In this case, the digital filter unit 310 may perform digital processing corresponding to the first and second terms on the right-hand side of equation (33).

[0084] Figure 15 shows a third modified example of the delta-sigma modulator 200 according to the reference example. In the third modified delta-sigma modulator 200, the analog amplifier 100 has a configuration that switches between amplification operation and integrator 10 operation. The third modified delta-sigma modulator 200 further includes a reset circuit 460 and a control circuit 470, and the analog amplifier 100 further includes a switch circuit 480.

[0085] The reset circuit 460 resets the output A of the analog amplifier 100 at predetermined intervals. OUTThe feedback capacitor 120 is reset. In this case, the analog amplification unit 100 is configured to reset the feedback capacitor 120 by connecting, for example, one input terminal of the analog amplifier 110 to the output terminal 104. The reset circuit 460 may supply a reset signal to the analog amplification unit 100 to reset the feedback capacitor 120. The reset circuit 460 may also supply a reset signal to the digital filter unit 310 if the delta-sigma modulator 200 is provided in the delta-sigma converter 300.

[0086] The control circuit 470 supplies a control signal to the switch circuit 480 to switch the operation of the analog amplifier 100. The control circuit 470 may switch the operation of the analog amplifier 100 at a predetermined timing. The control circuit 470 may also notify the reset circuit 460 of the timing when a reset signal should be supplied.

[0087] The switch circuit 480 switches whether or not to insert the amplifier 114 into the feedback path according to the control signal received from the control circuit 470. If the amplifier 114 is not in the feedback path, the analog amplifier 100 will have the same configuration as the integrator 10 shown in Figure 1 and will perform an integrating operation. If the amplifier 114 is inserted into the feedback path, the analog amplifier 100 will have the same configuration as the analog amplifier 100 shown in Figure 6 and will perform an amplifying operation. In other words, the switch circuit 480 switches whether to perform an integrating operation or an amplifying operation of the analog amplifier 100 according to the control signal from the control circuit 470.

[0088] The delta-sigma converter 300 in the reference example was shown to be able to perform accurate AD conversion by having the digital filter section 310 perform the calculation shown in equation (26). However, the DC gain and bandwidth of the actual amplifier are finite, and variations may occur in the constants of the electronic components, and mismatches in capacitor capacitance may occur. Therefore, when the delta-sigma converter 300 is actually operated with the electronic components mounted, the amplification factor of the analog amplifier section 100 may deviate from the design value. In this case, even if the digital filter section 310 performs the calculation shown in equation (26), the calculation will be different from the amplification operation of the analog amplifier section 100, which may degrade the linearity of the AD conversion.

[0089] In contrast, the integrator 10 shown in Figures 1 and 3 differs from the amplification operation of the analog amplifier 100 in that even if there is variation in the capacitance of the feedback capacitor 24, the integrated charge is retained in the feedback capacitor 24, so the feedback coefficient hardly shifts. Therefore, the delta-sigma modulator 200 of the third modified example improves the linearity of the AD conversion by combining the integration operation and amplification operation of the analog amplifier 100. For example, the delta-sigma modulator 200 causes the analog amplifier 100 to perform an integration operation for a predetermined period of time.

[0090] The delta-sigma modulator 200 in the reference example describes an example in which the analog amplifier 100 operates in an integral manner from the time the analog amplifier 100 is reset until the kth clock signal. In this case, the delta-sigma modulator 200 amplifies the analog amplifier 100 for the remaining (nk) clock signals, and resets the analog amplifier 100 again for the (n+1)th clock signal.

[0091] Here, the output signal A of the analog amplifier 100. OUT The initial value is 0, and analog signal A is input to the delta-sigma modulator 200. SIG If we assume that is a nearly constant value, the output of the i-th quantizer 210 is D OUT (i) Then, output signal A OUT This is expressed by the following equation.

number

[0092] By rearranging equation (35), we obtain the following equation. Note that the quantization error is set to E2.

number

[0093] Here, if the feedback loop of the delta-sigma modulator 200 is stabilized, the output signal A of the analog amplifier 100 OUT This can be kept within a value of approximately a constant voltage V. When stabilized in this way, the quantization error E2 of the delta-sigma modulator 200 of the third modified example is given by the following equation.

number

[0094] As described above, the delta-sigma modulator 200 of the third modification reduces the degradation of linearity while maintaining high resolution by integrating the operation of the analog amplifier 100 for a certain period of time. For example, when n=10, k=5, and x=2, according to equation (37), the delta-sigma modulator 200 of the third modification has a quantization error E2 of less than V / 191. Thus, the delta-sigma converter 300 using the delta-sigma modulator 200 of the third modification can perform AD conversion with good linearity while maintaining high resolution, compared to the first-order delta-sigma modulator 30 and the third-order delta-sigma modulator 30.

[0095] Figure 16 shows an example of the actual circuit configuration of the analog amplifier 100 of the third modified example. In the analog amplifier 100 of the third modified example in Figure 16, components whose operation is substantially the same as those of the analog amplifier 100 of the reference example shown in Figure 9 are given the same reference numerals, and their explanations are omitted. The analog amplifier 100 of the third modified example further includes a switch circuit 480.

[0096] The switch circuit 480 switches whether or not to connect the second switched capacitor circuit 140 to the feedback circuit of the analog amplifier 110. When the switch circuit 480 electrically disconnects the second switched capacitor circuit 140 from the feedback circuit of the analog amplifier 110, the analog amplifier section 100 operates in integral mode. When the switch circuit 480 electrically connects the second switched capacitor circuit 140 to the feedback circuit of the analog amplifier 110, the analog amplifier section 100 operates in amplification mode. In other words, the analog amplifier section 100 of the third modified example switches whether the feedback coefficient is greater than 1 or 1.

[0097] The delta-sigma modulator 200 of the third modified example controls such a switch circuit 480. For example, the control circuit 470 controls the output A of the analog amplifier 100. OUT After resetting, the control circuit 470 supplies a control signal to the switch circuit 480 that electrically disconnects the second switched-capacitor circuit 140 and the feedback circuit of the analog amplifier 110 until a predetermined period of time has elapsed. After the predetermined period of time has elapsed, the control circuit 470 supplies a control signal to the switch circuit 480 that electrically connects the second switched-capacitor circuit 140 and the feedback circuit of the analog amplifier 110.

[0098] Figure 17 shows an example of the actual circuit configuration of an analog amplifier 800 according to one embodiment of the present invention. The analog amplifier 800 is a modified example of the analog amplifier 100 shown in Figure 16. The analog amplifier 800 has at least a first-order feedback coefficient and receives an analog signal A IN The signal is amplified. The analog amplifier 800 can be applied to the delta-sigma modulator 200 shown in Figure 15 by replacing equation (Equation 17) with the following equation. As shown in Figure 15, the analog amplifier 800 is controlled by the control circuit 470 and the reset circuit 460.

number

[0099] The analog amplifier section 800 in this example includes an input terminal 102, an output terminal 104, an analog amplifier 110, a feedback capacitor 120, a first switched capacitor circuit 130, and a second switched capacitor circuit 140. The analog amplifier section 800 in this example does not include the switch circuit 480 shown in Figure 16.

[0100] In Figure 17, elements with the same reference numerals as in Figure 16 may have the configuration and function described in Figure 16, etc. The input terminal 102, output terminal 104, analog amplifier 110, feedback capacitor 120, and first switched-capacitor circuit 130 in this example have the same function and configuration as in the example in Figure 16. The second switched-capacitor circuit 140 has the same configuration as in the example in Figure 16, but the operation patterns of each switch differ from those in the example in Figure 16.

[0101] The control circuit 470 in this example has a first operating mode and a second operating mode. In the first operating mode, the control circuit 470 controls the second switched capacitor circuit 140 so that the second capacitor C2 is connected in parallel with the feedback capacitor C0 between the input terminal (-) and output terminal of the analog amplifier 110, while switching the first switched capacitor circuit 130. In the second operating mode, the control circuit 470 synchronously controls the first switched capacitor circuit 130 and the second switched capacitor circuit 140. Synchronous control means controlling them at the same timing. The control circuit 470 may supply control signals generated from the same clock signal to the first switched capacitor circuit 130 and the second switched capacitor circuit 140. The operation of the first switched capacitor circuit 130 and the second switched capacitor circuit 140 in the second operating mode is the same as in the example in Figure 9 (or the example in Figure 16 when the switch circuit 480 is turned on).

[0102] As described above, in the first operating mode, the feedback capacitor C0 and the second capacitor C2 are connected in parallel, and their combined capacitance functions as the feedback capacitor of the analog amplifier 110. Therefore, the input coefficient k of the analog amplifier 110 is given by the following equation. The input coefficient k is the ratio of the capacitance of the first capacitor C1 to the combined capacitance of the capacitors that function as the feedback capacitor of the analog amplifier 110.

number

[0103] As shown in equation (38), the input coefficient k of the analog amplifier 110 in the first operating mode is determined by the ratio of the capacitance of the first capacitor C1 to the combined capacitance of the feedback capacitor C0 and the second capacitor C2 (in this example, the sum of their capacitances). On the other hand, the input coefficient k in the example in Figure 16 is given by the following equation.

number

[0104] On the other hand, in the second operating mode, the analog amplifier 800 operates in the same way as the analog amplifier 100, so the amplification factor x is determined by equation (Equation 19). As shown by equation (Equation 19), the amplification factor x of the analog amplifier 110 in the second operating mode is determined according to the ratio of the capacitance of the second capacitor C2 to the capacitance of the feedback capacitor C0. Therefore, in the analog amplifier 800, even when using a feedback capacitor C0 and a second capacitor C2 with smaller capacitances than in the example in Figure 16, the same amplification factor x as in the example in Figure 16 can be achieved by adjusting the ratio of the feedback capacitor C0 to the second capacitor C2. In other words, the analog amplifier 800 and control circuit 470 in this example can achieve the same functionality as in the example in Figure 16 while using smaller capacitances for the second capacitor C2 and the feedback capacitor C0 than in the example in Figure 16.

[0105] For example, to achieve an input coefficient k=1 and an amplification factor x=2, in the example shown in Figure 16, the capacitances of the first capacitor C1, the feedback capacitor C0, and the second capacitor C2 are made equal to each other. In other words, the sum of the capacitances is about three times that of the first capacitor C1. In contrast, in the analog amplifier 800, the input coefficient k=1 and amplification factor x=2 can be achieved by making the capacitances of the feedback capacitor C0 and the second capacitor C2 half the capacitance of the first capacitor C1. In other words, the analog amplifier 800 can achieve an input coefficient k=1 and amplification factor x=2 with about 67% of the sum of the capacitances in the example shown in Figure 16. The input coefficient k and amplification factor x in the analog amplifier 800 are not limited to these values. The analog amplifier 800 can be implemented using elements with relatively small capacitances for a variety of input coefficients k and amplification factors x. This allows for a reduction in circuit size.

[0106] Furthermore, when achieving the same input coefficient k and amplification factor x with the same circuit scale, the analog amplifier 800 can use a first capacitor C1 with a larger capacitance than the analog amplifier 100. So-called kT / C noise can be reduced by increasing the capacitance of the first capacitor C1 that samples the signal. Since the analog amplifier 800 can use elements with relatively large capacitance, kT / C noise can be reduced.

[0107] The capacitances of the first capacitor C1, the feedback capacitor C0, and the second capacitor C2 are not limited to the examples above. The sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 may be designed to be relatively close to the capacitance of the first capacitor C1. For example, the sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 may be between 0.5 and 1.5 times the capacitance of the first capacitor C1. As described above, by making the sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 relatively close to the capacitance of the first capacitor C1, the input coefficient k can be made close to 1. In other words, the analog amplifier 800 can be operated with characteristics close to those of an integrator.

[0108] The sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 may be 1.3 times or less the capacitance of the first capacitor C1, or 1.1 times or less. The sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 may be 0.7 times or more the capacitance of the first capacitor C1, or 0.9 times or more. The sum of the capacitances of the feedback capacitor C0 and the second capacitor C2 may be equal to the capacitance of the first capacitor C1. The capacitance of the feedback capacitor C0 and the capacitance of the second capacitor C2 may be equal. The capacitances of the feedback capacitor C0 and the second capacitor C2 may each be half the capacitance of the first capacitor C1.

[0109] In the first operating mode, the control circuit 470 may stop the switching operation of each switch in the second switched-capacitor circuit 140. In this case, the control circuit 470 stops the switching operation of the second switched-capacitor circuit 140 while the second capacitor C2 is connected in parallel with the feedback capacitor C0. This allows the state to be maintained.

[0110] In the second operating mode, the control circuit 470 controls the second switched capacitor circuit 140 so that the operation of charging the second capacitor C2 with power from the output terminal of the analog amplifier 110 and discharging the charge of the second capacitor C2 to the input terminal of the analog amplifier 110 is repeated. In this case, the operation of the second switched capacitor circuit 140 is the same as in the example in Figure 9.

[0111] The reset circuit 460 may reset the analog amplifier 800 at predetermined intervals. The control circuit 470 may, after resetting the analog amplifier 800, control the analog amplifier 800 so that it operates as an integrator with a first-order feedback coefficient of 1 until a predetermined first period has elapsed, and then operates as an amplifier with a first-order feedback coefficient greater than 1 after the first period has elapsed. The control circuit 470 may operate in a first operating mode during the first period and in a second operating mode after the first period has elapsed. In this case, for example, the input coefficient k in the first operating mode is 1, and the amplification factor x in the second operating mode is greater than 1.

[0112] The second switched-capacitor circuit 140 in this example includes a second capacitor C2, a first switching element 801, a second switching element 802, a third switching element 803, and a fourth switching element 804. Of the two terminals of the second capacitor C2, the terminal on the input side of the analog amplifier 110 is designated as the first terminal 851, and the terminal on the output side of the analog amplifier 110 is designated as the second terminal 852. Each switching element in each switched-capacitor circuit is, for example, a MOSFET, but is not limited to this.

[0113] The first switch element 801 is provided between the first terminal 851 of the second capacitor C2 and the input terminal (-) of the analog amplifier 110. The signal controlling the switching operation of the first switch element 801 is denoted as Φ2'. The second switch element 802 is provided between the first terminal 851 of the second capacitor C2 and the reference potential. The signal controlling the switching operation of the second switch element 802 is denoted as Φ1''. The third switch 803 is provided between the second terminal 852 of the second capacitor C2 and the output terminal of the analog amplifier 110. The signal controlling the switching operation of the third switch element 803 is denoted as Φ1'. The fourth switch 804 is provided between the second terminal 852 of the second capacitor C2 and the reference potential. The signal controlling the switching operation of the fourth switch element 804 is denoted as Φ2''.

[0114] The first switched-capacitor circuit 130 in this example includes a first capacitor C1, a fifth switching element 805, a sixth switching element 806, a seventh switching element 807, and an eighth switching element 808. Of the two terminals of the first capacitor C1, the terminal on the input terminal 102 side is designated as the third terminal 853, and the terminal on the input terminal (-) side of the analog amplifier 110 is designated as the fourth terminal 854.

[0115] The fifth switch element 805 is located between the third terminal 853 of the first capacitor C1 and the input terminal 102. The signal controlling the switching operation of the fifth switch element 805 is denoted as Φ1. The sixth switch element 806 is located between the third terminal 853 of the first capacitor C1 and the reference potential. The signal controlling the switching operation of the sixth switch element 806 is denoted as Φ2. The seventh switch 807 is located between the fourth terminal 854 of the first capacitor C1 and the input terminal (-) of the analog amplifier 110. The signal controlling the switching operation of the seventh switch element 807 is denoted as Φ2. The eighth switch 808 is located between the fourth terminal 854 of the first capacitor C1 and the reference potential. The signal controlling the switching operation of the eighth switch element 808 is denoted as Φ1.

[0116] Figure 18 is a timing chart showing an example of each control signal Φ. In this example, the control circuit 470 operates in the first operating mode until the first period has elapsed after the reset circuit 460 resets the analog amplifier 800, and operates in the second operating mode during the second period after the first period has elapsed.

[0117] The operation of each switch in the first switched-capacitor circuit 130 in the first and second operating modes is the same as in the example in Figure 16. That is, the control circuit 470 uses signals Φ1 and Φ2 to synchronously switch the fifth switch element 805, the sixth switch element 806, the seventh switch element 807, and the eighth switch element 808 at a predetermined period in both the first and second operating modes. The control circuit 470 also controls the fifth switch element 805 and the eighth switch element 808 to the same state using signal Φ1, and controls the sixth switch element 806 and the seventh switch element 807 to a different state from the fifth switch element 805 and the eighth switch element 808 using signal Φ2. In this example, signals Φ1 and Φ2 are signals with inverted on-level (on) and off-level (off) patterns. In the first operating mode, each switch element of the first switched-capacitor circuit 130 may be switched multiple times.

[0118] In the first operating mode, the control circuit 470 maintains the first switch element 801 and the third switch element 803 in the ON state by signals Φ2' and Φ1'. In the first operating mode, the control circuit 470 also maintains the second switch element 802 and the fourth switch element 804 in the OFF state by signals Φ1'' and Φ2''. This maintains the state in which the second capacitor C2 is connected in parallel with the feedback capacitor C0.

[0119] In the second operating mode, the control circuit 470 synchronously switches the first switch element 801, the second switch element 802, the third switch element 803, and the fourth switch element 804. In the second operating mode, the control circuit 470 controls the first switch element 801 and the fourth switch element 804 to the same state using signals Φ2' and Φ2''. In addition, in the second operating mode, the control circuit 470 controls the second switch element 802 and the third switch element 803 to a different state from the first switch element 801 and the fourth switch element 804 using signals Φ1'' and Φ1'.

[0120] In this example, signals Φ1, Φ1', and Φ1'' in the second period are signals with the same pattern. Also, signals Φ2, Φ2', and Φ2'' in the second period are signals with the same pattern. In the second operating mode, the control circuit 470 controls the first switch element 801 and the fourth switch element 804 to the same state as the sixth switch element 806 and the seventh switch element 807 using signals Φ2, Φ2', and Φ2''. In the second operating mode, the control circuit 470 also controls the second switch element 802 and the third switch element 803 to the same state as the fifth switch element 805 and the eighth switch element 808 using signals Φ1, Φ1', and Φ1''. With such control signals, the control circuit 470 can sequentially control the analog amplifier 800 in the first and second operating modes.

[0121] Figure 19 shows an example configuration of a delta-sigma modulator 900 according to one embodiment. The delta-sigma modulator 900 in this example includes an input terminal 106, an output terminal 108, a quantizer 210, a DA converter 220, an adder / subtractor 230, a first amplifier 410, a second amplifier 420, a third amplifier 430, a reset circuit 460, a control circuit 470, and an analog amplification section 800. Elements in Figure 19 that are denoted by the same reference numerals as in other drawings may have the same function and configuration as elements described in other drawings.

[0122] Figure 19 shows a schematic equivalent circuit of the analog amplifier 800 described in Figures 17 and 18. The analog amplifier 800 in this example has an input terminal 102, an output terminal 104, an adder 820, a delay element 830, and an amplifier 840. The adder 820, delay element 830, and amplifier 840 correspond to the first switched-capacitor circuit 130, the second switched-capacitor circuit 140, the analog amplifier 110, and the feedback capacitor C0 in Figure 17.

[0123] In this example, the second amplifier 420 and the third amplifier 430 are amplifiers with variable amplification. The second amplifier 420 and the third amplifier 430 receive the analog signal A input to the input terminal 102 of the analog amplification unit 800. IN This is an example of an input amplifier that amplifies the signal. The control circuit 470 controls the amplification ratios of the second amplifier 420 and the third amplifier 430. The control circuit 470 controls the first amplification ratio (α) of the second amplifier 420 and the third amplifier 430 in the first operating mode. 1_1 , α 1fb_1 ) and the second amplification factor (α) of the second amplifier 420 and the third amplifier 430 in the second operating mode. 1_2 , α 1fb_2 ) may be made different. The control circuit 470 may control the amplification factor of both the second amplifier 420 and the third amplifier 430 according to the operating mode.

[0124] As described above, the first input coefficient k1 of the analog amplifier 110 in the first operating mode is given by equation (Equation 38). On the other hand, the second input coefficient k2 of the analog amplifier 110 in the second operating mode is given using the ratio of the capacitance of the first capacitor C1 to the capacitance of the feedback capacitor C0, similar to equation (Equation 39). In other words, the input coefficient of the analog amplifier 110 fluctuates between the first and second operating modes. The control circuit 470 may control the amplification factors of the second amplifier 420 and the third amplifier 430 to cancel out the fluctuations in the input coefficient.

[0125] As an example, the control circuit 470 has a first amplification factor (α 1_1 , α 1fb_1 ) with respect to the second amplification factor (α1_2 , α 1fb_2 ) ratio (α 1_1 / α 1_2 , and α 1fb_1 / α 1fb_2 The second amplification factor is controlled according to the ratio (k1 / k2) of the first input coefficient k1 and the second input coefficient k2. For example, if the second input coefficient k2 is p times the first input coefficient k1, the control circuit 470 may control the second amplification factor to 1 / p of the first amplification factor.

[0126] The control circuit 470 may control the amplification factors of the second amplifier 420 and the third amplifier 430 according to the ratio of the capacitances of the feedback capacitor C0 and the second capacitor C2. As described above, the first input coefficient k1 is given by equation (38) and the second input coefficient k2 is given by equation (39). Therefore, the ratio of the first input coefficient k1 to the second input coefficient k2 is given by the following equation.

number

[0127] The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. Blocks in flowcharts and block diagrams may be represented as (1) stages of a process in which an operation is performed, or (2) "parts" of a device that has the role of performing an operation. Specific stages and "parts" may be implemented by dedicated circuits, programmable circuits supplied with computer-readable instructions stored on a computer-readable storage medium, and / or processors supplied with computer-readable instructions stored on a computer-readable storage medium.

[0128] The dedicated circuit may include digital and / or analog hardware circuits, and may include integrated circuits (ICs) and / or discrete circuits. The programmable circuit may include reconfigurable hardware circuits, such as field-programmable gate arrays (FPGAs) and programmable logic arrays (PLAs), which include logical AND, logical OR, exclusive OR, negated AND, negated OR, and other logical operations, flip-flops, registers, and memory elements.

[0129] A computer-readable storage medium may include any tangible device capable of storing instructions to be executed by a suitable device. Thus, a computer-readable storage medium having instructions stored in such tangible device comprises a product containing instructions that can be executed to create means for performing operations specified in a flowchart or block diagram.

[0130] Examples of computer-readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, etc. More specific examples of computer-readable storage media may include floppy disks (registered trademark), diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital multipurpose discs (DVDs), Blu-ray (registered trademark) discs, memory sticks, integrated circuit cards, etc.

[0131] Computer-readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, etc. Furthermore, computer-readable instructions may include source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, Java®, and C++, and traditional procedural programming languages ​​such as the C programming language or similar languages.

[0132] Computer-readable instructions may be provided locally or via a wide area network (WAN), such as a local area network (LAN) or the internet, to the processor or programmable circuit of a general-purpose computer, a special-purpose computer, or other programmable data processing device. This allows the general-purpose computer, special-purpose computer, or other programmable data processing device's processor or programmable circuit to execute the computer-readable instructions to generate means for performing operations specified in a flowchart or block diagram. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, and microcontrollers.

[0133] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0134] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0135] 2 Input terminals, 4 Output terminals, 6 Input terminals, 8 Output terminals, 10 Integrator, 12 Delay element, 14 Adder, 22 Amplifier, 24 Feedback capacitor, 26 Switched capacitor circuit, 30 Delta-sigma modulator, 32 Quantizer, 34 DA converter, 36 Adder / subtractor, 40 Delta-sigma converter, 42 Digital filter section, 100 Analog amplifier section, 102 Input terminal, 104 Output terminal, 106 Input terminal, 108 Output terminal, 110 Analog amplifier, 112 Delay element, 114 Amplifier, 116 Adder, 120 Feedback capacitor, 130 First switched capacitor circuit, 140 Second switched capacitor circuit, 200 Delta-sigma modulator, 210 Quantizer, 220 DA converter, 230 Adder / subtractor, 300 Delta-sigma converter, 310 Digital filter section, 410 First amplifier, 420 Second amplifier, 430 Third amplifier, 440 Fourth amplifier, 442 Adder, 450 AD converter, 452 Output terminal, 460 Reset circuit, 470 Control circuit, 480 Switch circuit, 500 Op-amp circuit, 510 Op-amp, 600 Integrator, 610 First voltage-current converter, 620 Second voltage-current converter, 630 Amplifier circuit, 700 Analog amplifier section, 702 Differential input terminal, 704 Differential output terminal, 710 Analog amplifier, 722 First feedback capacitor, 724 Second feedback capacitor, 732 Positive first voltage-current converter, 734 Negative first voltage-current converter, 742 Positive second voltage-current converter, 744 Negative second voltage-current converter, 800 Analog amplifier section, 801 802 First switch element, 803 Second switch element, 804 Third switch element, 805 Fourth switch element, 806 Fifth switch element, 806 Sixth switch element, 807 Seventh switch element, 808 Eighth switch element, 820 Adder, 830 Delay element, 840 Amplifier, 851 First terminal, 852 Second terminal, 853 Third terminal, 854 Fourth terminal, 900 Delta-sigma modulator

Claims

1. An analog amplification section having at least a first-order feedback coefficient and amplifying an analog signal, A quantizer that quantizes the output signal of the analog amplifier section, A DA converter that performs D / A conversion on the output of the quantizer and outputs a feedback signal to be fed back to the analog amplifier, An adder / subtractor inputs an analog signal obtained by subtracting the feedback signal from the input analog signal to the analog amplifier. A reset circuit that resets the analog amplification section at predetermined intervals, The analog amplifier section comprises a control circuit for controlling the analog amplifier section, The aforementioned analog amplification section is An analog amplifier is provided between the input terminal and output terminal of the aforementioned analog amplification section, A first switched capacitor circuit, which includes a first capacitor, is provided between the input terminal and the analog amplifier. Between the input terminal and output terminal of the analog amplifier, a feedback capacitor is provided as a feedback circuit for the analog amplifier, A second switched capacitor circuit, which includes a second capacitor, is provided in parallel with the aforementioned feedback capacitor. It has, The aforementioned control circuit is A first operating mode controls the second switched-capacitor circuit such that, while the first switched-capacitor circuit is in switching operation, the second capacitor is connected in parallel with the feedback capacitor between the input terminal and the output terminal of the analog amplifier. A second operating mode that synchronously controls the first switched-capacitor circuit and the second switched-capacitor circuit. A delta-sigma modulator having the following characteristics.

2. The control circuit stops the switching operation of each switch in the second switched-capacitor circuit in the first operating mode. The delta-sigma modulator according to claim 1.

3. The control circuit controls the second switched-capacitor circuit such that, in the second operating mode, the second capacitor is charged by power from the output terminal of the analog amplifier, and the charge of the second capacitor is discharged to the input terminal of the analog amplifier, and this operation is repeated. The delta-sigma modulator according to claim 1.

4. The control circuit controls the analog amplifier so that, after resetting the analog amplifier, it operates as an integrator with a first-order feedback coefficient of 1 until a predetermined first period has elapsed, and after the first period has elapsed, it operates as an amplifier with a first-order feedback coefficient greater than 1. The control circuit operates in the first operating mode during the first period, and operates in the second operating mode after the first period has elapsed. The delta-sigma modulator according to claim 1.

5. The sum of the capacitances of the feedback capacitor and the second capacitor is 0.5 times or more and 1.5 times or less the capacitance of the first capacitor. The delta-sigma modulator according to claim 1.

6. The sum of the capacitances of the feedback capacitor and the second capacitor is equal to the capacitance of the first capacitor. The delta-sigma modulator according to claim 5.

7. The capacitance of the feedback capacitor is equal to the capacitance of the second capacitor. The delta-sigma modulator according to claim 6.

8. The input coefficient of the analog amplifier in the first operating mode is determined according to the ratio of the capacitance of the first capacitor to the combined capacitance of the feedback capacitor and the second capacitor. The amplification factor of the analog amplifier in the second operating mode is determined according to the ratio of the capacitance of the second capacitor to the capacitance of the feedback capacitor. The delta-sigma modulator according to claim 1.

9. The analog amplification section further comprises an input amplifier that amplifies the analog signal input to the input terminal, The control circuit causes the first amplification factor of the input amplifier in the first operating mode to be different from the second amplification factor of the input amplifier in the second operating mode. A delta-sigma modulator according to any one of claims 1 to 8.

10. The control circuit controls the ratio of the second amplification factor to the first amplification factor according to the ratio of the second input coefficient of the analog amplifier in the second operating mode to the first input coefficient of the analog amplifier in the first operating mode. The delta-sigma modulator according to claim 9.

11. The second switched-capacitor circuit is, A first switching element is provided between the first terminal of the second capacitor and the input terminal of the analog amplifier, A second switching element is provided between the first terminal of the second capacitor and a reference potential, A third switch is provided between the second terminal of the second capacitor and the output terminal of the analog amplifier, A fourth switch is provided between the second terminal of the second capacitor and a reference potential. It has, The aforementioned control circuit is In the first operating mode, the first switch element and the third switch element are kept in the ON state, and the second switch element and the fourth switch element are kept in the OFF state. In the second operating mode, the first switch element, the second switch element, the third switch element, and the fourth switch element are switched synchronously, the first switch element and the fourth switch element are controlled to the same state, and the second switch element and the third switch element are controlled to a different state from the first switch element and the fourth switch element. A delta-sigma modulator according to any one of claims 1 to 8.

12. The first switched-capacitor circuit is, A fifth switch element is provided between the third terminal of the first capacitor and the input terminal of the analog amplifier section, A sixth switching element is provided between the third terminal of the first capacitor and a reference potential, A seventh switch is provided between the fourth terminal of the first capacitor and the input terminal of the analog amplifier, An eighth switch is provided between the fourth terminal of the first capacitor and a reference potential. It has, The aforementioned control circuit is In the first and second operating modes, the fifth switch element, the sixth switch element, the seventh switch element, and the eighth switch element are switched synchronously, the fifth switch element and the eighth switch element are controlled to the same state, and the sixth switch element and the seventh switch element are controlled to a different state from the fifth switch element and the eighth switch element. In the second operating mode, the first switch element is controlled to be in the same state as the sixth switch element. The delta-sigma modulator according to claim 11.

13. A delta-sigma modulator according to any one of claims 1 to 8, A digital filter unit that filters the modulated digital signal output by the delta-sigma modulator. A delta-sigma converter equipped with this feature.

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