Microcontroller and method for self-diagnosticating a microcontroller

Abstract

We provide a microcontroller that reduces the amount of data to be communicated and the computational load on the CPU. [Solution] The microcontroller 30 includes post-reception processing circuits 50 and 52. The post-reception processing circuits 50 and 52 are hardware processing circuits that decompress compressed archive format data. When the CPU 42 receives compressed archive format data, it instructs the post-reception processing circuits 50 and 52 and the DMAC 46 to decompress the received data and send it to the RAM 44.

Description

Technical Field

[0001] The present disclosure relates to a microcontroller and a self-diagnosis method for a microcontroller.

Background Art

[0002] Patent Document 1 describes that a test program is written in the memory in the microcomputer during the shipment inspection of the microcomputer to execute a self-test. Patent Document 2 describes that a computer of an air conditioner equipped with a camera stores the photographed data of the camera in a storage unit and then uploads the stored photographed data to a server in a lump (paragraph "0043").

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When transferring the above test program to the microcomputer, if the data volume of the test program is large, the load on communication increases. Therefore, it is conceivable to compress the data to be transmitted to the microcomputer in advance. However, in that case, the computational load on the computer increases due to decompression / extraction of the compressed data. Also, when uploading the photographed data stored in the storage unit in a lump, it is conceivable to make archive data. However, in that case, the computational load on the computer increases due to processing for compressing the photographed data and adding metadata. [[ID=​​​​A microcontroller in the first aspect that solves the above problem is a microcontroller that exchanges archive data with the outside, wherein the archive data includes a plurality of files and metadata which is data indicating additional information of the plurality of files, and at least the plurality of files are compressed data, and comprises a software processing circuit and a hardware processing circuit, wherein the hardware processing circuit includes at least one of two circuits, a post-reception processing circuit and a pre-transmission processing circuit, the post-reception processing circuit includes a decompression circuit for decompressing the plurality of files contained in the archive data and an extraction circuit for extracting the plurality of files and the metadata contained in the archive data, the pre-transmission processing circuit includes at least a compression circuit (60a, 62a) for compressing the plurality of files and an addition circuit for adding the metadata, and the software processing circuit is configured to instruct the hardware processing circuit to process the archive data.

[0006] The archived data described above consists of multiple compressed files. Therefore, if the above configuration includes a post-reception processing circuit, the amount of data received by the microcontroller can be reduced compared to a configuration where the multiple files are not compressed. Furthermore, including a post-reception processing circuit can suppress the increased computational load on the software processing circuit caused by the process of decompressing multiple files. Also, if the above configuration includes a pre-transmission processing circuit, the amount of data transmitted by the microcontroller can be reduced compared to a configuration where the multiple files are not compressed. Furthermore, including a pre-transmission processing circuit can suppress the increased computational load on the software processing circuit caused by the process of compressing multiple files.

[0007] The microcontroller in the second aspect is the microcontroller described in the first aspect, wherein the hardware processing circuit includes the post-reception processing circuit. In the above configuration, the amount of data received by the microcontroller can be reduced compared to when multiple files are not compressed. Moreover, the computational load on the software processing circuit, which would increase due to the process of decompressing multiple files, can be suppressed.

[0008] The microcontroller in the third aspect is the microcontroller described in the second aspect, wherein the post-reception processing circuit has both a configuration in which the decompression circuit is provided upstream of the extraction circuit and a configuration in which the extraction circuit is provided upstream of the decompression circuit, when the side from which the archive data is input from outside the microcontroller is considered the upstream side.

[0009] Archive data compression formats include those that compress only multiple files, and those that compress both multiple files and metadata. Therefore, the above configuration includes both a configuration where the decompression circuit is upstream and a configuration where the extraction circuit is upstream. This allows for the decompression of archive data using various compression formats.

[0010] The microcontroller of aspect 4 is the microcontroller described in the second or third aspect, wherein the post-reception processing circuit includes multiple types of circuits for at least one of the two, the decompression circuit and the extraction circuit, in order to handle multiple types of archived data of different formats.

[0011] In the above configuration, the post-reception processing circuit includes multiple types of circuits for at least one of the two components, the decompression circuit and the extraction circuit, thereby enabling the handling of multiple types of archived data in different formats.

[0012] The microcontroller of the fifth aspect is a microcontroller described in any one of the second to fourth aspects, further comprising a memory and a direct memory access controller, wherein the post-reception processing circuit is configured to decompress the archived data and store the plurality of files and the metadata in the memory in cooperation with the direct memory access controller in response to the instructions from the software processing circuit.

[0013] In the above configuration, the software processing circuit only needs to instruct the post-reception processing circuit and the direct memory access controller to process the archived data in cooperation, thus reducing the computational load on the software processing circuit when processing the archived data.

[0014] The microcontroller in the sixth aspect is a microcontroller described in any one of the second to fifth aspects, wherein the hardware processing circuit includes a circuit that chooses to acquire external data by bypassing at least one of the decompression circuit and the extraction circuit.

[0015] For example, data that has not been compressed is not processed by the decompression circuit. Also, for example, data without metadata is not processed by the extraction circuit. Therefore, in the above configuration, by including a circuit that selects to bypass at least one of the above and acquire external data, it is possible to receive and appropriately process data other than compressed archive data.

[0016] The microcontroller in the seventh aspect is the microcontroller described in any one of the first to sixth aspects, wherein the hardware processing circuit includes the pre-transmission processing circuit. In the above configuration, because a pre-transmission processing circuit is included, the amount of data transmitted by the microcontroller can be reduced compared to when multiple files are not compressed. Moreover, because a pre-transmission processing circuit is included, the computational load on the software processing circuit, which is increased by the process of compressing multiple files, can be suppressed compared to when the software processing circuit performs the compression process.

[0017] The microcontroller of the eighth aspect is the microcontroller described in the seventh aspect, wherein the pre-transmission processing circuit has both a configuration in which the additional circuit is connected downstream of the compression circuit and a configuration in which the compression circuit is connected downstream of the additional circuit, when the side that transmits the archived data from the microcontroller to the outside is the downstream side.

[0018] There are two types of compression formats for archive data: one that compresses only multiple files, and another that compresses both multiple files and metadata. Therefore, the above configuration includes both a configuration where the compression circuit is upstream and a configuration where the additive circuit is upstream. This allows for the compression of archive data using various compression formats.

[0019] The microcontroller of the ninth aspect is the microcontroller of the seventh or eighth aspect, wherein the pre-transmission processing circuit includes multiple types of circuits for at least one of the two, the compression circuit and the additive circuit, to handle multiple types of archived data of different formats.

[0020] In the above configuration, the pre-transmission processing circuit includes multiple types of circuits for at least one of the two components: the compression circuit and the additive circuit. This allows for handling multiple types of archived data in different formats.

[0021] The microcontroller according to the tenth aspect is the microcontroller described in any one of the seventh to ninth aspects, and includes a memory and a direct memory access controller. The pre-transmission processing circuit is configured to execute a process of generating one of the archive data from the plurality of files stored in the memory and the metadata in cooperation with the direct memory access controller according to the instruction from the software processing circuit, and transferring the generated archive data outside the microcontroller.

[0022] In the above configuration, since the software processing circuit only needs to instruct the post-transmission processing circuit and the direct memory access controller to execute the processing of the archive data in cooperation, the arithmetic load of the software processing circuit during the execution of the processing of the archive data can be reduced.

[0023] The microcontroller according to the eleventh aspect is the microcontroller described in any one of the seventh to tenth aspects, and the hardware processing circuit includes a circuit that selects to transfer data outside by bypassing at least one of the compression circuit and the addition circuit.

[0024] For example, data that is not subjected to compression processing is not a processing target of the compression circuit. Also, for example, data to which metadata is not added is not a processing target of the addition circuit. Therefore, in the above configuration, by providing a circuit that selects to obtain external data by bypassing at least one of the above, it is possible to create and transmit data other than the compressed archive data.

[0025] The microcontroller according to the twelfth aspect is the microcontroller described in any one of the first to eleventh aspects, and the post-reception processing circuit includes a decoding circuit that decodes the archive data, and the pre-transmission processing circuit includes an encryption circuit that encrypts the archive data.

[0026] The above-described post-reception processing circuit includes a decryption circuit, enabling it to handle encrypted archive data. Furthermore, the above-described pre-transmission processing circuit includes an encryption circuit, allowing it to encrypt archive data.

[0027] The microcontroller of the 13th aspect is a microcontroller described in any one of the 2nd to 12th aspects (excluding disclosure 2), wherein the archived data includes data that defines the processing to be performed by the software processing circuit, and the post-reception processing circuit is configured to extract the data from the archived data and provide it to the software processing circuit.

[0028] In the above configuration, the archived data includes data that defines the processing to be performed by the software processing circuit, and the archived data is compressed. This reduces the communication load when the data defining the processing to be performed by the software processing circuit is taken in from outside the microcontroller into the microcontroller. Furthermore, since the post-reception processing circuit handles at least a portion of the process of taking in the data defining the processing to be performed by the software processing circuit from outside the microcontroller into the microcontroller, the computational load on the software processing circuit during the execution of the data acquisition process can be reduced.

[0029] The microcontroller of the 14th aspect is a microcontroller described in any one of the seventh to thirteenth aspects (excluding disclosure seven), wherein the software processing circuit is configured to perform processing for controlling a controlled object and processing for generating data for identifying the state of the controlled object, and the pre-transmission processing circuit is configured to generate the archive data including the data for identifying the state of the controlled object.

[0030] In the above configuration, since the archived data includes data for identifying the state of the controlled object and the data is compressed, the communication load when transmitting the data outside the microcontroller can be reduced. Furthermore, in the above configuration, since the data compression is performed by the pre-transmission processing circuit, the computational load on the software processing circuit when generating data for identifying the state of the air conditioning unit can be reduced compared to when the compression is performed by the software processing circuit.

[0031] A microcontroller according to any one of the 2nd to 14th aspects (excluding disclosure 2) comprises a memory, the software processing circuit is configured to perform processing to control a controlled quantity of a controlled object, the archive data includes a program that specifies a command for the software processing circuit to perform self-diagnosis processing of the microcontroller, and a self-diagnosis method for a microcontroller according to the 15th aspect comprises the steps of inputting the archive data from outside the microcontroller, writing the program to the memory, and the software processing circuit performing self-diagnosis processing of the microcontroller by executing the program written to the memory.

[0032] In the method described above, the program that defines the commands to execute the microcontroller's self-diagnostic process is compressed and input to the microcontroller as archived data. This allows the microcontroller to perform the self-diagnostic process. Furthermore, because the archived data is compressed, the communication load on the microcontroller when receiving data for the self-diagnostic process can be reduced. [Brief explanation of the drawing]

[0033] [Figure 1] This figure shows an air conditioning system and equipment capable of communicating with the air conditioning system according to the first embodiment. [Figure 2] This is a block diagram showing the configuration of the microcontroller included in the above-mentioned air conditioning system. [Figure 3A]This is a block diagram showing the configuration of the post-reception processing circuit included in the above-mentioned microcontroller. [Figure 3B] This is a block diagram showing the configuration of the post-reception processing circuit included in the above-mentioned microcontroller. [Figure 4] This figure shows an example of items in the metadata table according to the same embodiment. [Figure 5] This figure illustrates the structure of the metadata table according to the same embodiment. [Figure 6] This figure illustrates the structure of the metadata table according to the same embodiment. [Figure 7] This figure illustrates the structure of the metadata table according to the same embodiment. [Figure 8] This figure illustrates the memory arrangement of the file contents according to the same embodiment. [Figure 9] This figure illustrates a file content management method according to the same embodiment. [Figure 10] This figure illustrates a file content management method according to the same embodiment. [Figure 11] This is a block diagram showing the configuration of the expansion circuit included in the above-mentioned post-reception processing circuit. [Figure 12A] This is a block diagram showing the configuration of the pre-transmission processing circuit included in the above-mentioned microcontroller. [Figure 12B] This is a block diagram showing the configuration of the pre-transmission processing circuit included in the above-mentioned microcontroller. [Figure 13] This is a block diagram showing the configuration of the compressor included in the above-mentioned pre-transmission processing circuit. [Figure 14] This is a flowchart showing the procedure for processing air conditioning equipment before shipment. [Figure 15] This diagram illustrates the data arrangement in the above process. [Figure 16] This is a flowchart illustrating the post-shipment processing procedures for air conditioning equipment. [Figure 17] This diagram illustrates the data arrangement in the above process. [Figure 18] This is a block diagram showing the configuration of the post-reception processing circuit according to the second embodiment. [Figure 19]This is a block diagram showing the configuration of the pre-transmission processing circuit according to the second embodiment. [Figure 20] This block diagram shows the configuration of the post-reception processing circuit in the modified examples of each of the above embodiments. [Figure 21] This block diagram shows the configuration of the post-reception processing circuit in the modified examples of each of the above embodiments. [Figure 22] This block diagram shows the configuration of the pre-transmission processing circuit in the modified examples of each of the above embodiments. [Figure 23] This block diagram shows the configuration of the pre-transmission processing circuit in the modified examples of each of the above embodiments. [Modes for carrying out the invention]

[0034] <First Embodiment> The first embodiment will be described below with reference to the drawings. "Overall structure" Figure 1 shows the configuration of the air conditioning system according to this embodiment.

[0035] In the air conditioning unit 10, the rotating shaft 12a of the compressor 12 is mechanically connected to the rotating shaft 14a of the motor 14. The output voltage of the inverter 16 is applied to the terminals of the motor 14. The inverter 16 is supplied with power from the grid power supply 20, which has been converted to DC power by the converter 18.

[0036] The microcontroller (hereinafter referred to as "microcontroller 30") is a control device that controls the motor 14. The microcontroller 30 operates the inverter 16 to control the amount of control of the motor 14. The amount of control is, for example, the rotational speed of the rotating shaft 14a. The microcontroller 30 acquires image data Dp related to the state of the compressor 12, which is captured by the camera 32.

[0037] Before the air conditioning unit 10 is shipped, it is made capable of communicating with the factory terminal 34. After the air conditioning unit 10 is shipped, it becomes capable of communicating with the server 38 via the network 36. The network 36 may be the internet, for example.

[0038] "Microcontroller Configuration" Figure 2 shows the configuration of the microcontroller 30. As shown in Figure 2, the microcontroller 30 is equipped with a bus line 40. The central processing unit (hereinafter referred to as CPU 42), RAM 44, and Direct Memory Access Controller (hereinafter referred to as DMAC 46) are connected to the bus line 40.

[0039] Bus line 40 is connected to post-reception processing circuits 50 and 52 and bypass line 54. Data input to the microcontroller 30 from an external source is transferred via one of three methods, the decompression method selector 56, through the post-reception processing circuits 50, 52, and the bypass line 54.

[0040] Figure 3A shows the configuration of the post-reception processing circuit 50. The data input to the post-reception processing circuit 50 is input to the extraction circuit 50a. The extraction circuit 50a is a circuit that extracts metadata and multiple files from the input archive data. The metadata includes, for example, the file path name and file size for each of the multiple files contained in the archive data. Based on the above path name and file size, the extraction circuit 50a determines the location in the RAM 44's storage area to expand the file contents. Then, the extraction circuit 50a performs processing to write the file name, file size, and the starting address of the destination for expanding the file contents to the RAM 44 according to the settings in the setting register 50b. Note that the data extracted as metadata is not limited to the above set. Therefore, the data items stored in the metadata table will also differ depending on the data extracted as metadata.

[0041] Figure 4 shows an example of items in the metadata table. Metadata tables can take on various structures. For example, a metadata table may be managed by an array, as illustrated in Figure 5. Alternatively, a metadata table may be managed by a binary search tree, as illustrated in Figure 6. Furthermore, a metadata table may be managed by a doubly linked list, as illustrated in Figure 7.

[0042] There are various methods that can be used to determine where the contents of files within the RAM44 memory area are extracted. The left side of Figure 8 shows an example where different data storage capacities are allocated to each file content. The right side of Figure 8 shows an example where the same storage capacity is allocated uniformly to each file content.

[0043] Figure 9 shows an example of deleting the data for file content 2 and writing the data for file content 4, given that the data for file content 1 to 3 is already stored in RAM 44. In the example shown in Figure 9, the data for file content 3 is moved to the memory area previously allocated to the data for file content 2, and then the data for file content 4 is written. On the other hand, Figure 10 shows an example where the data for file content 2 is deleted, but the data for file content 3, which is already stored, is not moved. The example shown in Figure 10 is also an example where the data storage area is divided into uniform data storage capacities. Since the data for file content 3 and file content 4 are larger than the respective divided data storage capacities, the data for file content 3 and file content 4 are each allocated two data storage capacities.

[0044] Returning to Figure 3A, the decompression circuit 50c is a circuit that decompresses the above-mentioned compressed files. Figure 11 illustrates an example of a decompression circuit 50c when the post-reception processing circuit 50 is a circuit that decompresses archived data in zip format.

[0045] As shown in Figure 11, the expansion circuit 50c comprises, in order from the input side, a Huffman decoder M10, a literal stacker M12, a data queue M14, an LZ77 decoder M16, and a byte packer M18.

[0046] Figure 3B shows the configuration of the post-reception processing circuit 52. The archive data that the post-reception processing circuit 52 decompresses is, as an example, data in tar.gz format. The data input to the post-reception processing circuit 52 is input to the decompression circuit 52c. The archived data decompressed by the decompression circuit 52c is input to the extraction circuit 52a. The extraction circuit 52a is a circuit that extracts multiple files and metadata from the decompressed archived data. The metadata includes, for example, data indicating the file path name and file size for each of the multiple files contained in the archived data. Based on the above path name and file size, the extraction circuit 52a determines the location in the RAM 44's storage area to expand the file contents. Then, the extraction circuit 52a performs processing to write the file name, file size, and the starting address of the destination for expanding the file contents to the RAM 44 according to the contents set in the setting register 52b.

[0047] Returning to Figure 2, the bus line 40 is connected to the pre-transmission processing circuits 60 and 62 and the bypass line 64. Data output from inside the microcontroller 30 to outside the microcontroller 30 is transferred via one of three methods: the pre-transmission processing circuits 60, 62, and the bypass line 64, by the compression method selector 66.

[0048] Figure 12A shows the configuration of the transmission pre-processing circuit 60. The transmission pre-processing circuit 60 includes a compression circuit 60a, an additive circuit 60b, and a setting register 60c. The compression circuit 60a is a circuit that compresses multiple input files.

[0049] Figure 13 shows an example of a compression circuit 60a. The example shown in Figure 13 shows a circuit that compresses data into zip format. As shown in Figure 13, the compression circuit 60a includes a circuit in which an LZ77 encoder M20 and a Huffman encoder M22 are connected in series, starting from the upstream side.

[0050] Returning to Figure 12A, the additional circuit 60b is a circuit that adds the metadata written to the setting register 60c to the compressed data to create archive data and output it. Figure 12B shows the configuration of the transmission pre-processing circuit 62. The transmission pre-processing circuit 62 includes a compression circuit 62a, an addition circuit 62b, and a setting register 62c.

[0051] The data for multiple files input to the pre-transmission processing circuit 62 is first input to the addition circuit 62b. The addition circuit 62b adds metadata stored in the setting register 62c to the multiple files. Then, the multiple files with the added metadata are input to the compression circuit 62a. The compression circuit 62a is a circuit that compresses the multiple files and metadata and outputs them.

[0052] Returning to Figure 2, the user setting register 70 is a memory that stores data for setting the selection of the decompression method selector 56 and the compression method selector 66. ROM72 stores programs that instruct the CPU42 to perform certain tasks.

[0053] "Pre-shipment processing" Prior to the shipment of the air conditioning unit 10, a program is written to the RAM 44 in the microcontroller 30 that specifies commands for the CPU 42 to execute control of the motor 14. If the ROM 72 is an electrically rewritable read memory, it is desirable that the program written to RAM 44 is subsequently written to ROM 72. Also prior to shipment, a program is written to the RAM 44 in the microcontroller 30 that specifies commands for the CPU 42 to execute pre-shipment inspections.

[0054] Figure 14 shows the steps of processing performed by the factory terminal 34 and the CPU 42 of the microcontroller 30 before shipment. The processing on the left side of Figure 14 shows the steps of processing performed by the factory terminal 34. The processing on the right side of Figure 14 is achieved by the CPU 42 executing a program stored in RAM 44. In the following, the step number of each process will be represented by a number preceded by "S". Furthermore, the following will explain each process shown in Figure 14 in chronological order of the actual process before shipment.

[0055] In the series of processes shown on the left side of Figure 14, the factory terminal 34 normally transmits control software to the microcontroller 30 (S10). The normal control software includes a program that defines commands for the CPU 42 to execute the control of the motor 14. Here, the normal control software is transmitted as archive data, which is compressed archive data. The transmission of the archive data may be done by wired or wireless means.

[0056] In response to this, as shown on the right side of Figure 14, the CPU 42 of the microcontroller 30 instructs the corresponding post-reception processing circuits 50 and 52 and the DMAC 46 to write the archive data to the RAM 44, depending on the archive data being transmitted (S20). Specifically, for example, when using the post-reception processing circuit 50, the CPU 42 sets the following in the setting register 50b of the post-reception processing circuit 50. That is, the CPU 42 sets the starting address of the metadata table in the RAM 44's storage area, the size of the metadata table, the starting address for writing the file to RAM 44, and the amount of data in the file.

[0057] As a result, the extraction circuit 50a of the post-reception processing circuit 50 extracts the metadata attached to the received archive data and then performs processing to write it to RAM 44 according to the setting of the setting register 50b. Specifically, according to the instructions of the extraction circuit 50a, the DMAC 46 writes the file name, file size, and destination address for expanding the file contents to RAM 44 to a specified area of ​​RAM 44. The decompression circuit 50c then decompresses the data of multiple compressed files in the archive data. The data decompressed by the decompression circuit 50c is written to a specified area of ​​RAM 44 by the DMAC 46.

[0058] Figure 15 illustrates the setting of the setting register 50b by the post-reception processing circuit 50 and the writing of data to the RAM 44 by the DMAC 46. The DMAC 46 writes the metadata table 80 data to the RAM 44 according to the starting address of the metadata table written to the setting register 50b. The DMAC 46 also writes data indicating the file contents 82 to the RAM 44 according to the destination of the file contents written to the setting register 50b.

[0059] Returning to Figure 14, the factory terminal 34 transmits software for pre-shipment inspection to the microcontroller 30 (S12). The transmission method here may be the same as that used in S10. In response, the CPU 42 of the microcontroller 30 instructs the corresponding circuit among the post-reception processing circuits 50 and 52 and the DMAC 46 to write the archive data to the RAM 44 (S22). The processing in S22 may be the same as that used in S20.

[0060] Subsequently, the factory terminal 34 sends a command to the microcontroller 30 to perform pre-shipment inspection (S14). Upon completion of the S14 process, the factory terminal 34 terminates the series of processes shown on the left side of Figure 14. In response, the CPU 42 performs the pre-shipment inspection by executing the inspection program stored in the RAM 44 (S24). Upon completion of the S24 process, the CPU 42 terminates the series of processes shown on the right side of Figure 14.

[0061] "Post-shipment processing" After the product is shipped, the air conditioning unit 10 is diagnosed for any abnormalities based on the results of images taken by the camera 32 of the internal condition of the air conditioning unit 10, such as the compressor 12.

[0062] Figure 16 shows the procedure for diagnosing the presence or absence of abnormalities. The process shown on the left side of Figure 16 is achieved by the CPU 42 of the microcontroller 30 repeatedly executing a program stored in RAM 44, for example, at a predetermined cycle. The process shown on the right side of Figure 16 is executed by the server 38.

[0063] In the series of processes shown on the left side of Figure 16, the CPU 42 first acquires image data Dp (S30). The CPU 42 stores the acquired image data Dp in the RAM 44 (S32). If the ROM 72 is an electrically rewritable read-only memory, the CPU 42 may store the acquired image data in the ROM 72. The CPU 42 then determines whether the amount of data of the stored image data Dp is greater than or equal to a predetermined amount (S34). If the CPU 42 determines that it is greater than or equal to the predetermined amount (S34: YES), it instructs either of the pre-transmission processing circuits 60, 62 and the DMAC 46 to create and transmit archive data related to the image data Dp (S36). Specifically, the CPU 42 writes a metadata table containing data related to the file name, file size, and the starting address of the file content to the RAM 44. The CPU 42 also writes data related to the file content to the storage area in the RAM 44 specified in the metadata table. Then, if the CPU 42 uses, for example, the pre-transmission processing circuit 60, it sets the following in the setting register 60c of the pre-transmission processing circuit 60. Specifically, the CPU 42 sets the starting address of the metadata table, the size of the metadata table, the archive format, and the starting address and size of the storage location of the file contents in RAM 44.

[0064] Figure 17 illustrates the settings of the setting register 60c and the data written to RAM 44. As a result, the DMAC46 sends multiple files stored in RAM44 to the pre-transmission processing circuit60. The compression circuit60a compresses the sent files. Then, the appending circuit60b adds metadata to the compressed files to create archive data. The archive data is then sent to the network36 via the compression method selector66.

[0065] Furthermore, when the process in S36 shown in Figure 16 is completed, or when a negative result is determined in the process in S34, the CPU 42 temporarily terminates the series of processes shown on the left side of Figure 16. Meanwhile, as shown on the right side of Figure 16, the server 38 receives the archived data (S40). The server 38 then obtains the image data files contained in the archived data (S42). The server 38 then analyzes the image data to determine whether or not there is a malfunction in the air conditioning unit 10 (S44). If the server 38 determines that there is a malfunction, it may send a signal to the air conditioning unit 10 or the user's terminal indicating this.

[0066] Furthermore, when server 38 completes the processing of S44, it temporarily terminates the series of processes shown on the right side of Figure 16. "The operation and effects of this embodiment" The microcontroller 30 is equipped with post-reception processing circuits 50 and 52 that decompress compressed archive data. Therefore, when sending software or other data to the microcontroller 30 from an external source, the software or other data can be sent as compressed archive data. As a result, the amount of data received by the microcontroller can be reduced compared to when uncompressed data is sent to the microcontroller 30. In addition, since the decompression of the compressed archive data is performed by the post-reception processing circuits 50 and 52, the computational load on the CPU 42 can be suppressed.

[0067] Furthermore, the microcontroller 30 includes pre-transmission processing circuits 60 and 62 that compress multiple files along with their metadata into archive data. Therefore, when the microcontroller 30 sends multiple files externally, the amount of data sent by the microcontroller 30 can be reduced compared to when the files are not compressed. Moreover, since the pre-transmission processing circuits 60 and 62 perform the compression processing of multiple files, the computational load on the CPU 42 caused by the compression process can be suppressed.

[0068] According to the embodiment described above, the following effects and benefits can be obtained. (1-1) The microcontroller 30 is equipped with multiple post-processing circuits 50 and 52. This allows it to handle multiple types of archived data in different formats.

[0069] (1-2) The microcontroller 30 includes a post-reception processing circuit 50 whose upstream side is an extraction circuit 50a, and a post-reception processing circuit 52 whose upstream side is a decompression circuit 52c. Archive data compression formats include formats that compress only multiple files, and formats that compress both multiple files and metadata. Therefore, by providing both post-reception processing circuits 50 and 52, archive data using various compression formats can be decompressed.

[0070] (1-3) The CPU 42 instructed the post-reception processing circuits 50, 52 and the DMAC 46 to perform post-reception processing of the archived data in cooperation. This reduces the computational load on the CPU 42 when performing post-reception processing of the archived data.

[0071] (1-4) The microcontroller 30 is equipped with a bypass line 54 that bypasses the post-reception processing circuits 50 and 52. This allows the CPU 42 and other components to process data other than compressed archive format data appropriately when receiving such data.

[0072] (1-5) The microcontroller 30 is equipped with multiple transmission preprocessing circuits 60 and 62. This allows it to handle multiple types of archived data in different formats. (1-6) The microcontroller 30 includes a pre-transmission processing circuit 60 whose upstream side is a compression circuit 60a, and a pre-transmission processing circuit 62 whose upstream side is an add-on circuit 62b. There are two types of compression formats for archive data: one that compresses only multiple files, and another that compresses both multiple files and metadata. Therefore, by providing both pre-transmission processing circuits 60 and 62, it is possible to generate archive data using various compression formats.

[0073] (1-7) The CPU 42 instructed the pre-transmission processing circuits 60, 62 and the DMAC 46 to perform processing for transmitting the archived data. This reduces the computational load on the CPU 42 when performing processing for transmitting the archived data.

[0074] (1-8) The microcontroller 30 is equipped with a bypass line 64 that bypasses the transmission pre-processing circuits 60 and 62. This allows the CPU 42 and other components to transmit data other than compressed archive data.

[0075] (1-9) Before the microcontroller 30 was shipped, archive data containing testing software was sent to the microcontroller 30. This allowed the microcontroller 30 to perform self-diagnosis. In particular, by sending compressed archive data containing both normal control software and testing software before product shipment, the communication time can be reduced compared to sending uncompressed data. Therefore, the time required for pre-product shipment work can be reduced.

[0076] (1-10) When the microcontroller 30 found that the image data Dp exceeded a predetermined amount, it sent compressed archive data to the server 38. Therefore, the communication load can be reduced compared to when image data is sent without compression.

[0077] <Second Embodiment> The second embodiment will be described below, focusing on the differences from the first embodiment, with reference to the drawings.

[0078] Figure 18 shows the post-reception processing circuit 52 according to this embodiment. Note that, for convenience, the same reference numerals are used for the circuits corresponding to the circuit shown in Figure 3B in Figure 18. As shown in Figure 18, the post-reception processing circuit 52 according to this embodiment includes a decoding circuit 52d. The decoding circuit 52d is a circuit that decodes the received archive data. In the post-reception processing circuit 52, the data decoded by the decoding circuit 52d is input to the decompression circuit 50c.

[0079] Figure 19 shows the transmission pre-processing circuit 62 according to this embodiment. For convenience, the same reference numerals are used in Figure 19 for circuits corresponding to the circuit shown in Figure 12B. As shown in Figure 19, the pre-transmission processing circuit 62 includes an encryption circuit 62d. The encryption circuit 62d is a circuit that encrypts the archive data compressed by the compression circuit 62a. The archive data encrypted by the encryption circuit 62d is the data output by the pre-transmission processing circuit 62.

[0080] <Correspondence> The correspondence between the matters in the above embodiment and the disclosures described in the "Means for Solving the Problems" section is as follows. Below, the correspondence is shown for each number of the perspective described in the "Means for Solving the Problems" section. [1,2,7] The software processing circuit corresponds to the CPU 42. [3] The "configuration in which a decompression circuit is provided upstream of the extraction circuit" corresponds to the configuration illustrated in Figure 3B. The "configuration in which an extraction circuit is provided upstream of the decompression circuit" corresponds to the configuration illustrated in Figure 3A. [4] The matters described in perspective 4 correspond to the post-reception processing circuits 50 and 52 that handle data of different formats. [5] The memory corresponds to the RAM 44. [6] The matters described in perspective 6 correspond to the provision of a bypass line 54 in Figure 2. [8] The "configuration in which an additional circuit is connected downstream of the compression circuit" corresponds to the configuration illustrated in Figure 12A. The "configuration in which a compression circuit is connected downstream of the additional circuit" corresponds to the configuration illustrated in Figure 12B. [9] The matters described in perspective 9 correspond to the transmission pre-processing circuits 60 and 62 which handle data in different formats.

[10] The memory corresponds to the RAM 44.

[11] The matters described in perspective 11 correspond to the provision of the bypass line 64 in Figure 2.

[12] The matters described in perspective 12 correspond to the matters described in Figures 18 and 19.

[13] The data that defines the processing to be performed by the software processing circuit corresponds to the normal control software and the inspection software.

[14] The controlled object corresponds to the motor 14. The process of generating archive data that includes data for identifying the state of the controlled object corresponds to the processing performed by the transmission pre-processing circuits 60 and 62 in accordance with the processing of S36.

[15] The program that defines the command to perform the self-diagnosis processing corresponds to the inspection software. The step of inputting archive data corresponds to the process related to the processing of S12. The step of writing to memory corresponds to the process associated with the processing of S22. The step of performing the self-diagnosis processing corresponds to the step of performing the processing of S24.

[0081] <Other Embodiments> Furthermore, this embodiment can be implemented with the following modifications. This embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0082] "Regarding the post-reception processing circuit" The post-reception processing circuits mounted on the microcontroller 30 are not limited to post-reception processing circuits 50 and 52. In other words, it is not essential that the microcontroller 30 is equipped with one circuit each of a circuit whose upstream side is an expansion circuit and a circuit whose upstream side is an extraction circuit. For example, all post-reception processing circuits mounted on the microcontroller 30 may be circuits whose upstream side is an expansion circuit. Alternatively, all post-reception processing circuits mounted on the microcontroller 30 may be circuits whose upstream side is an extraction circuit.

[0083] It is not mandatory for the microcontroller 30 to have two post-reception processing circuits. For example, the microcontroller 30 may have one post-reception processing circuit. Alternatively, for example, the microcontroller 30 may have three or more post-reception processing circuits.

[0084] In the second embodiment described above, the post-reception processing circuit 52 is shown to include a decoding circuit 52d, but the post-reception processing circuit 50 may also include a decoding circuit. Alternatively, for example, the post-reception processing circuit 50 may include a decoding circuit, while the post-reception processing circuit 52 may not include a decoding circuit.

[0085] "Regarding the pre-transmission processing circuit" The pre-transmission processing circuits mounted on the microcontroller 30 are not limited to pre-transmission processing circuits 60 and 62. In other words, it is not essential that the microcontroller 30 is equipped with one circuit each of a circuit whose upstream side is a compression circuit and a circuit whose upstream side is an additive circuit. For example, all of the pre-transmission processing circuits mounted on the microcontroller 30 may be circuits whose upstream side is a compression circuit. Also, for example, all of the post-reception processing circuits mounted on the microcontroller 30 may be circuits whose upstream side is an additive circuit.

[0086] It is not mandatory for the microcontroller 30 to have two transmission pre-processing circuits. For example, the microcontroller 30 may have one transmission pre-processing circuit. Alternatively, for example, the microcontroller 30 may have three or more transmission pre-processing circuits.

[0087] In the second embodiment described above, the transmission preprocessing circuit 62 is shown to include an encryption circuit 62d, but the transmission preprocessing circuit 60 may also include an encryption circuit. Alternatively, for example, the transmission preprocessing circuit 60 may include an encryption circuit, while the transmission preprocessing circuit 62 may not.

[0088] "Regarding bypassing the expansion and extraction circuits" Figure 2 shows an example in which the decompression method selector 56 chooses to bypass the post-reception processing circuits 50 and 52 and acquire data from outside the microcontroller 30 via the bypass line 54, but it is not limited to this. For example, as illustrated in Figure 20, the decompression method selector 56 may choose to bypass only the extraction circuit 50a of the post-reception processing circuit 50. Figure 20 shows an example in which the post-reception processing circuit 50 includes a selector 50f that selects either the bypass line 50e or the extraction circuit 50a and connects it to the decompression circuit 50c. In that case, the decompression method selector 56 only needs to operate the selector 50f.

[0089] Alternatively, as illustrated in Figure 21, the decompression method selector 56 may choose whether or not to output the data extracted by the extraction circuit 50a, bypassing only the decompression circuit 50c of the post-reception processing circuit 50. Figure 21 shows an example in which the post-reception processing circuit 50 includes a selector 50h that connects either the bypass line 50g or the decompression circuit 50c to the extraction circuit 50a. In this case, the decompression method selector 56 only needs to operate the selector 50h.

[0090] Furthermore, a post-reception processing circuit in which only one of the extraction circuit or the decompression circuit is bypassed is not limited to circuits where the extraction circuit is located upstream. "Regarding bypassing compression circuits and additional circuits" Figure 2 shows an example in which the compression method selector 66 chooses to bypass the transmission preprocessing circuits 60 and 62 and transmit data to the outside of the microcontroller 30 via the bypass line 64, but it is not limited to this. For example, as illustrated in Figure 22, the compression method selector 66 may choose to bypass only the compression circuit 60a of the transmission preprocessing circuit 60. Figure 22 shows an example in which the transmission preprocessing circuit 60 includes a selector 60f that selects either the bypass line 60e or the compression circuit 60a and connects it to the add-on circuit 60b. In that case, the compression method selector 66 only needs to operate the selector 60f.

[0091] Alternatively, as illustrated in Figure 23, the compression method selector 66 may choose whether or not to bypass the additional circuit 60b and output the data compressed by the compression circuit 60a. Figure 23 shows an example in which the transmission pre-processing circuit 60 includes a selector 60h that connects either the bypass line 60g or the additional circuit 60b to the compression circuit 60a. In this case, the compression method selector 66 only needs to operate the selector 60h.

[0092] Furthermore, a transmission pre-processing circuit in which only one of either the compression circuit or the add-on circuit is bypassed is not limited to circuits where the compression circuit is located upstream. "Regarding the exchange of archived data" The exchange of compressed archive data is not limited to transactions with external devices. For example, compressed archive data may be exchanged between ROM 72 and RAM 44. That is, if the CPU 42 can access data faster by using data stored in RAM 44 than by using data stored in ROM 72, the data stored in ROM 72 may be written to RAM 44 for use. In that case, the data stored in ROM 72 should be written to RAM 44 as compressed archive data, in cooperation with the post-reception processing circuits 50, 52 and DMAC 46.

[0093] "Regarding the movement of data within microcontroller 30" • In the above embodiment, an example was shown in which the processing related to the movement of data within the microcontroller 30 is performed using the DMAC 46, but this is not limited to this. For example, the extraction circuits 50a and 52a may write data to the RAM 44 without using the DMAC 46. For example, the movement of data may be performed via the CPU 42. In that case, for example, dedicated input / output instructions may be used to read or write the data. Alternatively, for example, if there are no dedicated instructions, memory addresses may be assigned to the I / O registers of the data destination and source, and the CPU 42 may perform data reading and writing using load / store instructions for the I / O registers.

[0094] "Regarding data used to identify the state of the controlled object." In the above embodiment, image data Dp was used as an example of data for identifying the state of the motor 14 as the controlled object, but the embodiment is not limited to this. For example, the data for identifying the state may include the detected value of a sensor that detects vibration of the compressor 12. Alternatively, the data for identifying the state may include at least one of the rotational speed, current, and voltage of the motor 14 that drives the compressor 12.

[0095] "Regarding the controlled object" It is not mandatory that the microcontroller 30 controls the motor 14 that drives the compressor 12. For example, the microcontroller 30 may control a motor that drives a fan.

[0096] "Regarding the data that defines the processing performed by the software processing circuit." The data that defines the processing performed by the software processing circuit is not limited to control software and test software.

[0097] "Regarding software processing circuits" The software processing circuit does not necessarily have to be a CPU. The software processing circuit may include, for example, a GPU.

[0098] Although embodiments have been described above, it should be understood that various modifications to the form and details are possible without departing from the spirit and scope of the claims. [Explanation of Symbols]

[0099] 10...Air conditioner 12... Compressor 12a... Rotation axis 14…motor 14a... Rotation axis 16…Inverter 18… Converter 20…grid power supply 30... Microcontroller 34...Factory terminals 36…Network 38… Server

Claims

1. A microcontroller that exchanges archived data with the outside world, The aforementioned archive data includes a plurality of files and metadata which is data indicating additional information about the plurality of files, and at least the plurality of files are compressed data. It comprises a software processing circuit (42) and a hardware processing circuit, The hardware processing circuit includes at least one of two circuits: a post-reception processing circuit (50, 52) and a pre-transmission processing circuit (60, 62). The post-reception processing circuits (50, 52) include decompression circuits (50c, 52c) for decompressing the plurality of files contained in the archive data, and extraction circuits (50a, 52a) for extracting the plurality of files and metadata contained in the archive data. The transmission preprocessing circuits (60, 62) include at least compression circuits (60a, 62a) for compressing the plurality of files, and addition circuits (60b, 62b) for adding the metadata, The software processing circuit (42) is a microcontroller configured to instruct the hardware processing circuit to process the archived data.

2. The microcontroller according to claim 1, wherein the hardware processing circuit includes the post-reception processing circuits (50, 52).

3. The microcontroller according to claim 2, wherein the post-reception processing circuits (50, 52) have both configurations: one in which the decompression circuits (50c, 52c) are provided upstream of the extraction circuits (50a, 52a) when the side from which the archive data is input from outside the microcontroller is the upstream side; and another in which the extraction circuits (50a, 52a) are provided upstream of the decompression circuits (50c, 52c).

4. The microcontroller according to claim 2, wherein the post-reception processing circuits (50, 52) include multiple types of circuits for at least one of the two circuits, the decompression circuits (50c, 52c) and the extraction circuits (50a, 52a), in order to handle multiple types of archived data of different formats.

5. The system includes memory (44) and a direct memory access controller (46), The microcontroller according to claim 2, wherein the post-reception processing circuits (50, 52) are configured to decompress the archived data and store the plurality of files and the metadata in the memory (44) in cooperation with the direct memory access controller (46) in response to the instructions from the software processing circuit (42).

6. The microcontroller according to claim 2, wherein the hardware processing circuit includes a circuit that selects to acquire external data by bypassing at least one of the expansion circuits (50c, 52c) and the extraction circuits (50a, 52a).

7. The microcontroller according to claim 1, wherein the hardware processing circuit includes the pre-transmission processing circuits (60, 62).

8. The microcontroller according to claim 7, wherein the pre-transmission processing circuits (60, 62) have both configurations: one in which the additional circuits (60b, 62b) are connected downstream of the compression circuits (60a, 62a), and another in which the compression circuits (60a, 62a) are connected downstream of the additional circuits (60b, 62b), when the side transmitting the archived data from the microcontroller to the outside is the downstream side.

9. The microcontroller according to claim 7, wherein the pre-transmission processing circuits (60, 62) include multiple types of circuits for at least one of the two, the compression circuits (60a, 62a) and the additional circuits (60b, 62b), in order to handle multiple types of archive data of different formats.

10. The system includes memory (44) and a direct memory access controller (46), The microcontroller according to claim 7, wherein the pre-transmission processing circuits (60, 62) are configured to, in cooperation with the direct memory access controller (46), in response to the instructions from the software processing circuit (42), to generate a single archive data from the plurality of files stored in the memory (44) and the metadata, and transfer it to the outside of the microcontroller.

11. The microcontroller according to claim 7, wherein the hardware processing circuit includes a circuit that selects to transfer data to the outside by bypassing at least one of the compression circuit (60a, 62a) and the addition circuit (60b, 62b).

12. The post-reception processing circuits (50, 52) include a decoding circuit (50d) for decoding the archived data. The microcontroller according to claim 1, wherein the pre-transmission processing circuits (60, 62) include an encryption circuit (62d) for encrypting the archived data.

13. The archived data includes data that defines the processing to be performed by the software processing circuit (42), The microcontroller according to claim 2, wherein the post-reception processing circuits (50, 52) are configured to extract the data from the archived data and provide it to the software processing circuit (42).

14. The software processing circuit (42) is configured to perform a process for controlling the controlled object and a process for generating data to identify the state of the controlled object. The microcontroller according to claim 7, wherein the pre-transmission processing circuits (60, 62) are configured to generate the archive data which includes data for identifying the state of the controlled object.

15. The microcontroller according to claim 2 includes a memory (44), The software processing circuit (42) is configured to execute a process for controlling the control amount of the controlled object, The archived data includes a program that defines a command for the software processing circuit (42) to perform a self-diagnostic process of the microcontroller. The process of inputting the archive data from outside the microcontroller, The process of writing the program to the memory (44), A method for self-diagnosing a microcontroller, comprising the step of performing a self-diagnosis process of the microcontroller by having the software processing circuit (42) execute the program written to the memory (44).

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