Active matrix substrate and display device

Abstract

In an active matrix substrate equipped with oxide semiconductor TFTs with a top-gate or double-gate structure as ESD protection elements, this invention avoids problems caused by excessively high current driving capability of the ESD protection elements. [Solution] The active matrix substrate comprises a plurality of TFTs and a plurality of ESD protection elements arranged within the non-display area, each electrically connected to a corresponding wiring. At least some of the plurality of TFTs have a first oxide semiconductor layer. Each ESD protection element is formed in a separate layer from the first oxide semiconductor layer and has a second oxide semiconductor layer having a lower mobility than the first oxide semiconductor layer.

Description

Technical Field

[0005] ,

[0001] The present invention relates to an active matrix substrate, and particularly to an active matrix substrate provided with an oxide semiconductor TFT. The present invention also relates to a display device provided with such an active matrix substrate.

Background Art

[0002] An active matrix substrate used in a liquid crystal display device, an organic electroluminescence (EL) display device, etc. has a display area including a plurality of pixel regions and a region other than the display area (non-display area). In the display area, a thin film transistor (Thin Film Transistor; hereinafter "TFT") is provided as a switching element for each pixel region. Conventionally, as such a TFT, a TFT having an amorphous silicon layer as an active layer (hereinafter "amorphous silicon TFT") or a TFT having a polycrystalline silicon layer as an active layer (hereinafter "polycrystalline silicon TFT") has been widely used.

[0003] In recent years, it has been proposed to use an oxide semiconductor as a material for the active layer of a TFT. A TFT having an oxide semiconductor layer as an active layer is hereinafter referred to as an "oxide semiconductor TFT". Since an oxide semiconductor has a higher mobility than amorphous silicon, an oxide semiconductor TFT can operate at a higher speed than an amorphous silicon TFT.

[0004] The structure of a TFT is roughly classified into a bottom gate structure and a top gate structure. Currently, a bottom gate structure is often adopted for an oxide semiconductor TFT, but the use of a top gate structure has also been proposed (for example, Patent Document 1). In the top gate structure, the gate insulating layer can be made thin, so that a high current driving ability can be obtained. Recently, a double gate structure in which gate electrodes are provided above and below the active layer has also been proposed (for example, Patent Document 2). <0000 (017> In some cases, peripheral circuits, including TFTs, are monolithically (integrally) formed in the non-display area of ​​an active matrix substrate. For example, forming the drive circuit monolithically can reduce the size of the non-display area and lower costs by simplifying the mounting process. For instance, gate drive circuits are monolithically formed in the non-display area. In devices with a high demand for narrow bezels, such as smartphones, demultiplexer circuits, also known as Source Shared Driving (SSD) circuits, may also be monolithically formed.

[0006] In this specification, the TFTs (or, in the case of an active matrix substrate used in an organic EL display device, the multiple TFTs that constitute the pixel circuit) placed in each pixel of the display area are referred to as "pixel TFTs." Furthermore, the TFTs that constitute the peripheral circuits provided in the non-display area are referred to as "circuit TFTs."

[0007] The manufacturing process for active matrix substrates includes steps that are prone to generating static electricity. Therefore, active matrix substrates are sometimes provided with protective elements (referred to as "ESD protection elements" in this specification) to protect pixel TFTs, circuit TFTs, etc., from electrostatic discharge (ESD). Patent Document 3 discloses an active matrix substrate in which diode-connected oxide semiconductor TFTs are provided as ESD protection elements.

[0008] The ESD protection element described in Patent Document 3 includes an oxide semiconductor layer formed in the same layer as the oxide semiconductor layer of the pixel TFT and has a bottom gate structure. The oxide semiconductor layer of this ESD protection element has offset regions between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, which do not overlap with any of the gate electrode, source electrode, or drain electrode in a plan view. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2015-109315 [Patent Document 2] Patent No. 6486174 [Patent Document 3] Patent No. 5284553 [Overview of the project] [Problems that the invention aims to solve]

[0010] When oxide semiconductor TFTs are used as ESD protection elements, the high mobility of the oxide semiconductor layer can lead to problems such as excessive current flowing through the ESD protection element during operation, causing damage to the element, or a decrease in the voltage of various signals flowing through the wiring due to leakage current from the ESD protection element. In the active matrix substrate described in Patent Document 3, the oxide semiconductor layer of the ESD protection element has an offset region, thereby suppressing the above-mentioned problems.

[0011] However, when using an oxide semiconductor TFT with a top gate structure as an ESD protection element, even if an offset region as disclosed in Patent Document 3 is provided in the oxide semiconductor layer, it is difficult to suppress malfunctions for the following reasons.

[0012] First, in a top-gate oxide semiconductor TFT, the portion of the oxide semiconductor layer corresponding to the aforementioned offset region is a low-resistance (conductor) region, and therefore has little effect on suppressing current. Also, generally, a thinner gate insulating layer is used in a top-gate structure than in a bottom-gate structure, so a top-gate oxide semiconductor TFT has higher current driving capability than a bottom-gate oxide semiconductor TFT.

[0013] For these reasons, when using top-gate oxide semiconductor TFTs as ESD protection elements, it is difficult to suppress problems caused by the high mobility of the oxide semiconductor layer. Furthermore, in recent years, the development of oxide semiconductors with even higher mobility has progressed, and when such oxide semiconductors are used, the current driving capability of the ESD protection element becomes even higher, making it even more difficult to suppress the aforementioned problems.

[0014] Even when using a double-gate oxide semiconductor TFT as an ESD protection element, it is difficult to suppress malfunctions caused by the high mobility of the oxide semiconductor layer for the same reasons as in the case of a top-gate structure.

[0015] Embodiments of the present invention have been made in view of the above-mentioned problems, and their purpose is to avoid problems caused by excessively high current driving capability of an ESD protection element in an active matrix substrate equipped with an oxide semiconductor TFT having a top gate structure or a double gate structure as an ESD protection element. [Means for solving the problem]

[0016] This specification discloses active matrix substrates and display devices as described in the following sections.

[0017] [Item 1] It has a display area that includes multiple pixel regions and a non-display area located around the display area, circuit board and A plurality of wirings provided on the substrate, the plurality of wirings including a plurality of gate wirings and a plurality of source wirings, A plurality of TFTs supported on the substrate, the plurality of TFTs including a plurality of pixel TFTs arranged in the display area and a plurality of circuit TFTs arranged in the non-display area, A plurality of ESD protection elements are arranged within the non-display area, each electrically connected to a corresponding wire among the plurality of wires, An active matrix substrate comprising, At least some of the plurality of TFTs include a first oxide semiconductor layer including a first channel region, a first source contact region and a first drain contact region located on both sides of the first channel region, a first gate insulating layer provided at least on the first channel region, a first gate electrode facing the first channel region through the first gate insulating layer, a first source electrode and a first drain electrode electrically connected to the first source contact region and the first drain contact region, respectively, and have Each of the plurality of ESD protection elements is a second oxide semiconductor layer including a second channel region, a second source contact region and a second drain contact region located on both sides of the second channel region, the second oxide semiconductor layer being formed in a layer different from the first oxide semiconductor layer and having a mobility lower than that of the first oxide semiconductor layer, a second gate insulating layer provided at least on the second channel region, a second gate electrode facing the second channel region through the second gate insulating layer, a second source electrode and a second drain electrode electrically connected to the second source contact region and the second drain contact region, respectively, and have an active matrix substrate.

[0018] [Item 2] The active matrix substrate according to item 1, wherein the second gate insulating layer includes a first layer and a second layer provided on the first layer, the second layer being formed in the same layer as the first gate insulating layer.

[0019] [Item 3] The active matrix substrate further includes an interlayer insulating layer covering the second oxide semiconductor layer, the second gate insulating layer and the second gate electrode. A source contact hole that exposes a portion of the second source contact region and a drain contact hole that exposes a portion of the second drain contact region are formed in at least the interlayer insulating layer. The active matrix substrate according to item 2, wherein the first layer of the second gate insulating layer covers the portion of the second source contact region that does not overlap with the source contact hole and the portion of the second drain contact region that does not overlap with the drain contact hole.

[0020] [Item 4] The active matrix substrate according to item 3, wherein the second layer of the second gate insulating layer covers the portion of the second source contact region that does not overlap with the source contact hole and the portion of the second drain contact region that does not overlap with the drain contact hole.

[0021] [Item 5] An active matrix substrate according to any one of items 1 to 4, wherein, in a plan view, the protrusion width of the second gate insulating layer from the second gate electrode toward the second source contact region is greater than the protrusion width of the first gate insulating layer toward the first source contact region, and the protrusion width of the second gate insulating layer from the second gate electrode toward the second drain contact region is greater than the protrusion width of the first gate insulating layer toward the first drain contact region.

[0022] [Item 6] The aforementioned TFTs, at least some of them, A third gate electrode located below the first oxide semiconductor layer and facing at least the first channel region, A third gate insulating layer located between the first oxide semiconductor layer and the third gate electrode, An active matrix substrate according to any one of items 1 to 5, further comprising the above.

[0023] [Item 7] In a plan view, the third gate electrode protrudes from the first gate electrode toward the first source contact region and the first drain contact region, respectively, in the active matrix substrate according to item 6.

[0024] [Item 8] Each of the aforementioned plurality of ESD protection elements is A fourth gate electrode located below the second oxide semiconductor layer and facing at least the second channel region, A fourth gate insulating layer located between the second oxide semiconductor layer and the fourth gate electrode, An active matrix substrate according to any one of items 1 to 7, further comprising:

[0025] [Item 9] In a plan view, the fourth gate electrode protrudes from the second gate electrode toward the second source contact region and the second drain contact region, respectively, in the active matrix substrate according to item 8.

[0026] [Item 10] An active matrix substrate according to any one of items 1 to 9, wherein the second gate electrode and the second source electrode are electrically connected to each other.

[0027] [Item 11] The second gate electrode is formed in the same layer as the first gate electrode, The active matrix substrate according to any one of items 1 to 10, wherein the second source electrode and the second drain electrode are formed in the same layer as the first source electrode.

[0028] [Item 12] An active matrix substrate according to any one of items 1 to 11, wherein at least a portion of the plurality of pixel TFTs includes a third oxide semiconductor layer formed in the same layer as the second oxide semiconductor layer.

[0029] [Item 13] The active matrix substrate according to item 12, wherein each of the plurality of pixel TFTs includes the third oxide semiconductor layer.

[0030] [Item 14] A portion of the plurality of pixel TFTs includes the third oxide semiconductor layer, The active matrix substrate according to item 12, wherein the other portion of the plurality of pixel TFTs includes the first oxide semiconductor layer.

[0031] [Item 15] An active matrix substrate according to any one of items 1 to 14, wherein at least a portion of the plurality of circuit TFTs includes the first oxide semiconductor layer.

[0032] [Item 16] The first oxide semiconductor layer and the second oxide semiconductor layer each contain In and / or Sn, An active matrix substrate according to any one of items 1 to 15, wherein the sum of the atomic ratios of In and Sn to all metal elements in the second oxide semiconductor layer is less than the sum of the atomic ratios of In and Sn to all metal elements in the first oxide semiconductor layer.

[0033] [Item 17] The active matrix substrate according to any one of items 1 to 15, wherein both the first oxide semiconductor layer and the second oxide semiconductor layer contain an In-Ga-Zn-O semiconductor, and the atomic ratio of In to all metal elements in the second oxide semiconductor layer is lower than the atomic ratio of In to all metal elements in the first oxide semiconductor layer.

[0034] [Item 18] A display device comprising an active matrix substrate as described in any of items 1 to 17.

[0035] [Item 19] A liquid crystal display device, as described in item 18.

[0036] [Item 20] The display device described in item 18, which is an organic EL display device. [Effects of the Invention]

[0037] According to embodiments of the present invention, in an active matrix substrate equipped with an oxide semiconductor TFT with a top gate structure or a double gate structure as an ESD protection element, it is possible to avoid problems caused by the current driving capability of the ESD protection element being too high. [Brief explanation of the drawing]

[0038] [Figure 1] This is a schematic diagram showing an example of the planar structure of an active matrix substrate 100 according to an embodiment of the present invention, and shows the case where the active matrix substrate 100 is for a liquid crystal display device. [Figure 2] This is the equivalent circuit diagram of the pixel region P. [Figure 3] This is a schematic diagram showing an example of the planar structure of the active matrix substrate 100, illustrating the case where the active matrix substrate 100 is for use in an organic EL display device. [Figure 4] This is the equivalent circuit diagram of the pixel region P. [Figure 5] This is a schematic cross-sectional view showing a portion of the active matrix substrate 100. [Figure 6] This is a schematic plan view showing a portion of the active matrix substrate 100. [Figure 7A] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7B] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7C] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7D] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7E] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7F] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7G] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7H] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7I] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7J] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 8] This is a schematic cross-sectional view showing a part of the active matrix substrate 200A according to an embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view showing a part of the active matrix substrate 200B according to an embodiment of the present invention. [Figure 10] This is a schematic cross-sectional view showing a part of the active matrix substrate 300 according to an embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a part of the active matrix substrate 400A according to an embodiment of the present invention. [Figure 12] This is a schematic cross-sectional view showing a part of the active matrix substrate 400B according to an embodiment of the present invention. [Figure 13] This is a schematic cross-sectional view showing a part of the active matrix substrate 400C according to an embodiment of the present invention. [Figure 14A] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 400A. [Figure 14B] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 400A. [Figure 14C] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 400A. [Figure 14D] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 400A. [Figure 14E]This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 400A. [Figure 15] This is a schematic cross-sectional view showing a part of the active matrix substrate 500A according to an embodiment of the present invention. [Figure 16] This is a schematic cross-sectional view showing a part of the active matrix substrate 500B according to an embodiment of the present invention. [Figure 17] This is a schematic cross-sectional view showing a part of the active matrix substrate 500C according to an embodiment of the present invention. [Figure 18A] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 500A. [Figure 18B] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 500A. [Figure 18C] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 500A. [Figure 18D] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 500A. [Figure 18E] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 500A. [Figure 19] This is a cross-sectional view showing the process of patterning the upper gate conductive film CF, insulating film IF2 and IF1 when manufacturing the active matrix substrate 100. [Figure 20] This is a cross-sectional view showing the process of patterning the upper gate conductive film CF and insulating film IF2 when manufacturing the active matrix substrate 400A. [Figure 21] This is a cross-sectional view showing the process of patterning the conductive film CF for the upper gate when manufacturing the active matrix substrate 500A. [Modes for carrying out the invention]

[0039] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

[0040] [Embodiment 1] Referring to Figure 1, an example of the schematic structure of the active matrix substrate 100 in this embodiment will be described. Figure 1 is a schematic diagram showing an example of the planar structure of the active matrix substrate 100, and shows the case where the active matrix substrate 100 is for a liquid crystal display device. As shown in Figure 1, the active matrix substrate 100 has a display area DR and a non-display area FR.

[0041] The display area DR includes multiple pixel areas P arranged in a matrix. Each pixel area P corresponds to a pixel on the display device.

[0042] The non-display area (FR) is located around the display area (DR). The non-display area (FR) is sometimes called the "peripheral area" or "frame area."

[0043] The components of the active matrix substrate 100 are supported by the substrate 1. The substrate 1 is, for example, a glass substrate.

[0044] Multiple wirings, including multiple gate wirings GL and multiple source wirings SL, are provided on the substrate 1. Each of the multiple gate wirings GL extends along the row direction. Each of the multiple source wirings SL extends along the column direction.

[0045] Typically, the region enclosed by two adjacent gate traces GL and two adjacent source traces SL is the pixel region P. Figure 2 shows an example of the equivalent circuit of a pixel region P. Each pixel region P includes a pixel TFT 10 and a pixel electrode PE, as shown in Figure 2.

[0046] Each pixel TFT 10 is supported on a substrate 1 and has a gate electrode, source electrode, drain electrode, and oxide semiconductor layer.

[0047] The gate electrode and source electrode of the pixel TFT10 are electrically connected to the corresponding gate wiring GL and source wiring SL, respectively. The drain electrode of the pixel TFT10 is also electrically connected to the pixel electrode PE.

[0048] In the non-display area FR, a gate driver (gate wiring drive circuit) GD for driving the gate wiring GL and a source driver (source wiring drive circuit: not shown) for driving the source wiring SL are arranged. In this embodiment, the gate driver GD is a GDM circuit formed monolithically on the substrate 1. In the illustrated example, gate drivers GD are arranged on both the left and right sides of the non-display area DR, but a gate driver GD may be arranged on only one side. Each of the multiple output terminals of the gate driver GD is connected to each of the gate wirings GL. In this case, the source driver is mounted on the substrate 1 (e.g., COG mounting). Each of the multiple output terminals of the source driver is connected to each of the source wirings SL.

[0049] Although not shown in Figure 1, multiple circuit TFTs 20 (see Figure 5, etc., described later) are arranged in the non-display region FR. These multiple circuit TFTs 20 are supported by the substrate 1. When a GDM circuit is formed in the non-display region FR as illustrated, the multiple circuit TFTs 20 include the circuit TFTs 20 that constitute the GDM circuit.

[0050] Furthermore, in the non-display area FR, multiple wirings (hereinafter referred to as "GDM wirings") ML are provided on the substrate 1 for supplying signals to the gate driver (GDM circuit) GD. The multiple GDM wirings ML include, for example, multiple clock signal lines that supply the clock signal (CK), low-potential wiring that supplies the power supply voltage (VSS) on the low-potential side of the gate signal, start pulse wiring that provides a start signal (GSP) to the starting stage of the shift register, and reset wiring for resetting a specific node in the gate driver (GDM circuit) GD to a constant potential. In the illustrated example, the non-display area FR is also provided with common wiring CL for supplying a common voltage, surrounding the display area FR.

[0051] The active matrix substrate 100 further comprises a plurality of ESD protection elements 30 arranged within a non-display area FR. Each of the plurality of ESD protection elements 30 is electrically connected to the corresponding wiring. Each ESD protection element 30 is a diode-connected oxide semiconductor TFT, as described later, and can function as a diode element. Here, the plurality of ESD protection elements 30 include an ESD protection element 30A electrically connected to each gate wiring GL and common wiring CL, an ESD protection element 30B electrically connected to each source wiring SL and common wiring CL, and an ESD protection element 30C electrically connected to each GDM wiring ML and common wiring CL.

[0052] In the illustrated example, each gate wiring GL is provided with two ESD protection elements 30A, one on the left and one on the right side of the non-display area FR. The two ESD protection elements 30A are connected in parallel between the gate wiring GL and the common wiring CL, with their forward directions opposite to each other. Additionally, each source wiring SL is provided with two ESD protection elements 30B. The two ESD protection elements 30B are connected in parallel between the source wiring SL and the common wiring CL, with their forward directions opposite to each other. Similarly, each GDM wiring ML is provided with two ESD protection elements 30C. The two ESD protection elements 30C are connected in parallel between the GDM wiring ML and the common wiring CL, with their forward directions opposite to each other. Two ESD protection elements 30 connected in parallel between two wirings with their forward directions opposite to each other are sometimes collectively referred to as an "ESD protection circuit".

[0053] In the active matrix substrate 100, if static electricity enters any of the wirings from the outside, the gate of the ESD protection element 30 electrically connected to that wiring opens, and the charge diffuses sequentially to the other wirings via the common wiring CL, thereby suppressing damage to the pixel TFT 10 and circuit TFT 20 due to static electricity.

[0054] Next, with reference to Figure 3, another example of the schematic structure of the active matrix substrate 100 in this embodiment will be described. Figure 3 is a schematic diagram showing an example of the planar structure of the active matrix substrate 100, and shows the case where the active matrix substrate 100 is for an organic EL device. In the following, the explanation will focus on the differences between the structure exemplified in Figure 3 and the structure exemplified in Figure 1.

[0055] In the example shown in Figure 3, multiple gate wirings GL and multiple source wirings SL are provided on the substrate 1, in addition to multiple light emission control wirings EmL. Each of the multiple light emission control wirings EmL extends along the row direction.

[0056] Figure 4 shows an example of the equivalent circuit of a pixel region P in the active matrix substrate 100 shown in Figure 3. Each pixel region P includes three pixel TFTs 10, a capacitive element (holding capacitor) 41, and an OLED (organic light-emitting diode) 42, as shown in Figure 4.

[0057] The three pixel TFT10 are specifically a driving pixel TFT10A, a selection pixel TFT10B, and a light emission control pixel TFT10C.

[0058] The gate electrode of the selection pixel TFT10B is electrically connected to the gate wiring GL. One of the source electrode and drain electrode of the selection pixel TFT10B is electrically connected to the source wiring SL, and the other is electrically connected to the gate electrode of the driving pixel TFT10A.

[0059] One of the source and drain electrodes of the driving pixel TFT10A is electrically connected to the current supply line CSL, and the other is electrically connected to one of the source and drain electrodes of the light emission control pixel TFT10C.

[0060] The source electrode and the other drain electrode of the light emission control pixel TFT10C are electrically connected to the OLED42. The gate electrode of the light emission control pixel TFT10C is electrically connected to the light emission control wiring EmL.

[0061] One of the pair of electrodes constituting the capacitive element 41 is electrically connected to the gate electrode of the driving pixel TFT 10A, and the other is electrically connected to the current supply line CSL.

[0062] In the non-display area FR of the active matrix substrate 100 shown in Figure 3, an emission driver (light emission control wiring drive circuit) ED is arranged in addition to the gate driver GD and source driver (not shown). Each of the multiple output terminals of the emission driver ED is connected to each of the light emission control wirings EmL. Here, the emission driver ED is formed monolithically on the substrate 1. In addition, in the display area FR, multiple wirings ML' (hereinafter referred to as "EDM wiring") for supplying signals to the emission driver ED are provided on the substrate 1.

[0063] The multiple ESD protection elements 30 arranged within the non-display area FR include an ESD protection element 30A electrically connected to each gate wiring GL and common wiring CL, an ESD protection element 30B electrically connected to each source wiring SL and common wiring CL, an ESD protection element 30C electrically connected to each GDM wiring ML and common wiring CL, and an ESD protection element 30D electrically connected to each EDM wiring ML' and common wiring CL.

[0064] In the active matrix substrate 100 illustrated in Figure 3, the ESD protection element 30 can suppress damage to the pixel TFT 10 and circuit TFT 20 due to static electricity.

[0065] The structure of the oxide semiconductor TFTs (the pixel TFT 10, circuit TFT 20, and ESD protection element 30 described above) in the active matrix substrate 100 will be explained with reference to Figures 5 and 6. The oxide semiconductor TFTs in the active matrix substrate 100 have either a top-gate structure or a double-gate structure. In the following explanation, the double-gate structure will be used as an example. Figures 5 and 6 are schematic cross-sectional and plan views, respectively, showing a part of the active matrix substrate 100. In Figures 5 and 6, the structure of the pixel TFT 10 and circuit TFT 20 is shown on the right side of the figure, and the structure of the ESD protection element 30 is shown on the left side of the figure.

[0066] In this embodiment, the pixel TFT 10 and the circuit TFT 20 have substantially the same structure. The pixel TFT 10 and the circuit TFT 20 each have an oxide semiconductor layer 2, an upper gate electrode 3, a lower gate electrode 4, a source electrode 5, and a drain electrode 6. Furthermore, the pixel TFT 10 and the circuit TFT 20 each have an upper gate insulating layer 7 and a lower gate insulating layer 8.

[0067] The oxide semiconductor layer 2 includes a channel region 2c and a source contact region 2s and a drain contact region 2d located on either side of the channel region 2c. The source contact region 2s and the drain contact region 2d may be low-resistance regions with lower resistivity than the channel region 2c. Such low-resistance regions can be formed, for example, by performing a resistance reduction treatment on the oxide semiconductor layer 2 using the upper gate electrode 3 as a mask.

[0068] The upper gate electrode 3 is located above the oxide semiconductor layer 2. The upper gate electrode 3 faces the channel region 2c via the upper gate insulating layer 7. The upper gate electrode 3 of the pixel TFT 10 is electrically connected to the corresponding gate wiring GL.

[0069] The upper gate insulating layer 7 is positioned between the oxide semiconductor layer 2 and the upper gate electrode 3. The upper gate insulating layer 7 is provided at least on the channel region 2c.

[0070] The lower gate electrode 4 is located between the substrate 1 and the oxide semiconductor layer 2. In other words, the lower gate electrode 4 is located below the oxide semiconductor layer 2 and is positioned on the opposite side of the oxide semiconductor layer 2 from the upper gate electrode 3.

[0071] The lower gate insulating layer 8 is provided so as to cover the lower gate electrode 4 and is positioned between the lower gate electrode 4 and the oxide semiconductor layer 2. The lower gate insulating layer 8 includes a first layer 8a and a second layer 8b provided on the first layer 8a.

[0072] The source electrode 5 is electrically connected to the source contact region 2s of the oxide semiconductor layer 2. The drain electrode 6 is electrically connected to the drain contact region 2d of the oxide semiconductor layer 2. The source electrode 5 of the pixel TFT 10 is electrically connected to the corresponding source wiring SL.

[0073] In the illustrated example, an interlayer insulating layer 9 is provided to cover the oxide semiconductor layer 2, the upper gate insulating layer 7, and the upper gate electrode 3, and the source electrode 5 and drain electrode 6 are placed on the interlayer insulating layer 9.

[0074] The interlayer insulating layer 9 has a source contact hole CHs1 that exposes a portion of the source contact region 2s of the oxide semiconductor layer 2, and a drain contact hole CHd1 that exposes a portion of the drain contact region 2d of the oxide semiconductor layer 2. The source electrode 5 is connected to the source contact region 2s through the source contact hole CHs1. The drain electrode 6 is connected to the drain contact region 2d through the drain contact hole CHd1.

[0075] In the illustrated example, the width of the lower gate electrode 4 along the channel length direction is greater than the width of the upper gate electrode 3 along the channel length direction, and in a plan view, the lower gate electrode 4 protrudes from the upper gate electrode 3 on both sides (source contact region 2s side and drain contact region 2d side).

[0076] Furthermore, in the illustrated example, the upper gate insulating layer 7 is patterned such that it does not at least partially cover the portion of the source contact region 2s that does not overlap with the source contact holes CHs, and the portion of the drain contact region 2d that does not overlap with the drain contact holes CHd. In addition, in a plan view, the upper gate insulating layer 7 protrudes slightly from the upper gate electrode 3 towards the source contact region 2s and the drain contact region 2d. Hereinafter, the protrusion width W1 of the upper gate insulating layer 7 from the upper gate electrode 3 towards the source contact region 2s will be referred to as the "first protrusion width," and the protrusion width W2 of the upper gate insulating layer 7 from the upper gate electrode 3 towards the drain contact region 2d will be referred to as the "second protrusion width."

[0077] The ESD protection element 30 has an oxide semiconductor layer 32, an upper gate electrode 33, a lower gate electrode 34, a source electrode 35, and a drain electrode 36. The ESD protection element 30 further has an upper gate insulating layer 37 and a lower gate insulating layer 38.

[0078] The oxide semiconductor layer 32 includes a channel region 32c and a source contact region 32s and a drain contact region 32d located on either side of the channel region 32c. The source contact region 32s and the drain contact region 32d may be low-resistance regions with lower resistivity than the channel region 32c. Such low-resistance regions can be formed, for example, by performing a resistance reduction treatment on the oxide semiconductor layer 32 using the upper gate electrode 33 as a mask.

[0079] The upper gate electrode 33 is located above the oxide semiconductor layer 32. The upper gate electrode 33 faces the channel region 32c via the upper gate insulating layer 37. The upper gate electrode 33 is formed in the same layer as the upper gate electrode 3 of the pixel TFT 10 and the circuit TFT 20.

[0080] The upper gate insulating layer 37 is located between the oxide semiconductor layer 32 and the upper gate electrode 33. The upper gate insulating layer 37 is provided at least on the channel region 32c.

[0081] The lower gate electrode 34 is positioned between the substrate 1 and the oxide semiconductor layer 32. That is, the lower gate electrode 34 is located below the oxide semiconductor layer 32 and is positioned on the opposite side of the oxide semiconductor layer 32 from the upper gate electrode 33. There are several possible electrical connection configurations for the lower gate electrode 34. These will be described in detail later.

[0082] The lower gate insulating layer 38 is provided so as to cover the lower gate electrode 34 and is positioned between the lower gate electrode 34 and the oxide semiconductor layer 32.

[0083] The source electrode 35 is electrically connected to the source contact region 32s of the oxide semiconductor layer 32. The drain electrode 36 is electrically connected to the drain contact region 32d of the oxide semiconductor layer 32. The source electrode 35 and the drain electrode 36 are formed in the same layer as the source electrode 5 of the pixel TFT 10 and the circuit TFT 20.

[0084] The oxide semiconductor layer 32, the upper gate insulating layer 37, and the upper gate electrode 33 are covered by an interlayer insulating layer 9, and the source electrode 35 and the drain electrode 36 are placed on the interlayer insulating layer 9.

[0085] The interlayer insulating layer 9 has a source contact hole CHs2 that exposes a portion of the source contact region 32s of the oxide semiconductor layer 32, and a drain contact hole CHd2 that exposes a portion of the drain contact region 32d of the oxide semiconductor layer 32. The source electrode 35 is connected to the source contact region 32s through the source contact hole CHs2. The drain electrode 36 is connected to the drain contact region 32d through the drain contact hole CHd2.

[0086] The upper gate electrode 33 and source electrode 35 of the ESD protection element 30 are electrically connected to each other. In other words, the ESD protection element 30 is diode-connected.

[0087] In the illustrated example, the width of the lower gate electrode 34 along the channel length direction is greater than the width of the upper gate electrode 33 along the channel length direction, and in a plan view, the lower gate electrode 34 protrudes from the upper gate electrode 33 on both sides (source contact region 32s side and drain contact region 32d side).

[0088] Furthermore, in the illustrated example, the upper gate insulating layer 37 is patterned such that it does not at least partially cover the portion of the source contact region 32s that does not overlap with the source contact hole CHs2 and the portion of the drain contact region 32d that does not overlap with the drain contact hole CHd2. In addition, in a plan view, the upper gate insulating layer 37 protrudes slightly from the upper gate electrode 33 toward the source contact region 32s and the drain contact region 32d. The first protrusion width W1 of the upper gate insulating layer 37 of the ESD protection element 30 is greater than the first protrusion width W1 of the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20, and the second protrusion width W2 of the upper gate insulating layer 37 of the ESD protection element 30 is greater than the second protrusion width W2 of the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20.

[0089] The oxide semiconductor layer 32 of the ESD protection element 30 is formed as a separate layer from the oxide semiconductor layer 2 of the pixel TFT 10 and circuit TFT 20. Furthermore, the oxide semiconductor layer 32 of the ESD protection element 30 has a lower mobility than the oxide semiconductor layer 2 of the pixel TFT 10 and circuit TFT 20.

[0090] The upper gate insulating layer 37 of the ESD protection element 30 includes a first layer 37a and a second layer 37b provided on the first layer 37a. The first layer 37a is formed in the same layer as the second layer 8b of the lower gate insulating layer 8 of the pixel TFT 10 and circuit TFT 20. The second layer 37b is formed in the same layer as the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20. The lower gate insulating layer 38 of the ESD protection element 30 is formed in the same layer as the first layer 8a of the lower gate insulating layer 8 of the pixel TFT 10 and circuit TFT 20.

[0091] As described above, in the active matrix substrate 100 of this embodiment, the oxide semiconductor layer 32 of the ESD protection element 30 is formed in a separate layer from the oxide semiconductor layer 2 of the pixel TFT 10 and circuit TFT 20, and has a lower mobility than the oxide semiconductor layer 2 of the pixel TFT 10 and circuit TFT 20. Therefore, when the ESD protection element 30 is operating, it is prevented from being damaged by too much current flowing through the ESD protection element 30, and the voltage of various signals flowing through the wiring is prevented from being reduced by the leakage current of the ESD protection element 30.

[0092] Furthermore, to suppress the decrease in signal voltage due to leakage current of the ESD protection element, it is conceivable to increase the channel length of the ESD protection element. However, in that case, the size of the ESD protection element would increase. In the active matrix substrate 100 of this embodiment, leakage current can be reduced with a relatively short channel length, thus also achieving the effect of reducing the size of the ESD protection element 30.

[0093] Furthermore, in the active matrix substrate 100 of this embodiment, the upper gate insulating layer 37 of the ESD protection element 30 has a laminated structure including a first layer 37a and a second layer 37b provided on the first layer 37a and formed in the same layer as the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20. Therefore, since the thickness of the upper gate insulating layer 37 of the ESD protection element 30 is greater than the thickness of the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20, dielectric breakdown between the source and gate in the ESD protection element 30 can be suppressed.

[0094] Furthermore, in the active matrix substrate 100 of this embodiment, the first protrusion width W1 of the upper gate insulating layer 37 of the ESD protection element 30 is larger than the first protrusion width W1 of the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20, and the second protrusion width W2 of the upper gate insulating layer 37 of the ESD protection element 30 is larger than the second protrusion width W2 of the upper gate insulating layer 7 of the pixel TFT 10 and circuit TFT 20, thereby increasing the source-drain breakdown voltage of the ESD protection element 30. This is because the portion of the oxide semiconductor layer 32 covered by the upper gate insulating layer 37 is less likely to have its resistance reduced compared to the uncovered portion, so the large first and second protrusion widths W1 and W2 make it less likely for the high voltage applied between the source and drain to concentrate in the channel region 32c.

[0095] Furthermore, in the active matrix substrate 100 of this embodiment, the lower gate electrode 34 of the ESD protection element 30 protrudes from both sides (source contact region 32s side and drain contact region 32d side) from the upper gate electrode 33. This makes it possible to increase the source-drain breakdown voltage of the ESD protection element 30.

[0096] In the illustrated example, the lower gate electrodes 4 of the pixel TFT 10 and circuit TFT 20 also protrude from the upper gate electrode 3 on both sides (source contact region 2s side and drain contact region 2d side). This allows for a higher source-drain breakdown voltage of the pixel TFT 10 and circuit TFT 20. Furthermore, by appropriately setting the protrusion width of the lower gate electrode 4 from the upper gate electrode 3, the mobility of the pixel TFT 10 and circuit TFT 20 can be controlled and adjusted. Specifically, by increasing the protrusion width (for example, to 1 μm or more), the mobility of the pixel TFT 10 and circuit TFT 20 can be further increased.

[0097] The active matrix substrate 100 may further include a demultiplexer (DEMUX) circuit (sometimes called an "SSD circuit") that drives the source wiring SL in a time-division manner. The DEMUX circuit is located in the non-display area FR. The DEMUX circuit may be monolithically formed on the substrate 1. In that case, the circuit TFT constituting the DEMUX circuit may have the same structure as the circuit TFT 20 illustrated in Figures 5 and 6.

[0098] The composition, crystal structure, thickness, and formation method of the oxide semiconductor layers 2 and 32 are not particularly limited.

[0099] The compositions of oxide semiconductor layers 2 and 32 may be different from each other. Here, "different compositions" means that the types or compositional ratios of metal elements contained in each layer are different. For example, oxide semiconductor layers 2 and 32 may each contain In and / or Sn, and the sum of the atomic ratios of In and Sn to all metal elements in oxide semiconductor layer 32 may be smaller than the sum of the atomic ratios of In and Sn to all metal elements in oxide semiconductor layer 2.

[0100] Alternatively, both oxide semiconductor layers 2 and 32 may be In-Ga-Zn-O based oxide semiconductor layers, and the atomic ratio of In in oxide semiconductor layer 32 may be lower than the atomic ratio of In in oxide semiconductor layer 2. In this case, in one of the oxide semiconductor layers 2 or 32, the atomic ratio of In to the total metal elements may be the same as the atomic ratio of Zn.

[0101] Furthermore, the oxide semiconductor layer 2 may contain Sn, while the oxide semiconductor layer 32 may not contain Sn. Alternatively, the oxide semiconductor layer 32 may contain Sn at a lower concentration than the oxide semiconductor layer 2. In other words, the atomic ratio of Sn to all metal elements in the oxide semiconductor layer 32 may be smaller than the atomic ratio of Sn in the oxide semiconductor layer 2.

[0102] For example, an In-Ga-Zn-O semiconductor layer (In:Ga:Zn=1:1:1, etc.) can be used as the oxide semiconductor layer 32. For example, an In-Ga-Zn-O semiconductor layer (In:Ga:Zn=3:1:2, etc.), an In-Sn-Zn-O semiconductor layer, an In-Al-Sn-Zn-O semiconductor layer, an In-W-Zn-O semiconductor layer, an In-Sn-O semiconductor layer, an In-Zn-O semiconductor layer, an In-Ga-Sn-O semiconductor layer, an In-Sn-Ti-Zn-O semiconductor layer, etc. can be used as the oxide semiconductor layer 2.

[0103] Furthermore, the oxide semiconductor layers 2 and 32 may have different crystal structures. For example, one of the oxide semiconductor layers 2 and 32 may be an amorphous oxide semiconductor layer, and the other may be a crystalline oxide semiconductor layer containing a crystalline portion.

[0104] Even if the ratios of each metal element in oxide semiconductor layers 2 and 32 are the same, it is possible to make the mobilities of these oxide semiconductor layers different by varying the deposition method or deposition conditions. For example, when forming oxide semiconductor layers 2 and 32 with the same ratio of each metal element by sputtering, the atmosphere inside the chamber (e.g., the flow rate ratio of oxygen and Ar supplied to the chamber) may be varied. Specifically, when forming oxide semiconductor film 32, the flow rate ratio of oxygen to Ar may be set high (e.g., 80%), and when forming oxide semiconductor layer 2, the flow rate ratio of oxygen to Ar may be set lower than that of oxide semiconductor layer 32 (e.g., 20%). This makes it possible to lower the mobility of oxide semiconductor layer 32 to that of oxide semiconductor layer 2.

[0105] Here, the manufacturing method of the active matrix substrate 100 will be explained with reference to Figures 7A to 7J. Figures 7A to 7J are cross-sectional view diagrams illustrating the manufacturing process of the active matrix substrate 100.

[0106] First, as shown in Figure 7A, the lower gate electrodes 4 and 34 are formed on the substrate 1. Specifically, a conductive film for the lower gate (thickness: for example, 50 nm to 500 nm) is formed on the insulating substrate 1 by sputtering or the like, and then the lower gate electrodes 4 and 34 can be formed by patterning the conductive film for the lower gate.

[0107] For example, the substrate 1 can be a glass substrate, a heat-resistant plastic substrate (resin substrate), or the like.

[0108] As the conductive film for the lower gate, a metal film containing an element selected from, for example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy film composed of these elements can be used. Alternatively, a multilayer film containing multiple of these films may be used. Here, a metal film or alloy film containing Cu or Al is used as the conductive film for the lower gate.

[0109] Next, as shown in Figure 7B, the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38 are formed to cover the lower gate electrodes 4 and 34. The first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38 can be formed, for example, by CVD. The thickness of the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38 is, for example, 200 nm to 600 nm.

[0110] As the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38, silicon oxide (SiO2) layer, silicon nitride (SiNx) layer, silicon oxynitride (SiOxNy; x>y) layer, silicon oxide nitride (SiNxOy; x>y) layer, etc., can be used as appropriate. The first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38 may have a laminated structure. For example, a silicon nitride layer, silicon oxide nitride layer, etc. may be formed on the substrate 1 side (lower layer) to prevent diffusion of impurities from the substrate 1, and a silicon oxide layer, silicon oxide nitride layer, etc. may be formed on the layer above (upper layer) to ensure insulation.

[0111] Next, as shown in Figure 7C, an oxide semiconductor layer 32 for the ESD protection element 30 (i.e., a relatively low-mobility layer) is formed on the lower gate insulating layer 38. Specifically, the oxide semiconductor layer 32 can be formed by first depositing an oxide semiconductor film using a sputtering method, and then patterning the oxide semiconductor film. Here, an In-Ga-Zn-O semiconductor film with a thickness of 40 nm (for example, In:Ga:Zn = 1:1:1 or 4:2:4) is used as the oxide semiconductor film. Patterning of the In-Ga-Zn-O semiconductor film can be performed, for example, by wet etching using a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etching solution.

[0112] Next, as shown in Figure 7D, an insulating film IF1 is deposited to cover the oxide semiconductor layer 32, forming the second layer 8b of the lower gate insulating layer 8 and the first layer 37a of the upper gate insulating layer 37. The insulating film IF1 can be deposited, for example, by CVD. The same material as that used for the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38 can be used for the insulating film IF1. Here, a silicon oxide film is formed as the insulating film IF1. By using an oxide film such as a silicon oxide film as the insulating film IF1, oxidation defects generated in the channel region can be reduced by the oxide film. The thickness of the insulating film IF1 is, for example, 20 nm to 200 nm.

[0113] Next, as shown in Figure 7E, an oxide semiconductor layer 2 (i.e., with relatively high mobility) for the pixel TFT 10 and circuit TFT 20 is formed on the insulating film IF. Specifically, the oxide semiconductor layer 2 can be formed by first depositing an oxide semiconductor film using a sputtering method, and then patterning the oxide semiconductor film. Here, an In-Ga-Zn-O semiconductor film with a thickness of 35 nm (e.g., In:Ga:Zn=5:1:4) is formed as the oxide semiconductor film. Alternatively, a film containing Sn, such as an In-Sn-Zn-O semiconductor film with a thickness of 35 nm (e.g., In2O3-SnO2-ZnO), may be formed. Patterning of the In-Sn-Zn-O semiconductor film can be performed, for example, by wet etching using an oxalic acid-based etching solution.

[0114] Next, as shown in Figure 7F, insulating film IF2, which will become the second layer 37b of the upper gate insulating layer 7 and upper gate insulating layer 37, and conductive film CF for the upper gate, which will become the upper gate electrodes 3 and 33, are sequentially deposited on the insulating film IF1 and oxide semiconductor layer 2.

[0115] The insulating film IF2 can be deposited, for example, by CVD. The same insulating film as insulating film IF1 can be used for insulating film IF2. Insulating film IF2 may be formed from the same material as insulating film IF1, or from a different material. Here, a silicon oxide film is formed as insulating film IF2. The thickness of insulating film IF2 is, for example, between 80 nm and 250 nm.

[0116] The upper gate conductive film CF can be deposited, for example, by sputtering. The thickness of the upper gate conductive film CF is, for example, 50 nm to 500 nm. The same conductive film as the lower gate conductive film can be used as the upper gate conductive film CF.

[0117] Next, as shown in Figure 7G, the patterning of the upper gate conductive film CF and the insulating films IF2 and IF1 are performed sequentially. As a result, the upper gate electrodes 3 and 33 are formed from the upper gate conductive film CF, the upper gate insulating layer 7 and the second layer 37b of the upper gate insulating layer 37 are formed from the insulating film IF2, and the second layer 8b of the lower gate insulating layer 8 and the first layer 37a of the upper gate insulating layer 37 are formed from the insulating film IF1.

[0118] Subsequently, the oxide semiconductor layers 2 and 32 may be subjected to a low-resistance treatment. This low-resistance treatment may be, for example, a plasma treatment. As a result of this low-resistance treatment, the region of the oxide semiconductor layer 2 that does not overlap with the upper gate electrode 3 becomes a low-resistance region (source contact region 2s and drain contact region 2d) with lower resistivity than the region overlapping with the upper gate electrode 3 (channel region 2c). Similarly, the region of the oxide semiconductor layer 32 that does not overlap with the upper gate electrode 33 becomes a low-resistance region (source contact region 32s and drain contact region 32d) with lower resistivity than the region overlapping with the upper gate electrode 33 (channel region 32c). Note that the method of the low-resistance treatment is not limited to those exemplified here.

[0119] Next, as shown in Figure 7H, an interlayer insulating layer 9 is formed to cover the oxide semiconductor layers 2 and 32, the upper gate electrodes 3 and 33, etc. The interlayer insulating layer 9 can be formed, for example, by the CVD method. As the interlayer insulating layer 9, inorganic insulating layers such as silicon oxide (SiO2) layers, silicon nitride (SiNx) layers, silicon oxynitride (SiOxNy; x>y) layers, and silicon oxide nitride (SiNxOy; x>y) layers can be used as a single layer or in stacked layers. The thickness of the interlayer insulating layer 9 is, for example, 200 nm to 700 nm. Here, a silicon oxide layer is used as the interlayer insulating layer 9.

[0120] Next, as shown in Figure 7I, source contact holes CHs1, CHs2 and drain contact holes CHd1, CHd2 are formed in the interlayer insulating layer 9. Specifically, the formation of source contact holes CHs1, CHs2 and drain contact holes CHd1, CHd2 can be carried out by a photolithography process and etching. Etching may be dry etching, for example.

[0121] Subsequently, as shown in Figure 7J, source electrodes 5 and 35 and drain electrodes 6 and 36 are formed on the interlayer insulating layer 9. Specifically, a conductive film for the source (thickness: e.g., 50 nm to 500 nm) is formed on the interlayer insulating layer 9, and then the conductive film for the source is patterned to form the source electrodes 5 and 35 and the drain electrodes 6 and 36. The conductive film for the source can be patterned by, for example, dry etching or wet etching. As the conductive film for the source, elements selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys containing these elements, can be used. For example, it may have a three-layer structure such as titanium film-aluminum film-titanium film, or a three-layer structure such as molybdenum film-aluminum film-molybdenum film. Note that the conductive film for the source is not limited to a three-layer structure, but may have a single layer, a two-layer structure, or a laminated structure of four or more layers. Here, a multilayer film is used, consisting of a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0122] In this way, an active matrix substrate 100 is obtained, which includes a pixel TFT 10, a circuit TFT 20, and an ESD protection element 30.

[0123] [Embodiment 2] The active matrix substrate 200A in this embodiment will be described with reference to Figure 8. The following description will focus on the differences between the active matrix substrate 200A and the active matrix substrate 100 of Embodiment 1. Figure 8 is a schematic cross-sectional view showing a part of the active matrix substrate 200A. In Figure 8, the structure of the pixel TFT 10 is shown on the right, the structure of the circuit TFT 20 is shown in the center, and the structure of the ESD protection element 30 is shown on the left.

[0124] The circuit TFT 20 and ESD protection element 30 of the active matrix substrate 200A have the same structure as the circuit TFT 20 and ESD protection element 30 of the active matrix substrate 100 of Embodiment 1, respectively. In contrast, the pixel TFT 10 of the active matrix substrate 200A has a different structure from the pixel TFT 10 of the active matrix substrate 100 of Embodiment 1.

[0125] The oxide semiconductor layer 2' of the pixel TFT 10 on the active matrix substrate 200A is formed in a separate layer from the oxide semiconductor layer 2 of the circuit TFT 20, and is formed in the same layer as the oxide semiconductor layer 32 of the ESD protection element 30. Therefore, the oxide semiconductor layer 2' of the pixel TFT 10 has a lower mobility than the oxide semiconductor layer 2 of the circuit TFT 20.

[0126] The upper gate insulating layer 7' of the pixel TFT 10 includes a first layer 7a and a second layer 7b provided on the first layer 7a. The first layer 7a is formed in the same layer as the second layer 8b of the lower gate insulating layer 8 of the circuit TFT 20. The second layer 7b is formed in the same layer as the upper gate insulating layer 7 of the circuit TFT 20. In other words, the upper gate insulating layer 7' of the pixel TFT 10 has the same stacked structure as the upper gate insulating layer 37 of the ESD protection element 30.

[0127] The lower gate insulating layer 8' of the pixel TFT 10 is formed in the same layer as the first layer 8a of the lower gate insulating layer 8 of the circuit TFT 20. In other words, the lower gate insulating layer 8' of the pixel TFT 10 has the same structure as the lower gate insulating layer 38 of the ESD protection element 30.

[0128] With reference to Figure 9, another active matrix substrate 200B in this embodiment will be described. Figure 9 is a schematic cross-sectional view showing a part of the active matrix substrate 200B.

[0129] The active matrix substrate 200B shown in Figure 9 is for an organic EL display device, and multiple pixel TFTs are provided in each pixel region P. Some of the multiple pixel TFTs, pixel TFTs 10H, have the same structure as the pixel TFTs 10 of the active matrix substrate 100 of Embodiment 1, while the other pixel TFTs 10L have the same structure as the pixel TFTs 10 of the active matrix substrate 200A shown in Figure 8. Therefore, the former pixel TFTs 10H have relatively high mobility, and the latter pixel TFTs 10L have relatively low mobility.

[0130] For example, in the pixel circuit illustrated in Figure 4, it is preferable that the driving pixel TFT 10A has a relatively smooth (i.e., not steep) Vg (gate voltage)-Id (drain current) characteristic from the viewpoint of current control and for suitable multi-gradation display. On the other hand, it is preferable that the selection pixel TFT 10B has high mobility (i.e., a large on-current). Therefore, it is preferable that the selection pixel TFT 10B is a relatively high-mobility pixel TFT 10H, and the driving pixel TFT 10A is a relatively low-mobility pixel TFT 10L. It is preferable that the light emission control pixel TFT 10C is a relatively high-mobility pixel TFT 10H.

[0131] The same effects as those of the active matrix substrate 100 of Embodiment 1 can be obtained with the active matrix substrates 200A and 200B described above.

[0132] [Embodiment 3] The active matrix substrate 300 in this embodiment will be described with reference to Figure 10. Figure 10 is a schematic cross-sectional view showing a part of the active matrix substrate 300. In the following description, the differences between the active matrix substrate 300 and the active matrix substrate 200A of Embodiment 2 will be the main focus.

[0133] In the active matrix substrate 300 of this embodiment, some of the circuit TFTs 20H among the multiple circuit TFTs have the same structure as the circuit TFT 20 of the active matrix substrate 200A of Embodiment 2, and the other circuit TFTs 20L have the same structure as the pixel TFT 10 of the active matrix substrate 200A of Embodiment 2. Therefore, the former circuit TFTs 20H have relatively high mobility, and the latter circuit TFTs 20L have relatively low mobility.

[0134] A relatively high-mobility circuit TFT 20H could be, for example, the output TFT of a gate driver GD or the output TFT of an emission driver ED. Conversely, a relatively low-mobility circuit TFT 20L could be, for example, the switching TFT of a gate driver GD or the switching TFT of an emission driver ED.

[0135] [Regarding the lower gate electrode] The lower gate electrode of the oxide semiconductor TFT in the active matrix substrate according to an embodiment of the present invention can take any of the following configurations A to E. The same applies to the lower gate electrode of the oxide semiconductor TFT (circuit TFT) constituting the DEMUX circuit when the active matrix substrate has a DEMUX circuit.

[0136] <Configuration A> In this configuration, the lower gate electrode is electrically connected to the upper gate electrode.

[0137] <Configuration B> In this configuration, the lower gate electrode is omitted. In other words, the oxide semiconductor TFT has a top-gate structure.

[0138] <Configuration C> In this configuration, a predetermined fixed potential is applied to the lower gate electrode.

[0139] <Configuration D> In this configuration, the lower gate electrode is electrically connected to either the source electrode or the drain electrode.

[0140] <Configuration E> In this configuration, the lower gate electrode is electrically floating together with the upper gate electrode and is capacitively coupled to the low-resistance region of the oxide semiconductor layer.

[0141] Here, we will explain which of configurations A to E is preferable when the active matrix substrate is for an organic EL display device or for a liquid crystal display device.

[0142] <Active matrix substrate for OLED display devices> In an active matrix substrate for an organic EL display device, from the viewpoint of suppressing damage to the ESD protection element 30 due to ESD, configuration B is preferred over configuration A for the lower gate electrode 34 of the ESD protection element 30, configurations C and D are preferred over configuration B, and configuration E is preferred over configurations C and D. In other words, configuration E is the most preferred.

[0143] Furthermore, for the lower gate electrode 4 of the selection pixel TFT 10B in the pixel circuit illustrated in Figure 4, configuration B is preferred over configuration A. Omitting the lower gate electrode 4 allows for a space-saving layout. Also, for the lower gate electrode 4 of the driving pixel TFT 10A, configuration C or D is preferred from the viewpoint of suitably performing multi-gradation display.

[0144] For the lower gate electrodes 4 of the output TFT of the gate driver GD and the output TFT of the emission driver ED, configuration A is preferred from the viewpoint of achieving high mobility. For the lower gate electrodes 4 of the switching TFT of the gate driver GD and the switching TFT of the emission driver ED, configurations A, C, or D are preferred from the viewpoint of raising the threshold voltage to stably operate the gate driver GD and the emission driver ED.

[0145] <Active matrix substrate for liquid crystal display devices> In an active matrix substrate for a liquid crystal display device, from the viewpoint of suppressing damage to the ESD protection element 30 by ESD, configurations C and D are preferred over configuration A for the lower gate electrode 34 of the ESD protection element 30, and configuration E is preferred over configurations C and D. In other words, configuration E is the most preferred. Configuration B is undesirable because its reliability is reduced by incident light from the backlight.

[0146] With respect to the lower gate electrode 4 of the pixel TFT 10, configuration A or C is preferred from the viewpoint of ensuring reliability against incident light from the backlight.

[0147] Regarding the lower gate electrode 4 of the output TFT of the gate driver GD, configuration A is preferred from the viewpoint of achieving high mobility. Regarding the lower gate electrode 4 of the switching TFT of the gate driver GD, configuration A or C is preferred from the viewpoint of reliability against incident light from the backlight and stable operation of the gate driver GD by increasing the threshold voltage.

[0148] [Embodiment 4] The active matrix substrates 400A, 400B, and 400C in this embodiment will be described with reference to Figures 11, 12, and 13. Figures 11, 12, and 13 are schematic cross-sectional views showing parts of the active matrix substrates 400A, 400B, and 400C, respectively. In the following description, the differences between the active matrix substrates 400A, 400B, and 400C and the active matrix substrate 100 of Embodiment 1, the active matrix substrate 200A of Embodiment 2, and the active matrix substrate 300 of Embodiment 3 will be explained in detail.

[0149] In the active matrix substrate 100 of Embodiment 1, the active matrix substrate 200A of Embodiment 2, and the active matrix substrate 300 of Embodiment 3, as shown in Figures 5, 8, and 10, the upper gate insulating layer 37 of the ESD protection element 30 is patterned such that it does not at least partially cover the portion of the source contact region 32s that does not overlap with the source contact hole CHs2 and the portion of the drain contact region 32d that does not overlap with the drain contact hole CHd2. In contrast, in the active matrix substrates 400A, 400B, and 400C, as shown in Figures 11, 12, and 13, the first layer 37a of the upper gate insulating layer 37 of the ESD protection element 30 covers the portion of the source contact region 32s that does not overlap with the source contact hole CHs2 and the portion of the drain contact region 32d that does not overlap with the drain contact hole CHd2.

[0150] Therefore, in the active matrix substrates 400A, 400B, and 400C, the source contact region 32s and drain contact region 32d of the oxide semiconductor layer 32 of the ESD protection element 30 are less likely to have low resistance than those in the active matrix substrate 100 of Embodiment 1, the active matrix substrate 200A of Embodiment 2, and the active matrix substrate 300 of Embodiment 3, thus further enhancing the effect of suppressing damage to the ESD protection element 30 by ESD.

[0151] Here, we will explain how to manufacture the active matrix substrate 400A.

[0152] First, as explained with reference to Figures 7A to 7F, the following steps are sequentially performed on the substrate 1: formation of lower gate electrodes 4 and 34, formation of the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38, formation of an oxide semiconductor layer 32 for the ESD protection element 30 (i.e., with relatively low mobility), deposition of insulating film IF1, formation of an oxide semiconductor layer 2 for the pixel TFT 10 and circuit TFT 20 (i.e., with relatively high mobility), deposition of insulating film IF2, and deposition of the upper gate conductive film CF. Figure 14A shows the state after deposition of the upper gate conductive film CF.

[0153] Next, as shown in Figure 14B, the patterning of the upper gate conductive film CF and the insulating film IF2 are performed sequentially. As a result, the upper gate electrodes 3 and 33 are formed from the upper gate conductive film CF, and the upper gate insulating layer 7 and the second layer 37b of the upper gate insulating layer 37 are formed from the insulating film IF2. In this embodiment, since the insulating film IF1 is not patterned at this time, it can be said that the second layer 8b of the lower gate insulating layer 8 and the first layer 37a of the upper gate insulating layer 37 are formed when the insulating film IF1 is deposited.

[0154] After this, the oxide semiconductor layers 2 and 32 may be subjected to a resistance reduction treatment (e.g., plasma treatment). In this case, the source contact region 32s and the drain contact region 32d of the oxide semiconductor layer 32 remain covered by the first layer 37a of the upper gate insulating layer 37, and are therefore less susceptible to resistance reduction compared to when they are exposed.

[0155] Next, as shown in Figure 14C, an interlayer insulating layer 9 is formed to cover the oxide semiconductor layers 2 and 32, the upper gate electrodes 3 and 33, and the like.

[0156] Next, as shown in Figure 14D, source contact holes CHs1 and drain contact holes CHd1 are formed in the interlayer insulating layer 9, and source contact holes CHs2 and drain contact holes CHd2 are formed in the first layer 37a of the upper gate insulating layer 37 and the interlayer insulating layer 9.

[0157] Subsequently, as shown in Figure 14E, source electrodes 5 and 35 and drain electrodes 6 and 36 are formed on the interlayer insulating layer 9.

[0158] In this way, the active matrix substrate 400A of this embodiment is obtained. Active matrix substrates 400B and 400C can be manufactured in the same manner.

[0159] [Embodiment 5] The active matrix substrates 500A, 500B, and 500C in this embodiment will be described with reference to Figures 15, 16, and 17. Figures 15, 16, and 17 are schematic cross-sectional views showing parts of the active matrix substrates 500A, 500B, and 500C, respectively. In the following description, the differences between the active matrix substrates 500A, 500B, and 500C and the active matrix substrates 400A, 400B, and 400C of Embodiment 4 will be the main focus of the explanation.

[0160] In the active matrix substrates 500A, 500B, and 500C, as shown in Figures 15, 16, and 17, not only the first layer 37a of the upper gate insulating layer 37 of the ESD protection element 30, but also the second layer 37b covers the portion of the source contact region 32s that does not overlap with the source contact hole CHs2 and the portion of the drain contact region 32d that does not overlap with the drain contact hole CHd2.

[0161] Therefore, in the active matrix substrates 500A, 500B, and 500C, the source contact region 32s and drain contact region 32d of the oxide semiconductor layer 32 of the ESD protection element 30 are less likely to have their resistance reduced than those in the active matrix substrates 400A, 400B, and 400C of Embodiment 4, thus further enhancing the effect of suppressing damage to the ESD protection element 30 by ESD.

[0162] Here, we will explain the manufacturing method of the active matrix substrate 500A.

[0163] First, as explained with reference to Figures 7A to 7F, the following steps are sequentially performed on the substrate 1: formation of lower gate electrodes 4 and 34, formation of the first layer 8a of the lower gate insulating layer 8 and the lower gate insulating layer 38, formation of an oxide semiconductor layer 32 for the ESD protection element 30 (i.e., with relatively low mobility), deposition of insulating film IF1, formation of an oxide semiconductor layer 2 for the pixel TFT 10 and circuit TFT 20 (i.e., with relatively high mobility), deposition of insulating film IF2, and deposition of the upper gate conductive film CF. Figure 18A shows the state after deposition of the upper gate conductive film CF.

[0164] Next, as shown in Figure 18B, the conductive film CF for the upper gate is patterned. This forms the upper gate electrodes 3 and 33 from the conductive film CF for the upper gate. In this embodiment, the insulating film IF1 and insulating film IF2 are not patterned at this time. Therefore, it can be said that when insulating film IF1 is deposited, the second layer 8b of the lower gate insulating layer 8 and the first layer 37a of the upper gate insulating layer 37 are formed, and when insulating film IF2 is deposited, the upper gate insulating layer 7 and the second layer 37b of the upper gate insulating layer 37 are formed.

[0165] After this, the oxide semiconductor layers 2 and 32 may be subjected to a resistance reduction treatment (e.g., plasma treatment). In this case, the source contact region 32s and the drain contact region 32d of the oxide semiconductor layer 32 remain covered by the first layer 37a and the second layer 37b of the upper gate insulating layer 37, so they are less susceptible to resistance reduction compared to when they are exposed or covered only by the first layer 37a.

[0166] Next, as shown in Figure 18C, an interlayer insulating layer 9 is formed to cover the oxide semiconductor layers 2 and 32, the upper gate electrodes 3 and 33, and the like.

[0167] Next, as shown in Figure 18D, source contact holes CHs1 and drain contact holes CHd1 are formed in the upper gate insulating layer 7 and the interlayer insulating layer 9, while source contact holes CHs2 and drain contact holes CHd2 are formed in the first layer 37a, the second layer 37b of the upper gate insulating layer 37 and the interlayer insulating layer 9.

[0168] Subsequently, as shown in Figure 18E, source electrodes 5 and 35 and drain electrodes 6 and 36 are formed on the interlayer insulating layer 9.

[0169] In this way, the active matrix substrate 500A of this embodiment is obtained. Active matrix substrates 500B and 500C can be manufactured in the same manner.

[0170] As described above, the configurations of Embodiments 4 and 5 are advantageous over the configurations of Embodiments 1, 2, and 3 in that they suppress damage to the ESD protection element 30. Furthermore, the configurations of Embodiments 4 and 5 are also advantageous over the configurations of Embodiments 1, 2, and 3 in terms of achieving high resolution. This point will be explained below.

[0171] Figure 19 is a diagram that shows a detailed breakdown of the manufacturing process of the active matrix substrate 100 of Embodiment 1, as described with reference to Figure 7G, and shows the region where two adjacent ESD protection elements 30 are formed. Note that in Figure 19, the lower gate insulating layer 38, the lower gate electrode 34, and the substrate 1 are omitted, and adjacent oxide semiconductor layers 32 are shown as continuous (the same applies to Figures 20 and 21, which will be described later).

[0172] When performing the process described with reference to Figure 7G, first, a resist layer RL is formed on the upper gate conductive film CF, as shown in the top row (first row) of Figure 19. Specifically, the resist layer RL can be formed by first depositing a resist film on the upper gate conductive film CF, then exposing the resist film using a photomask, and finally developing it. The resist layer RL includes a mask portion m1 located in a region corresponding to one of the two ESD protection elements 30, and a mask portion m2 located in a region corresponding to the other. The distance d1 between mask portions m1 and m2 is set to be greater than or equal to a predetermined size so that they are not continuous with each other.

[0173] Next, as shown in the second stage of Figure 19, wet etching is performed on the upper gate conductive film CF using the resist layer RL as a mask. As a result, the upper gate electrode 33 is formed below the mask portions m1 and m2, respectively.

[0174] Next, as shown in the third stage of Figure 19, dry etching is performed on the insulating films IF2 and IF1 using the resist layer RL as a mask. As a result, the second layer 37b and the first layer 37a of the upper gate insulating layer 37 are formed below the upper gate electrode 33. At this time, as the dry etching progresses, the edges of the mask portions m1 and m2 of the resist layer RL recede.

[0175] Subsequently, the resist layer RL is peeled off as shown in the bottom row (fourth row) of Figure 19. In this way, the patterning of the upper gate conductive film CF, insulating film IF2 and IF1 is completed. Note that a resistance reduction treatment may be performed before peeling off the resist layer RL.

[0176] Figure 20 is a diagram that shows a detailed breakdown of the manufacturing process of the active matrix substrate 400A of Embodiment 4, as described with reference to Figure 14B.

[0177] When performing the process described with reference to Figure 14B, first, a resist layer RL is formed on the upper gate conductive film CF, as shown in the top row (first row) of Figure 20. Specifically, the resist layer RL can be formed by first depositing a resist film on the upper gate conductive film CF, then exposing the resist film using a photomask, and finally developing it. The resist layer RL includes a mask portion m1 located in a region corresponding to one of the two ESD protection elements 30, and a mask portion m2 located in a region corresponding to the other. The distance d1 between mask portions m1 and m2 is set to be greater than or equal to a predetermined size so that they are not continuous with each other.

[0178] Next, as shown in the second stage of Figure 20, wet etching is performed on the upper gate conductive film CF using the resist layer RL as a mask. As a result, the upper gate electrode 33 is formed below the mask portions m1 and m2, respectively.

[0179] Next, as shown in the third stage of Figure 20, dry etching is performed on the insulating film IF2 using the resist layer RL as a mask. This forms the second layer 37b of the upper gate insulating layer 37 below the upper gate electrode 33. At this time, as the dry etching progresses, the edges of the mask portions m1 and m2 of the resist layer RL recede.

[0180] Subsequently, the resist layer RL is peeled off as shown in the bottom row (fourth row) of Figure 20. In this way, the patterning of the upper gate conductive film CF and insulating film IF2 is completed. Note that a resistance reduction treatment may be performed before peeling off the resist layer RL.

[0181] In the active matrix substrate 400A (or 400B, 400C) of Embodiment 4, since dry etching is not performed on the insulating film IF1, the amount of edge recession of the mask portions m1 and m2 of the resist layer RL is less than the amount of recession in the active matrix substrate 100 of Embodiment 1. Therefore, in the configuration of Embodiment 4, the distance d2 between adjacent upper gate electrodes 33 can be reduced compared to the configuration of Embodiment 1, which is advantageous for high resolution.

[0182] Figure 21 is a diagram that shows a detailed breakdown of the manufacturing process of the active matrix substrate 500A of Embodiment 5, as described with reference to Figure 18B.

[0183] When performing the process described with reference to Figure 18B, first, a resist layer RL is formed on the upper gate conductive film CF, as shown in the top row (first row) of Figure 21. Specifically, the resist layer RL can be formed by first depositing a resist film on the upper gate conductive film CF, then exposing the resist film using a photomask, and finally developing it. The resist layer RL includes a mask portion m1 located in a region corresponding to one of the two ESD protection elements 30, and a mask portion m2 located in a region corresponding to the other. The distance d1 between mask portions m1 and m2 is set to be greater than or equal to a predetermined size so that they are not continuous with each other.

[0184] Next, as shown in the second stage of Figure 21, wet etching is performed on the upper gate conductive film CF using the resist layer RL as a mask. As a result, the upper gate electrode 33 is formed below the mask portions m1 and m2, respectively.

[0185] Subsequently, the resist layer RL is peeled off as shown in the bottom row (third row) of Figure 21. In this way, the patterning of the upper gate conductive film CF is completed. Note that a resistance reduction treatment may be performed before peeling off the resist layer RL.

[0186] In the active matrix substrate 500A (or 500B, 500C) of Embodiment 5, dry etching is not performed on both the insulating film IF2 and IF1, so no recession occurs at the edges of the mask portions m1 and m2 of the resist layer RL due to dry etching. Therefore, in the configuration of Embodiment 5, the distance d2 between adjacent upper gate electrodes 33 can be made even smaller compared to the configuration of Embodiment 4, which is even more advantageous for high resolution.

[0187] [About oxide semiconductors] The oxide semiconductor (also called a metal oxide or oxide material) contained in the oxide semiconductor layer of an oxide semiconductor TFT may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors in which the c-axis is oriented generally perpendicular to the layer plane.

[0188] The materials, structure, film formation method, and configuration of oxide semiconductor layers having a stacked structure for amorphous oxide semiconductors and the crystalline oxide semiconductors described above are described, for example, in Japanese Patent Application Publication No. 2014-0073911. For reference, all disclosures of Japanese Patent Application Publication No. 2014-0073911 are incorporated herein by reference.

[0189] The oxide semiconductor layer may contain, for example, at least one metal element from among In, Ga, and Zn. In this embodiment, the oxide semiconductor layer includes, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited, and include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0190] In-Ga-Zn-O semiconductors may be amorphous or crystalline. Among crystalline In-Ga-Zn-O semiconductors, those in which the c-axis is oriented approximately perpendicular to the layer plane are preferred.

[0191] The crystal structure of crystalline In-Ga-Zn-O semiconductors is disclosed, for example, in Japanese Patent Publication No. 2014-0073911, Japanese Patent Publication No. 2012-134475, and Japanese Patent Publication No. 2014-2090627. For reference, all disclosures of Japanese Patent Publication No. 2012-134475 and Japanese Patent Publication No. 2014-2090627 are incorporated herein by reference. TFTs having an In-Ga-Zn-O semiconductor layer have high mobility (more than 20 times that of a-SiTFTs) and low leakage current (less than 1 / 100th that of a-SiTFTs), and are therefore suitably used as driving TFTs (for example, TFTs included in a driving circuit provided on the same substrate as the display area around a display area containing multiple pixels) and pixel TFTs (TFTs provided on pixels).

[0192] The oxide semiconductor layer may contain other oxide semiconductors instead of the In-Ga-Zn-O system semiconductor. For example, it may contain an In-Sn-Zn-O system semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O system semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, In-W-Zn-O semiconductors, and the like. [Industrial applicability]

[0193] According to embodiments of the present invention, in an active matrix substrate equipped with an oxide semiconductor TFT with a top gate structure or a double gate structure as an ESD protection element, it is possible to avoid problems caused by the current driving capability of the ESD protection element being too high. [Explanation of Symbols]

[0194] 1 circuit board 2, 2', 32 oxide semiconductor layer 2c, 32c channel region 2s, 32s source contact area 2d, 32d drain contact area 3, 33 Top detergent 4, 34 Lower Gate 5.35 Source electrode 6.36 Drain electrode 7, 7', 37 Upper gate insulating layer 7a First layer of the upper gate insulating layer 7b Second layer of the upper gate insulating layer 8, 8', 38 Lower gate insulating layer 8a First layer of the lower gate insulating layer 8b Second layer of the lower gate insulating layer 9 interlayer insulating layer 10, 10H, 10L Pixel TFT 10A drive pixel TFT 10B Selective Pixel TFT 10C Pixel TFT for light emission control 20, 20H, 20L circuit TFT 30, 30A, 30B, 30C, 30D ESD protection element 37a First layer of the upper gate insulating layer 37b Second layer of the upper gate insulating layer 41 Capacitive elements 42 OLED 100, 200A, 200B, 300 Active Matrix Substrates 400A, 400B, 400C Active Matrix Boards 500A, 500B, 500C Active Matrix Substrates DR display area FR hidden area P pixel region PE pixel electrode GL gate wiring SL Source Wiring EML Light Emission Control Wiring ML GDM wiring ML' EDM wiring CL Common Wiring CSL current supply line GD Gate Driver ED Emission Driver CHs1, CHs2 Source Contact Holes CHd1, CHd2 Drain Contact Holes

Claims

1. It has a display area that includes multiple pixel regions and a non-display area located around the display area, circuit board and A plurality of wirings provided on the substrate, the plurality of wirings including a plurality of gate wirings and a plurality of source wirings, A plurality of TFTs supported on the substrate, comprising a plurality of pixel TFTs arranged within the display area and a plurality of circuit TFTs arranged within the non-display area, A plurality of ESD protection elements are arranged within the non-display area, each electrically connected to a corresponding wire among the plurality of wires, An active matrix substrate comprising, At least some of the aforementioned multiple TFTs are A first oxide semiconductor layer comprising a first channel region and a first source contact region and a first drain contact region located on both sides of the first channel region, A first gate insulating layer provided at least on the first channel region, A first gate electrode facing the first channel region via the first gate insulating layer, A first source electrode and a first drain electrode are electrically connected to the first source contact region and the first drain contact region, respectively. It has, Each of the aforementioned plurality of ESD protection elements is A second oxide semiconductor layer comprising a second channel region and a second source contact region and a second drain contact region located on both sides of the second channel region, wherein the second oxide semiconductor layer is formed as a separate layer from the first oxide semiconductor layer and has a mobility lower than that of the first oxide semiconductor layer, A second gate insulating layer provided at least on the second channel region, A second gate electrode facing the second channel region via the second gate insulating layer, A second source electrode and a second drain electrode are electrically connected to the second source contact region and the second drain contact region, respectively. An active matrix substrate having the following characteristics.

2. The active matrix substrate according to claim 1, wherein the second gate insulating layer includes a first layer and a second layer provided on the first layer and formed in the same layer as the first gate insulating layer.

3. The second oxide semiconductor layer, the second gate insulating layer, and the second gate electrode are further comprising an interlayer insulating layer covering them. At least the interlayer insulating layer is formed with a source contact hole that exposes a portion of the second source contact region and a drain contact hole that exposes a portion of the second drain contact region. The active matrix substrate according to claim 2, wherein the first layer of the second gate insulating layer covers a portion of the second source contact region that does not overlap with the source contact hole and a portion of the second drain contact region that does not overlap with the drain contact hole.

4. The active matrix substrate according to claim 3, wherein the second layer of the second gate insulating layer covers a portion of the second source contact region that does not overlap with the source contact hole and a portion of the second drain contact region that does not overlap with the drain contact hole.

5. In a plan view, the protrusion width of the second gate insulating layer from the second gate electrode toward the second source contact region is greater than the protrusion width of the first gate insulating layer toward the first source contact region, and the protrusion width of the second gate insulating layer from the second gate electrode toward the second drain contact region is greater than the protrusion width of the first gate insulating layer toward the first drain contact region, according to any one of claims 1 to 4.

6. The aforementioned TFTs, at least some of them, A third gate electrode located below the first oxide semiconductor layer and facing at least the first channel region, A third gate insulating layer located between the first oxide semiconductor layer and the third gate electrode, An active matrix substrate according to any one of claims 1 to 4, further comprising the above.

7. The active matrix substrate according to claim 6, wherein, in a plan view, the third gate electrode protrudes from the first gate electrode toward the first source contact region and the first drain contact region, respectively.

8. Each of the aforementioned plurality of ESD protection elements is A fourth gate electrode located below the second oxide semiconductor layer and facing at least the second channel region, A fourth gate insulating layer located between the second oxide semiconductor layer and the fourth gate electrode, An active matrix substrate according to any one of claims 1 to 4, further comprising the above.

9. The active matrix substrate according to claim 8, wherein, in a plan view, the fourth gate electrode protrudes from the second gate electrode toward the second source contact region and the second drain contact region, respectively.

10. The active matrix substrate according to any one of claims 1 to 4, wherein the second gate electrode and the second source electrode are electrically connected to each other.

11. The second gate electrode is formed in the same layer as the first gate electrode, The active matrix substrate according to any one of claims 1 to 4, wherein the second source electrode and the second drain electrode are formed in the same layer as the first source electrode.

12. The active matrix substrate according to any one of claims 1 to 4, wherein at least a portion of the plurality of pixel TFTs includes a third oxide semiconductor layer formed in the same layer as the second oxide semiconductor layer.

13. The active matrix substrate according to claim 12, wherein each of the plurality of pixel TFTs includes the third oxide semiconductor layer.

14. A portion of the plurality of pixel TFTs includes the third oxide semiconductor layer, The active matrix substrate according to claim 12, wherein the other portion of the plurality of pixel TFTs includes the first oxide semiconductor layer.

15. The active matrix substrate according to any one of claims 1 to 4, wherein at least a portion of the plurality of circuit TFTs includes the first oxide semiconductor layer.

16. The first oxide semiconductor layer and the second oxide semiconductor layer each contain In and / or Sn, The active matrix substrate according to any one of claims 1 to 4, wherein the sum of the atomic ratios of In and Sn to all metal elements in the second oxide semiconductor layer is smaller than the sum of the atomic ratios of In and Sn to all metal elements in the first oxide semiconductor layer.

17. The active matrix substrate according to any one of claims 1 to 4, wherein both the first oxide semiconductor layer and the second oxide semiconductor layer contain an In-Ga-Zn-O semiconductor, and the atomic ratio of In to all metal elements in the second oxide semiconductor layer is lower than the atomic ratio of In to all metal elements in the first oxide semiconductor layer.

18. A display device comprising an active matrix substrate according to any one of claims 1 to 4.

19. The display device according to claim 18, which is a liquid crystal display device.

20. The display device according to claim 18, which is an organic EL display device.

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