Active matrix substrate

Abstract

An active matrix substrate includes a plurality of oxide semiconductor TFTs including a first TFT and a second TFT. Each first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed from a normal direction of the substrate. The first lower electrode has a first light shielding portion overlapping the entire first channel region. The first light shielding portion includes a first metal film. Each second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion overlapping at least a portion of the second channel region. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film.

Description

Technical Field

[0001] This invention relates to active matrix substrates. Background Technology

[0002] The active matrix substrate used in a display device includes: a display area, which contains multiple pixel areas; and a non-display area outside the display area (also called a "bezel area" or "peripheral area"). A pixel area is the area corresponding to a pixel of the display device. Thin-film transistors (TFTs) are disposed in each pixel area as switching elements.

[0003] In recent years, the use of oxide semiconductors to replace amorphous silicon or polycrystalline silicon as the active layer material for TFTs has been proposed. This type of TFT is called an "oxide semiconductor TFT." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds compared to amorphous silicon TFTs. Furthermore, since oxide semiconductor films are formed using a simpler process than polycrystalline silicon films, they can also be applied to devices requiring large areas.

[0004] Sometimes, drive circuits such as gate drivers are integrally formed on a single chip in the non-display area of ​​an active matrix substrate. Furthermore, in devices with high requirements for narrow bezels, such as smartphones, it has been proposed to form multiplexing circuits, including source-shared driving (SSD) circuits, on a single chip in addition to the gate drivers. The SSD circuit distributes display signals from a single video signal line from each terminal of the source driver to multiple source buses. By incorporating the SSD circuit, the area for configuring terminals in the non-display area (terminal formation area) can be further narrowed. Additionally, the number of outputs from the source driver is reduced, allowing for a smaller circuit size and thus lowering the cost of the driver IC.

[0005] Peripheral circuits such as driving circuits or SSD circuits include TFTs. In this specification, TFTs configured as switching elements in each pixel of the display area are called "pixel TFTs," and TFTs constituting peripheral circuits are called "circuit TFTs." In addition, TFTs used as switching elements in SSD circuits are called "TFTs for SSD circuits," and TFTs used in gate driving circuits are called "TFTs for gate driving circuits."

[0006] Most oxide semiconductor TFTs are bottom-gate TFTs, but top-gate oxide semiconductor TFTs have also been proposed. For example, Patent Document 1 discloses a top-gate TFT in which a gate electrode is disposed on a portion of an oxide semiconductor layer, separated by a gate insulating layer. A light-shielding layer (light-shielding wiring) is provided on the substrate side of the oxide semiconductor layer to protect the portion of the oxide semiconductor layer that forms a channel from the influence of backlight.

[0007] For a portion of a circuit TFT (e.g., a TFT for an SSD circuit), a large on-current flow and a small driving load are required. Therefore, these TFTs preferably employ a top-gate structure. By using the light-shielding layer of the SSD circuit TFT as the lower gate electrode, the on-current flow can be further improved. Furthermore, from a manufacturing process point of view, in this case, other TFTs such as pixel TFTs formed on the same substrate preferably use the same oxide semiconductor film as the SSD circuit TFT and employ the same top-gate structure.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2020-076051 Summary of the Invention

[0011] The problem the invention aims to solve

[0012] However, the inventors of this invention have discovered that if top-gate type oxide semiconductor TFTs with the same structure are used as pixel TFTs and circuit TFTs (e.g., TFTs for SSD circuits), the differences in characteristics between the TFTs after degradation due to the driving of the active matrix substrate will increase. For example, it can be imagined that in pixel TFTs and SSD circuit TFTs, due to the different duty cycles of the driving signal applied to the gate, the degradation phenomena (threshold voltage shift direction, shift amount, etc.) will differ. Details of the degradation phenomena will be described later.

[0013] Therefore, if multiple oxide semiconductor TFTs with different duty cycles of driving signals are formed on the same substrate, it will be difficult to fully suppress characteristic degradation in all TFTs and achieve long lifespan, and the reliability of the active matrix substrate may decrease.

[0014] One embodiment of the present invention aims to improve reliability in an active matrix substrate having multiple oxide semiconductor TFTs by suppressing characteristic differences caused by degradation between TFTs.

[0015] Solution for solving the problem

[0016] This specification discloses the active matrix substrate described in the following items.

[0017] [Project 1]

[0018] An active matrix substrate includes: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate.

[0019] In the aforementioned active matrix substrate, the plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs.

[0020] Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer.

[0021] In each of the aforementioned first TFTs,

[0022] The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate.

[0023] The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film.

[0024] Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer.

[0025] In each of the aforementioned second TFTs,

[0026] The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate.

[0027] The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film.

[0028] [Project 2]

[0029] According to the active matrix substrate described in Project 1, wherein,

[0030] The first lower electrode of each of the first TFTs has a stacked structure comprising the first metal film and the first transparent conductive film.

[0031] [Project 3]

[0032] According to the active matrix substrate described in Project 2, wherein,

[0033] In the first lower electrode of each of the first TFTs, the first transparent conductive film is disposed on the first metal film in such a way that it covers the side and upper surface of the first metal film.

[0034] [Project 4]

[0035] According to the active matrix substrate described in Project 2, wherein,

[0036] In the first lower electrode of each of the first TFTs, the first metal film is disposed on the first transparent conductive film.

[0037] [Project 5]

[0038] The active matrix substrate according to any one of items 1 to 4, wherein...

[0039] In the second lower electrode of each of the second TFTs, when viewed from the normal direction of the substrate, the light-transmitting portion overlaps with the entire second channel region.

[0040] [Project 6]

[0041] The active matrix substrate according to any one of items 1 to 4, wherein...

[0042] The second lower electrode of each of the aforementioned second TFTs further includes a second light-shielding portion, which includes the aforementioned first metal film.

[0043] In the second lower electrode of each of the second TFTs, when viewed from the normal direction of the substrate, the light-transmitting portion overlaps only with a portion of the second channel region, and the second light-shielding portion overlaps with another portion of the second channel region.

[0044] [Project 7]

[0045] According to the active matrix substrate described in Project 1, wherein,

[0046] The aforementioned active matrix substrate further comprises a second insulating layer between the first insulating layer and the substrate.

[0047] In each of the aforementioned first TFTs, the first lower electrode is disposed between the substrate and the second insulating layer, and the first insulating layer and the second insulating layer are located between the first oxide semiconductor layer and the first lower electrode.

[0048] In each of the above-mentioned second TFTs, the second lower electrode is disposed between the second insulating layer and the first insulating layer, the first insulating layer is located between the second oxide semiconductor layer and the second lower electrode, but the second insulating layer is not located between the second oxide semiconductor layer and the second lower electrode.

[0049] [Project 8]

[0050] The active matrix substrate according to any one of items 1 to 7, wherein...

[0051] In each of the aforementioned second TFTs, the second lower electrode is electrically connected to the second gate electrode and functions as the lower gate electrode of each of the aforementioned second TFTs.

[0052] [Project 9]

[0053] The active matrix substrate according to any one of items 1 to 8, wherein...

[0054] When the active matrix substrate is driven, the duty cycle of the driving signal applied to the second gate electrode of each of the second TFTs is higher than the duty cycle of the driving signal applied to the first gate electrode of each of the first TFTs.

[0055] [Project 10]

[0056] According to the active matrix substrate described in Project 9, wherein...

[0057] When the aforementioned active matrix substrate is driven, the duty cycle of the driving signal applied to the first gate electrode of each of the aforementioned first TFTs is less than 5%.

[0058] The duty cycle of the drive signal applied to the second gate electrode of each of the second TFTs is 10% or more.

[0059] [Project 11]

[0060] The active matrix substrate according to any one of items 1 to 10, wherein,

[0061] The aforementioned active matrix substrate also features:

[0062] The display area contains multiple pixel regions;

[0063] The non-display area is located around the display area and includes a circuit forming area where peripheral circuitry is formed.

[0064] Multiple source buses and multiple gate buses are supported on the aforementioned substrate;

[0065] Multiple pixel TFTs, each disposed in a separate pixel region; and

[0066] Multiple TFT circuits constitute the aforementioned peripheral circuit.

[0067] The source electrode of each pixel TFT is electrically connected to one of the plurality of source buses, and the gate electrode of each pixel TFT is electrically connected to one of the plurality of gate buses.

[0068] The aforementioned plurality of first TFTs include the aforementioned plurality of pixel TFTs.

[0069] The aforementioned plurality of second TFTs include at least a portion of the aforementioned plurality of circuit TFTs.

[0070] [Project 12]

[0071] According to the active matrix substrate described in Project 11, wherein,

[0072] The aforementioned peripheral circuitry includes an SSD circuit that distributes display signals to n of the multiple source buses.

[0073] The aforementioned plurality of second TFTs include a plurality of SSD circuit TFTs constituting the aforementioned SSD circuit, and each SSD circuit TFT supplies a video signal to one of the corresponding source buses among the aforementioned n source buses.

[0074] [Project 13]

[0075] The active matrix substrate according to any one of items 2 to 6, wherein...

[0076] The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film.

[0077] The second lower electrode of each of the second TFTs is electrically connected to the wiring.

[0078] [Project 14]

[0079] The active matrix substrate according to any one of items 2 to 6, wherein...

[0080] The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film and the aforementioned first transparent conductive film.

[0081] When viewed from the normal direction of the substrate, the portion of the wiring that does not overlap with the second lower electrode of each of the second TFTs has a low resistance portion, which includes the first metal film and the first transparent conductive film. The portion of the wiring that overlaps with the second channel region of each of the second TFTs has a high resistance portion, which includes the first transparent conductive film but does not include the first metal film. The high resistance portion functions as the light transmission portion of the second lower electrode.

[0082] [Project 15]

[0083] The active matrix substrate according to any one of items 1 to 14, wherein,

[0084] The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

[0085] [Project 16]

[0086] According to the active matrix substrate described in Project 15, wherein,

[0087] The aforementioned In-Ga-Zn-O semiconductors include a crystalline portion.

[0088] Invention Effects

[0089] According to one embodiment of the present invention, an active matrix substrate is provided having a plurality of oxide semiconductor TFTs, and reliability can be improved by suppressing characteristic differences between TFTs caused by degradation. Attached Figure Description

[0090] Figure 1 This is a schematic diagram illustrating an example of the planar structure of an active matrix substrate 1000.

[0091] Figure 2A This is a top view illustrating the first TFT 100 and the second TFT 200 in the active matrix substrate 1000.

[0092] Figure 2B yes Figure 2A The cross-sectional view of line IIb-IIb' shown.

[0093] Figure 2C This is a cross-sectional view showing another example of the first TFT100 and the second TFT200.

[0094] Figure 3A It is shown Figure 2A A diagram showing an example of the cross-sectional structure of line III-III'.

[0095] Figure 3B It is shown Figure 2A A diagram showing another example of the cross-sectional structure of line III-III'.

[0096] Figure 4A This is a top view illustrating the first TFT 101 and the second TFT 201 in the active matrix substrate 1001 of Modified Example 1.

[0097] Figure 4B yes Figure 4AThe cross-sectional view of line IVb-IVb' shown.

[0098] Figure 5 It is shown Figure 4A A diagram showing an example of the cross-sectional structure of the V-V' line.

[0099] Figure 6A This is a top view illustrating the first TFT 102 and the second TFT 202 in the active matrix substrate 1002 of Modified Example 2.

[0100] Figure 6B yes Figure 6A The cross-sectional view of line VIb-VIb' is shown.

[0101] Figure 7A This is a top view illustrating the first TFT 103 and the second TFT 203 in the active matrix substrate 1003 of Modified Example 3.

[0102] Figure 7B yes Figure 7A The cross-sectional view of line VIIb-VIIb' shown.

[0103] Figure 8 This is a cross-sectional view illustrating the first TFT 104 and the second TFT 204 in the active matrix substrate 1004 of Modified Example 4.

[0104] Figure 9 This is a cross-sectional view illustrating the pixel TFT 20 and the SSD circuit TFT 21 in the active matrix substrate 1000.

[0105] Figure 10 This is a top view showing an example of an active matrix substrate 1000 containing pixel TFTs 20 and SSD circuit TFTs 21.

[0106] Figure 11 This is a diagram used to illustrate the structure and operation of the SSD circuit Sc.

[0107] Figure 12 This is a timing diagram illustrating the driving signal (SSD control signal) applied to the TFT 21 of the SSD circuit and the driving signal (scan signal) applied to the pixel electrode 20.

[0108] Figure 13A This is a cross-sectional view showing TFT901, which is used as a TFT for SSD circuitry in an active matrix substrate in an embodiment.

[0109] Figure 13B This is a cross-sectional view showing TFT902, which is used as a TFT for SSD circuitry in an active matrix substrate of a comparative example.

[0110] Figure 14This is a graph showing the offset ΔVth of the threshold voltage caused by the gate bias stress of TFTs 901 and 902.

[0111] Figure 15 This is a diagram illustrating a process flow for explaining an example of a manufacturing method for an active matrix substrate 1000. Detailed Implementation

[0112] The following describes the insights discovered by the inventors of this invention.

[0113] The degradation of top-gate oxide semiconductor TFTs depends on the voltage applied to the gate, the duration of the applied voltage, and the presence or absence of incident light into the channel region of the oxide semiconductor layer. In other words, in top-gate oxide semiconductor TFTs, the degradation phenomena caused by gate bias stress vary greatly depending on the driving signal applied to the gate and the presence or absence of a light-shielding layer that blocks light from the channel region. The degradation phenomena discussed here include the direction of the TFT threshold voltage shift (a shift towards the positive voltage side is called "positive shift," and a shift towards the negative voltage side is called "negative shift") and the magnitude of the threshold voltage shift. Furthermore, the "channel region" refers to the area in the oxide semiconductor layer that overlaps with the gate (top gate) when viewed from the normal direction of the substrate.

[0114] Table 1 shows an example of the stress characteristics of an oxide semiconductor TFT. Here, the relationship between the gate applied voltage (positive and negative bias), incident light in the omnidirectional channel region, and the threshold voltage shift caused by the gate bias stress is shown.

[0115] Table 1

[0116]

[0117] As shown in Table 1, when a positive bias voltage is applied to the gate of an oxide semiconductor TFT for a specified time, the threshold voltage will shift to the positive side due to the gate bias stress, regardless of whether there is incident light in the omnidirectional channel region.

[0118] On the other hand, when a negative bias voltage is applied to the gate of the oxide semiconductor TFT for a specified time while light is incident on the channel region, the threshold voltage shifts to the negative side. This is conceivable because the incident light on the channel region of the oxide semiconductor layer increases oxygen defects in the oxide semiconductor, resulting in lower resistance. In this specification, the degradation caused by light incident on the oxide semiconductor layer is sometimes referred to as "optical degradation."

[0119] However, when a negative bias voltage is applied to the gate of the oxide semiconductor TFT for a specified time without light incident on the channel region, the threshold voltage shifts to the negative side, but the shift is very small. Therefore, it can be seen that, for example, by providing a light-shielding layer to reduce the amount of light incident on the channel region, the negative shift of the threshold voltage caused by light degradation can be suppressed.

[0120] As described above, multiple TFTs with different drive signals applied to their gates are typically formed on the same active matrix substrate. Due to the differences in the drive signals, the degradation phenomena affecting the components may vary among these TFTs. According to Table 1, in TFTs where the proportion of time with a negative bias applied to the gate is large (i.e., the off duty cycle of the drive signal applied to the gate is large), the negative shift of the threshold voltage caused by light degradation is larger. Conversely, in TFTs where the proportion of time with a positive bias applied to the gate is large (i.e., the on duty cycle of the drive signal applied to the gate is large), the positive shift of the threshold voltage is larger.

[0121] In this specification, the duty cycle of the drive signal is simply referred to as the "duty cycle". The duty cycle refers to the proportion of time within one cycle (here, one horizontal scan period) that the drive signal applied to the gate is at a high level. In other words, in a TFT supplied with a drive signal of a high duty cycle, the period of conduction is greater than that of one horizontal scan period. Furthermore, one horizontal scan period (1H) refers to the time from selecting one pixel row to selecting the next row in a linear sequential scan. The time from selecting a row to selecting that row again is called the vertical scan period (1V) or frame.

[0122] As an example, such as Figure 12 As shown, the gate of a pixel TFT is applied with a drive signal having a relatively low duty cycle (small cutoff duty cycle). The duty cycle is, for example, less than 1%. Therefore, in a pixel TFT, a negative shift in the threshold voltage becomes a problem. In contrast, the gate of a TFT for an SSD circuit is applied with a drive signal having a relatively high duty cycle (large on-state duty cycle). The duty cycle is, for example, about 35% or about 50%. Therefore, in a TFT for an SSD circuit, the duty cycle of the drive signal is hundreds of times that of a pixel TFT, and compared to a pixel TFT, the positive shift in the threshold voltage associated with the driving of the active matrix substrate becomes much larger.

[0123] Thus, the degradation phenomena that should be improved in each TFT vary depending on the duty cycle of the driving signal. Therefore, it is difficult to simultaneously suppress the characteristic degradation of multiple TFTs with different duty cycles and achieve long lifespan.

[0124] In response, the inventors of this application discovered that by varying the TFT structure (particularly the light-shielding structure pointing towards the channel region) according to the duty cycle of the driving signal, the characteristics of each TFT can be optimized simultaneously. Specifically, in TFTs with a small duty cycle of the driving signal (e.g., pixel TFTs), a light-shielding layer is provided to suppress negative shift of the threshold voltage. On the other hand, in TFTs with a large duty cycle of the driving signal (e.g., TFTs for SSD circuits), a predetermined amount of backlight light is intentionally incident on the channel region to cause light degradation. Thus, a portion or all of the positive shift of the threshold voltage can be offset by the negative shift of the threshold voltage caused by light degradation, thereby suppressing positive shift of the threshold voltage. In this specification, the effect of negative shift of the threshold voltage when a negative bias voltage is applied, which utilizes this light degradation, is referred to as the "negative shift effect of the threshold voltage (or simply the "negative shift effect")".

[0125] In TFTs with large duty cycles for drive signals (e.g., TFTs for SSD circuits), to incident a specified amount of light into the channel region, a structure without a light-shielding layer on the substrate side of the oxide semiconductor layer can be considered. This suppresses positive shift of the threshold voltage by utilizing the negative shift effect caused by light degradation. However, since the light-shielding layer cannot function as the lower gate electrode, the TFT capability (mobility) per unit area decreases, and the desired on-state current may not be obtained. Alternatively, a structure can be considered where the light-shielding layer is provided to shield only a portion of the channel region, allowing the light-shielding layer to function as the lower gate electrode. However, since the area of ​​the lower gate electrode is smaller relative to the channel region, sometimes insufficient TFT capability is not obtained.

[0126] Based on the above insights, the inventors of this application conducted research and discovered that in a TFT subjected to a drive signal with a large duty cycle, by providing a transparent lower electrode formed of a transparent conductive film on the substrate side of the channel region, it is possible to ensure both high mobility and suppress positive shift of the threshold voltage. According to this TFT structure, backlight light is not blocked by the transparent lower electrode and is incident on the channel region; therefore, the positive shift of the threshold voltage can be suppressed by utilizing the negative shift effect caused by light degradation. Furthermore, by utilizing the transparent lower electrode as a lower gate electrode, the conduction current can be further improved.

[0127] On the other hand, in a TFT subjected to a drive signal with a small duty cycle, a light-shielding lower electrode formed of a metal film is provided on the substrate side of the channel region. This light-shielding lower electrode functions as a light-shielding layer to suppress backlight incidence into the channel region, thus suppressing negative shift of the threshold voltage. Furthermore, by also functioning the light-shielding electrode as a lower gate electrode, mobility can be improved.

[0128] Table 2 illustrates the relationship between the duty cycle of the drive signal, the structure of the lower electrode of the TFT, the stress resistance of the TFT, and the mobility.

[0129] Table 2

[0130]

[0131] As shown in Table 2, by setting a light-shielding lower electrode made of a metal film in a TFT with a small duty cycle of the driving signal (e.g., a pixel TFT), and setting a transparent lower electrode made of a transparent conductive film in a TFT with a large duty cycle of the driving signal (e.g., a TFT for SSD circuits), high mobility can be ensured and characteristic degradation can be suppressed, thereby improving reliability, regardless of which TFT is used.

[0132] In one embodiment of this disclosure, a portion of a plurality of oxide semiconductor TFTs formed on an active matrix substrate has a lower electrode including a light-shielding portion. The light-shielding portion of the lower electrode overlaps with the entire channel region when viewed from the normal direction of the substrate. The lower electrode may include a metal film or a transparent conductive film. In this specification, a TFT structure having a lower electrode with a light-shielding portion overlapping the entire channel region when viewed from the normal direction of the substrate is referred to as a "light-shielding structure," and a TFT having a light-shielding structure is referred to as a "first TFT." On the other hand, in another portion of the plurality of oxide semiconductor TFTs, the lower electrode includes a light-transmitting portion that at least partially overlaps with the channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a transparent conductive film but does not include a light-shielding metal film. This lower electrode may be a transparent electrode or may include a metal film in the portion other than the light-transmitting portion. A TFT structure having a lower electrode that has a light-transmitting portion that overlaps entirely or partially with the channel region when viewed from the normal direction of the substrate is called a "non-shielding structure", and a TFT structure having a non-shielding structure is called a "second TFT".

[0133] Furthermore, in embodiments of this disclosure, the plurality of oxide semiconductor TFTs formed on the active matrix substrate may include at least a first TFT with a light-shielding structure and a second TFT with a non-light-shielding structure, or may also include TFTs with other structures. Additionally, the application of each TFT is not limited. The first TFT is not limited to a pixel TFT; for example, it may be a TFT constituting a gate driving circuit for a gate driver. Furthermore, the second TFT is not limited to a TFT for an SSD circuit; it may be an anti-oscillation transistor in a TFT for a gate driving circuit.

[0134] The above examples illustrate how the TFT structure can be optimized based on the duty cycle of the drive signal. However, in embodiments of this disclosure, the TFT structure used for each TFT can be appropriately selected from the viewpoint of the required characteristics of each TFT or the manufacturing process. For example, a light-shielding structure can be used in TFTs requiring low leakage current, while a non-light-shielding structure can be used in TFTs requiring high on-current.

[0135] (First Embodiment)

[0136] Hereinafter, the active matrix substrate of the first embodiment will be described with reference to the accompanying drawings.

[0137] Figure 1 This diagram schematically illustrates an example of the planar structure of an active matrix substrate 1001. The active matrix substrate 1001 has: a display area DR, which contributes to display; and a peripheral area (border area) FR, located outside the display area DR. The display area DR comprises a plurality of pixel areas PIX arranged in a matrix. A pixel area PIX (sometimes simply referred to as a "pixel") is an area corresponding to a pixel of a display device. The non-display area FR is located around the display area DR and is an area that does not contribute to display.

[0138] The active matrix substrate 1001 includes, in the display area DR: a substrate 1; a plurality of pixel TFTs 20 supported on the substrate 1; a plurality of pixel electrodes PE; a plurality of gate buses GL1 to GLx (x is an integer of 2 or more, hereinafter collectively referred to as "gate bus GL") supplying gate signals to the pixel TFTs 20; and a plurality of source buses SL1 to SLy (y is an integer of 2 or more, hereinafter collectively referred to as "source bus SL") supplying source signals to the pixel TFTs 20. Each pixel area PIX is defined, for example, by the gate bus GL and the source bus SL. The source bus SL extends in a direction intersecting with the gate bus GL.

[0139] Each pixel TFT 20 and each pixel electrode PE are correspondingly arranged with one pixel region PIX among multiple pixel regions PIX. The gate electrode of the pixel TFT 20 is electrically connected to one gate bus GL in the gate bus GL, and the source electrode is electrically connected to one source bus SL in the source bus SL. The drain electrode is electrically connected to the pixel electrode PE.

[0140] When the active matrix substrate 1001 is applied to a display device in a transverse electric field mode such as FFS (Fringe Field Switching) mode, a common electrode (common electrode) CE is provided for multiple pixels in the active matrix substrate 1001.

[0141] In the non-display area FR, peripheral circuits such as drivers can be set. For example, the gate driver GD that drives the gate bus GL and the SSD circuit Sc that time-divisions to drive the source bus SL can also be formed as a single chip. The SSD circuit Sc is connected, for example, to the source driver SD that is mounted in a COG (Chip on Glass) manner. The peripheral circuits such as the SSD circuit and the gate drive circuit each contain multiple circuit TFTs.

[0142] The SSD circuit Sc is positioned between the source driver SD and the display area DR. The source driver SD includes multiple output terminals (not shown). Multiple signal output lines (video signal lines) VL1 to VLz (z is an integer greater than or equal to 2, hereinafter collectively referred to as "signal output lines VL") are located in the area between the source driver SD and the SSD circuit Sc. The SSD circuit Sc distributes the display signal V supplied by one signal output line VL to two or more source buses SL (z < y). This reduces the number of output terminals (output pins) of the source driver SD, thus reducing the area of ​​the non-display area FR (narrowing the bezel).

[0143] Although not illustrated, the active matrix substrate 1000 may also include electrodes for multiple touch sensors, as well as multiple touch wirings for driving and / or detecting the touch sensors. This active matrix substrate is used, for example, in in-cell touch panel display devices. In-cell touch panel display devices may incorporate self-capacitance type touch sensors or mutual capacitance type touch sensors.

[0144] <Structure of Oxide Semiconductor TFT>

[0145] The active matrix substrate of this embodiment includes a plurality of oxide semiconductor TFTs having a top gate structure. The plurality of oxide semiconductor TFTs include: a first TFT having a light-shielding lower electrode; and a second TFT having a transparent lower electrode.

[0146] The active matrix substrate of this embodiment includes a plurality of first TFTs and a plurality of second TFTs, but here, only one first TFT and one second TFT are shown to illustrate its configuration.

[0147] Figure 2A and Figure 2B These are schematic top views and cross-sectional views illustrating the first TFT100 and the second TFT200, respectively. Figure 2B Show along Figure 2A The cross section of line IIb-IIb' in the middle.

[0148] ·No.1TFT100

[0149] The first TFT100 is a top-gate type TFT supported on a substrate 1 and having an oxide semiconductor layer 6A as an active layer.

[0150] The first TFT100 includes: a lower electrode (first lower electrode) 3A disposed on a substrate 1; an oxide semiconductor layer (first oxide semiconductor layer) 6A disposed on the lower electrode 3A with a first insulating layer 5 in between; a gate insulating layer (first gate insulating layer) 7A disposed on the oxide semiconductor layer 6A; a gate electrode (first gate electrode) 8A disposed on the gate insulating layer 7A; and a source electrode (first source electrode) 9As and a drain electrode (first drain electrode) 9Ad.

[0151] When viewed from the normal direction of the main surface of the substrate 1, the oxide semiconductor layer 6A has: a channel region 61c; and a first region and a second region, which are located on both sides of the channel region 61c, respectively.

[0152] Region 1 and Region 2 are low-resistance regions with resistivity lower than that of channel region 61c. Region 1 and Region 2 can also be conductive regions. A portion 61s of Region 1 is electrically connected to the source electrode 9As. A portion 61d of Region 2 is electrically connected to the drain electrode 9Ad. In this specification, the region 61s in Region 1 that is electrically connected to the source electrode 9As is referred to as the "source contact region," and the region 61d in Region 2 that is electrically connected to the drain electrode 9Ad is referred to as the "drain contact region." Furthermore, "channel region 61c" refers to the region that overlaps with the gate electrode 8A when viewed from the normal direction of substrate 1 and is located between the source contact region 61s and the drain contact region 61d.

[0153] The lower electrode 3A is located between the substrate 1 and the first insulating layer 5. The lower electrode 3A includes a region (referred to as the "overlapping region") that overlaps with the channel region 61c when viewed from the normal direction of the substrate 1.

[0154] The lower electrode 3A has a light-shielding portion (also called the "first light-shielding portion") 31m that includes a first metal film m1. The first metal film m1 can be any light-shielding metal film, and can be a single-layer film or a multilayer film. The light-shielding portion 31m is configured to overlap with the entire channel region 61c when viewed from the normal direction of the substrate 1. That is, the entire overlapping region 31 of the lower electrode 3A is the light-shielding portion 31m. As a result, the negative shift of the threshold voltage caused by light degradation can be suppressed more effectively. When viewed from the normal direction of the substrate 1, the light-shielding portion 31m may also overlap with a part or the entire region (called the "intercalation region") located in the oxide semiconductor layer 6A between the channel region 61c and the source contact region 61s and the drain contact region 61d. By also shielding the intercalation region, the amount of light incident on the channel region 61c can be further reduced more effectively.

[0155] In the illustrated example, the lower electrode 3A has a laminated structure comprising a first metal film m1 and a first transparent conductive film t1 that is light-transmitting. The light-shielding portion 31m is defined by the first metal film m1. Here, the first transparent conductive film t1 is disposed on the first metal film m1. The first transparent conductive film t1 may also cover the upper surface and side surfaces of the first metal film m1.

[0156] In addition, such as Figure 2C As shown, the lower electrode 3A may also consist only of a metal layer (first metal film m1) without the transparent conductive film. That is, the entire lower electrode 3A may be a light-shielding part 31m.

[0157] The lower electrode 3A can be fixed at a fixed potential (e.g., the source potential) or it can be electrically floating. Alternatively, the lower electrode 3A can also function as the lower gate electrode of the first TFT 100. For example, the lower electrode 3A can also be electrically connected to the gate electrode 8A.

[0158] The gate insulating layer 7A is configured, for example, to cover a portion of the oxide semiconductor layer 6A (at least the channel region 61c), but not to cover the source contact region 61s and the drain contact region 61d. The gate insulating layer 7A may also be located only between the oxide semiconductor layer 6A and the gate electrode 8A. When viewed from the normal direction of the substrate 1, the periphery of the gate insulating layer 7A (or the periphery of the upper surface of the gate insulating layer 7A if the gate insulating layer 7A has a tapered shape) may also be aligned with the periphery of the gate electrode 8A. This structure can be obtained by using a mask for patterning the gate electrode 8A or by patterning the gate insulating layer 7A using the gate electrode 8A as a mask.

[0159] The gate electrode 8A is formed, for example, using the same conductive film (conductive film for the gate) as the gate bus GL. In this specification, the layer containing the electrode and wiring formed using the conductive film for the gate is referred to as the "gate metal layer".

[0160] The oxide semiconductor layer 6A, the gate insulating layer 7A, and the gate electrode 8A are covered by an interlayer insulating layer 10. The interlayer insulating layer 10 can be a reducing insulating film (e.g., a silicon nitride film) capable of reducing the oxide semiconductor. This suppresses the increase in resistivity of the portion of the oxide semiconductor layer 6A in contact with the interlayer insulating layer 10. The interlayer insulating layer 10 has a source opening p1 that exposes the source contact region 61s and a drain opening p2 that exposes the drain contact region 61d.

[0161] A source electrode 9As is formed on the interlayer insulating layer 10 and within a source opening p1, connecting to the source contact region 61s of the oxide semiconductor layer 6A within the source opening p1. A drain electrode 9Ad is formed on the interlayer insulating layer 10 and within a drain opening p2, connecting to the drain contact region 61d of the oxide semiconductor layer 6A within the drain opening p2. The source electrode 9As and the drain electrode 9Ad can be formed using the same conductive film as the source bus SL. In this specification, the layer containing the electrodes and wiring formed using the source conductive film is referred to as the "source metal layer".

[0162] When the first TFT100 is used as a pixel TFT ( Figure 1 In this case, gate electrode 8A is electrically connected to the corresponding gate bus GL, source electrode 9As is electrically connected to the corresponding source bus SL, and drain electrode 9Ad is electrically connected to the corresponding pixel electrode PE.

[0163] ·2 TFT200

[0164] Like the first TFT 100, the second TFT 200 is a top-gate TFT supported on the substrate 1 and having an oxide semiconductor layer 6B as the active layer. The difference between the second TFT 200 and the first TFT 100 is that the lower electrode 3B has a light-transmitting portion 32t. Other configurations may be the same as the first TFT 100. For configurations identical to the first TFT 100, descriptions are sometimes omitted.

[0165] The second TFT 200 includes: a lower electrode (second lower electrode) 3B disposed on a substrate 1; an oxide semiconductor layer (second oxide semiconductor layer) 6B disposed on the lower electrode 3B with a first insulating layer 5 in between; a gate insulating layer (second gate insulating layer) 7B disposed on the oxide semiconductor layer 6B; a gate electrode (second gate electrode) 8B disposed on the gate insulating layer 7B; and a source electrode (second source electrode) 9Bs and a drain electrode (second drain electrode) 9Bd.

[0166] The oxide semiconductor layer 6B may be formed from the same oxide semiconductor film as the oxide semiconductor layer 6A of the first TFT 100. Similarly, the gate electrode 8B may be formed using the same conductive film (e.g., within the gate metal layer) as the gate electrode 8A of the first TFT 100. The source electrode 9Bs and drain electrode 9Bd may be formed using the same conductive film (e.g., within the source metal layer) as the source electrode 9As and drain electrode 9Ad of the first TFT 100.

[0167] Similar to the first TFT 100, the oxide semiconductor layer 6B has: a channel region 62c that overlaps with the gate electrode 8B when viewed from the normal direction of the main surface of the substrate 1; and a first region and a second region located on opposite sides of the channel region 62c. The first region includes a source contact region 62s electrically connected to the source electrode 9Bs. The second region includes a drain contact region 62d electrically connected to the drain electrode 9Bd.

[0168] The lower electrode 3B is located between the substrate 1 and the first insulating layer 5. The lower electrode 3B includes a region (referred to as the "overlapping region") that overlaps with the channel region 62c when viewed from the normal direction of the substrate 1.

[0169] The lower electrode 3B has a light-transmitting portion 32t that allows light to pass through in the thickness direction. The light-transmitting portion 32t includes a first transparent conductive film t1 that is transparent to light, but does not include a light-shielding conductive film (such as a metal film). The light-transmitting portion 32t overlaps with at least a portion of the channel region 61c when viewed from the normal direction of the substrate 1. In other words, the overlapping region 32 of the lower electrode 3B at least partially includes the light-transmitting portion 32t. The light-transmitting portion 32t may also overlap with the entire channel region 61c when viewed from the normal direction of the substrate 1. By providing the light-transmitting portion 32t on the lower electrode 3B, light (backlight) can pass through the light-transmitting portion 32t from the substrate 1 side and enter the channel region 62c. Therefore, the positive shift of the threshold voltage can be suppressed by utilizing the negative shift effect caused by light degradation.

[0170] In the illustrated example, the lower electrode 3B is a transparent electrode that contains only a transparent conductive layer (here, the first transparent conductive film t1). That is, the entire lower electrode 3B is the light-transmitting portion 32t. Furthermore, as described later, the lower electrode 3B may also partially contain a metal film (e.g., the first metal film m1). In this case, when viewed from the normal direction of the substrate 1, the portion of the lower electrode 3B that does not contain the first metal film m1 becomes the light-transmitting portion 32t.

[0171] The lower electrode 3B can also function as the lower gate electrode of the second TFT 200. For example, the lower electrode 3B can also be electrically connected to the gate electrode 8B. By making the lower electrode 3B function as the lower gate electrode, the mobility of the second TFT 200 can be improved more effectively. In this case, it is preferable that the lower electrode 3B (lower gate electrode) overlaps with the entire channel region 62c when viewed from the normal direction of the substrate 1. Thus, the mobility of the second TFT 200 can be further improved. Alternatively, the lower electrode 3B can be fixed at a fixed potential (e.g., the source potential) or it can be electrically floating.

[0172] In the second TFT 200, similar to the first TFT 100, a gate electrode 8B is disposed on a portion of the oxide semiconductor layer 6B, separated by a gate insulating layer 7B. An interlayer insulating layer 10 extends from the gate electrode 8B, and a source electrode 9Bs and a drain electrode 9Bd are disposed on the interlayer insulating layer 10. A source opening p3 exposing the source contact region 62s and a drain opening p4 exposing the drain contact region 62d are formed in the interlayer insulating layer 10. The source electrode 9Bs is connected to the source contact region 62s of the oxide semiconductor layer 6B within the source opening p3. The drain electrode 9Bd is connected to the drain contact region 62d of the oxide semiconductor layer 6B within the drain opening p4.

[0173] <Wiring using the first metal film m1>

[0174] In the active matrix substrate 1000, the first metal film m1 can be used not only for the lower electrode 3A, but also for various electrodes and wiring (wiring for peripheral circuits such as gate drivers, wiring for winding, etc.). These electrodes and wiring can be metal wiring formed solely by the first metal film m1, or they can be stacked wiring that includes the first metal film m1 and the first transparent conductive film t1.

[0175] For example, when a predetermined driving signal is applied to the lower electrode 3B or the lower electrode 3B is fixed at a predetermined potential, the lower electrode 3B is electrically connected to a wiring formed by the first metal film m1. The lower electrode 3B may also be part of such wiring. In this case, only the portion of the wiring that becomes the light-transmitting portion 32t of the lower electrode 3B needs to be transparent; the other portions may contain a low-resistance metallic material (e.g., the first metal film m1).

[0176] Figure 3A and Figure 3B These are cross-sectional views of line III-III' of the second TFT200 (cross-sectional views in the channel width direction).

[0177] The lower electrode 3B is electrically connected to wiring L1. Figure 3A In the example shown, wiring L1 is a multilayer wiring comprising a first metal film m1 and a first transparent conductive film t1. Alternatively, as... Figure 3B As shown, wiring L1 can also be a metal wiring that includes the first metal film m1.

[0178] The lower electrode 3B can also be considered part of the wiring L1. That is, when viewed from the normal direction of the substrate 1, the portion of the wiring L1 that does not overlap with the channel region 62c has a low-resistance portion Lm containing the first metal film m1, and the portion that overlaps with the channel region 62c has a high-resistance portion Lt. The high-resistance portion Lt contains the first transparent conductive film t1 but does not contain the first metal film m1. Part or all of the high-resistance portion Lt functions as the light-transmitting portion 32t of the lower electrode 3B.

[0179] Furthermore, although not shown, the lower electrode 3A of the first TFT 100 can also be connected to the wiring containing the first metal film m1. Alternatively, the lower electrode 3A may also be part of the wiring containing the first metal film m1. In this case, the portion of such wiring that overlaps with the channel region 61c when viewed from the normal direction of the substrate 1 functions as a light-shielding portion 31m.

[0180] (Effect)

[0181] According to this embodiment, the TFT structure can be optimized for each of the multiple oxide semiconductor TFTs formed on the active matrix substrate, based on the application or required characteristics. Therefore, characteristic degradation (threshold voltage shift) of each TFT can be suppressed based on degradation phenomena. As a result, the difference in characteristics caused by degradation between TFTs can be reduced, thus obtaining an active matrix substrate with high reliability.

[0182] Specifically, in a portion of the multiple oxide semiconductor TFTs (the first TFT) 100, a lower electrode 3A (light-shielding structure) is provided on the substrate 1 side of the oxide semiconductor layer 6A, functioning as a light-shielding layer. This reduces the amount of light (backlight) incident on the channel region 61c of the oxide semiconductor layer 6A, thus suppressing excessive negative shift of the threshold voltage. Therefore, both desired TFT characteristics and improved reliability can be ensured. The light-shielding structure is suitable for TFTs with relatively low duty cycles of the drive signal applied to the gate. This is because TFTs with low duty cycles (large cutoff duty cycles) experience large negative shifts in the threshold voltage due to the application of negative bias stress. For example, a light-shielding structure can be used for TFTs where the duty cycle of the drive signal supplied to its gate is less than 10%, preferably less than 5%, for example, less than 1%.

[0183] As an example, it is preferable to apply a light-shielding structure in the pixel TFT (duty cycle of the driving signal: for example, less than 1%). For pixel TFTs, a low cutoff leakage current is required. This is because if the cutoff leakage current is large, the retention characteristics of the potential written to the pixel electrode will deteriorate, potentially causing display defects such as uneven brightness or flickering. By equipping the pixel TFT with a light-shielding structure, the negative shift of the threshold voltage caused by light degradation can be suppressed, thus suppressing the increase in cutoff leakage current.

[0184] On the other hand, in another portion of the multiple oxide semiconductor TFTs (the second TFT) 200, a lower electrode 3B (non-shielding structure) including a light-transmitting portion 32t is provided on the substrate 1 side of the oxide semiconductor layer 6B. In the non-shielding structure, a portion of the backlight light is transmitted through the light-transmitting portion 32t and incident on the oxide semiconductor layer 6B. Therefore, by generating a negative shift in the threshold voltage caused by light degradation, a positive shift in the threshold voltage when a positive bias stress (a positive bias is applied to the gate) is suppressed, improving reliability. The non-shielding structure is suitable for TFTs with relatively high duty cycles of the drive signal. This is because TFTs with high duty cycles (large on-state duty cycles) experience large positive shifts in the threshold voltage caused by the application of positive bias stress. For example, a non-shielding structure can be used for TFTs where the duty cycle of the drive signal supplied to its gate is 5% or more, preferably 10% or more.

[0185] As an example, it is preferable to apply a non-shielding structure in the TFT for SSD circuits (duty cycle of the drive signal: for example, around 33% (which varies with the value of n described later)). High on-state current is required for TFTs used in SSD circuits. By giving the TFT for SSD circuits a non-shielding structure, the shift of the threshold voltage to the positive side can be reduced, thus suppressing the decline in conduction characteristics caused by degradation. Furthermore, by using the oxide semiconductor layer 6B as the lower gate electrode, mobility can be further improved.

[0186] Furthermore, in non-shielded structures, the cutoff leakage current can sometimes increase due to the negative offset effect of the threshold voltage. Therefore, non-shielded structures are suitable for TFTs used in applications where cutoff leakage is not a significant issue. For example, in TFTs used in SSD circuits, because the time that should be cut off beforehand is as short as a few μs within one horizontal scan period (1H), the amount of pre-charged charge is much greater than that of pixel TFTs, and the potential difference Vds with the leakage destination is small (greater than 0 and below the source amplitude voltage). Therefore, even if the cutoff leakage current increases, the problem is not as significant as in pixel TFTs.

[0187] Furthermore, according to this embodiment, by using different lower electrode structures, TFTs with light-shielding structures and those without light-shielding structures can be formed respectively. Therefore, TFTs with optimal TFT structures that can suppress characteristic degradation can be formed through a simple process, depending on the application or duty cycle.

[0188] (Modified Example)

[0189] Hereinafter, a modified example of the active matrix substrate of this embodiment will be described with reference to the accompanying drawings. In the following drawings, for... Figures 2A to 3B The same constituent elements are labeled with the same reference numerals. Descriptions of the same constituent elements are appropriately omitted.

[0190] <Variation Example 1>

[0191] Figure 4A This is a top view showing the first TFT 101 and the second TFT 201 in the active matrix substrate 1001 of Modified Example 1. Figure 4B yes Figure 4A The cross-sectional view of the IVb-IVb' line is shown. Additionally... Figure 5 yes Figure 4A The cross-sectional view of the V-V' line is shown.

[0192] The first TFT101 in Modified Example 1 and Figure 2A and Figure 2B The difference in the first TFT 100 shown is that a first metal film m1 is disposed on the first transparent conductive film t1 in the lower electrode 3A. In this modified example, similar to the first TFT 100, when viewed from the normal direction of the substrate 1, the first metal film m1, which serves as the light-shielding portion 31m, is configured to overlap with the entire channel region 61c. The other structures are the same as those of the first TFT 100.

[0193] On the other hand, the second TFT201 has the same Figure 2A and Figure 2B The second TFT200 shown has the same structure.

[0194] Alternatively, the active matrix substrate 1001 in this modified example may further have wiring using the first metal film m1. For example... Figure 5 As shown, the lower electrode 3B of the second TFT 201 can also be part of wiring L1. Wiring L1 is a stacked wiring that includes a first transparent conductive film t1 and a first metal film m1 disposed on the first transparent conductive film t1. The portion of wiring L1 that overlaps with the channel region 62c of the second TFT 201 may not include the first metal film m1. Alternatively, although not shown, wiring L1 can also be a metal wiring that includes the first metal film m1.

[0195] <Variation Example 2>

[0196] Figure 6A This is a top view showing the first TFT 102 and the second TFT 202 in the active matrix substrate 1002 of Modified Example 2. Figure 6B yes Figure 6A The cross-sectional view of line VIb-VIb' is shown.

[0197] The first TFT 102 in Modified Example 2 has the same as Figure 2A and Figure 2B The first TFT100 shown has the same structure.

[0198] In the second TFT 202, the lower electrode 3B is configured to partially block the channel region 62c, so that light only enters a portion of the channel region 62c. That is, in this modified example, the lower electrode 3B has a light-transmitting portion 32t that overlaps only a portion of the channel region 62c when viewed from the normal direction of the substrate 1. The structure of the second TFT 202, except for the lower electrode 3B, is the same as that of the second TFT 200. In this specification, non-shielding structures such as... Figure 2A and Figure 2B The structure of the second TFT200 shown, which has a light-transmitting portion 32t that overlaps with the entire channel region 62c, is called the "first non-shielding structure". The structure of the non-shielding structure, such as this modified example, which has a light-transmitting portion 32t that overlaps only with a part of the channel region 62c, is called the "second non-shielding structure".

[0199] The lower electrode 3B has a laminated structure comprising a first transparent conductive film t1 and a first metal film m1. Viewed from the normal direction of the substrate 1, the lower electrode 3B comprises: a light-shielding portion (also referred to as a "second light-shielding portion") 32m, which includes the first metal film m1; and a light-transmitting portion 32t, which includes the first transparent conductive film t1 but does not include the first metal film m1. Alternatively, the first metal film m1 may be formed of the same first metal film as the first metal film m1, and the first transparent conductive film t1 may be formed of the same first transparent conductive film as the first transparent conductive film t1. Viewed from the normal direction of the substrate 1, the light-transmitting portion 32t need only overlap with at least a portion of the channel region 62c.

[0200] Alternatively, the light-transmitting portion 32t may overlap with a portion of the channel region 62c, and the light-shielding portion 32m may overlap with another portion of the channel region 62c. In other words, the overlapping region 32 of the lower electrode 3B, which overlaps with the channel region 61c when viewed from the normal direction of the substrate 1, may also include the light-transmitting portion 32t and the light-shielding portion 32m. By providing the light-shielding portion 32m in the overlapping region 32 of the lower electrode 3B, the channel region 61c can be partially shielded. According to this structure, the amount of light incident on the channel region 61c can be adjusted by adjusting the area ratio of the light-transmitting portion 32t and the light-shielding portion 32m. Therefore, the negative offset effect when a negative bias voltage is applied can be controlled according to the application of the TFT or the driving signal.

[0201] Preferably, when viewed from the normal direction of the substrate 1, the lower electrode 3B (the lower electrode as a whole, including the light-transmitting portion 32t and the light-shielding portion 32m) overlaps with the entire channel region 61c. Therefore, by enabling the lower electrode 3B to function as the lower gate electrode, the TFT capability (mobility) can be improved.

[0202] Furthermore, if the lower electrode is composed only of a light-shielding portion that partially blocks the channel region, the area of ​​the lower electrode, which also functions as the lower gate electrode, becomes smaller relative to the channel region, sometimes failing to sufficiently improve mobility. In contrast, in this modified example, by configuring the light-transmitting portion 32t to overlap with the unshielded portion of the channel region 62c when viewed from the normal direction of the substrate 1, a lower electrode 3B that blocks only a portion of the channel region 62c and has a sufficient area relative to the area of ​​the channel region 62c can be formed.

[0203] When viewed from the normal direction of the substrate 1, the channel region 62c includes: a light-shielding portion c1 that overlaps with the light-shielding portion 32m of the lower electrode 3B; and an irradiated portion c2 that overlaps with the light-transmitting portion 32t of the lower electrode 3B. The area percentage (%) of the light-shielding portion c1 relative to the entire channel region 62c is not particularly limited, but may be, for example, more than 25% and less than 75%.

[0204] In addition, Figure 6A and Figure 6B The example shown is of a first transparent conductive film t1 formed on a first metal film m1, but it is also possible for the first metal film m1 to be formed on the first transparent conductive film t1. In this case, in the lower electrodes 3A and 3B, the first metal film m1 is disposed on the first transparent conductive film t1 (see reference). Figure 4B ).

[0205] In this modified example, the active matrix substrate 1002 may also include, in addition to the first TFT 102 and the second TFT 202 described above, a further feature Figure 2A and Figure 2B The second TFT 200 is shown. For example, the TFT supplied with a drive signal having a first duty cycle may employ a first non-shielding structure (second TFT 200) that allows light to be incident on the entire channel region, the TFT supplied with a drive signal having a second duty cycle lower than the first duty cycle may employ a second non-shielding structure (second TFT 202) that allows light to be incident on only a portion of the channel region, and the TFT supplied with a drive signal having a third duty cycle lower than the second duty cycle may employ a light-shielding structure that shields the entire channel region (first TFT 102).

[0206] <Variation Example 3>

[0207] Figure 7A This is a top view showing the first TFT 103 and the second TFT 203 in the active matrix substrate 1003 of Modified Example 3. Figure 7B yes Figure 7A The cross-sectional view of line VII-VII' shown.

[0208] In Modified Example 3, the active matrix substrate 1003 further comprises a second insulating layer 2 between the first insulating layer 5 and the substrate 1. The material of the second insulating layer 2 may be the same as or different from that of the first insulating layer 5.

[0209] The first metal film m1 of the first TFT 103 is disposed between the substrate 1 and the second insulating layer 2. The lower electrode 3A includes the first metal film m1 formed of the first metal film. The first metal film m1 (light-shielding portion 31m) overlaps with the entire channel region 61c when viewed from the normal direction of the substrate 1. In the illustrated example, the lower electrode 3A is a metal electrode made of a metal film, and may not include a transparent conductive film.

[0210] In the first TFT 103, the second insulating layer 2 and the first insulating layer 5 are located between the oxide semiconductor layer 6A and the lower electrode 3A. Therefore, when the lower electrode 3A is used as the lower gate electrode, the second insulating layer 2 and the first insulating layer 5 function as the lower gate insulating film.

[0211] On the other hand, the second TFT203 has the same Figure 2A and Figure 2B The second TFT 200 shown has the same structure. That is, the lower electrode 3B is disposed between the second insulating layer 2 and the first insulating layer 5. The lower electrode 3B includes a first transparent conductive film t1 formed of a first transparent conductive film. In the illustrated example, the lower electrode 3B is a transparent electrode made of a transparent conductive film. Furthermore, in this modified example, it is also acceptable as long as at least a portion of the overlapping region 32 of the lower electrode 3B is a light-transmitting portion 32t containing the first transparent conductive film t1.

[0212] In the second TFT 203, the first insulating layer 5 is located between the oxide semiconductor layer 6B and the lower electrode 3B, but the second insulating layer 2 is not located between the oxide semiconductor layer 6B and the lower electrode 3B. Therefore, when the lower electrode 3B is used as the lower gate electrode, only the first insulating layer 5 functions as the lower gate insulating film.

[0213] According to this modified example, the thickness of the lower gate insulating film of each TFT can be controlled independently. For example, the lower gate insulating film (first insulating layer 5) of the second TFT 203 can be thinned, thereby further improving the mobility of the second TFT 203. Since the resistance of the lower gate electrode (lower electrode 3B) of the second TFT 203 can be high, the insulation withstand voltage between the lower electrode 3B and the oxide semiconductor layer 6B can be ensured even if the first insulating layer 5 is thinned. In addition, in the first TFT 103, since the thickness of the lower gate insulating film is the total thickness of the first insulating layer 5 and the second insulating layer 2, the insulation withstand voltage between the lower electrode 3A and the oxide semiconductor layer 6A can be ensured by adjusting the thickness of the second insulating layer 2.

[0214] Although not illustrated, the first metal film m1 can also be used for wiring in this variation. For example, the lower electrode 3B can also be electrically connected to the wiring formed by the first metal film m1. In this case, the lower electrode 3B can be directly connected to the wiring including the first metal film m1 within the opening formed in the second insulating layer 2. Alternatively, the lower electrode 3B can be connected to the wiring via other conductive films formed in other layers such as the source metal layer.

[0215] Figure 8 This is a cross-sectional view showing the first TFT 104 and the second TFT 204 in another active matrix substrate 1004.

[0216] Active matrix substrate 1004 and Figure 7A and Figure 7BThe difference in the first TFT 103 shown is that the lower electrode 3B of the first TFT 104 is a metal electrode formed by the second metal film m2. The metal material of the second metal film m2 can be the same as or different from that of the first metal film m1. In this modified example, similar to the active matrix substrate 1003, the thickness of the lower gate insulating film of each TFT can be controlled independently.

[0217] In this example, the lower electrode 3B has a better tapered shape than the lower electrode 3A. That is, the slope of the side surface (end face) of the lower electrode 3B is gentler than that of the side surface of the lower electrode 3A. To form a lower electrode 3B with this tapered shape, for example, it is only necessary to make the second metal film m2 thinner than the first metal film m1.

[0218] If the tapered shape of the lower electrode 3B is gently sloping, the first insulating layer 5 covering the lower electrode 3B will become a smooth shape reflecting the surface shape of the lower electrode 3B, making it less prone to defects. Therefore, even if the first insulating layer 5 is thinned, higher insulation can be ensured. Thus, by thinning the first insulating layer 5, both the insulation withstand voltage between the lower electrode 3B and the oxide semiconductor layer 6B can be ensured, and the mobility of the second TFT 204 can be further improved. On the other hand, in the first TFT 104, by adjusting the thickness of the second insulating layer 2, the insulation withstand voltage between the lower electrode 3A and the oxide semiconductor layer 6A can be ensured.

[0219] Furthermore, if the first metal film m1 and the second metal film m2 are made of the same metal material, then, for example, by making the second metal film m2 thinner than the first metal film m1, the tapered shape of the lower electrode 3B can be made gentler than that of the lower electrode 3A. When the first metal film m1 and the second metal film m2 are made of different metal materials, a better tapered shape for the lower electrode 3B can be achieved by adjusting the material, thickness, etching method, etching conditions, etc., of each metal film.

[0220] (Application example in active matrix substrate)

[0221] In this embodiment, the first TFT includes, for example, a pixel TFT, and the second TFT includes, for example, a circuit TFT. The pixel TFT is disposed in each of a plurality of pixel regions (PIX). The circuit TFT is disposed in the non-display area and constitutes peripheral circuitry.

[0222] The structure of each TFT will be described in more detail below using an active matrix substrate applied to a display device in FFS mode as an example. FFS mode is a mode in which a pair of electrodes are disposed on a substrate, and an electric field is applied to the liquid crystal molecules in a lateral electric field manner in a direction parallel to the substrate surface (lateral). Furthermore, the active matrix substrate of this embodiment can also be applied to display devices in a vertical electric field manner (e.g., TN mode or vertical alignment mode) in which a voltage is applied in the thickness direction of the liquid crystal layer.

[0223] Figure 9 This is a cross-sectional view illustrating the pixel TFT 20 and circuit TFT (here, an SSD circuit TFT) 21 in the active matrix substrate 1000. Additionally, Figure 10 This diagram illustrates a portion of the circuitry in the active matrix substrate 1000, which includes a pixel TFT 20 and an SSD circuit TFT 21. The active matrix substrate 1000 has multiple pixel TFTs and multiple SSD circuit TFTs, but only a single pixel TFT 20 and a single SSD circuit TFT 21 are shown here.

[0224] Each pixel TFT 20 is disposed in a pixel area (PIX) within the display area (DR). Each pixel TFT 20 has a light-shielding structure. Figure 9 In the example shown, the pixel TFT20 is Figure 2A and Figure 2B The first TFT 100 shown is used, but it can be replaced by any of the first TFTs in the modified examples. Detailed descriptions of the TFT structure are omitted here.

[0225] In the pixel TFT 20, the source contact region 61s of the oxide semiconductor layer 6A is electrically connected to the corresponding source bus SL via the source electrode 9As. The drain contact region 61d is electrically connected to the pixel electrode PE via the drain electrode 9Ad.

[0226] The gate electrode 8A is electrically connected to the gate bus GL. The gate electrode 8A may also be integrally formed (connected) with the gate bus GL. For example, the gate electrode 8A may also be part of the gate bus GL. In this case, the portion of the gate bus GL that overlaps with the oxide semiconductor layer 6A when viewed from the normal direction of the substrate 1 is sometimes referred to as "gate electrode 8A".

[0227] The source electrode 9As can also be integrally formed (connected) with the source bus SL. For example, the source electrode 9As can also be part of the source bus SL.

[0228] An upper insulating layer 13 is formed on the source metal layer to cover the pixel TFT 20. The upper insulating layer 13 includes, for example, an inorganic insulating layer (e.g., a passivation film) 11. As shown, the upper insulating layer 13 may also have a stacked structure including the inorganic insulating layer 11 and an organic insulating layer 12 formed on the inorganic insulating layer 11. Alternatively, the organic insulating layer 12 may not be formed. Or, the organic insulating layer 12 may be formed only in the display area.

[0229] A common electrode CE is formed on the upper insulating layer 13. The common electrode CE may not be separated for each pixel region PIX. For example, the common electrode CE may have an opening in the pixel contact area (the area forming the pixel contact hole CHp) connecting the pixel electrode PE and the drain electrode 9Ad, and may be formed in the entire pixel region PIX except for the pixel contact area.

[0230] The pixel electrode PE is disposed on the common electrode CE through the dielectric layer 17. The pixel electrode PE is separated for each pixel region PIX. In each pixel region PIX, one or more slits (openings) or cutouts are provided on the pixel electrode PE.

[0231] The pixel electrode PE is disposed on the dielectric layer 17 and connected to the drain electrode 9Ad within the pixel contact hole CHp formed in the upper insulating layer 13 and the dielectric layer 17.

[0232] Furthermore, in the illustrated example, the pixel electrode PE is formed on the common electrode CE with the dielectric layer 17 in between, but the common electrode CE can also be formed on the pixel electrode PE with the dielectric layer 17 in between. In this case, a slit or cutout is provided on the common electrode CE in each pixel region PIX.

[0233] Alternatively, the pixel TFT 20 may not have a drain electrode within the source metal layer. For example, the pixel electrode PE can be directly connected to the drain contact region 61d of the oxide semiconductor layer 6A. That is, the portion of the pixel electrode PE that contacts the drain contact region 61d can also function as a drain electrode.

[0234] Furthermore, although not illustrated, the source bus SL and the source electrode 9As of the pixel TFT 20 can also be formed using the first metal film m1 (i.e., on the same layer as the lower electrode 3A). A substrate structure in which the source bus SL is arranged on the side of the gate metal layer and the oxide semiconductor layer 6A closer to the substrate 1 is called a "lower source structure".

[0235] The SSD circuit uses TFT21 to form the SSD circuit Sc located in the non-display area FR. Figure 10The diagram only shows one unit circuit constituting the SSD circuit Sc. In this example, the unit circuit contains two SSD circuit TFTs 21 (n=2). The structure of the SSD circuit will be described later.

[0236] The SSD circuit uses a TFT21 with a non-shielded structure. Figure 9 In the example shown, the SSD circuit uses TFT21. Figure 2A and Figure 2B The second TFT 200 shown is alternatively represented by the SSD circuit TFT 21, which can be any of the second TFTs in the modified example. The SSD circuit TFT 21 can also be covered by the inorganic insulating layer 11 and the dielectric layer 17. Detailed description of the TFT structure is omitted here.

[0237] The SSD circuit uses the source electrode 9Bs of TFT21, which is electrically connected to the signal output line VL supplied with the video signal V, and the drain electrode 9Bd, which is electrically connected to the corresponding source bus SL. The SSD circuit uses the gate electrode 8B of TFT21, which is supplied with the SSD control signal SW.

[0238] (SSD circuit structure and operation)

[0239] Figure 11 This diagram illustrates the configuration and operation of the SSD circuit Sc in the active matrix substrate 1000 of this embodiment. Furthermore, Figure 11 This is just an example; the configuration of the SSD circuit Sc is not limited to the configuration shown in the figure.

[0240] The SSD circuit Sc is positioned between the source driver SD and the display area DR. The SSD circuit Sc contains multiple TFTs 21 for SSD circuitry.

[0241] The SSD circuit Sc comprises multiple unit circuits U1 to Ui (hereinafter collectively referred to as "unit circuits U") supported on substrate 1. Each unit circuit U distributes display signals from one signal output line VL to n (n is an integer of 2 or more) source buses SL. Figure 11 The diagram shows the case where n=3, which is the case where each unit circuit U distributes the display signal from one signal output line VL to three source buses SL.

[0242] Each unit circuit U contains n (3 in this case) sub-controller lines BL and n (3 in this case) SSD circuit TFTs 21 (TFTs 21(1), 21(2), and 21(3) in unit circuit U1). The three sub-controller lines BL are connected to one signal output line VL. In addition, the three TFTs 21 are connected to each of the three sub-controller lines BL. These TFTs 21 individually (independently) control the on / off connection of the three sub-controller lines BL to the three source buses SL (SL1 to SL3 in unit circuit U1).

[0243] The following section will use unit circuit U1 as an example to illustrate the composition of each unit circuit U in more detail.

[0244] The unit circuit U1 distributes the display signal V(1) from the signal output line VL1 to the source bus SL1~SL3.

[0245] In unit circuit U1, the source electrode and drain electrode of TFT21 are connected to the corresponding sub-control line BL and source bus SL, respectively, and the electrical connection between the corresponding sub-control line BL and source bus SL is controlled to be turned on / off.

[0246] The SSD circuit Sc also has n (in this case, 3) control signal trunks CL1 to CL3 (collectively referred to as "control signal trunks CL"). The control signal trunks CL are connected to the control circuit located in the non-display area FR.

[0247] A selection signal (SSD control signal) SW1 is supplied from control signal line CL1 to the gate electrode of TFT21(1), and an SSD control signal SW2 is supplied from control signal line (second control signal line) CL2 to the gate electrode of TFT21C. These SSD control signals define the on-time of the selection switches within the same group and are synchronized with the timing signal output from the source driver SD. Each unit circuit U writes the data potential obtained by time-division multiplexing the output of the signal output line VL into the corresponding three source buses SL in a time sequence (time-division driving).

[0248] In the illustrated example, each unit circuit U is configured for three source buses SL (e.g., three source buses corresponding to R, G, and B pixels) (n=3). In this case, the gate electrodes of the three TFTs 21 in each unit circuit U are respectively applied with an SSD control signal (drive signal) SW having a high duty cycle of about 33%.

[0249] Furthermore, the SSD circuit Sc of this embodiment is not limited to the configuration illustrated above and can have various configurations. n is not particularly limited, but can be, for example, 2 or more and 6 or less, preferably 2 or 3. The duty cycle of the SSD control signal SW can vary depending on the value of n or whether an embedded touch panel is present. For example, in the case of n=2, the gate electrodes of the two TFTs 21 in each unit circuit U are respectively subjected to an SSD control signal (drive signal) SW with a high duty cycle of approximately 50% (see reference). Figure 10 Additionally, when the active matrix substrate 1000 has an embedded touch panel, the duty cycle of the SSD control signal may sometimes be reduced to about half.

[0250] In this specification, all disclosures in Japanese Patent Application Publication Nos. 2008-225036, 2006-119404, and International Publication No. 2011 / 118079 are used for reference regarding the operation of display devices using SSD circuits Sc and timing diagrams of time-sharing drive.

[0251] (Example)

[0252] The inventors of this invention investigated the effect of applying a non-light-shielding structure to a TFT for SSD circuits, and therefore, the method and results are described.

[0253] First, as an example, an active matrix substrate having a TFT for SSD circuits with a lower electrode including a transparent conductive film was fabricated. Additionally, as a comparative example, an active matrix substrate having a TFT for SSD circuits with a lower electrode including a metal film was fabricated. The active matrix substrates of the example and the comparative example have the same structure except for the TFT for SSD circuits.

[0254] Figure 13A and Figure 13B The figures show cross-sectional views of TFTs 901 and 902 for SSD circuits in the embodiments and comparative examples, respectively. The TFT 901 for SSD circuits in the embodiment includes: a transparent lower electrode 3(t) disposed on a substrate 1, an oxide semiconductor layer 6, a gate insulating layer 7, a gate electrode 8, and source and drain electrodes (not shown). Here, an In-Ga-Zn-O semiconductor layer is used as the oxide semiconductor layer 6. The lower electrode 3(t) is a transparent electrode including an indium-tin oxide film (thickness: 50 nm). The TFT 902 for SSD circuits in the comparative example has a light-shielding lower electrode 3(m). The lower electrode 3(m) is a metal electrode including a Cu / Ti film (thickness: 230 nm). The TFT 902 for SSD circuits has the same structure as the TFT 901 for SSD circuits, except for the material of the lower electrode.

[0255] Next, the display panels using the active matrix substrates of the examples and comparative examples were subjected to an aging test at a high temperature (70°C) for 1000 hours to investigate the characteristic changes of TFTs 901 and 902 for the SSD circuit caused by the aging test. During the aging test, the duty cycle of the drive signals for the TFTs 901 and 902 for the SSD circuit was set to approximately 33%. Here, the Vg-Id characteristics of each TFT 901 and 902 for the SSD circuit were measured before and after the aging test, and the shift of the threshold voltage Vth to the positive side, ΔVth, was determined.

[0256] Figure 14 This is a graph showing the offset ΔVth of TFTs 901 and 902 for SSD circuits in the embodiment and comparative example. As shown in the figure, the offset ΔVth of TFT 901 for SSD circuits in the embodiment is significantly reduced compared to the offset ΔVth of TFT 902 for SSD circuits in the comparative example. Therefore, it can be seen that the active matrix substrate according to the embodiment can achieve a long lifespan for TFTs for SSD circuits.

[0257] Based on the above results, it can be confirmed that by using a transparent electrode as the lower electrode of the TFT for SSD circuits, the positive shift of the threshold voltage Vth can be suppressed compared to using a light-shielding lower electrode. Furthermore, the lower electrode of the TFT for SSD circuits is not limited to a transparent electrode; as long as it has a light-transmitting portion that overlaps with the channel region when viewed from the normal direction of the substrate, the same effect can be achieved.

[0258] (Manufacturing method of active matrix substrate 1001)

[0259] Next, an example of a method for manufacturing an active matrix substrate according to this embodiment will be described with reference to the accompanying drawings. Here, a method for manufacturing... Figure 9 The method shown is illustrated using the first TFT100 as a pixel TFT20 and the second TFT200 as a TFT21 for SSD circuitry as an example.

[0260] Figure 15 This is a process flow diagram illustrating an example of a manufacturing method for an active matrix substrate 1001.

[0261] STEP 1: Formation of lower electrodes 3A and 3B

[0262] A first metal film m1 (thickness: for example, 50 nm to 500 nm) is formed on a substrate 1 by sputtering. Next, the first metal film m1 is patterned using a known photolithography process (e.g., wet etching). Then, a first transparent conductive film t1 (thickness: for example, 30 nm to 300 nm) is formed, and the first transparent conductive film is patterned using a known photolithography process (e.g., wet etching). Thus, a lower electrode 3A comprising the first metal film m1 and the first transparent conductive film t1, and a transparent lower electrode 3B comprising the first transparent conductive film t1 are formed.

[0263] As substrate 1, a transparent and insulating substrate can be used, such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate).

[0264] The material of the first metal film is not particularly limited, and films containing metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or their alloys or metal nitrides, can be used appropriately. Alternatively, a laminated film formed by stacking these multiple films can also be used. Here, as the first metal film, a laminated film (Cu / Ti film) containing a Ti film (thickness: 30 nm) and a Cu film (thickness: 200 nm) in sequence from the substrate 1 side is used.

[0265] The material for the first transparent conductive film is not particularly limited, but metal oxides such as indium zinc oxide, indium tin oxide (ITO), and ZnO can be used. Here, indium tin oxide (ITO) (thickness: 50 nm) is used as the first transparent conductive film by sputtering.

[0266] STEP 2: Formation of the first insulating layer 5

[0267] Next, a first insulating layer 5 (thickness: for example, 200 nm or more and 600 nm or less) is formed to cover the lower electrode 3A and the lower electrode 3B.

[0268] The first insulating layer 5 is formed, for example, by a CVD method. As the first insulating layer 5, silicon oxide (SiOx) layer, silicon nitride (SiNx) layer, silicon oxynitride (SiOxNy; x>y) layer, silicon oxynitride (SiNxOy; x>y) layer, etc., can be appropriately used. The first insulating layer 5 can be a single layer or have a stacked structure. For example, it can be formed on the substrate side (lower layer) to prevent the diffusion of impurities from the substrate 1, such as silicon nitride (SiNx) layer or silicon oxynitride layer, etc., and on the layer above it (upper layer) to ensure insulation, such as silicon oxide (SiO2) layer or silicon oxynitride layer, etc. Here, as the first insulating layer 5, a stacked film with a silicon nitride (SiNx) layer (thickness: 50-600 nm) as the lower layer and a silicon oxide (SiO2) layer (thickness: 50-600 nm) as the upper layer can also be formed. If an oxide film such as silicon oxide is used as the first insulating layer 5 (in the case that the first insulating layer 5 has a stacked structure, it is used as the top layer), the oxide film can reduce the oxidation defects generated in the channel region of the oxide semiconductor layer formed subsequently, and thus can suppress the low resistance of the channel region.

[0269] STEP 3: Formation of oxide semiconductor layers 6A and 6B

[0270] Next, an oxide semiconductor film is formed on the first insulating layer 5. Afterward, an annealing process can be performed on the oxide semiconductor film. The thickness of the oxide semiconductor film can be, for example, 15 nm or more and 200 nm or less.

[0271] Next, the oxide semiconductor film is patterned using a known photolithography process. The patterning of the oxide semiconductor film can be performed, for example, by wet etching using a PAN-based etchant containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etchant. Thus, oxide semiconductor layers 6A and 6B, which become the active layers of the first TFT 100 and the second TFT 200, are obtained.

[0272] Oxide semiconductor films can be formed, for example, by sputtering. Here, as an oxide semiconductor film, an In-Ga-Zn-O semiconductor film (thickness: 50 nm) containing In, Ga, and Zn is formed.

[0273] STEP 4: Formation of gate insulating layer and gate metal layer

[0274] Next, a gate insulating film (thickness: for example, 80 nm or more and 250 nm or less) and a gate conductive film (thickness: for example, 50 nm or more and 500 nm or less) are formed sequentially in a manner that covers oxide semiconductor layers 6A and 6B.

[0275] As the gate insulating film, the same insulating film as the first insulating layer 5 (the insulating film exemplified as the first insulating layer 5) can be used. Here, a silicon oxide (SiO2) layer is formed as the gate insulating film. If an oxide film such as a silicon oxide film is used as the insulating film, the oxidation defects generated in the channel region of the oxide semiconductor layers 6A and 6B can be reduced by the oxide film, and thus, the low resistance of the channel region can be suppressed.

[0276] As the conductive film for the gate, metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), and tantalum (Ta), or alloys thereof, can be used. The conductive film for the gate can also have a stacked structure comprising multiple layers formed of different conductive materials. Here, as the conductive film for the gate, a Cu / Ti stacked film with a Ti film as the lower layer and a Cu film as the upper layer, or a Cu / Mo stacked film with a Mo film as the lower layer and a Cu film as the upper layer, is used.

[0277] Next, a photoresist layer is formed on the gate conductive film. Using the photoresist layer as a mask, the gate conductive film is patterned to form a gate metal layer comprising gate electrode 8A, gate electrode 8B, and gate bus GL. Then, using the photoresist layer or gate metal layer as a mask, the gate insulating film is etched to obtain gate insulating layer 7A and gate insulating layer 7B. Thus, the region in oxide semiconductor layer 6A that overlaps with gate electrode 8A across gate insulating layer 7A becomes channel region 61c. The region in oxide semiconductor layer 6B that overlaps with gate electrode 8B across gate insulating layer 7B becomes channel region 62c.

[0278] STEP 5: Low-resistance treatment and formation of interlayer insulation layer 10

[0279] Next, a low-resistivity treatment can be performed on the oxide semiconductor layers 6A and 6B. For example, plasma treatment can be performed as a low-resistivity treatment. Thus, when viewed from the normal direction of the main surface of the substrate 1, the exposed areas on both sides of the channel regions 61c and 62c in the oxide semiconductor layers 6A and 6B become low-resistivity regions with a lower resistivity than the channel regions 61c and 62c. The low-resistivity region can also be a conductive region (e.g., sheet resistance: 200 Ω / □ or less).

[0280] Next, an interlayer insulating layer 10 is formed covering the oxide semiconductor layers 6A and 6B, the gate insulating layers 7A and 7B, and the gate metal layer. As the interlayer insulating layer 10, inorganic insulating layers such as silicon oxide films, silicon nitride films, silicon oxynitride films, and silicon oxynitride films can be formed as a single layer or stacked layers. The thickness of the inorganic insulating layer can be 100 nm or more and 500 nm or less. If an insulating film that reduces the oxide semiconductor, such as a silicon nitride film, is used to form the interlayer insulating layer 10, the resistivity of the regions in the oxide semiconductor layers 6A and 6B that are in contact with the interlayer insulating layer 10 (in this case, low-resistance regions) can be maintained at a low level, which is therefore preferred. Here, as the interlayer insulating layer 10, for example, a stacked film with a SiO2 layer as the lower layer and a SiNx layer as the upper layer is formed by CVD.

[0281] Then, the interlayer insulating layer 10 is patterned, for example, by dry etching. Thus, openings p1 to p4 are formed in the interlayer insulating layer 10, exposing portions 61s and 61d of the oxide semiconductor layer 6A and portions 62s and 62d of the oxide semiconductor layer 6B, respectively.

[0282] STEP 6: Formation of the source metal layer

[0283] Next, a source conductive film (thickness: for example, 50 nm to 500 nm) is formed on the interlayer insulating layer 10, and the source conductive film is patterned. This forms an upper metal layer comprising a source electrode 9As, a drain electrode 9Ad, a drain electrode 9Bs, a drain electrode 9Bd, and a source bus SL. Thus, the first TFT 100 and the second TFT 200 are manufactured.

[0284] As the conductive film for the source electrode, elements selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys containing these elements, can be used. For example, a three-layer structure such as titanium film-aluminum film-titanium film, or molybdenum film-aluminum film-molybdenum film, can be used. Here, a stacked film with a Ti film (thickness: 15-70 nm) as the lower layer and a Cu film (thickness: 200-400 nm) as the upper layer is used.

[0285] STEP 7: Formation of inorganic insulating layer 11 and organic insulating layer 12

[0286] Next, an upper insulating layer 13 is formed to cover the interlayer insulating layer 10 and the source metal layer. Here, as the upper insulating layer 13, an inorganic insulating layer 11 (thickness: for example, 100 nm to 500 nm) and an organic insulating layer 12 (thickness: for example, 1 to 3 μm, preferably 2 to 3 μm) are formed sequentially. Alternatively, the entire portion of the organic insulating layer 12 located in the non-display area may be removed. Or, the organic insulating layer 12 may not be formed.

[0287] As the inorganic insulating layer 11, the same inorganic insulating film as the interlayer insulating layer 10 can be used (the insulating film exemplified as the interlayer insulating layer 10). Here, as the inorganic insulating layer 11, for example, a SiNx layer (thickness: 300 nm) is formed by CVD. The organic insulating layer 12 may also be, for example, an organic insulating film containing a photosensitive resin material (e.g., an acrylic resin film).

[0288] Next, the organic insulating layer 12 is patterned. Thus, in each pixel region (PIX), a first opening is formed in the organic insulating layer 12, exposing a portion of the inorganic insulating layer 11. The first opening is configured to overlap with the drain electrode 9Ad of the first TFT 100, which serves as a pixel TFT, when viewed from the normal direction of the substrate 1.

[0289] STEP 8: Formation of the common electrode CE

[0290] Next, a common electrode CE is formed on the upper insulating layer 13.

[0291] First, a lower transparent conductive film (thickness: 20-300 nm), not shown, is formed on the upper insulating layer 13 and within the first opening. Here, for example, an indium-zinc oxide film is formed as the lower transparent conductive film by sputtering. Metal oxides such as indium-tin oxide (ITO), indium-zinc oxide, and ZnO can be used as the material for the first transparent electrode film. Next, the lower transparent conductive film is patterned. In the patterning, for example, wet etching can be performed using an oxalic acid-based etchant. Thus, a common electrode CE is obtained. The common electrode CE can, for example, be disposed over approximately the entire display area except for the pixel contact hole formation area where the pixel contact hole CHp is formed.

[0292] STEP 9: Formation of dielectric layer 17

[0293] Next, a dielectric layer 17 (thickness: 50-500 nm) is formed to cover the common electrode CE, and the dielectric layer 17 and the inorganic insulating layer 11 are patterned.

[0294] A dielectric layer 17 is formed in the pixel region PIX on the organic insulating layer 12, the common electrode CE, and within the first opening. The material of the dielectric layer 17 can be the same as the material exemplified as the inorganic insulating layer 11. Here, the dielectric layer 17 is, for example, a SiN film formed by CVD.

[0295] Next, a photoresist layer (not shown) is formed on the dielectric layer 17 using a photolithography process. Using this photoresist layer and the organic insulating layer 12 as a mask, the dielectric layer 17 and the inorganic insulating layer 11 are etched (e.g., dry etching). The etching of the dielectric layer 17 and the inorganic insulating layer 11 can be performed in the same etching process. Thus, a pixel contact hole CHp is formed in the pixel region, exposing a portion of the drain contact region 61d of the oxide semiconductor layer 6A. The pixel contact hole CHp is composed of an opening formed in the inorganic insulating layer 11, a first opening in the organic insulating layer 12, and an opening in the dielectric layer 17.

[0296] STEP 10: Formation of the pixel electrode PE

[0297] Next, an upper transparent conductive film (thickness: 20-300 nm) is formed on the dielectric layer 17 and within the pixel contact hole CHp. The material of the upper transparent conductive film can be the same as the material exemplified as the material of the upper transparent conductive film (e.g., ITO).

[0298] Next, the upper transparent conductive film is patterned. For example, an oxalic acid-based etching solution can be used to wet-etch the upper transparent conductive film. This yields the pixel electrode PE. The pixel electrode PE is formed in the pixel region PIX on the dielectric layer 17 and within the pixel contact hole CHp, and is connected to the drain electrode 9Ad of the pixel TFT within the pixel contact hole CHp. In this way, the active matrix substrate 1000 is manufactured.

[0299] Furthermore, the active matrix substrates 1001 and 1002 of Variations 1 and 2 can also be manufactured by the same method as described above. However, in the active matrix substrate 1001 of Variation 1, in STEP 1, the formation and patterning of the first transparent conductive film t1 are performed before the formation and patterning of the first metal film m1.

[0300] In STEP 1, the active matrix substrate 1003 of Modified Example 3 is formed by forming and patterning the first metal film m1 and forming the lower electrode 3A, and then forming the second insulating layer 2 (thickness: for example, 50 nm or more and 600 nm or less) to cover the lower electrode 3A.

[0301] As the second insulating layer 2, the same insulating film as the first insulating layer 5 can be used (the insulating film exemplified as the first insulating layer 5). The material of the second insulating layer 2 can be the same as or different from that of the first insulating layer 5. For example, a SiN layer (thickness: for example, 150 nm) can be formed as the second insulating layer 2, and a SiO2 layer (thickness: for example, 150 nm) can be formed as the first insulating layer 5. By making the thickness of the insulating layer between the lower electrode and the channel region different between the two TFTs, the electric field strength from the lower electrode can be changed. Therefore, the thickness of the insulating layer can be selected more optimally from the perspective of device degradation or mobility for each TFT. The thickness of the second insulating layer 2 is not particularly limited, but it can also be thinner than the first insulating layer 5. Then, by forming a first transparent conductive film t1 on the second insulating layer 2 and patterning it, the lower electrode 3B is obtained. The subsequent processes are the same as described above.

[0302] The active matrix substrate 1004 of Modified Example 4 can be manufactured by the same method as the active matrix substrate 1003. However, a second metal film m2 is used instead of the first transparent conductive film t1. The material of the second metal film m2 can be the same as or different from that of the first metal film m1. For example, a Cu / Ti film (thickness: for example, 230 nm) can be formed as the first metal film m1, and a Mo film (thickness: for example, 50 nm) can be formed as the second metal film m2.

[0303] <Oxide Semiconductor>

[0304] The oxide semiconductor (also called metal oxide or oxide material) included in the oxide semiconductor layer of each TFT in this embodiment can be an amorphous oxide semiconductor or a crystalline oxide semiconductor having crystalline portions. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors oriented with the c-axis substantially perpendicular to the layer.

[0305] The oxide semiconductor layer can also have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, it can include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it can include multiple crystalline oxide semiconductor layers with different crystal structures. Additionally, it can include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the bandgap of the oxide semiconductor in the layer located on the gate electrode side (the lower layer if it's a bottom-gate structure, and the upper layer if it's a top-gate structure) can be smaller than the bandgap of the oxide semiconductor in the layer located on the opposite side of the gate electrode (the upper layer if it's a bottom-gate structure, and the lower layer if it's a top-gate structure). However, when the difference in bandgap between these layers is small, the bandgap of the oxide semiconductor in the layer located on the gate electrode side can also be larger than the bandgap of the oxide semiconductor in the layer located on the opposite side of the gate electrode.

[0306] Materials, structures, film-forming methods, and configurations of oxide semiconductor layers with stacked structures for amorphous oxide semiconductors and the aforementioned crystalline oxide semiconductors are described, for example, in Japanese Patent Application Publication No. 2014-007399. All disclosures in Japanese Patent Application Publication No. 2014-007399 are incorporated herein by reference.

[0307] The oxide semiconductor layer may, for example, contain at least one metal element selected from In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, for example, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. This oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0308] In-Ga-Zn-O semiconductors can be either amorphous or crystalline. For crystalline In-Ga-Zn-O semiconductors, those with their c-axis oriented substantially perpendicular to the surface are preferred.

[0309] Furthermore, the crystal structure of crystalline In-Ga-Zn-O semiconductors is disclosed, for example, in Japanese Patent Application Publication Nos. 2014-007399, 2012-134475, and 2014-209727, etc. All disclosures of Japanese Patent Application Publication Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. TFTs having an In-Ga-Zn-O semiconductor layer have high mobility (more than 20 times that of a-Si TFTs) and low leakage current (less than one percent compared to a-Si TFTs), therefore, they are suitable for use as driving TFTs (e.g., TFTs included in driving circuits disposed on the same substrate as the display area around a display area containing multiple pixels) and pixel TFTs (TFTs disposed in pixels).

[0310] The oxide semiconductor layer can also contain other oxide semiconductors to replace the In-Ga-Zn-O semiconductor. For example, it can also contain In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, In-W-Zn-O semiconductors, etc.

[0311] The embodiments of the present invention are suitable for use with active matrix substrates having peripheral circuits formed as a single chip. Such active matrix substrates are applied to various electronic devices such as liquid crystal display devices, organic electroluminescent (EL) display devices, and inorganic electroluminescent display devices, as well as imaging devices such as image sensor devices, image input devices, fingerprint reading devices, and semiconductor memories.

Claims

1. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. The first lower electrode of each of the first TFTs has a stacked structure comprising the first metal film and the first transparent conductive film.

2. The active matrix substrate according to claim 1, wherein, In the first lower electrode of each of the first TFTs, the first transparent conductive film is disposed on the first metal film in such a way that it covers the side and upper surface of the first metal film.

3. The active matrix substrate according to claim 1, wherein, In the first lower electrode of each of the first TFTs, the first metal film is disposed on the first transparent conductive film.

4. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film. The second lower electrode of each of the second TFTs is electrically connected to the wiring.

5. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film and the aforementioned first transparent conductive film. When viewed from the normal direction of the substrate, the portion of the wiring that does not overlap with the second lower electrode of each of the second TFTs has a low resistance portion, which includes the first metal film and the first transparent conductive film. The portion of the wiring that overlaps with the second channel region of each of the second TFTs has a high resistance portion, which includes the first transparent conductive film but does not include the first metal film. The high resistance portion functions as the light transmission portion of the second lower electrode.

6. The active matrix substrate according to any one of claims 1 to 3, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

7. The active matrix substrate according to claim 6, wherein, The aforementioned In-Ga-Zn-O semiconductors include a crystalline portion.

8. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. In the second lower electrode of each of the second TFTs, when viewed from the normal direction of the substrate, the light-transmitting portion overlaps with the entire second channel region.

9. The active matrix substrate according to claim 8, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film. The second lower electrode of each of the second TFTs is electrically connected to the wiring.

10. The active matrix substrate according to claim 8, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film and the aforementioned first transparent conductive film. When viewed from the normal direction of the substrate, the portion of the wiring that does not overlap with the second lower electrode of each of the second TFTs has a low resistance portion, which includes the first metal film and the first transparent conductive film. The portion of the wiring that overlaps with the second channel region of each of the second TFTs has a high resistance portion, which includes the first transparent conductive film but does not include the first metal film. The high resistance portion functions as the light transmission portion of the second lower electrode.

11. The active matrix substrate according to any one of claims 8 to 10, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

12. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. The second lower electrode of each of the aforementioned second TFTs further includes a second light-shielding portion, which includes the aforementioned first metal film. In the second lower electrode of each of the second TFTs, when viewed from the normal direction of the substrate, the light-transmitting portion overlaps only with a portion of the second channel region, and the second light-shielding portion overlaps with another portion of the second channel region.

13. The active matrix substrate according to claim 12, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film. The second lower electrode of each of the second TFTs is electrically connected to the wiring.

14. The active matrix substrate according to claim 12, wherein, The aforementioned active matrix substrate also includes wiring comprising the aforementioned first metal film and the aforementioned first transparent conductive film. When viewed from the normal direction of the substrate, the portion of the wiring that does not overlap with the second lower electrode of each of the second TFTs has a low resistance portion, which includes the first metal film and the first transparent conductive film. The portion of the wiring that overlaps with the second channel region of each of the second TFTs has a high resistance portion, which includes the first transparent conductive film but does not include the first metal film. The high resistance portion functions as the light transmission portion of the second lower electrode.

15. The active matrix substrate according to any one of claims 12 to 14, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

16. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. The aforementioned active matrix substrate further comprises a second insulating layer between the first insulating layer and the substrate. In each of the aforementioned first TFTs, the first lower electrode is disposed between the substrate and the second insulating layer, and the first insulating layer and the second insulating layer are located between the first oxide semiconductor layer and the first lower electrode. In each of the above-mentioned second TFTs, the second lower electrode is disposed between the second insulating layer and the first insulating layer, the first insulating layer is located between the second oxide semiconductor layer and the second lower electrode, but the second insulating layer is not located between the second oxide semiconductor layer and the second lower electrode.

17. The active matrix substrate according to claim 16, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

18. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. In each of the aforementioned second TFTs, the second lower electrode is electrically connected to the second gate electrode and functions as the lower gate electrode of each of the aforementioned second TFTs.

19. The active matrix substrate according to claim 18, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

20. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. When the active matrix substrate is driven, the duty cycle of the driving signal applied to the second gate electrode of each of the second TFTs is higher than the duty cycle of the driving signal applied to the first gate electrode of each of the first TFTs.

21. The active matrix substrate according to claim 20, wherein, When the aforementioned active matrix substrate is driven, the duty cycle of the driving signal applied to the first gate electrode of each of the aforementioned first TFTs is less than 5%. The duty cycle of the drive signal applied to the second gate electrode of each of the second TFTs is 10% or more.

22. The active matrix substrate according to claim 20 or 21, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

23. An active matrix substrate comprising: a substrate; and a plurality of oxide semiconductor TFTs supported on the substrate. The aforementioned active matrix substrate is characterized in that, The aforementioned plurality of oxide semiconductor TFTs include a plurality of first TFTs and a plurality of second TFTs. Each first TFT includes: a first lower electrode; a first insulating layer covering the first lower electrode; a first oxide semiconductor layer disposed on the first insulating layer; and a first gate electrode disposed on a portion of the first oxide semiconductor layer through the first gate insulating layer. In each of the aforementioned first TFTs, The first oxide semiconductor layer includes a first channel region that overlaps with the first gate electrode when viewed from the normal direction of the substrate. The first lower electrode has a first light-shielding portion that overlaps with the entire first channel region when viewed from the normal direction of the substrate, and the first light-shielding portion includes a first metal film. Each second TFT includes: a second lower electrode; the first insulating layer extending to cover the second lower electrode; a second oxide semiconductor layer disposed on the first insulating layer; and a second gate electrode disposed on a portion of the second oxide semiconductor layer, separated by the second gate insulating layer. In each of the aforementioned second TFTs, The second oxide semiconductor layer includes a second channel region that overlaps with the second gate electrode when viewed from the normal direction of the substrate. The second lower electrode has a light-transmitting portion that overlaps with at least a portion of the second channel region when viewed from the normal direction of the substrate. The light-transmitting portion includes a first transparent conductive film but does not include a light-shielding metal film. The aforementioned active matrix substrate also features: The display area contains multiple pixel regions; The non-display area is located around the display area and includes a circuit forming area where peripheral circuitry is formed. Multiple source buses and multiple gate buses are supported on the aforementioned substrate; Multiple pixel TFTs, each disposed in a separate pixel region; and Multiple TFT circuits constitute the aforementioned peripheral circuit. The source electrode of each pixel TFT is electrically connected to one of the plurality of source buses, and the gate electrode of each pixel TFT is electrically connected to one of the plurality of gate buses. The aforementioned plurality of first TFTs include the aforementioned plurality of pixel TFTs. The aforementioned plurality of second TFTs include at least a portion of the aforementioned plurality of circuit TFTs.

24. The active matrix substrate according to claim 23, wherein, The aforementioned peripheral circuitry includes an SSD circuit that distributes display signals to n of the multiple source buses. The aforementioned plurality of second TFTs include a plurality of SSD circuit TFTs constituting the aforementioned SSD circuit, and each SSD circuit TFT supplies a video signal to one of the corresponding source buses among the aforementioned n source buses.

25. The active matrix substrate according to claim 23 or 24, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer described above comprise In-Ga-Zn-O semiconductors.

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