Pulsing the RF coils of the plasma chamber in reverse synchronization.

Abstract

A system and method for pulsing radio frequency (RF) coils. [Solution] One method includes supplying a first RF signal to a first impedance matching circuit coupled to a first RF coil, supplying a second RF signal to a second impedance matching circuit coupled to a second RF coil, and pulsing the first RF signal between a first parameter level and a second parameter level. The method also includes pulsing the second RF signal between a third parameter level and a fourth parameter level in reverse synchronization with the pulsing of the first RF signal.

Description

Technical Field

[0001] This embodiment relates to a system and method for pulsing a radio frequency (RF) coil in a plasma chamber in reverse synchronization.

Background Art

[0002] The description of the background art provided herein is for the purpose of generally presenting the background of the present disclosure. Within the scope described in this background art section, the research of the inventors named herein, as well as aspects of the description that may not separately qualify as prior art at the time of filing, are not admitted as prior art to the present disclosure, either expressly or implicitly.

[0003] Plasma tools include one or more radio frequency (RF) generators. The RF generator is coupled to the plasma chamber via one or more impedance matches. A substrate is placed within the plasma chamber.

[0004] The RF generator supplies an RF signal to the plasma chamber via one or more impedance matches to process the substrate. However, the substrate is not processed uniformly.

[0005] In such a background, the embodiments described in the present disclosure arise.

Summary of the Invention

[0006] Embodiments of the present disclosure provide a system, apparatus, method, and computer program for pulsing a radio frequency (RF) coil in a plasma chamber in reverse synchronization. It should be understood that the present embodiments can be implemented in a number of ways, for example, as a process, apparatus, system, device, or method on a computer-readable medium. Some embodiments are described below.

[0007] If the ion density or bundle of plasma formed on a semiconductor wafer is non-uniform, the thickness of the plasma sheath is also non-uniform. Since ions enter the sheath perpendicular to the sheath boundary, a sloped or non-uniform sheath results in a sloped ion direction. Such a slope in the ion direction is undesirable because it can result in a sloped etch profile. To minimize the slope, the systems and methods described herein generate a plasma with a uniform plasma sheath.

[0008] In one embodiment, the system includes separately pulsed radio frequency (RF) coils. When the first of two RF coils is on during the pulsing cycle, the second of the two RF coils is switched off for the duration of the pulsing time. This reverse synchronization reduces interference between the first and second RF coils and improves uniformity of both plasma density and sheath thickness.

[0009] In one embodiment, the system includes separately pulsed RF coil sets. When the first of two RF coil sets is on for the duration of the pulsing time, the second of the two RF coil sets is switched off for the duration of the pulsing time. Each RF coil set includes two or more RF coils. This reverse synchronization reduces interference between the first and second RF coil sets and increases the uniformity of the plasma sheath thickness.

[0010] In one embodiment, when the first RF coil is turned on for part of the pulsing cycle, the first RF coil increases the plasma density in a first region beneath it, further increasing the uniformity of the plasma in the first region. When the second RF coil is turned off, the plasma density in a second region beneath it decreases, further decreasing the uniformity of the plasma in the second region. On the other hand, when the second RF coil is turned on and the first RF coil is turned off for the remainder of the pulsing cycle, the second region begins to acquire plasma and becomes more uniform. The first region also becomes considerably more uniform as plasma density from the second region diffuses and moves into the plasma within the first region. Again, when the first RF coil is turned on, the uniformity of the plasma in the first region increases, and plasma from the first region moves into the second region, achieving uniformity in the second region. In this configuration, time-division multiplexing of the first and second RF coils increases the time-averaged density or flux uniformity of plasma ions and electrons, resulting in a uniform plasma sheath thickness, where plasma ions entering the plasma sheath of the uniform plasma have an extremely minimal or no gradient.

[0011] In one embodiment, a method for pulsing an RF coil is described. The method includes supplying a first RF signal to a first impedance matching circuit coupled to a first RF coil; supplying a second RF signal to a second impedance matching circuit coupled to a second RF coil; and pulsing the first RF signal between a first parameter level and a second parameter level. The method also includes pulsing the second RF signal between a third parameter level and a fourth parameter level in reverse synchronization with the pulsing of the first RF signal.

[0012] In one embodiment, a method for reverse pulsing of RF coils is described. The method includes receiving an indication of the multiplexed operation of a first RF generator and a second RF generator. The first RF generator is coupled to a first RF coil, and the second RF generator is coupled to a second RF coil. The method further includes receiving a selection indicating that the first RF generator will begin operating in one state, receiving a duty cycle of operation of the first RF generator, and controlling the first RF generator to have the duty cycle and to begin operating in one state. The method includes controlling the second RF generator to operate in reverse synchronous with the first RF generator. The reverse synchronous operation of the first RF generator and the second RF generator with respect to each other causes the first RF generator to generate a first RF signal and the second RF generator to generate a second RF signal. The second RF signal pulsates in reverse synchronous with the first RF signal.

[0013] In one embodiment, a system for pulsing an RF coil is described. The system includes a first RF generator configured to supply a first RF signal to a first impedance matching circuit coupled to a first RF coil of a plasma chamber. The system further includes a second RF generator configured to supply a second RF signal to a second impedance matching circuit coupled to a second RF coil of the plasma chamber. The first RF generator pulsates the first RF signal between a first parameter level and a second parameter level. The second RF generator pulsates the second RF signal between a third parameter level and a fourth parameter level, in reverse synchronization with the first RF signal.

[0014] In one embodiment, in order to pulsate the second RF signal in reverse synchronization with the first RF signal, the second RF generator transitions the second RF signal from the third parameter level to the fourth parameter level for the duration of the transition of the first RF signal from the first parameter level to the second parameter level. Also, in order to pulsate the second RF signal in reverse synchronization with the first RF signal, the second RF generator transitions the second RF signal from the fourth parameter level to the third parameter level for the duration of the transition of the first RF signal from the second parameter level to the first parameter level.

[0015] In one embodiment, the second RF generator maintains the second RF signal at a third parameter level for the duration that the first RF generator maintains the first RF signal at a first parameter level. Furthermore, the second RF generator maintains the second RF signal at a fourth parameter level for the duration that the first RF generator maintains the first RF signal at a second parameter level.

[0016] In one embodiment, each of the first RF generator and the second RF generator receives a synchronization signal. The first and second parameter levels occur during the cycle of the synchronization signal, and the third and fourth parameter levels occur during the same cycle.

[0017] In one embodiment, to pulsate a first RF signal, the first RF generator transitions the first RF signal from a first parameter level to a second parameter level during the synchronization signal cycle. Furthermore, to pulsate an RF signal, the first RF generator transitions the first RF signal from a second parameter level to a first parameter level during the synchronization signal cycle. Additionally, to pulsate a second RF signal, the second RF generator transitions the second RF signal from a third parameter level to a fourth parameter level during the synchronization signal cycle. Furthermore, to pulsate a second RF signal, the second RF generator transitions the second RF signal from a fourth parameter level to a third parameter level during the synchronization signal cycle.

[0018] In one embodiment, the system includes a third RF generator that supplies a third RF signal to a third RF coil in a plasma chamber via a third impedance matching circuit. The third RF generator pulsates the third RF signal between a fifth parameter level and a sixth parameter level. The third RF signal is pulsed in reverse synchronization with the first RF signal and the second RF signal.

[0019] In one embodiment, a controller is described. The controller includes a processor that controls a first RF generator to supply a first RF signal to a first impedance matching circuit coupled to a first RF coil of a plasma chamber. The processor also controls a second RF generator to supply a second RF signal to a second impedance matching circuit coupled to a second RF coil of the plasma chamber. The processor further controls the first RF generator to pulsate the first RF signal between a first parameter level and a second parameter level. The processor controls the second RF generator to pulsate the second RF signal between a third parameter level and a fourth parameter level, in reverse synchronization with the first RF signal. The controller includes a memory device coupled to the processor for storing the first, second, third, and fourth parameter levels.

[0020] In one embodiment, in order to pulsate the second RF signal in reverse synchronization with the first RF signal, the processor controls the second RF generator to transition the second RF signal from a third parameter level to a fourth parameter level. The second RF signal transitions from the third parameter level to the fourth parameter level for the duration that the first RF signal transitions from the first parameter level to the second parameter level. Furthermore, in order to pulsate the second RF signal in reverse synchronization with the first RF signal, the processor controls the second RF generator to transition the second RF signal from the fourth parameter level to the third parameter level. The second RF signal transitions from the fourth parameter level to the third parameter level for the duration that the first RF signal transitions from the second parameter level to the first parameter level.

[0021] In one embodiment, a controller is described. The controller includes a processor that receives a selection indicating whether a first RF generator will be pulsed in reverse synchronization with a second RF generator. The first RF generator is coupled to a first impedance matching circuit which is coupled to a first RF coil of a plasma chamber. The second RF generator is coupled to a second impedance matching circuit which is coupled to a second RF coil of a plasma chamber. The controller includes a memory device coupled to the processor.

[0022] In one embodiment, the processor receives a selection indicating whether the first RF generator or the second RF generator will start operating in a first state. In response to receiving a selection indicating that the first RF generator will start operating in a first state, the processor controls the second RF generator to start operating in a second state.

[0023] Some of the advantages of the systems and methods described herein include increasing uniformity in processing semiconductor wafers and reducing the ion tilt to a minimum or zero. The method includes pulsing two RF coils in an anti-phase manner. When the first RF coil has a high state and the second RF coil has a low state, there is an increase in sheath thickness towards the central region above the semiconductor wafer and a decrease in sheath thickness towards the edge region above the semiconductor wafer. The ion tilt of the ions entering the sheath increases towards the central region and decreases towards the edge region. On the other hand, when the first RF coil has a low state and the second RF coil has a high state, there is an increase in sheath thickness towards the edge region of the semiconductor wafer and a decrease in sheath thickness towards the central region of the substrate. The ion tilt of the ions entering the sheath increases towards the edge region and decreases towards the central region. When the RF coils are pulsed in an anti-phase manner over a period of time, multiple cycles of anti-pulsing occur. Over that period of time, the plasma sheath becomes more uniform across the central and edge regions above the semiconductor wafer. Also, because the plasma sheath becomes more uniform, the ion tilt decreases to a minimum to process the semiconductor wafer uniformly across the upper surface of the semiconductor wafer.

[0024] Other aspects will become apparent from the following detailed description in conjunction with the accompanying drawings.

[0025] Embodiments can be best understood by referring to the following description in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0026] [Figure 1A] FIG. is a diagram showing an embodiment of a system for explaining the anti-pulsing of a first radio frequency (RF) coil and a second RF coil.

[0027] [Figure 1B]FIG. is a diagram showing an embodiment of a system for explaining a horizontal RF coil for inverse parsing.

[0028] [Figure 2A] FIG. is a diagram showing an embodiment of a graph for explaining a synchronization signal.

[0029] [Figure 2B] FIG. is a diagram showing an embodiment of a graph for explaining a digital pulse signal for explaining a duty cycle of parameters of an RF signal generated by an RF generator.

[0030] [Figure 2C] FIG. is a diagram showing an embodiment of a graph for explaining a digital pulse signal for explaining a duty cycle of parameters of an RF signal generated by an RF generator.

[0031] [Figure 2D] FIG. is a diagram showing an embodiment of a graph for explaining parameters of an RF signal.

[0032] [Figure 2E] FIG. is a diagram showing an embodiment of a graph for explaining parameters of an RF signal.

[0033] [Figure 3A] FIG. is a diagram showing an embodiment of the graph of FIG. 2A for explaining a synchronization signal.

[0034] [Figure 3B] FIG. is a diagram showing an embodiment of a graph for explaining a digital pulse signal for explaining a duty cycle of parameters of an RF signal generated by an RF generator.

[0035] [Figure 3C]This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0036] [Figure 3D] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0037] [Figure 3E] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0038] [Figure 4A] This figure shows an embodiment of the graph in Figure 2A for explaining the synchronization signal.

[0039] [Figure 4B] This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0040] [Figure 4C] This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0041] [Figure 4D] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0042] [Figure 4E] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0043] [Figure 5]This figure shows a computer system for describing a user interface for describing the control of multiplexing operation between multiple RF generators.

[0044] [Figure 6A] This figure shows an embodiment of a graph illustrating the plot of the ion bundle of plasma in the plasma chamber against the radius of the substrate placed in the plasma chamber.

[0045] [Figure 6B] This figure shows an embodiment of a graph illustrating the plot of the ion bundle of plasma in the plasma chamber against the radius of the substrate placed in the plasma chamber.

[0046] [Figure 6C] This figure shows an embodiment of a graph illustrating the plot of the ion bundle of plasma in the plasma chamber against the radius of the substrate placed in the plasma chamber.

[0047] [Figure 7A] This figure shows an embodiment illustrating a substrate that is etched when multiple RF generators are in the same state for the same period of time.

[0048] [Figure 7B] This figure shows an embodiment illustrating a substrate that is etched when multiple RF generators are in the same state for the same period of time.

[0049] [Figure 7C] This figure shows an embodiment of a substrate that is etched when multiple RF generators are pulsed in opposite synchronous motion to each other.

[0050] [Figure 8] This figure shows an embodiment of a graph used to explain the ion angular distribution function.

[0051] [Figure 9] This figure shows an embodiment of a system illustrating the use of three RF coils operating in a multiplexed configuration.

[0052] [Figure 10A] This figure shows an embodiment of the graph in Figure 2A for explaining the synchronization signal.

[0053] [Figure 10B] This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0054] [Figure 10C] This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0055] [Figure 10D] This figure shows an embodiment of a graph illustrating a digital pulse signal to describe the duty cycle of the parameters of an RF signal generated by an RF generator.

[0056] [Figure 10E] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0057] [Figure 10F] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0058] [Figure 10G] This figure shows a graph embodiment illustrating the parameters of an RF signal.

[0059] [Figure 11]This figure shows a computer system illustrating a user interface for controlling the multiplexed operation of three RF generators.

[0060] [Figure 12] This figure shows an embodiment of a system illustrating the internal components of three RF generators. [Modes for carrying out the invention]

[0061] The following embodiments describe a system and method for pulsing radio frequency (RF) coils in a plasma chamber in reverse synchronization. It will be apparent that these embodiments can be practiced without some or all of these specific details. Furthermore, well-known process behaviors are not described in detail so as not to unnecessarily obscure these embodiments.

[0062] Figure 1A is a diagram of an embodiment of system 100, illustrating the inverse pulsing of RF coils 114 and 116. System 100 includes RF generators 102 and 104, matches 108 and 110, plasma chamber 118, RF generator 106, match 112, and host computer 120. An example of plasma chamber 118 is a transformer-coupled plasma (TCP) chamber or an inductively coupled plasma (ICP) chamber.

[0063] It should be noted that the terms match, impedance match, impedance matching circuit, and impedance matching network are used synonymously in this specification. Furthermore, it should be noted that the terms RF coil, TCP coil, or ICP coil are used synonymously in this specification.

[0064] The host computer 120 includes a processor 122 and a memory device 124. Examples of host computers include desktops, laptops, tablets, and smartphones. As used herein, a processor is an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), or a central processing unit (CPU), or a microprocessor, or a microcontroller. Examples of memory devices include random access memory (RAM) and read-only memory (ROM). For example, a memory device may be flash memory, a hard disk, or a storage device. A memory device is an example of computer-readable media.

[0065] Each of the RF generators 102, 104, and 106 has an operating frequency. For example, each of the RF generators 102 and 104 has an operating frequency in the range of 10 kilohertz (kHz) to 100 kHz. As an example, RF generator 106 has an operating frequency in the range of 10 kHz to 100 kHz. As another example, RF generator 106 has an operating frequency of 400 kHz or 2 megahertz (MHz) or 13.56 MHz or 27 MHz or 60 MHz.

[0066] In one embodiment, RF generator 104 operates at substantially the same frequency as RF generator 102. For example, the operating frequency of RF generator 104 is within a predetermined range, such as within ±10% of the operating frequency of RF generator 102. In another example, RF generators 102 and 104 both have the same operating frequency.

[0067] Matches as described herein include a network of one or more resistors, or one or more capacitors, or one or more inductors, or combinations thereof. For example, a match includes multiple series circuits and multiple shunt circuits that are coupled to one another. Each series circuit includes a resistor, or a capacitor, or an inductor, or combinations thereof. Similarly, each shunt circuit includes a resistor, or a capacitor, or an inductor, or combinations thereof. Each shunt circuit is coupled to a series circuit at one end and to ground potential at the other end. An example of ground potential is zero potential. The ends of each series circuit are not coupled to ground potential. For example, the first end of a series circuit is coupled to the input of a match, and the second end of a series circuit is coupled to a shunt circuit and to the output of a match.

[0068] The plasma chamber 118 includes a chamber wall which is a dielectric window 126 and a side wall 119. The dielectric window 126 is positioned above the side wall 119 of the plasma chamber 118. The dielectric window 126 forms the upper wall of the plasma chamber 118. RF coils 114 and 116 are located above the dielectric window 126. The plasma chamber 118 further includes a substrate support 128 and an edge ring 130. An example of the substrate support 128 is a chuck such as an electrostatic chuck (ESC). The substrate support 128 has a lower electrode 158 embedded within the substrate support 128. The edge ring 130 surrounds the substrate support 128. As an example, the edge ring 130 is fabricated from a dielectric material such as silicon, boron-doped single-crystal silicon, alumina, silicon carbide, or a silicon carbide layer on an alumina layer, or a silicon alloy, or a combination thereof. Please note that the edge ring 130 has an annular shape, such as a ring-shaped or dish-shaped body.

[0069] RF coil 114 is the outer coil, and RF coil 116 is the inner coil. For example, RF coil 114 is located above the edge ring 130, and the inner RF coil 116 is located above the substrate support 128, with no overlap between RF coils 114 and 116. Also, there is no portion of RF coil 114 above the substrate support 128, and no portion of RF coil 116 above the edge ring 130. RF coil 114 has a larger diameter than RF coil 116. For example, RF coil 114 is located next to the outer circumference of RF coil 116. Both RF coils 114 and 116 are located in the same horizontal plane.

[0070] The processor 122 is coupled to the RF generator 102 via a transmission cable 132. Similarly, the processor 122 is coupled to the RF generator 104 via a transmission cable 134 and to the RF generator 106 via a transmission cable 136. Examples of transmission cables, as used herein, include coaxial cables used for transmitting data in parallel, cables used for transmitting data in continuous, and Universal Serial Bus (USB) cables. The processor 122 is also coupled to the memory device 124.

[0071] The output O102 of RF generator 102 is coupled to the input I108 of match 108 via RF cable 138, and the output O108 of match 108 is coupled to the first end of RF coil 116 via RF transmission line 144. The second end of RF coil 116 is coupled to ground. Similarly, the output O104 of RF generator 104 is coupled to the input I110 of match 110 via RF cable 140, and the output O110 of match 110 is coupled to the first end of TCP coil 114 via RF transmission line 146. The second end of TCP coil 114 is coupled to ground. In addition, the output O106 of RF generator 106 is coupled to the input I112 of match 112 via RF cable 142, and the output O112 of match 112 is coupled to the lower electrode 151 of substrate support 128 via RF transmission line 148.

[0072] As an example, an RF transmission line such as RF transmission line 144, 146, or 148 includes an RF cable that is coupled to the RF rods of an RF cylinder. The RF cable is surrounded by insulating material which is surrounded by an RF sheath. The RF rods of the RF cylinder are surrounded by an RF cylinder. An RF strap couples the RF cable to the RF rods of the RF cylinder. As another example, an RF transmission line such as RF transmission line 144, 146, or 148 includes an RF cable. The RF cable is surrounded by insulating material which is surrounded by an RF sheath. There is no use of an RF cylinder within the RF transmission line.

[0073] The processor 122 generates a recipe signal 150. The recipe signal 150 includes recipe information, such as the parameters of the RF signal 152 to be generated by the RF generator 102, and the frequency of the RF signal 152. As used herein, the parameters of the RF signal are the voltage or power of the RF signal. The recipe information of the recipe signal 150 further includes the duty cycle of the parameters of the RF signal 152. The processor 122 transmits the recipe signal 150 to the RF generator 102 via the transmission cable 132. Upon receiving the recipe signal 150, the RF generator 102 stores the recipe information of the recipe signal 150 in one or more memory devices of the RF generator 102.

[0074] Similarly, processor 122 generates a recipe signal 154. The recipe signal 154 includes recipe information, such as the parameters of the RF signal 156 to be generated by RF generator 104, and the frequency of RF signal 156. The recipe information of recipe signal 154 further includes the duty cycle of the parameters of RF signal 156. Processor 122 transmits the recipe signal 154 to RF generator 104 via transmission cable 134. Upon receiving the recipe signal 154, RF generator 104 stores the recipe information of the recipe signal 154 in one or more memory devices of RF generator 104.

[0075] The processor 122 also generates a recipe signal 158. The recipe signal 158 includes recipe information, such as the parameters of the RF signal 160 to be generated by the RF generator 106, and the frequency of the RF signal 160. The recipe information of the recipe signal 158 further includes the duty cycle of the parameters of the RF signal 160. For example, the duty cycle of the parameters of the RF signal 160 is 100%, in which case the RF signal 160 is a continuous wave RF signal. A continuous wave RF signal has a single parameter level and does not transition from a first parameter level to a second parameter level. A continuous wave RF signal has a single parameter level during each cycle of the synchronization signal 162. As another example, the duty cycle of the parameters of the RF signal 160 is 50%, in which case the RF signal 160 is pulsed between two states. For example, the RF signal 160 transitions from a first parameter level to a second parameter level and back to the first parameter level during each cycle of the synchronization signal 162. The processor 122 transmits a recipe signal 158 to the RF generator 106 via the transmission cable 136. Upon receiving the recipe signal 158, the RF generator 106 stores the recipe information of the recipe signal 158 in one or more memory devices of the RF generator 106.

[0076] Furthermore, processor 122 generates a synchronization signal 162. Processor 122 transmits the synchronization signal 162 to RF generator 102 via transmission cable 132, to RF generator 104 via transmission cable 134, and to RF generator 106 via transmission cable 136.

[0077] Upon receiving the synchronization signal 162, the RF generator 102 generates an RF signal 152 having the parameters and frequency received in the recipe signal 150. The frequency of the RF signal 152 is the same as the operating frequency of the RF generator 102. The RF generator 102 transmits the RF signal 152 to the input I108 of the match 108 via output O102 and RF cable 138.

[0078] Match 108 modifies the impedance of the RF signal 152 to provide the modified RF signal 164 at output O108 by matching the impedance of the load coupled to output O108 with the impedance of the source coupled to input I108. Examples of loads coupled to output O108 include the RF transmission line 144 and the plasma chamber 118. Examples of sources coupled to input I108 include the RF generator 102 and the RF cable 138. The modified RF signal 164 is supplied from output O108 to the RF coil 116 via the RF transmission line 144. When the modified RF signal 164 is supplied to the RF coil 116, the induced power from the RF coil 116 is supplied to the central region 129 formed by the gap between the substrate support 128 and the dielectric window 126, processing the central region of the substrate S, such as a semiconductor wafer.

[0079] In a similar manner, in response to receiving the synchronization signal 162, the RF generator 104 generates an RF signal 156 having the parameters and frequency received in the recipe signal 154. The frequency of the RF signal 156 is the same as the operating frequency of the RF generator 104. The RF generator 104 transmits the RF signal 156 to the input I110 of the match 110 via output O104 and RF cable 140.

[0080] Match 110 modifies the impedance of the RF signal 156 to provide the modified RF signal 166 at output O110 by matching the impedance of the load coupled to output O110 with the impedance of the source coupled to input I110. Examples of loads coupled to output O110 include the RF transmission line 146 and the plasma chamber 118. Examples of sources coupled to input I110 include the RF generator 104 and the RF cable 140. The modified RF signal 166 is supplied from output O110 to the RF coil 114 via the RF transmission line 146. When the modified RF signal 166 is supplied to the RF coil 114, induced power is supplied from the RF coil 114 to the edge region 131 formed by the gap between the edge ring 130 and the dielectric window 126, thereby processing the edge region of the substrate S.

[0081] The edge region 131 is the periphery of the central region 129. Also, the edge region of the substrate S is the periphery of the central region of the substrate S.

[0082] Furthermore, upon receiving the synchronization signal 162, the RF generator 106 generates an RF signal 160 having the parameters and frequency received in the recipe signal 158. The frequency of the RF signal 160 is the same as the operating frequency of the RF generator 106. The RF generator 106 transmits the RF signal 160 to the input I112 of the match 112 via output O106 and RF cable 142.

[0083] Match 112 modifies the impedance of the RF signal 160 to provide a modified RF signal 168 at output O112 by matching the impedance of the load coupled to output O112 with the impedance of the source coupled to input I112. Examples of loads coupled to output O112 include the RF transmission line 148 and the plasma chamber 118. Examples of sources coupled to input I112 include the RF cable 142 and the RF generator 106. The modified RF signal 168 is supplied from output O112 to the lower electrode 151 via the RF transmission line 148.

[0084] In addition to supplying the modified RF signals 164, 166, and 168, when one or more process gases are supplied to the plasma chamber 118, the plasma is struck or maintained within the plasma chamber 118 to process the substrate S placed on the upper surface of the substrate support 128. Examples of one or more process gases include oxygen-containing gases such as O2. Other examples of one or more process gases include chlorine-containing gases and fluorine-containing gases such as tetrafluoromethane (CF4), sulfur hexafluoride (SF6), and ethane hexafluoride (C2F6). Examples of processing the substrate S include depositing material on the substrate S, etching the substrate S, cleaning the substrate S, and sputtering the substrate S.

[0085] In one embodiment, any of the RF generators 102, 104, and 106 have operating frequencies different from those described with respect to Figure 1A. For example, RF generator 102 has an operating frequency of 400 kHz or 2 MHz or 13.56 MHz or 27 MHz or 60 MHz. As an example, RF generator 104 has an operating frequency of 400 kHz or 2 MHz or 13.56 MHz or 27 MHz or 60 MHz.

[0086] In one embodiment, the RF coil 114 is located in a horizontal plane above or below the horizontal plane in which the RF coil 116 is located.

[0087] In one embodiment, the lower electrode 151 of the substrate support 128 is coupled to ground potential instead of being coupled to the RF generator 106 via a match 112.

[0088] In one embodiment, the dielectric ring is placed between the edge ring 130 and the substrate support 128.

[0089] Figure 1B is a diagram illustrating an embodiment of system 170, which illustrates a lateral RF coil 172. System 170 is structurally and functionally similar to system 100 in Figure 1A, except that system 170 includes a plasma chamber 174 having the lateral RF coil 172. The plasma chamber 174 further includes a dielectric window 176 that replaces a portion of the side wall 178 of the plasma chamber 174. For example, the dielectric window 176 forms the upper wall of the plasma chamber 174 and the upper portion of the side wall 178 of the plasma chamber 174. The dielectric window 176 is positioned over the remaining portion of the side wall 178 of the plasma chamber 174.

[0090] The horizontal RF coil 172 is positioned to the side of the portion of the side wall 178 formed by the dielectric window 176. For example, the horizontal RF coil 172 is in the same horizontal plane as the portion of the side wall 178 formed by the dielectric window 176.

[0091] The output O110 of match 110 is coupled to one end of the horizontal RF coil 172 via the RF transmission line 146. The other end of the horizontal RF coil 172 is coupled to ground potential.

[0092] Figure 2A is an embodiment of Graph 200, illustrating the synchronization signal 202. Graph 200 plots the logic level of the synchronization signal 202 against time t. The synchronization signal 202 is an example of the synchronization signal 162 (Figures 1A and 1B). An example of the synchronization signal 202 is a clock signal. Another example of the synchronization signal 202 is a digital pulse signal with a duty cycle. The logic level of the synchronization signal 202 is plotted on the y-axis, and time t is plotted on the x-axis. As an example, the logic level is a voltage level. For example, logic level 1 corresponds to a voltage level of 5 volts (V), and logic level 0 corresponds to a voltage of 0 volts.

[0093] The x-axis of Graph 200 is divided into equal time intervals, periods, or time segments. For example, the x-axis of Graph 200 is divided into a first time segment between time t0 and time t1, a second time segment between time t1 and time t2, and so on, up to a 20th time segment between time t19 and time 20.

[0094] The synchronization signal 202 has multiple consecutive cycles, such as cycle 1 and cycle 2. Cycle 2 is consecutive to cycle 1. Cycle 1 of the synchronization signal 202 occurs from time t0 to time t10, and cycle 2 of the synchronization signal 202 occurs from time t10 to time t20.

[0095] The synchronization signal 202 pulsates, transitioning from logic level 0 to logic level 1 at time t0, and remains at logic level 1 from time t0 to time t5. Furthermore, the synchronization signal 202 transitions from logic level 1 to logic level 0 at time t5, and remains at logic level 0 from time t5 to time t10. Moreover, the synchronization signal 202 pulsates from logic level 0 to logic level 1 at time t10, and remains at logic level 1 from time t10 to time t15. The synchronization signal 202 transitions from logic level 1 to logic level 0 at time t15, and remains at logic level 0 from time t15 to time t20.

[0096] In one embodiment, the synchronization signal 202 has a duty cycle different from the 50% duty cycle described with respect to Figure 2A. For example, the synchronization signal 202 has a duty cycle of 10%, 20%, 30%, or 60%.

[0097] Figure 2B is an embodiment of Graph 204, illustrating a digital pulse signal 206 for illustrating the duty cycle of the parameters of the RF signal 152 generated by the RF generator 102. Graph 204 plots the logic level of the digital pulse signal 206 against time t. The logic level of the digital pulse signal 206 is plotted on the y-axis, and time t is plotted on the x-axis.

[0098] The digital pulse signal 206 has a duty cycle of 45%. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 206 transitions from logic level 0 to logic level 1 at time t0, and remains at logic level 1 from time t0 to time t4.5, which is half the time period between times t4 and t5. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 206 transitions from logic level 1 to logic level 0 at time t4.5, and remains at logic level 0 from time t4.5 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 206 transitions from logic level 0 to logic level 1 at time t10, and remains at logic level 1 from time t10 to time t14.5, which is half the time period between times t14 and t15. During cycle 2 of the synchronization signal 202, the digital pulse signal 206 transitions from logic level 1 to logic level 0 at time t14.5 and remains at logic level 0 from time t14.5 to time t20. Thus, during each cycle of the synchronization signal 202, the digital pulse signal 206 has logic level 1 for a period of time accounting for 45% of the cycle and logic level 0 for the remaining period accounting for 55% of the cycle. The duty cycle of the parameters of the RF signal 152 is provided in the recipe signal 150 transmitted from the processor 122 (Figures 1A and 1B) to the RF generator 102 (Figures 1A and 1B) via the transmission cable 132.

[0099] In one embodiment, instead of a 45% duty cycle, the digital pulse signal 206 has a duty cycle greater than or less than 45%. For example, the digital pulse signal 206 has a duty cycle of 35%, 55%, or 65%.

[0100] Figure 2C is an embodiment of Graph 208 illustrating a digital pulse signal 210 for illustrating the duty cycle of the parameters of the RF signal 156 generated by the RF generator 104. Graph 208 plots the logic level of the digital pulse signal 210 against time t. The logic level of the digital pulse signal 210 is plotted on the y-axis, and time t is plotted on the x-axis.

[0101] The digital pulse signal 210 has a duty cycle of 55% and is inversely synchronized with the digital pulse signal 206 (Figure 2B). For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t0 and remains at logic level 0 from time t0 to time t4.5. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t4.5 and remains at logic level 1 from time t4.5 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t14.5. During cycle 2 of the synchronization signal 202, the digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t14.5 and remains at logic level 1 from time t14.5 to time t20. Thus, during each cycle of the synchronization signal 202, the digital pulse signal 210 has logic level 1 for a period of time accounting for 55% of the cycle and logic level 0 for the remaining period accounting for 45% of the cycle. Also, during each cycle of the synchronization signal 202, the digital pulse signal 210 has an opposite logic level compared to the logic level of the digital pulse signal 206 so as to be inversely synchronized with the digital pulse signal 206. The duty cycle of the parameters of the RF signal 156 is provided in the recipe signal 154 transmitted from the processor 122 (Figures 1A and 1B) to the RF generator 104 (Figures 1A and 1B) via the transmission cable 134.

[0102] In one embodiment, instead of a 55% duty cycle, the digital pulse signal 210 has a duty cycle greater than or less than 55%. For example, the digital pulse signal to time may have a duty cycle of 25%, 65%, or 75%. For example, when the digital pulse signal 206 has a 55% duty cycle, the digital pulse signal 210 has a duty cycle that is the difference between 100% and 55%, and this difference is 45%. As another example, when the digital pulse signal 206 has a 25% duty cycle, the digital pulse signal 210 has a duty cycle that is the difference between 100% and 25%, and this difference is 75%.

[0103] Figure 2D is an embodiment of Graph 212, illustrating the parameters 214 of the RF signal 216. The RF signal 216 is an example of the RF signal 152 generated by the RF generator 102 (Figures 1A and 1B). Graph 212 plots the parameters 214 on the y-axis and time t on the x-axis.

[0104] An example of parameter levels for RF signal parameters is the envelope of the RF signal, such as the peak-to-peak amplitude or zero-to-peak amplitude. For example, parameter 214 is the envelope of RF signal 216, having a set of parameter levels P1 and -P1 during a portion of each cycle of synchronization signal 202, and a zero parameter level for the remainder of the cycle. For example, the first parameter level includes one or more parameter values, the second parameter level includes one or more parameter values, and one or more parameter values ​​of the second parameter level are different from one or more values ​​of the first parameter level, and so on. For example, when the first parameter level is greater than the second parameter level, the minimum value of one or more parameter values ​​of the first parameter level is greater than the maximum value of one or more parameter values ​​of the second parameter level.

[0105] The parameter 214 of the RF signal 216 is synchronized with the duty cycle of the digital pulse signal 206 (Figure 2B). For example, during cycle 1 of the synchronization signal 202 (Figure 2A), the parameter 214 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t0. During cycle 1 of the synchronization signal 202, the parameter 214 remains at parameter levels P1 and -P1 from time t0 to time t4.5, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t4.5. Also, during cycle 1 of the synchronization signal 202, the parameter 214 remains at parameter level 0 from time t4.5 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 2A), the parameter 214 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t10. During cycle 2 of the synchronization signal 202, parameter 214 remains at parameter levels P1 and -P1 from time t10 to time t14.5, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t14.5. Also, during cycle 2 of the synchronization signal 202, parameter 214 remains at parameter level 0 from time t14.5 to time t20.

[0106] It should be noted that a set of parameter levels for an RF signal corresponds to a state of the RF signal. For example, parameter levels P1 and -P1 define state S1 of RF signal 216, and a parameter level of zero defines state S0 of RF signal 216.

[0107] It should be further noted that each parameter level of an RF signal contains one or more values ​​of the RF signal's parameters. For example, parameter level P1 contains multiple positive values ​​of the power or voltage of RF signal 216, and parameter level -P1 contains multiple negative values ​​of the power or voltage of RF signal 216. As another example, the parameter level of zero contains multiple values ​​of the power or voltage of RF signal 216. For illustrative purposes, the parameter level of zero is substantially zero. For further illustrative purposes, the parameter level of zero contains a set of two parameter levels, where the first parameter level is a positive parameter level between zero and parameter level P1, and the second parameter level is a negative parameter level between -P1 and zero. Positive and negative parameter levels are substantially zero, for example, from zero to a default range. An example of a default range is 1% to 5%.

[0108] In one embodiment, instead of transitioning to parameter level zero at times t4.5 and t14.5, parameter 214 transitions to a positive parameter level greater than zero at times t4.5 and t14.5. For example, at each time t4.5 and t14.5, parameter 214 transitions from parameter level P1 to a positive parameter level between zero and P1, and from parameter level -P1 to a negative parameter level between zero and -P1. At each time t10 and t20, parameter 214 transitions from a positive parameter level to parameter level P1, and from a negative parameter level to parameter level -P1. Parameter levels P1 and -P1 define state S1 of RF signal 216, and the positive and negative parameter levels define state S0 of RF signal 216. Note that one or more values ​​of a positive parameter level do not include one or more values ​​of parameter level P1, and one or more values ​​of a negative parameter level do not include one or more values ​​of parameter level -P1. For example, the minimum value of one or more values ​​of parameter level P1 is greater than the maximum value of one or more values ​​of a positive parameter level, and the minimum value of one or more values ​​of a negative parameter level is greater than the maximum value of one or more values ​​of parameter level -P1.

[0109] In one embodiment, instead of an RF signal parameter transitioning from a first state to a second state at a given time, the parameter transitions from a first state to a second state over a certain time period or interval. For example, instead of parameter 214 transitioning at time t4.5, it transitions from state S1 to state S0 over a certain time period, such as the time interval from time t4.5 to time t5.5 or from time t4.5 to time t5. Similarly, instead of a parameter transitioning from a second state to a first state at a given time, the parameter transitions from a second state to a first state over a certain time period or interval.

[0110] Figure 2E is an embodiment of Graph 218, illustrating the parameter 220 of the RF signal 222. The RF signal 222 is an example of the RF signal 156 generated by the RF generator 104 (Figures 1A and 1B). Graph 218 plots the parameter 220 on the y-axis and time t on the x-axis. The parameter 220 is the envelope of the RF signal 222.

[0111] The parameter 220 of the RF signal 222 is synchronized with the duty cycle of the digital pulse signal 210 (Figure 2C), and during each cycle of the synchronization signal 202, parameter 220 has the opposite state compared to the state of parameter 214 so as to be inversely synchronized with parameter 214 (Figure 2C). For example, during cycle 1 of the synchronization signal 202 (Figure 2A), parameter 220 transitions at time t0 from a set of parameter levels P2 and -P2 to a parameter level of zero, where P2 is a different parameter level from parameter level P1. For example, parameter level P1 is greater than or less than parameter level P1.

[0112] During cycle 1 of the synchronization signal 202, parameter 220 remains at a parameter level of zero from time t0 to time t4.5, and at time t4.5, it transitions from a parameter level of zero to parameter levels P2 and -P2. Also during cycle 1 of the synchronization signal 202, parameter 220 remains at parameter levels P2 and -P2 from time t4.5 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 2A), parameter 220 transitions from parameter levels P2 and -P2 to a parameter level of zero at time t10. During cycle 2 of the synchronization signal 202, parameter 220 remains at a parameter level of zero from time t10 to time t14.5, and at time t14.5, it transitions from a parameter level of zero to parameter levels P2 and -P2. Furthermore, during cycle 2 of the synchronization signal 202, the parameter 220 remains at parameter levels P2 and -P2 from time t14.5 to time t20.

[0113] It should be noted that a parameter level of zero defines state S0 of the RF signal 222, and parameter levels P2 and -P2 define state S1 of the RF signal 222. It should be further noted that parameter level P2 includes multiple positive values ​​of the power or voltage of the RF signal 222, and parameter level -P2 includes multiple negative values ​​of the power or voltage of the RF signal 222. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of the RF signal 222. For example, the parameter level of zero for parameter 220 of the RF signal 222 is substantially zero.

[0114] In one embodiment, instead of transitioning to parameter level zero at times t0 and t10, parameter 220 transitions to a positive parameter level greater than zero at times t0 and t10. For example, at each time t0 and t10, parameter 220 transitions from parameter level P2 to a positive parameter level between zero and P2, and from parameter level -P2 to a negative parameter level between zero and -P2. At each time t4.5 and t14.5, parameter 220 transitions from a positive parameter level to parameter level P2, and from a negative parameter level to parameter level -P2. Parameter levels P2 and -P2 define state S1 of RF signal 222, and the positive and negative parameter levels define state S0 of RF signal 222. Note that one or more values ​​of a positive parameter level do not include one or more values ​​of parameter level P2, and one or more values ​​of a negative parameter level do not include one or more values ​​of parameter level -P2. For example, the minimum value of one or more values ​​at parameter level P2 is greater than the maximum value of one or more values ​​at a positive parameter level, and the minimum value of one or more values ​​at a negative parameter level is greater than the maximum value of one or more values ​​at parameter level -P2.

[0115] In one embodiment, instead of the parameter 220 transitioning at time t4.5, it transitions from state S0 to state S1 over a certain time period, such as from time t4.5 to time t5.5 or from time t4.5 to time t5. Similarly, instead of the parameter transitioning from a second state to a first state at a certain time, the parameter 220 transitions from a second state to a first state over a certain time period or time interval.

[0116] In one embodiment, parameter level P2 is the same as or equal to parameter level P1.

[0117] Figure 3A is an embodiment of Graph 200 and is intended to illustrate the synchronization signal 202.

[0118] Figure 3B is an embodiment of graph 300, illustrating a digital pulse signal 302 for illustrating the duty cycle of the parameters of the RF signal 152 generated by the RF generator 102. Graph 300 plots the logic level of the digital pulse signal 302 against time t. The logic level of the digital pulse signal 302 is plotted on the y-axis, and time t is plotted on the x-axis.

[0119] The digital pulse signal 302 has a duty cycle of 25% instead of 45%. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 302 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t2.5, which is half the time period between times t2 and t3. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 302 transitions from logic level 1 to logic level 0 at time t2.5 and remains at logic level 0 from time t2.5 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 302 transitions from logic level 0 to logic level 1 at time t10 and remains at logic level 1 from time t10 to time t12.5. During cycle 2 of the synchronization signal 202, the digital pulse signal 302 transitions from logic level 1 to logic level 0 at time t12.5 and remains at logic level 0 from time t12.5 to time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 302 has logic level 1 for a period of time accounting for 25% of the cycle and logic level 0 for the remaining period accounting for 75% of the cycle.

[0120] Figure 3C is an embodiment of Graph 304, illustrating a digital pulsed signal 306 for illustrating the duty cycle of the parameters of the RF signal 156 generated by the RF generator 104 (Figures 1A and 1B). Graph 304 plots the logic level of the digital pulsed signal 306 against time t. The logic level of the digital pulsed signal 306 is plotted on the y-axis, and time t is plotted on the x-axis.

[0121] The digital pulse signal 306 has a duty cycle of 75% and is inversely synchronized with the digital pulse signal 302 (Figure 3B). For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 306 transitions from logic level 1 to logic level 0 at time t0 and remains at logic level 0 from time t0 to time t2.5. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 306 transitions from logic level 0 to logic level 1 at time t2.5 and remains at logic level 1 from time t2.5 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 306 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t12.5. During cycle 2 of the synchronization signal 202, the digital pulse signal 306 transitions from logic level 0 to logic level 1 at time t12.5 and remains at logic level 1 from time t12.5 to time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 306 has logic level 1 for a period of time accounting for 75% of the cycle and logic level 0 for the remaining period accounting for 25% of the cycle. Also, during each cycle of the synchronization signal 202, the digital pulse signal 306 has a logic level opposite to that of the digital pulse signal 302, so as to be inversely synchronized with the digital pulse signal 302.

[0122] Figure 3D is an embodiment of Graph 308, illustrating the parameters 310 of the RF signal 312. The RF signal 312 is an example of the RF signal 152 generated by the RF generator 102 (Figures 1A and 1B). Graph 308 plots the parameters 310 on the y-axis and time t on the x-axis. As an example, the parameters 310 are the envelope of the RF signal 312.

[0123] The parameter 310 of the RF signal 312 is synchronized with the duty cycle of the digital pulse signal 302 (Figure 3B). For example, during cycle 1 of the synchronization signal 202 (Figure 3A), the parameter 310 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t0. During cycle 1 of the synchronization signal 202, the parameter 310 remains at parameter levels P1 and -P1 from time t0 to time t2.5, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t2.5. Also, during cycle 1 of the synchronization signal 202, the parameter 310 remains at parameter level 0 from time t2.5 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 3A), the parameter 310 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t10. During cycle 2 of the synchronization signal 202, the parameter 310 remains at parameter levels P1 and -P1 from time t10 to time t12.5, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t12.5. Also, during cycle 2 of the synchronization signal 202, the parameter 310 remains at parameter level 0 from time t12.5 to time t20.

[0124] Note that parameter levels P1 and -P1 define state S1 of RF signal 312, and a parameter level of zero defines state S0 of RF signal 312.

[0125] It should be further noted that parameter level P1 includes multiple positive values ​​of the power or voltage of the RF signal 312, and parameter level -P1 includes multiple negative values ​​of the power or voltage of the RF signal 312. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of the RF signal 312. For example, a parameter level of zero is substantially zero.

[0126] In one embodiment, instead of transitioning to parameter level zero at times t2.5 and t12.5, parameter 310 transitions to a positive parameter level greater than zero at times t2.5 and t12.5. For example, at each time t2.5 and t12.5, parameter 310 transitions from parameter level P1 to a positive parameter level between zero and P1, and from parameter level -P1 to a negative parameter level between zero and -P1. At each time t10 and t20, parameter 310 transitions from a positive parameter level to parameter level P1, and from a negative parameter level to parameter level -P1. Parameter levels P1 and -P1 define state S1 of RF signal 312, and the positive and negative parameter levels define state S0 of RF signal 312.

[0127] In one embodiment, instead of transitioning at time t2.5, parameter 310 transitions from state S1 to state S0 over a certain time period, such as the time interval from time t2.5 to time t3.5 or from time t2.5 to time t3. Time t3.5 is halfway between times t3 and t4. Similarly, instead of the parameter transitioning from state S0 to state S1 at a certain time, parameter 310 transitions from state S0 to state S1 over a certain time period or time interval.

[0128] Figure 3E is an embodiment of Graph 314, illustrating the parameter 316 of the RF signal 318. The RF signal 318 is an example of the RF signal 156 generated by the RF generator 104 (Figures 1A and 1B). Graph 314 plots the parameter 316 on the y-axis and time t on the x-axis. The parameter 316 is the envelope of the RF signal 318.

[0129] The parameter 316 of the RF signal 318 is synchronized with the duty cycle of the digital pulse signal 306 (Figure 3C), and during each cycle of the synchronization signal 202, parameter 316 has a state opposite to that of parameter 310, so as to be inversely synchronized with parameter 310. For example, during cycle 1 of the synchronization signal 202 (Figure 3A), parameter 316 transitions from a set of parameter levels P2 and -P2 to a parameter level of zero at time t0. During cycle 1 of the synchronization signal 202, parameter 316 remains at a parameter level of zero from time t0 to time t2.5, and then transitions from a parameter level of zero to parameter levels P2 and -P2 at time t2.5. Also, during cycle 1 of the synchronization signal 202, parameter 316 remains at parameter levels P2 and -P2 from time t2.5 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 3A), the parameter 316 transitions from parameter levels P2 and -P2 to zero at time t10. During cycle 2 of the synchronization signal 202, the parameter 316 remains at zero from time t10 to time t12.5, and then transitions from zero to parameter levels P2 and -P2 at time t12.5. Also, during cycle 2 of the synchronization signal 202, the parameter 316 remains at parameter levels P2 and -P2 from time t12.5 to time t20.

[0130] It should be noted that a parameter level of zero defines state S0 of the RF signal 318, and parameter levels P2 and -P2 define state S1 of the RF signal 318. It should be further noted that parameter level P2 includes multiple positive values ​​of the power or voltage of the RF signal 318, and parameter level -P2 includes multiple negative values ​​of the power or voltage of the RF signal 318. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of the RF signal 318. For example, the parameter level of zero for parameter 316 of the RF signal 318 is substantially zero.

[0131] In one embodiment, instead of transitioning to parameter level zero at times t0 and t10, parameter 316 transitions to a positive parameter level greater than zero at times t0 and t10. For example, at each time t0 and t10, parameter 316 transitions from parameter level P2 to a positive parameter level between zero and P2, and from parameter level -P2 to a negative parameter level between zero and -P2. At each time t2.5 and t12.5, parameter 316 transitions from a positive parameter level to parameter level P2, and from a negative parameter level to parameter level -P2. Parameter levels P2 and -P2 define state S1 of RF signal 318, and the positive and negative parameter levels define state S0 of RF signal 318.

[0132] In one embodiment, instead of transitioning at time t2.5, parameter 316 transitions from state S0 to state S1 over a certain time period, such as from time t2.5 to time t3.5 or from time t2.5 to time t3. Similarly, instead of a parameter transitioning from state S1 to state S0 at a certain time, parameter 316 transitions from state S1 to state S0 over a certain time period or time interval.

[0133] Figure 4A is an embodiment of Graph 200 and is intended to illustrate the synchronization signal 202.

[0134] Figure 4B is an embodiment of graph 400, illustrating a digital pulse signal 402 to illustrate the duty cycle of the parameters of the RF signal 152 generated by the RF generator 102. Graph 400 plots the logic level of the digital pulse signal 402 against time t. The logic level of the digital pulse signal 402 is plotted on the y-axis, and time t is plotted on the x-axis.

[0135] The digital pulse signal 402 has a duty cycle of 45%, and the duty cycle is divided into two time intervals. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 0 to logic level 1 at time t0, and remains at logic level 1 from time t0 to time t2. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 1 to logic level 0 at time t2, and remains at logic level 0 from time t2 to time t5. Furthermore, during cycle 1 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 0 to logic level 1 at time t5, and remains at logic level 1 from time t5 to time t7.5, which is halfway between time t7 and time t8. Furthermore, during cycle 1 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 1 to logic level 0 at time t7.5, and remains at logic level 0 from time t7.5 to time t10. The time period accounting for 45% of cycle 1 is divided into the time interval from time t0 to t2 and the time interval from time t5 to t7.5. The time period accounting for 55% of cycle 1 is divided into the time interval from time t2 to t5 and the time interval from time t7.5 to t10.

[0136] Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 0 to logic level 1 at time t10, and remains at logic level 1 from time t10 to time t12. During cycle 2 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 1 to logic level 0 at time t12, and remains at logic level 0 from time t12 to time t15. Also, during cycle 2 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 0 to logic level 1 at time t15, and remains at logic level 1 from time t15 to time t17.5, which is half the time interval between times t17 and t18. During cycle 2 of the synchronization signal 202, the digital pulse signal 402 transitions from logic level 1 to logic level 0 at time t17.5, and remains at logic level 0 from time t17.5 to time t20. The time period accounting for 45% of Cycle 2 is divided into two time intervals: t10–t12 and t15–t17.5. The time period accounting for 55% of Cycle 2 is divided into two time intervals: t12–t15 and t17.5–t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 402 has a logic level of 1 for the time period accounting for 45% of the cycle and a logic level of 0 for the remaining time period accounting for 55% of the cycle. The 45% duty cycle is divided into two time intervals, and the zero logic level is also divided into two time intervals.

[0137] Figure 4C is an embodiment of Graph 404, illustrating a digital pulse signal 406 for illustrating the duty cycle of the parameters of the RF signal 156 generated by the RF generator 104. Graph 404 plots the logic level of the digital pulse signal 406 against time t. The logic level of the digital pulse signal 406 is plotted on the y-axis, and time t is plotted on the x-axis.

[0138] The digital pulse signal 406 has a 55% duty cycle that can be divided into two time intervals and is inversely synchronized with the digital pulse signal 402 (Figure 4B). For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 1 to logic level 0 at time t0 and remains at logic level 0 from time t0 to time t2. Also, during cycle 1 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 0 to logic level 1 at time t2 and remains at logic level 1 from time t2 to time t5. During cycle 1 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 1 to logic level 0 at time t5 and remains at logic level 0 from time t5 to time t7.5. Furthermore, during cycle 1 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 0 to logic level 1 at time t7.5, and remains at logic level 1 from time t7.5 to time t10.

[0139] Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t12. During cycle 2 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 0 to logic level 1 at time t12 and remains at logic level 1 from time t12 to time t15. During cycle 2 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 1 to logic level 0 at time t15 and remains at logic level 0 from time t15 to time t17.5. During cycle 2 of the synchronization signal 202, the digital pulse signal 406 transitions from logic level 0 to logic level 1 at time t17.5 and remains at logic level 1 from time t17.5 to time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 406 has a logic level of 1 for the duration occupying 55% of the cycle and a logic level of 0 for the remaining duration occupying 45% of the cycle. The duty cycle of the digital pulse signal 406 is 55%. Also, during each cycle of the synchronization signal 202, the digital pulse signal 406 has a logic level opposite to that of the digital pulse signal 402, so as to be inversely synchronized with the digital pulse signal 402.

[0140] Figure 4D is an embodiment of Graph 408, illustrating the parameter 410 of the RF signal 412. The RF signal 412 is an example of the RF signal 152 generated by the RF generator 102 (Figures 1A and 1B). Graph 408 plots the parameter 410 on the y-axis and time t on the x-axis. As an example, parameter 410 is the envelope of the RF signal 412.

[0141] The parameter 410 of the RF signal 412 is synchronized with the duty cycle of the digital pulse signal 402 (Figure 4B). For example, during cycle 1 of the synchronization signal 202 (Figure 4A), the parameter 410 transitions from parameter level zero to parameter levels P1 and -P1 at time t0. During cycle 1 of the synchronization signal 202, the parameter 410 remains at parameter levels P1 and -P1 from time t0 to time t2, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t2. Also during cycle 1 of the synchronization signal 202, the parameter 410 remains at parameter level 0 from time t2 to time t5. Furthermore, during cycle 1 of the synchronization signal 202, the parameter 410 remains at parameter levels P1 and -P1 from time t5 to time t7.5, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t7.5. Furthermore, during cycle 1 of the synchronization signal 202, parameter 410 remains at parameter level 0 from time t7.5 to time t10.

[0142] Similarly, during cycle 2 of the synchronization signal 202 (Figure 3A), parameter 410 transitions from parameter level zero to parameter levels P1 and -P1 at time t10. During cycle 2 of the synchronization signal 202, parameter 410 remains at parameter levels P1 and -P1 from time t10 to time t12, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t12. Also, during cycle 2 of the synchronization signal 202, parameter 410 remains at parameter level 0 from time t12 to time t15, and then transitions from parameter level 0 to parameter level P1 at time t15. During cycle 2 of the synchronization signal 202, parameter 410 remains at parameter levels P1 and -P1 from time t15 to time t17.5, and then transitions from parameter levels P1 and -P1 to parameter level zero at time t17.5. During cycle 2 of the synchronization signal 202, parameter 410 remains at parameter level zero from time t17.5 to time t20. Note that parameter levels P1 and -P1 define state S1 of RF signal 412, and a parameter level of zero defines state S0 of RF signal 412.

[0143] It should be further noted that parameter level P1 includes multiple positive values ​​of the power or voltage of the RF signal 412, and parameter level -P1 includes multiple negative values ​​of the power or voltage of the RF signal 412. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of the RF signal 412. For example, a parameter level of zero is substantially zero.

[0144] In one embodiment, instead of transitioning to parameter level zero at times t2 and t7.5, parameter 410 transitions to a positive parameter level greater than zero at times t2 and t7.5. For example, at each time t2 and t7.5, parameter 410 transitions from parameter level P1 to a positive parameter level between zero and P1, and from parameter level -P1 to a negative parameter level between zero and -P1. At each time t0 and t5, parameter 410 transitions from a positive parameter level to parameter level P1, and from a negative parameter level to parameter level -P1. Parameter levels P1 and -P1 define state S1 of RF signal 412, and the positive and negative parameter levels define state S0 of RF signal 412.

[0145] In one embodiment, instead of transitioning at time t2, parameter 410 transitions from state S1 to state S0 over a certain time period, such as the time interval from time t2 to time t3 or from time t2 to time t2.5. Similarly, instead of parameter 410 transitioning from state S0 to state S1 at some point in time, parameter 410 transitions from a second state to a first state over a certain time period or time interval.

[0146] While two instances of pulsing of parameter 410 are illustrated with respect to Figure 4D, it should be noted that in one embodiment, more instances of pulsing of parameter 410 occur during each cycle of the synchronization signal 202. For example, during cycle 1 of the synchronization signal 202, in addition to having two instances of pulsing as illustrated with respect to Figure 4D, parameter 410 pulsates at time t8, transitioning from parameter level 0 to parameter levels P1 and -P1, and remains at parameter levels P1 and -P1 from time t8 to time t9. During cycle 1 of the synchronization signal 202, parameter 410 pulsates at time t9, transitioning from parameter levels P1 and -P1 to parameter level zero, and remains at parameter level zero from time t9 to time t10. In this example, parameter 410 pulsates three times instead of two during cycle 1 of the synchronization signal 202.

[0147] Figure 4E is an embodiment of Graph 414, illustrating the parameter 416 of the RF signal 418. The RF signal 418 is an example of the RF signal 156 generated by the RF generator 104 (Figures 1A and 1B). Graph 414 plots the parameter 416 on the y-axis and time t on the x-axis. The parameter 416 is the envelope of the RF signal 418.

[0148] The parameter 416 of the RF signal 418 is synchronized with the duty cycle of the digital pulse signal 406 (Figure 4C), and during each cycle of the synchronization signal 202, parameter 416 has a state opposite to that of parameter 410, so as to be inversely synchronized with parameter 410. For example, during cycle 1 of the synchronization signal 402 (Figure 4A), parameter 416 transitions from a set of parameter levels P2 and -P2 to a parameter level of zero at time t0. During cycle 1 of the synchronization signal 202, parameter 416 remains at a parameter level of zero from time t0 to time t2, and then transitions from a parameter level of zero to parameter levels P2 and -P2 at time t2. Also, during cycle 1 of the synchronization signal 202, parameter 416 remains at parameter levels P2 and -P2 from time t2 to time t5. Furthermore, during cycle 1 of the synchronization signal 202, parameter 416 remains at a parameter level of zero from time t5 to time t7.5, and at time t7.5, it transitions from a parameter level of zero to parameter levels P2 and -P2. Also, during cycle 1 of the synchronization signal 202, parameter 416 remains at parameter levels P2 and -P2 from time t7.5 to time t10.

[0149] Similarly, during cycle 2 of the synchronization signal 202 (Figure 3A), parameter 416 transitions from parameter levels P2 and -P2 to zero at time t10. During cycle 2 of the synchronization signal 202, parameter 416 remains at zero from time t10 to time t12, and then transitions from zero to parameter levels P2 and -P2 at time t12. Also during cycle 2 of the synchronization signal 202, parameter 416 remains at parameter levels P2 and -P2 from time t12 to time t15. Furthermore, during cycle 2 of the synchronization signal 202, parameter 416 remains at zero from time t15 to time t17.5, and then transitions from zero to parameter levels P2 and -P2 at time t17.5. Furthermore, during cycle 2 of the synchronization signal 202, the parameter 416 remains at parameter levels P2 and -P2 from time t17.5 to time t20.

[0150] It should be noted that a parameter level of zero defines state S0 of the RF signal 418, and parameter levels P2 and -P2 define state S1 of the RF signal 418. It should be further noted that parameter level P2 includes multiple positive values ​​of the power or voltage of the RF signal 418, and parameter level -P2 includes multiple negative values ​​of the power or voltage of the RF signal 418. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of the RF signal 418. For example, the parameter level of zero for parameter 416 of the RF signal 418 is substantially zero.

[0151] In one embodiment, instead of transitioning to parameter level zero at times t0 and t10, parameter 416 transitions to a positive parameter level greater than zero at times t0 and t10. For example, at each time t0 and t10, parameter 416 transitions from parameter level P2 to a positive parameter level between zero and P2, and from parameter level -P2 to a negative parameter level between zero and -P2. At each time t2 and t7.5, parameter 416 transitions from a positive parameter level to parameter level P2, and from a negative parameter level to parameter level -P2. Parameter levels P2 and -P2 define state S1 of RF signal 418, and the positive and negative parameter levels define state S0 of RF signal 418.

[0152] In one embodiment, instead of transitioning at time t2, parameter 416 transitions from state S0 to state S1 over a certain time period, such as the time interval from time t2 to time t3 or the time interval from time t2 to time t2.5. Similarly, instead of parameter 416 transitioning from state S1 to state S0 at a certain time, parameter 416 transitions from state S1 to state S0 over a certain time period or time interval.

[0153] While two instances of pulsing of parameter 416 are illustrated with respect to Figure 4E, it should be noted that in one embodiment, more instances of pulsing of parameter 416 occur during each cycle of the synchronization signal 202. For example, during cycle 1 of the synchronization signal 202, in addition to having two instances of pulsing from time t2 to time t5 and from time t7.5 to time t10, as illustrated with respect to Figure 4E, parameter 416 pulsates at time t6, transitioning from parameter level zero to parameter levels P2 and -P2, and remaining at parameter levels P2 and -P2 from time t6 to time t7. During cycle 1 of the synchronization signal 202, parameter 416 pulsates at time t7, transitioning from parameter levels P2 and -P2 to parameter level zero, and remains at parameter level zero from time t7 to time t7.5. In this example, parameter 416 pulsates three times instead of twice during cycle 1 of the synchronization signal 202.

[0154] Figure 5 is a diagram of computer system 500, illustrating a user interface for controlling the multiplexing operation of RF generators 102 and 104 (Figure 1A). Computer system 500 is an example of host computer 120 (Figure 1A). System 500 includes a display device 502, a keyboard 504, and an optical mouse 506. The display device 502, keyboard 504, and optical mouse 506 are examples of input devices. For example, the display device 502 has a touchscreen for receiving selections from the user. The touchscreen is an example of an input device. An example of display device 502 includes a combination of a display screen 508, a central processing unit (CPU), a memory device, and a graphics processing unit (GPU). The CPU, GPU, memory device, and display screen 508 of display device 502 are coupled to each other via a bus. The CPU of display device 502 is an example of processor 122 (Figure 1A) of host computer 120. The keyboard 504 and optical mouse 506 are wirelessly coupled to the CPU of the display device 502.

[0155] During operation, the CPU and GPU control the display screen 508 to display graphic buttons 510 for selecting a multiplexing operation for time-division multiplexing of RF signals 152 and 156 (Figures 1A and 1B). For example, in response to receiving a selection of graphic buttons 510 from the user via a keyboard 504, optical mouse 506, or touchscreen, the CPU generates duty cycles described in Figures 2B, 2C, 3B, 3C, 4B, and 4C for transmission to the corresponding RF generators 102 and 104. The duty cycle of RF generator 104 is inversely synchronized with the duty cycle of RF generator 102.

[0156] Furthermore, the CPU and GPU control the display screen 508 to display a graphic button 512 in order to receive a selection regarding whether RF generator 102 will start in state S1 at time t0, or whether RF generator 104 will start in state S1 at time t0. For example, in response to receiving a selection from graphic button 514, the CPU decides to control RF generator 102 to start in state S1 at time t0, and RF generator 104 to start in state S0 at time t0. As another example, in response to receiving a selection from graphic button 516, the CPU decides to control RF generator 104 to start in state S1 at time t0, and RF generator 102 to start in state S0 at time t0. This selection regarding whether RF generator 102 will start in state S1 at time t0, or whether RF generator 104 will start in state S1 at time t0, is received from the user via the keyboard 504, optical mouse 506, or touchscreen.

[0157] The CPU and GPU also control the display screen 508 to show a graphics button 518 in order to receive the duty cycle of the RF generator 102. For example, duty cycles of 25%, 35%, 45%, or 28% of the operation of the RF generator 102 are received from the user via the keyboard 504, optical mouse 506, or touchscreen.

[0158] Note that in response to receiving selections of graphic buttons 510, 512, and 514 or 516, and 518, recipe signals 150 and 154 (Figures 1A and 1B) are generated. For example, recipe signal 150 includes the duty cycle of operation of RF generator 102 to generate parameter state S1 of RF signal 152, and recipe signal 154 includes the duty cycle of operation of RF generator 104 to generate parameter state S1 of RF signal 156. Recipe signal 150 also includes an instruction from processor 122 (Figure 1A) to RF generator 102 to operate in reverse sync with RF generator 104. Similarly, recipe signal 154 includes an instruction from processor 122 (Figure 1A) to RF generator 104 to operate in reverse sync with RF generator 102.

[0159] In one embodiment, instead of the CPU being contained within the display device 502, the CPU is implemented in a separate housing from the housing of the display device 502.

[0160] In one embodiment, each of the keyboard 504 and optical mouse 506 is connected to the CPU of the display device 502 via a wired connection such as a cable. For example, each of the keyboard 504 and optical mouse 506 is connected to the CPU of the display device 502 via a Universal Serial Bus (USB) cable.

[0161] In one embodiment, instead of graphics buttons, a dropdown menu is displayed on the display screen 508 by the CPU and GPU.

[0162] Figure 6A is an embodiment of graph 600, illustrating plot 602 of the ion flux η of the plasma in plasma chamber 118 or 174 (Figures 1A and 1B) against the radius r of the substrate S placed in the plasma chamber. The ion flux is plotted on the y-axis, and the radius r is plotted on the x-axis. Plot 602 is generated over one cycle of synchronization signal 162 (Figures 1A and 1B) when the parameters of RF signal 152 generated by RF generator 102 (Figures 1A and 1B) are in state S1, and when the parameters of RF signal 156 generated by RF generator 104 are in state S0. Note from plot 602 that the ion density decreases from 0 at the center of the substrate S to a positive value R of the radius r of the substrate S.

[0163] Graph 600 further includes plot 604 of the plasma sheath thickness s of the plasma in the plasma chamber 118 or 174, such as the upper plasma sheath, against the radius R of the substrate S. Note from plot 604 that the plasma sheath thickness s increases along the radius r of the substrate S from a central 0 to a positive value R of the substrate radius R. For example, the thickness s increases from a minimum value smin1 at the center 0 of the substrate S to a maximum value smax1 closer to the radius R. The values ​​smin1 and smax1 are measured from a reference value sref of the thickness s. For example, the reference value sref1 is the value at the bottom surface of the plasma sheath, and the values ​​smin1 and smax1 are the values ​​at the top surface of the plasma sheath.

[0164] It should be further noted that the ion flux is inversely proportional to the square of the thickness s, i.e., the thickness is inversely proportional to the square root of the ion flux. Also, the variable x is the difference between the maximum thickness smax of the plasma sheath and the minimum thickness smin of the plasma sheath. The angular slope Φ of the plasma ions in the plasma chamber 118 or 174 is the inverse tangent of the ratio of the difference x and the radius r. In the case of plot 604, the angular slope has a value Φ1 at the radius value R1 of the substrate S. The value Φ1 is measured relative to the vertical line 605 at the radius value R1.

[0165] In one embodiment, plot 602 is the ion density of the plasma in the plasma chamber 118 or 174.

[0166] Figure 6B is an embodiment of graph 606, illustrating plot 608 of the ion flux η of the plasma in plasma chamber 118 or 174 (Figures 1A and 1B) against the radius r of the substrate S placed in the plasma chamber. The ion flux η is plotted on the y-axis, and the radius r is plotted on the x-axis. Plot 608 is generated over one cycle of the synchronization signal 162 (Figures 1A and 1B) when the parameters of the RF signal 156 generated by RF generator 104 (Figures 1A and 1B) are in state S1, and when the parameters of the RF signal 152 generated by RF generator 102 are in state S0. Note from plot 608 that the ion density increases from 0 at the center of the substrate S to a positive value R of the radius r of the substrate S.

[0167] Graph 606 further includes plot 610 of the thickness s of the plasma sheath, such as the upper plasma sheath, of the plasma in the plasma chamber 118 or 174, against the radius R of the substrate S. Note from plot 610 that the thickness of the plasma sheath decreases along the radius r of the substrate S from a central 0 to a positive value R of the substrate radius R. For example, the thickness s decreases from a maximum value smax2 at the center 0 of the substrate S to a minimum value smin2 closer to the radius R. The values ​​smin2 and smax2 are measured from a reference value sref of the thickness s. For example, the values ​​smin2 and smax2 are values ​​at the top surface of the plasma sheath.

[0168] Furthermore, in the case of plot 610, the angular inclination has a value Φ2 at the radius value R1 of the substrate S. The value Φ2 is measured relative to the vertical line 605 at the radius value R1.

[0169] In one embodiment, plot 610 is the ion density of the plasma in the plasma chamber 118 or 174.

[0170] In one embodiment, the angle Φ1 or Φ2 is 200 millidegrees or greater. For example, the angle Φ1 is 0.2 degrees or 0.3 degrees. Angle Φ1 or Φ2 results in a non-uniform plasma. For example, the non-uniformity of the plasma in the plasma chamber 118 increases to approximately 24 percent.

[0171] Figure 6C is an embodiment of graph 612, illustrating plot 614 of the ion flux η of the plasma in plasma chamber 118 or 174 (Figures 1A and 1B) against the radius r of the substrate S placed in the plasma chamber. The ion flux η is plotted on the y-axis and the radius r is plotted on the x-axis. Plot 614 is generated when the parameters of the RF signal 156 generated by RF generator 104 (Figures 1A and 1B) are desynchronized with the parameters of the RF signal 152 generated by RF generator 102 over time t, such as over 10, 20, or 30 cycles of the synchronization signal 162 (Figures 1A and 1B). Note from plot 614 that the ion density is substantially constant from the center 0 of the substrate S to a positive value R of the radius r of the substrate S. For example, compared to plot 602 (Figure 6A), the ion density in plot 614 does not substantially decrease along the radius r from the center 0 to the value R. Furthermore, compared to plot 608 (Figure 6B), the ion density of plot 614 does not substantially increase from the central 0 to the value R along the radius r.

[0172] Graph 612 further includes plot 616 of the thickness s of the plasma sheath, such as the upper plasma sheath, of the plasma in the plasma chamber 118 or 174, against the radius R of the substrate S. Note from plot 616 that the thickness s of the plasma sheath is substantially constant along the radius r of the substrate S from the center 0 to a positive value R of the substrate radius R. For example, the thickness s is substantially the same thickness value s3, does not decrease from the maximum value smax2 to the minimum value smin2, and does not increase from the minimum value smin1 to the maximum value smax1. The value s3 is measured from a reference value sref of the thickness s. For example, the value s3 is the thickness of the top surface of the plasma sheath measured relative to the bottom surface of the plasma sheath.

[0173] Furthermore, in the case of plot 616, the angular inclination has a value Φ3 at the radius value R1 of the substrate S. The value Φ3 is measured relative to the vertical line 605 at the radius value R1. Examples of Φ3 are angles ranging from 0 to 0.03 degrees, and are therefore barely visible in Figure 6C. For example, an angle Φ3 is 20 millidegrees or 30 millidegrees. An angle Φ3 results in a uniform plasma. For example, the non-uniformity of the plasma in the plasma chamber 118 is reduced to less than 3 percent.

[0174] In one embodiment, plot 610 is the ion density of the plasma in the plasma chamber 118 or 174.

[0175] Figure 7A is a diagram of one embodiment illustrating a substrate 700 that is etched when both RF generators 102 and 104 are in the same state, such as S1 or S0, over multiple cycles of the synchronization signal 162 (Figure 1A). The substrate 700 is also an example of etching achieved when RF generator 102 is in state S1 and RF generator 104 is in state S0 over one cycle of the synchronization signal 162 (Figure 1A). The substrate 700 includes a substrate layer 702 and a substrate stack layer 704. An example of a substrate layer is a silicon layer 702. An example of a substrate stack layer 704 is one or more layers such as an oxide layer, a metal layer, and a mask layer. Within the substrate stack layer 704, feature portions such as feature portions 706 are etched when RF generators 102 and 104 are not operating in opposite synchronization with each other, for example, when they are in the same state. When RF generators 102 and 104 are not operated in opposite synchronous mode with respect to each other, the angular inclination Φ1 is large with respect to the vertical line 605. The ion density of the plasma in the plasma chamber 118 (Figure 1A) increases in the edge region of the substrate S and decreases in the central region of the substrate S. The plasma sheath of the plasma is thicker in the edge region 131 and thinner in the central region 129 (Figure 1A). Due to the higher density in the edge region 131 compared to the central region 129, the feature portion 706 is inclined at an angle Φ1 with respect to the vertical line 605.

[0176] Figure 7B is a diagram of one embodiment illustrating a substrate 710 that is etched when both RF generators 102 and 104 are in the same state, such as S1 or S0, for multiple cycles of the synchronization signal 162 (Figure 1A). The substrate 710 is also an example of etching achieved when RF generator 1042 is in state S1 and RF generator 102 is in state S0 for one cycle of the synchronization signal 162 (Figure 1A). The substrate 710 includes a substrate layer 702 and a substrate stack layer 704. Within the substrate stack layer 704, feature portions such as feature portion 712 are etched when RF generators 102 and 104 are not operating in opposite synchronous mode with each other, for example, when they are in the same state. When RF generators 102 and 104 are not operating in opposite synchronous mode with each other, the angular inclination Φ2 is large relative to the vertical line 605. The ion density of the plasma in the plasma chamber 118 (Figure 1A) increases in the central region of the substrate S and decreases in the edge region of the substrate S. The plasma sheath of the plasma is thicker in the central region 129 and thinner in the edge region 131 (Figure 1A). Due to the higher density in the central region 129 compared to the edge region 131, the feature portion 712 is inclined at an angle Φ2 with respect to the vertical line 605.

[0177] Figure 7C shows an example of a substrate S (Figures 1A and 1B) of one embodiment of a substrate 750 in which RF generators 102 and 104 are etched when they pulsing in opposite sync with each other over multiple cycles of the synchronization signal 162 (Figure 1A). The substrate 750 includes a substrate layer 702 and a substrate stack layer 704, wherein the substrate stack layer 704 includes feature portions such as feature portions 708 that are etched within the substrate stack layer 704. The feature portions 708 are etched into the substrate stack layer 704 when the RF generators 102 and 104 are operating in opposite sync with each other. Because the RF generators 102 and 104 are operating in opposite sync with each other, the feature portions 708 have a lower angle of inclination with respect to the vertical line 605 compared to the angle of inclination of feature portion 706 in Figure 7A or compared to feature portion 712 in Figure 7B. During each cycle of the synchronization signal 162, both RF generators 102 and 104 are pulsed in opposite synchronization with each other, and as the duty cycles of RF generators 102 and 104 are adjusted, the average angular slope gradually decreases over time t. The plasma in the plasma chamber 118 (Figure 1A) becomes more uniform in the central and edge regions 129 and 131 over time t.

[0178] In one embodiment, the terms central region and central region are used synonymously herein.

[0179] Figure 8 is an embodiment of Graph 800, illustrating the ion angular distribution function. Graph 800 shows the distribution of ions in the plasma within plasma chambers 118 or 174 (Figures 1A and 1B) at angles measured with respect to a vertical line 605. As illustrated with Graph 800, the angular slope is zero or substantially zero for the majority of ions in the plasma within plasma chambers 118 or 174, e.g., the majority, within the range of 0 to 0.03 degrees, and not substantially zero for a small number of ions. The iron angular distribution function illustrated with Graph 800 is achieved when RF generators 102 and 104 are pulsed in a time-division multiplexing manner, such as in opposite synchronization with each other.

[0180] Figure 9 is a diagram of one embodiment of system 900, illustrating the use of three RF coils 114, 116, and 908 operating in a multiplexed manner. System 900 is identical in structure and function to system 100 in Figure 1A, except that system 900 includes an RF generator 902, a match 904, and a plasma chamber 906. As an example, the RF generator 902 has an operating frequency range of 10 kHz to 100 kHz.

[0181] In one embodiment, RF generator 902 operates at substantially the same frequency as RF generator 102 or RF generator 104, or both RF generators 102 and 104. For example, the operating frequency of RF generator 902 is within a predetermined range, such as within ±10% of the operating frequency of RF generator 102. In another example, RF generators 102 and 902 both have the same operating frequency. In yet another example, the operating frequency of RF generator 902 is within a predetermined range, such as within ±10% of the operating frequency of RF generator 104. In yet another example, RF generators 104 and 902 both have the same operating frequency.

[0182] The plasma chamber 906 includes RF coils 114 and 116, and further includes a substrate support 128 and an edge ring 130. RF coil 908 is located above the dielectric window 126 of the plasma chamber 906. RF coil 904 is located between RF coils 114 and 116. For example, RF coil 904 is located in the same horizontal plane as the horizontal plane of RF coils 114 and 116. As another example, RF coil 904 is located in a horizontal plane above or below the horizontal plane in which RF coils 114 and 116 are located. As yet another example, each RF coil 114, 116, and 904 are located in different horizontal planes. As yet another example, RF coil 908 is located above the substrate support 128, and no portion of RF coil 908 is located above the edge ring 130. For example, the vertical plane of the edge ring 130 does not overlap with the vertical plane in which RF coil 908 is located.

[0183] The processor 122 is coupled to the RF generator 902 via the transmission cable 910. The output O902 of the RF generator 902 is coupled to the input I904 of the match 904 via the RF cable 912. The output O904 of the match 904 is coupled to one end of the RF coil 908 via the RF transmission line 914. The other end of the RF coil 908 is coupled to ground potential.

[0184] The processor 122 generates a recipe signal 916. The recipe signal 916 includes recipe information, such as the parameters of the RF signal 918 to be generated by the RF generator 902, and the frequency of the RF signal 918. The recipe information of the recipe signal 916 further includes the duty cycle of the parameters of the RF signal 918. The processor 122 transmits the recipe signal 916 to the RF generator 902 via the transmission cable 910. Upon receiving the recipe signal 916, the RF generator 902 stores the recipe information of the recipe signal 916 in one or more memory devices of the RF generator 902.

[0185] Furthermore, the processor 122 transmits a synchronization signal 162 to the RF generator 902 via the transmission cable 910. Upon receiving the synchronization signal 162, the RF generator 902 generates an RF signal 918 having the parameters and frequency received in the recipe signal 916. The frequency of the RF signal 918 is the same as the operating frequency of the RF generator 902. The RF generator 902 transmits the RF signal 918 to the input I904 of the match 904 via output O902 and RF cable 912.

[0186] Match 904 modifies the impedance of the RF signal 918 and provides the modified RF signal 920 at output O904 by matching the impedance of the load coupled to output O904 with the impedance of the source coupled to input I904. Examples of loads coupled to output O904 include the RF transmission line 914 and the plasma chamber 906. Examples of sources coupled to input I904 include the RF generator 902 and the RF cable 912. The modified RF signal 920 is supplied from output O904 to the RF coil 908 via the RF transmission line 914.

[0187] In addition to supplying the modified RF signals 164, 920, 166, and 168, when one or more process gases are supplied to the plasma chamber 906, the plasma is struck or maintained within the plasma chamber 906 to process the substrate S on the upper surface of the substrate support 128.

[0188] In one embodiment, the RF generator 902 has a different operating frequency than that described with respect to Figure 9. For example, the RF generator 902 has an operating frequency of 400 kHz, 2 MHz, 13.56 MHz, 27 MHz, or 60 MHz.

[0189] In one embodiment, two of the RF coils 114, 116, and 904 are located adjacent to the side wall 119 of the plasma chamber 906, but not above it. In this embodiment, the upper portion of the side wall 119 is a dielectric window, which is integrated with the dielectric window 126.

[0190] In one embodiment, the RF coil 908 is located above the edge ring 130 128, and no portion of the RF coil 908 is located above the substrate support 128. For example, the vertical plane of the substrate support 128 does not overlap with the vertical plane on which the RF coil 908 is located.

[0191] Figure 10A is an embodiment of Graph 200 and is intended to illustrate the synchronization signal 202.

[0192] Figure 10B is an embodiment of graph 1000, illustrating a digital pulse signal 1002 to illustrate the duty cycle of the parameters of the RF signal 152 (Figure 9) generated by the RF generator 102. Graph 1000 plots the logic level of the digital pulse signal 1002 against time t. The logic level of the digital pulse signal 1002 is plotted on the y-axis, and time t is plotted on the x-axis.

[0193] The digital pulse signal 1002 has a duty cycle of 32.5%. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 1002 transitions from logic level 0 to logic level 1 at time t0, and remains at logic level 1 from time t0 to time t3.25, which is one-quarter of the time period between times t3 and t4. Also during cycle 1 of the synchronization signal 202, the digital pulse signal 1002 transitions from logic level 1 to logic level 0 at time t3.5, and remains at logic level 0 from time t3.25 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 1002 transitions from logic level 0 to logic level 1 at time t10, and remains at logic level 1 from time t10 to time t13.25, which is one-quarter of the time period between times t13 and t14. During cycle 2 of the synchronization signal 202, the digital pulse signal 1002 transitions from logic level 1 to logic level 0 at time t13.25, and remains at logic level 0 from time t13.25 to time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 1002 has logic level 1 for a period of time accounting for 32.5% of the cycle, and logic level 0 for the remaining period accounting for 67.5% of the cycle.

[0194] Figure 10C is an embodiment of Graph 1004, illustrating a digital pulse signal 1006 for illustrating the duty cycle of the parameters of an RF signal 156 generated by an RF generator 104. Graph 1004 plots the logic level of the digital pulse signal 1006 against time t. The logic level of the digital pulse signal 1006 is plotted on the y-axis, and time t is plotted on the x-axis.

[0195] The digital pulse signal 1006 has a duty cycle of 35% and is inversely synchronized with the digital pulse signal 1002 (Figure 10B) for a portion of each cycle of the synchronization signal 202. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 1006 is at logic level 0 at time t0, remains at logic level 0 until time t3.25, transitions from logic level 0 to logic level 1 at time t3.25, and remains at logic level 1 from time t3.25 until time t6.75, which occurs three-quarters of the time period between times t6 and t7. Also, during cycle 1 of the synchronization signal 202, the digital pulse signal 1006 transitions from logic level 1 to logic level 0 at time t6.75, and remains at logic level 0 from time t6.75 until time t10.

[0196] Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 1006 is at logic level 0 at time t10, remains at logic level 0 until time t13.25, and then transitions from logic level 0 to logic level 1 at time t13.25. During cycle 2 of the synchronization signal 202, the digital pulse signal 1006 remains at logic level 1 from time t13.25 until time t16.75, which occurs three-quarters of the time period between times t16 and t17. During cycle 2 of the synchronization signal 202, the digital pulse signal 1006 transitions from logic level 1 to logic level 0 at time t16.75, and remains at logic level 0 from time t16.75 until time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 1006 has a logic level of 1 for a period of time accounting for 35% of the cycle and a logic level of 0 for the remaining period accounting for 65% of the cycle.

[0197] Furthermore, for a portion of each cycle of the synchronization signal 202, the digital pulse signal 1006 has a logic level opposite to that of the digital pulse signal 1002 so as to be inversely synchronized with the digital pulse signal 1002, and for the remainder of the cycle of the synchronization signal 202, the digital pulse signal 1006 has the same logic level as that of the digital pulse signal 1002. For example, during the time period t0 to t6.75, the digital pulse signals 1002 and 1006 are inversely synchronized with each other, and during the time period t6.75 to t10, the digital pulse signals 1002 and 1006 are not inversely synchronized with each other.

[0198] Figure 10D is an embodiment of Graph 1008, illustrating a digital pulse signal 1010 for illustrating the duty cycle of the parameters of the RF signal 918 (Figure 9) generated by the RF generator 902. Graph 1008 plots the logic level of the digital pulse signal 1010 against time t. The logic level of the digital pulse signal 1010 is plotted on the y-axis, and time t is plotted on the x-axis.

[0199] The digital pulse signal 1010 has a duty cycle of 32.5% and is inversely synchronized with the digital pulse signal 1002 (Figure 10B) and the digital pulse signal 1006 (Figure 10C) for a portion of each cycle of the synchronization signal 202. For example, during cycle 1 of the synchronization signal 202, the digital pulse signal 1010 transitions from logic level 1 to logic level 0 at time t0 and remains at logic level 0 from time t0 to time t6.75. During cycle 1 of the synchronization signal 202, the digital pulse signal 1010 transitions from logic level 0 to logic level 1 at time t6.75 and remains at logic level 1 from time t6.75 to time t10. Furthermore, during cycle 2 of the synchronization signal 202, the digital pulse signal 1010 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t16.75. During cycle 2 of the synchronization signal 202, the digital pulse signal 1010 transitions from logic level 0 to logic level 1 at time t16.75 and remains at logic level 1 from time t16.75 to time t20. Therefore, during each cycle of the synchronization signal 202, the digital pulse signal 1010 has logic level 1 for a period of time accounting for 32.5% of the cycle and logic level 0 for the remaining period accounting for 67.5% of the cycle.

[0200] Furthermore, for a portion of each cycle of the synchronization signal 202, the digital pulse signal 1010 has a logic level opposite to that of the digital pulse signal 1002 so as to be inversely synchronized with the digital pulse signal 1002, and for the remainder of the cycle of the synchronization signal 202, the digital pulse signal 1010 has the same logic level as that of the digital pulse signal 1002. For example, during the time periods t0 to t3.25 and t6.75 to t10, the digital pulse signals 1002 and 1010 are inversely synchronized with each other, and during the time period t3.25 to t6.75, the digital pulse signals 1002 and 1010 are not inversely synchronized with each other.

[0201] Similarly, for a portion of each cycle of the synchronization signal 202, the digital pulse signal 1010 has a logic level opposite to that of the digital pulse signal 1006 so as to be inversely synchronized with the digital pulse signal 1006, and for the remainder of the cycle of the synchronization signal 202, the digital pulse signal 1010 has the same logic level as that of the digital pulse signal 1006. For example, during the time period from t3.25 to t10, the digital pulse signals 1006 and 1010 are inversely synchronized with each other, and during the time period from t0 to t3.25, the digital pulse signals 1006 and 1010 are not inversely synchronized with each other.

[0202] Figure 10E is an embodiment of Graph 1012, illustrating the parameter 1014 of the RF signal 1016. The RF signal 1016 is an example of the RF signal 152 generated by the RF generator 102 (Figure 9). Graph 1012 plots the parameter 1014 on the y-axis and time t on the x-axis. As an example, parameter 1014 is the envelope of the RF signal 1016.

[0203] The parameter 1014 of the RF signal 1016 is synchronized with the duty cycle of the digital pulse signal 1002 (Figure 10B). For example, during cycle 1 of the synchronization signal 202 (Figure 10A), parameter 1014 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t0. During cycle 1 of the synchronization signal 202, parameter 1014 remains at parameter levels P1 and -P1 from time t0 to time t3.25, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t3.25. Also, during cycle 1 of the synchronization signal 202, parameter 1014 remains at parameter level 0 from time t3.25 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 10A), parameter 1014 transitions from a parameter level of zero to parameter levels P1 and -P1 at time t10. During cycle 2 of the synchronization signal 202, parameter 1014 remains at parameter levels P1 and -P1 from time t10 to time t13.25, and then transitions from parameter levels P1 and -P1 to parameter level 0 at time t13.25. Also, during cycle 2 of the synchronization signal 202, parameter 1014 remains at parameter level 0 from time t13.25 to time t20.

[0204] Note that parameter levels P1 and -P1 define state S1 of RF signal 1016, and a parameter level of zero defines state S0 of RF signal 1016.

[0205] It should be further noted that parameter level P1 includes multiple positive values ​​of the power or voltage of RF signal 1016, and parameter level -P1 includes multiple negative values ​​of the power or voltage of RF signal 1016. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of RF signal 1016. For example, a parameter level of zero is substantially zero.

[0206] In one embodiment, instead of transitioning to parameter level zero at times t3.25 and t13.25, parameter 1016 transitions to a positive parameter level greater than zero at times t3.25 and t13.25. For example, parameter 1014 transitions from parameter level P1 to a positive parameter level between zero and P1, and from parameter level -P1 to a negative parameter level between zero and -P1 at each time t3.25 and t13.25. Parameter 1014 transitions from a positive parameter level to parameter level P1, and from a negative parameter level to parameter level -P1 at each time t10 and t20. Parameter levels P1 and -P1 define state S1 of RF signal 1016, and the positive and negative parameter levels define state S0 of RF signal 1016.

[0207] In one embodiment, instead of transitioning at time t3.25, parameter 1014 transitions from state S1 to state S0 over a certain time period, such as from time t3.25 to time t3.5 or from time t3.25 to time t4. Similarly, instead of parameter 1014 transitioning from state S0 to state S1 at a certain time, parameter 1014 transitions from state S0 to state S1 over a certain time period or time interval.

[0208] Figure 10F is an embodiment of Graph 1018, illustrating the parameter 1020 of the RF signal 1022. The RF signal 1022 is an example of the RF signal 156 generated by the RF generator 104 (Figure 9). Graph 1018 plots the parameter 1020 on the y-axis and time t on the x-axis. The parameter 1020 is the envelope of the RF signal 1022.

[0209] The parameter 1020 of the RF signal 1022 is synchronized with the duty cycle of the digital pulse signal 1006 (Figure 10C). For example, during cycle 1 of the synchronization signal 202 (Figure 3A), parameter 1020 has a parameter level of zero at time t0, remains at zero from time t0 to time t3.25, and at time t3.25 transitions from a parameter level of zero to a set of parameter levels P2 and -P2. During cycle 1 of the synchronization signal 202, parameter 1020 remains at parameter levels P2 and -P2 from time t3.25 to time t6.75, and at time t6.75 transitions from parameter levels P2 and -P2 to a parameter level of zero. Also, during cycle 1 of the synchronization signal 202, parameter 1020 remains at a parameter level of zero from time t6.75 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 10A), parameter 1020 is at a parameter level of zero at time t10 and remains at a parameter level of zero from time t10 to time t13.25. During cycle 2 of the synchronization signal 202, parameter 1020 transitions from a parameter level of zero to parameter levels P2 and -P2 at time t13.25. Also during cycle 2 of the synchronization signal 202, parameter 1020 remains at parameter levels P2 and -P2 from time t13.25 to time t16.75. Furthermore, during cycle 2 of the synchronization signal 202, parameter 1020 transitions from parameter levels P2 and -P2 to a parameter level of zero at time t16.75 and remains at a parameter level of zero from time t16.75 to time t20.

[0210] It should be noted that a parameter level of zero defines state S0 of RF signal 1022, and parameter levels P2 and -P2 define state S1 of RF signal 1022. It should be further noted that parameter level P2 includes multiple positive values ​​of the power or voltage of RF signal 1022, and parameter level -P2 includes multiple negative values ​​of the power or voltage of RF signal 1022. Also, in one embodiment, a parameter level of zero includes multiple values ​​of the power or voltage of RF signal 1022. For example, the parameter level of zero for parameter 1020 of RF signal 1022 is substantially zero.

[0211] Furthermore, for a portion of each cycle of the synchronization signal 202, parameter 1020 has a state opposite to that of parameter 1014, so as to be inversely synchronized with parameter 1014, and for the remainder of the cycle of the synchronization signal 202, parameter 1020 has the same state as parameter 1014. For example, during the time period from t0 to t6.75, parameters 1020 and 1014 are inversely synchronized with each other, and during the time period from t6.75 to t10, parameters 1020 and 1014 are not inversely synchronized with each other.

[0212] In one embodiment, instead of transitioning from parameter levels P2 and -P2 to a parameter level of zero at times t6.75 and t16.75, parameter 1020 transitions to a positive parameter level greater than zero at times t6.75 and t16.75. For example, at each time t6.75 and t16.75, parameter 1020 transitions from parameter level P2 to a positive parameter level between zero and P2, and from parameter level -P2 to a negative parameter level between zero and -P2. At each time t3.25 and t13.25, parameter 1020 transitions from a positive parameter level to parameter level P2, and from a negative parameter level to parameter level -P2. Parameter levels P2 and -P2 define state S1 of RF signal 1022, and the positive and negative parameter levels define state S0 of RF signal 1022.

[0213] In one embodiment, instead of transitioning at time t3.25, parameter 1020 transitions from state S0 to state S1 over a certain time period, such as the time interval from time t3.25 to time t4 or from time t3.25 to time t3.75. Time t3.75 is three-quarters of the time period between times t3 and t4. Similarly, instead of parameter 1020 transitioning from state S1 to state S0 at a certain time, parameter 1020 transitions from state S1 to state S0 over a certain time period or time interval.

[0214] Figure 10G is an embodiment of Graph 1024, illustrating the parameter 1026 of the RF signal 1028. The RF signal 1028 is an example of the RF signal 918 generated by the RF generator 902 (Figure 9). Graph 1024 plots the parameter 1026 on the y-axis and time t on the x-axis. The parameter 1026 is the envelope of the RF signal 1028.

[0215] The parameter 1026 of the RF signal 1028 is synchronized with the duty cycle of the digital pulse signal 1010 (Figure 10D). For example, during cycle 1 of the synchronization signal 202 (Figure 10A), parameter 1026 transitions from the set of parameter levels P3 and -P3 to a parameter level of zero at time t0, remains at a parameter level of zero from time t0 to time t6.75, and then transitions from a parameter level of zero to the set of parameter levels P3 and -P3 at time t6.75. During cycle 1 of the synchronization signal 202, parameter 1026 remains at parameter levels P3 and -P3 from time t6.75 to time t10. Similarly, during cycle 2 of the synchronization signal 202 (Figure 10A), parameter 1026 transitions from parameter levels P3 and -P3 to a parameter level of zero at time t10, and remains at a parameter level of zero from time t10 to time t16.75. During cycle 2 of the synchronization signal 202, parameter 1026 transitions from parameter level zero to parameter levels P3 and -P3 at time t16.75. Furthermore, during cycle 2 of the synchronization signal 202, parameter 1026 remains at parameter levels P3 and -P3 from time t16.75 to time t20.

[0216] It should be noted that a parameter level of zero defines state S0 of RF signal 1028, and parameter levels P3 and -P3 define state S1 of RF signal 1028. It should be further noted that parameter level P3 includes multiple positive values ​​of power or voltage of RF signal 1028, and parameter level -P3 includes multiple negative values ​​of power or voltage of RF signal 1028. Also, in one embodiment, a parameter level of zero includes multiple values ​​of power or voltage of RF signal 1028. For example, the parameter level of zero for parameter 1026 of RF signal 1028 is substantially zero.

[0217] During a portion of each cycle of the synchronization signal 202, parameter 1026 has a state opposite to that of parameter 1014, so as to be inversely synchronized with parameter 1014, and during the remainder of the cycle of the synchronization signal 202, parameter 1026 has the same state as parameter 1014. For example, during the time periods t0 to t3.25 and t6.75 to t10, parameters 1014 and 1026 are inversely synchronized with each other. During the time period t3.25 to t6.75, parameters 1014 and 1026 are not inversely synchronized with each other.

[0218] Similarly, during a portion of each cycle of the synchronization signal 202, parameter 1026 has a state opposite to that of parameter 1020, so as to be inversely synchronized with parameter 1020, and during the remainder of the cycle of the synchronization signal 202, parameter 1026 has the same state as parameter 1020. For example, during the time period from t3.25 to t10, parameters 1020 and 1026 are inversely synchronized with each other, and during the time period from t0 to t3.25, parameters 1020 and 1026 are not inversely synchronized with each other.

[0219] In one embodiment, instead of transitioning from parameter levels P3 and -P3 to a parameter level of zero at times t0 and t10, parameter 1026 transitions to a positive parameter level greater than zero at times t0 and t10. For example, at each time t0 and t10, parameter 1026 transitions from parameter level P3 to a positive parameter level between zero and P3, and from parameter level -P3 to a negative parameter level between zero and -P3. At each time t6.75 and t16.75, parameter 1026 transitions from a positive parameter level to parameter level P3, and from a negative parameter level to parameter level -P3. Parameter levels P3 and -P3 define state S1 of RF signal 1028, and the positive and negative parameter levels define state S0 of RF signal 1028. Note that one or more values ​​of a positive parameter level do not include one or more values ​​of parameter level P3, and one or more values ​​of a negative parameter level do not include one or more values ​​of parameter level -P3. For example, the minimum value of one or more values ​​of parameter level P3 is greater than the maximum value of one or more values ​​of a positive parameter level, and the minimum value of one or more values ​​of a negative parameter level is greater than the maximum value of one or more values ​​of parameter level -P3.

[0220] In one embodiment, instead of the parameter 1026 transitioning at time t6.75, it transitions from state S0 to state S1 over a certain time period, such as the time interval from time t6.75 to time t7.5 or from time t6.75 to time t7. Time t7.5 is located halfway between times t7 and t8. Similarly, instead of the parameter transitioning from state S1 to state S0 at a certain time, the parameter 1026 transitions from state S1 to state S0 over a certain time period or time interval.

[0221] In one embodiment, parameter level P3 is the same as parameter level P2 or parameter level P1. In one embodiment, parameter level P3 is greater than parameter levels P1 and P2, and parameter level -P3 is less than parameter levels -P1 and -P2. In one embodiment, parameter level P3 is less than parameter levels P1 and P2, and parameter level -P3 is greater than parameter levels -P1 and -P2.

[0222] In one embodiment, parameter level P3 lies between parameter levels P1 and P2, and parameter level -P3 lies between parameter levels -P1 and -P2. For example, parameter level P3 is greater than parameter level P1 and less than parameter level P2. Also, parameter level -P3 is greater than parameter level -P1 and less than parameter level -P2. In another example, parameter level P3 is greater than parameter level P2 and less than parameter level P1. Also, parameter level -P3 is greater than parameter level -P2 and less than parameter level -P1.

[0223] In one embodiment, parameters 1014, 1020, and 1026 pulsate two or more times during each cycle of the synchronization signal 202, and parameters 1014, 1020, and 1026 pulsate in a time-division multiplexing manner.

[0224] Figure 11 is a diagram of the computer system 500, illustrating a user interface for controlling the multiplexing operation of RF generators 102, 104, and 902 (Figure 9). During operation, the CPU and GPU control the display screen 508 to display graphic buttons 1102 for selecting the multiplexing operation for time-division multiplexing of RF signals 152, 156, and 918 (Figure 9). For example, in response to receiving a selection of a graphic button 1102 from the user via the keyboard 504 or optical mouse 506, the CPU generates duty cycles, as described in Figures 10B to 10D, for transmission to the corresponding RF generators 102, 104, and 902.

[0225] The operating duty cycle of RF generator 104 is multiplexed with respect to the operating duty cycle of RF generator 102 and the operating duty cycle of RF generator 902. Note that the operating duty cycle of RF generator 102 is the same as the duty cycle of the RF signal 152 generated by RF generator 102, the operating duty cycle of RF generator 902 is the same as the duty cycle of the RF signal 918 generated by RF generator 902, and the operating duty cycle of RF generator 104 is the same as the duty cycle of the RF signal 156 generated by RF generator 104.

[0226] Furthermore, the CPU and GPU control the display screen 508 to display a graphic button 1104 to receive a selection regarding whether one or two of the RF generators 102, 104, and 902 will start in their respective state S1 at time t0. For example, in response to receiving a selection of graphic button 1106, the CPU decides to control RF generator 102 to start in state S1 at time t0. As another example, in response to receiving a selection of graphic button 1108, the CPU decides to control RF generator 104 to start in state S1 at time t0. As yet another example, in response to receiving a selection of graphic button 1110, the CPU decides to control RF generator 902 to start in state S1 at time t0. When none of the graphic buttons 1106-1110 are selected, the CPU decides to control each RF generator 102, 104, or 902 to start operating in state S0 at time t0. This choice regarding whether the RF generator 102, 104, or 902 will start in state S1 at time t0 is received from the user via the keyboard 504 or optical mouse 506.

[0227] The CPU and GPU also control the display screen 508 to display multiple graphic buttons 1112, 1114, 1116, and 1118 to receive duty cycles for two or more of the RF generators 102, 104, and 902. For example, when selections for graphic buttons 1112 and 1114 are received from the user via the keyboard 504 or optical mouse 506, the CPU allows selection of duty cycles for the operation of RF generator 102, such as 25%, 35%, 45%, or 28%. Similarly, as another example, when selections for graphic buttons 1112 and 1116 are received from the user via the keyboard 504 or optical mouse 506, the CPU allows selection of duty cycles for the operation of RF generator 104, such as 25%, 35%, 45%, or 28%. Furthermore, when the selection of graphic buttons 1112 and 1118 is received from the user via the keyboard 504 or optical mouse 506, the CPU allows the selection of a duty cycle for the operation of the RF generator 902, such as 25%, 35%, 45%, or 28%.

[0228] Note that a recipe signal 150 (Figure 9) is generated in response to the selection of graphic buttons 1102, 1104, 1106, 1112, and 1114. Similarly, a recipe signal 154 (Figure 9) is generated in response to the selection of graphic buttons 1102, 1104, 1108, 1112, and 1116. Also, a recipe signal 916 (Figure 9) is generated in response to the selection of graphic buttons 1102, 1104, 1110, 1112, and 1118. For example, the recipe signal 916 includes the duty cycle of the RF generator 902 for generating the RF signal 912.

[0229] Furthermore, the recipe signal 916 includes instructions from the processor 122 (Figure 1A) to the RF generator 902 to operate the RF generators 102 and 104 in a time-division multiplexing manner. For example, the recipe signal 916 includes instructions from the processor 122 (Figure 1A) to the RF generator 902 to operate in reverse sync with the operation of the RF generator 102 for a portion of each cycle of the synchronization signal 162 (Figure 9), and not to operate in reverse sync for the remainder of each cycle of the synchronization signal 162. Also, in this example, the recipe signal 916 includes instructions from the processor 122 (Figure 1A) to the RF generator 902 to operate in reverse sync with the operation of the RF generator 104 for a portion of each cycle of the synchronization signal 162 (Figure 9), and not to operate in reverse sync for the remainder of each cycle of the synchronization signal 162.

[0230] In one embodiment, the state of the RF generator is the same as the state of the RF signal generated by the RF generator. For example, both the RF generator 102 and the RF signal 152 generated by the RF generator 102 have the same state S1 for the duration of the synchronization signal 162, or have state S0 for the remainder of the duration of the synchronization signal 162.

[0231] Figure 12 is a diagram of one embodiment of system 1200, illustrating the internal components of RF generators 102, 104, and 902. System 1200 includes RF generators 102, 104, and 902, and further includes matches 108, 904, and 110.

[0232] The RF generator 102 includes a digital signal processor (DSP) DSPx, a parameter controller PWRS1x, a parameter controller PWRS0x, and a frequency controller FCx. The RF generator 102 also includes a driver and amplifier system (DAS) 1208. The RF generator 102 further includes an RF power supply 1202. An example of an RF power supply described herein is an electronic oscillator that generates a frequency signal having a radio frequency. An example of a digital signal processor, as used herein, is a microcontroller and a microprocessor chip. For example, a digital signal processor includes one or more memory caches for storing recipe information as described herein. Also, as an example, a controller, as used herein, includes a processor and one or more memory devices. The processor of the controller is coupled to the memory devices of the controller.

[0233] A driver and amplifier system includes one or more drivers and one amplifier. One or more drivers are coupled to an amplifier. Examples of drivers include one or more transistors.

[0234] Processor 122 is coupled to digital signal processor DSPx via transmission cable 132, and digital signal processor DSPx is coupled to controllers PWRS1x, PWRS0x, and FCx. Controllers PWRS1x, PWRS0x, and FCx are coupled to DAS1208, and DAS1208 is coupled to RF power supply 1202. RF power supply 1202 is coupled to input I108 of match 108 via RF cable 138.

[0235] Similarly, the RF generator 902 includes a digital signal processor DSPy, a parameter controller PWRS1y, a parameter controller PWRS0y, and a frequency controller FCy. The RF generator 902 includes a DAS1210. The RF generator 902 further includes an RF power supply 1204. The processor 122 is coupled to the digital signal processor DSPy via a transmission cable 910, and the digital signal processor DSPy is coupled to the controllers PWRS1y, PWRS0y, and FCy. The controllers PWRS1y, PWRS0y, and FCy are coupled to the DAS1210, and the DAS1210 is coupled to the RF power supply 1204. The RF power supply 1204 is coupled to the input I904 of the match 904 via an RF cable 912.

[0236] The RF generator 104 also includes a digital signal processor DSPz, a parameter controller PWRS1z, a parameter controller PWRS0z, and a frequency controller FCz. The RF generator 104 also includes a DAS 1212. The RF generator 104 further includes an RF power supply 1206. The processor 122 is coupled to the digital signal processor DSPz via a transmission cable 134, and the digital signal processor DSPz is coupled to the controllers PWRS1z, PWRS0z, and FCz. The controllers PWRS1z, PWRS0z, and FCz are coupled to the DAS 1212, and the DAS 1212 is coupled to the RF power supply 1206. The RF power supply 1206 is coupled to the input I110 of the match 110 via an RF cable 140.

[0237] During operation, the digital signal processor DSPx receives a recipe signal 150 from the processor 122 via the transmission cable 132 and identifies from the recipe signal 150 the recipe information to be sent to the parameter controller PWRS1x, the recipe information to be sent to the parameter controller PWRS0x, and the recipe information to be sent to the frequency controller FCx. For example, the digital signal processor DSPx identifies from the recipe signal 150 that the parameter level for state S1 of the RF signal 152 to be generated by the RF power supply 1202 will be sent to the parameter controller PWRS1x. The digital signal processor DSPx further identifies from the recipe signal 150 that the parameter level for state S0 of the RF signal 152 to be generated by the RF power supply 1202 will be sent to the parameter controller PWRS0x. The digital signal processor DSPx also identifies from the recipe signal 150 that the frequency levels for parameter states S0 and S1 of the RF signal 152 will be sent to the frequency controller FCx. As an example, the frequency level of the RF signal includes one or more frequency values ​​of the RF signal. One or more frequency values ​​of the frequency levels are within a predetermined range, such as within ±5% of each other.

[0238] Furthermore, in the example, the digital signal processor DSPx identifies that the duty cycle for parameter state S1 of RF signal 152 and the identification of time intervals for dividing the duty cycle between cycles of synchronization signal 162 will be transmitted from the recipe signal 150 to the parameter controller PWRS1x. For example, the digital signal processor DSPx identifies that the duty cycle of parameter 410 (Figure 4D) will be divided into a first time interval of time t0-t2 and a second time interval of time t5-t7.5, as illustrated in Figure 4D.

[0239] Continuing with the example, the digital signal processor DSPx transmits recipe information, identified in the recipe signal 152 for the parameter controller PWRS1x, to the parameter controller PWRS1x. The parameter controller PWRS1x stores the recipe information received from the digital signal processor DSPx in one or more memory devices of the parameter controller PWRS1x.

[0240] In the example, the digital signal processor DSPx transmits recipe information identified in recipe signal 152 for parameter controller PWRS0x to parameter controller PWRS0x. Parameter controller PWRS0x stores the recipe information received from the digital signal processor DSPx in one or more memory devices of parameter controller PWRS0x. Furthermore, in the example, the digital signal processor DSPx transmits recipe information identified in recipe signal 152 for frequency controller FCx to frequency controller FCx. Frequency controller FCx stores the recipe information received from the digital signal processor DSPx in one or more memory devices of frequency controller FCx.

[0241] Upon receiving a synchronization signal 162 from the processor 122 via the transmission cable 132, the digital signal processor DSPx transmits the synchronization signal 162 to the controllers PWRS1x, PWRS0x, and FCx. In response to receiving the synchronization signal 162, the parameter controller PWRS1x generates an instruction for each cycle of the synchronization signal 162, including the parameter level of state S1 of the RF signal 152 and the duty cycle of state S1, and transmits it to the DAS1208. Also in response to receiving the synchronization signal 162, the frequency controller FCx generates an instruction for each cycle of the synchronization signal 162, including the frequency level of the RF signal 152, and transmits it to the DAS1208.

[0242] When an instruction is received from the parameter controller PWRS1x and the frequency controller FCx, the DAS1208 generates a current signal 1214 based on the parameter level for state S1 of the RF signal 152 and the frequency level received from the frequency controller FCx over one or more time periods of the duty cycle of state S1, and transmits the current signal 1214 to the RF power supply 1202. One or more time periods of the duty cycle of state S1 of the RF signal 152 occur between one or more time periods of each cycle of the synchronization signal 162. During one or more time periods of the duty cycle of state S1 of the RF signal 152, while the current signal 1214 is received, the RF power supply 1202 generates an RF signal 152 having the parameter level of state S1 of the RF signal 152 and the frequency level of the RF signal 152.

[0243] Note that DAS1208 does not generate the current signal 1214 during the remaining time period between each cycle of the synchronization signal 162. The remaining time period between each cycle of the synchronization signal 162 corresponds to the parameter state S0 of the RF signal 152. When the current signal 1214 is not received, the RF power supply 1202 does not generate the parameter level of state S1 of the RF signal 152 or the frequency level of the RF signal 152.

[0244] Instead, during the remaining time period between each cycle of the synchronization signal 162, in response to receiving the synchronization signal 162, the parameter controller PWRS0x generates an instruction containing the parameter level of state S0 of the RF signal 152 and transmits it to the DAS1208. When the instruction is received from the parameter controller PWRS0x and the frequency controller FCx, the DAS1208 generates a current signal 1216 based on the parameter level for state S0 of the RF signal 152 and the frequency level received from the frequency controller FCx over the remaining time period of each cycle of the synchronization signal 162, and transmits the current signal 1216 to the RF power supply 1202. During the remaining time period of each cycle of the synchronization signal 162, while the current signal 1216 is received, the RF power supply 1202 generates an RF signal 152 having the parameter level of state S0 of the RF signal 152 and the frequency level of the RF signal 152.

[0245] It should be noted that DAS1208 does not generate the current signal 1216 for one or more time periods corresponding to the parameter state S1 of RF signal 152 during each cycle of the synchronization signal 162. When the current signal 1216 is not received, the RF power supply 1202 does not generate the parameter level of state S0 of RF signal 152 or the frequency level of RF signal 152.

[0246] Similarly, the digital signal processor DSPy receives the recipe signal 916 from the processor 122 via the transmission cable 910 and identifies from the recipe signal 916 the recipe information to be sent to the parameter controller PWRS1y, the recipe information to be sent to the parameter controller PWRS0y, and the recipe information to be sent to the frequency controller FCy. For example, the digital signal processor DSPy identifies from the recipe signal 916 that the parameter level for state S1 of the RF signal 918 to be generated by the RF power supply 1204 will be sent to the parameter controller PWRS1y. The digital signal processor DSPy further identifies from the recipe signal 916 that the parameter level for state S0 of the RF signal 916 to be generated by the RF power supply 1204 will be sent to the parameter controller PWRS0y. The digital signal processor DSPy also identifies from the recipe signal 916 that the frequency levels for parameter states S0 and S1 of the RF signal 918 will be sent to the frequency controller FCy.

[0247] Furthermore, in the example, the digital signal processor DSPy identifies from the recipe signal 916 that the duty cycle for the parameter state S1 of the RF signal 918, and the identification of time intervals for dividing the duty cycle between cycles of the synchronization signal 162, will be sent to the parameter controller PWRS1y.Continuing with the example, the digital signal processor DSPy sends the recipe information identified in the recipe signal 918 to the parameter controller PWRS1y.The parameter controller PWRS1y stores the recipe information received from the digital signal processor DSPy in one or more memory devices of the parameter controller PWRS1y.

[0248] In the example, the digital signal processor DSPy transmits recipe information identified in recipe signal 916 for parameter controller PWRS0y to parameter controller PWRS0y. Parameter controller PWRS0y stores the recipe information received from the digital signal processor DSPy in one or more memory devices of parameter controller PWRS0y. Furthermore, in the example, the digital signal processor DSPy transmits recipe information identified in recipe signal 916 for frequency controller FCy to frequency controller FCy. Frequency controller FCy stores the recipe information received from the digital signal processor DSPy in one or more memory devices of frequency controller FCy.

[0249] Upon receiving a synchronization signal 162 from the processor 122 via the transmission cable 910, the digital signal processor DSPy transmits the synchronization signal 162 to the controllers PWRS1y, PWRS0y, and FCy. In response to receiving the synchronization signal 162, the parameter controller PWRS1y generates an instruction for each cycle of the synchronization signal 162, including the parameter level of state S1 of the RF signal 918 and the duty cycle of state S1, and transmits it to the DAS1210. Also in response to receiving the synchronization signal 162, the frequency controller FCy generates an instruction for each cycle of the synchronization signal 162, including the frequency level of the RF signal 918, and transmits it to the DAS1210.

[0250] When an instruction is received from the parameter controller PWRS1y and the frequency controller FCy, the DAS1210 generates a current signal 1218 based on the parameter level for state S1 of the RF signal 918 and the frequency level received from the frequency controller FCy over one or more time periods of the duty cycle of state S1, and transmits the current signal 1218 to the RF power supply 1204. One or more time periods of the duty cycle of state S1 of the RF signal 918 occur between one or more time periods of each cycle of the synchronization signal 162. During one or more time periods of the duty cycle of state S1 of the RF signal 918, while the current signal 1218 is received, the RF power supply 1204 generates an RF signal 918 having the parameter level of state S1 of the RF signal 918 and the frequency level of the RF signal 918.

[0251] It should be noted that DAS1210 does not generate the current signal 1218 during the remaining time period between each cycle of the synchronization signal 162. The remaining time period between each cycle of the synchronization signal 162 corresponds to the parameter state S0 of the RF signal 918. When the current signal 1218 is not received, the RF power supply 1204 does not generate the parameter level of state S1 of the RF signal 918 and the frequency level of the RF signal 918. Instead, during the remaining time period between each cycle of the synchronization signal 162, in response to receiving the synchronization signal 162, the parameter controller PWRS0y generates an instruction including the parameter level of state S0 of the RF signal 918 and transmits it to DAS1210.

[0252] When commands are received from the parameter controller PWRS0y and the frequency controller FCy, the DAS1210 generates a current signal 1220 based on the parameter level for state S0 of the RF signal 918 and the frequency level received from the frequency controller FCy over the remainder of each cycle of the synchronization signal 162, and transmits the current signal 1220 to the RF power supply 1204. During the remainder of each cycle of the synchronization signal 162, while the current signal 1220 is received, the RF power supply 1204 generates an RF signal 918 having the parameter level for state S0 of the RF signal 918 and the frequency level of the RF signal 918.

[0253] It should be noted that the DAS1210 does not generate the current signal 1220 for one or more time periods corresponding to the parameter state S1 of the RF signal 918 during each cycle of the synchronization signal 162. When the current signal 1220 is not received, the RF power supply 1204 does not generate the parameter level of state S0 of the RF signal 918 or the frequency level of the RF signal 918.

[0254] Furthermore, the digital signal processor DSPz receives the recipe signal 158 from the processor 122 via the transmission cable 134 and identifies from the recipe signal 158 the recipe information to be sent to the parameter controller PWRS1z, the recipe information to be sent to the parameter controller PWRS0z, and the recipe information to be sent to the frequency controller FCz. For example, the digital signal processor DSPz identifies from the recipe signal 158 that the parameter level for state S1 of the RF signal 156 to be generated by the RF power supply 1206 will be sent to the parameter controller PWRS1z. The digital signal processor DSPz further identifies from the recipe signal 158 that the parameter level for state S0 of the RF signal 156 to be generated by the RF power supply 1206 will be sent to the parameter controller PWRS0z. The digital signal processor DSPz also identifies from the recipe signal 158 that the frequency levels for parameter states S0 and S1 of the RF signal 156 will be sent to the frequency controller FCz.

[0255] Furthermore, in the example, the digital signal processor DSPz identifies from the recipe signal 158 that the duty cycle for parameter state S1 of the RF signal 156 and the identification of time intervals for dividing the duty cycle between cycles of the synchronization signal 162 will be sent to the parameter controller PWRS1z.Continuing with the example, the digital signal processor DSPz sends the recipe information identified in the recipe signal 158 to the parameter controller PWRS1z.The parameter controller PWRS1z stores the recipe information received from the digital signal processor DSPz in one or more memory devices of the parameter controller PWRS1z.

[0256] In the example, the digital signal processor DSPz transmits recipe information identified in recipe signal 158 for parameter controller PWRS0z to parameter controller PWRS0z. Parameter controller PWRS0z stores the recipe information received from the digital signal processor DSPz in one or more memory devices of parameter controller PWRS0z. Furthermore, in the example, the digital signal processor DSPz transmits recipe information identified in recipe signal 158 for frequency controller FCz to frequency controller FCz. Frequency controller FCz stores the recipe information received from the digital signal processor DSPz in one or more memory devices of frequency controller FCz.

[0257] Upon receiving a synchronization signal 162 from the processor 122 via the transmission cable 134, the digital signal processor DSPz transmits the synchronization signal 162 to the controllers PWRS1z, PWRS0z, and FCz. In response to receiving the synchronization signal 162, the parameter controller PWRS1z generates an instruction for each cycle of the synchronization signal 162, including the parameter level of state S1 of the RF signal 156 and the duty cycle of state S1, and transmits it to the DAS1212. Also in response to receiving the synchronization signal 162, the frequency controller FCz generates an instruction for each cycle of the synchronization signal 162, including the frequency level of the RF signal 156, and transmits it to the DAS1212.

[0258] When an instruction is received from the parameter controller PWRS1z and the frequency controller FCz, the DAS1212 generates a current signal 1222 based on the parameter level for state S1 of the RF signal 156 and the frequency level received from the frequency controller FCz over one or more time periods of the duty cycle of state S1, and transmits the current signal 1222 to the RF power supply 1206. One or more time periods of the duty cycle of state S1 of the RF signal 156 occur between one or more time periods of each cycle of the synchronization signal 162. During one or more time periods of the duty cycle of state S1 of the RF signal 156, while the current signal 1222 is received, the RF power supply 1206 generates an RF signal 156 having the parameter level of state S1 of the RF signal 156 and the frequency level of the RF signal 156.

[0259] It should be noted that DAS1212 does not generate the current signal 1222 during the remaining time period between each cycle of the synchronization signal 162. The remaining time period between each cycle of the synchronization signal 162 corresponds to the parameter state S0 of the RF signal 156. When the current signal 1222 is not received, the RF power supply 1206 does not generate the parameter level of state S1 of the RF signal 156 and the frequency level of the RF signal 156. Instead, during the remaining time period between each cycle of the synchronization signal 162, in response to receiving the synchronization signal 162, the parameter controller PWRS0z generates an instruction including the parameter level of state S0 of the RF signal 156 and transmits it to DAS1212.

[0260] When commands are received from the parameter controller PWRS0z and the frequency controller FCy, the DAS1212 generates a current signal 1224 based on the parameter level for state S0 of the RF signal 156 and the frequency level received from the frequency controller FCz over the remainder of each cycle of the synchronization signal 162, and transmits the current signal 1224 to the RF power supply 1206. During the remainder of each cycle of the synchronization signal 162, while the current signal 1224 is received, the RF power supply 1206 generates an RF signal 156 having the parameter level for state S0 of the RF signal 156 and the frequency level of the RF signal 156.

[0261] It should be noted that DAS1212 does not generate the current signal 1224 for one or more time periods corresponding to the parameter state S1 of the RF signal 156 during each cycle of the synchronization signal 162. When the current signal 1224 is not received, the RF power supply 1206 does not generate the parameter level of state S0 of the RF signal 156 or the frequency level of the RF signal 156.

[0262] Note that if the parameter level of any of the RF signals 152, 918, and 156 is zero during parameter state S0 of the RF signals, then the current signals 1216, 1220, and 1224 will not be generated. If the current signal 1216 is not generated during parameter state S0 of RF signal 152, then the RF power supply 1202 will not generate RF signal 152. Similarly, if the current signal 1220 is not generated during parameter state S0 of RF signal 918, then the RF power supply 1204 will not generate RF signal 918. Also, if the current signal 1224 is not generated during parameter state S0 of RF signal 156, then the RF power supply 1206 will not generate RF signal 156.

[0263] The embodiments described herein can be implemented in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, and mainframe computers. The embodiments can also be implemented in a distributed computing environment where tasks are performed by remote processing hardware units linked over a network.

[0264] In some embodiments, the controller is part of a system which may be part of the examples described above. Such a system includes semiconductor processing equipment which includes processing tools, chambers, platforms for processing, and / or specific processing components (such as wafer bases, gas flow systems, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics are referred to as “controllers,” which may control various components or sub-components of the system. Depending on the processing requirements and / or the type of system, the controllers are programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer movement in and out of the tools, and / or other tools and / or load locks coupled to or linked to the system.

[0265] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that perform tasks such as receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, and enabling endpoint measurements. An integrated circuit includes a chip in the form of firmware that stores program instructions, a chip defined as a digital signal processor (DSP), ASIC, PLD, and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, factors, variables, etc., for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, program instructions are part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0266] In some embodiments, the controller is part of or coupled to a computer that is integrated with the system, coupled to the system, networked to the system separately, or a combination thereof. For example, the controller resides in the “cloud” or in all or part of a manufacturing plant host computer system that enables remote access to wafer processing. The computer enables remote access to the system to monitor the progress of manufacturing operations, examine the history of past manufacturing operations, and examine trends or performance metrics from multiple manufacturing operations in order to change the parameters of the current operation, set the processing steps that follow the current operation, or start a new process.

[0267] In some embodiments, a remote computer (e.g., a server) provides a process recipe to the system via a network including a local network or the Internet. The remote computer includes a user interface that allows input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, a controller receives instructions in the form of data, which specify parameters, factors, and / or variables for each of the processing steps to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process to be performed and the type of tool the controller is configured to work with or control. Thus, as described above, the controllers are distributed, for example, by including one or more individual controllers that are networked together and work toward a common purpose, such as the processes or controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that are in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that jointly control a process on the chamber.

[0268] Without limitation, examples of systems to which the methods described herein are applied in various embodiments include plasma etching chambers or modules, deposition chambers or modules, spin-rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel-edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0269] It should be further noted that in some embodiments, the above-described operation applies to several types of plasma chambers, such as plasma chambers containing capacitively coupled plasma (CCP) reactors, plasma chambers containing ICP reactors, transformer-coupled plasma chambers, conductive tools, dielectric tools, and plasma chambers containing electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are coupled to inductors within an ICP reactor. Examples of inductor shapes include solenoids, dome coils, and flat coils.

[0270] As described above, depending on the process step(s) to be performed by the tool, the host computer communicates with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, controllers, or tools used for material transport to or from the location of tools within the semiconductor manufacturing plant and / or load ports, or for transporting wafer containers from there.

[0271] With the above embodiments in mind, it should be understood that some of the embodiments engage in various computer operations involving data stored in a computer system. These operations involve physically manipulating physical quantities. Any of the operations described herein that form part of the embodiments are useful mechanical operations.

[0272] Some of the embodiments also relate to hardware units or devices for performing these operations. These devices are specifically constructed for special-purpose computers. When defined as a special-purpose computer, the computer can still operate for a special purpose while simultaneously performing other processes, program executions, or routines that are not part of the special purpose.

[0273] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, in a cache, or acquired through a computer network. When data is acquired through a computer network, the data may be processed by other computers on the computer network, such as on a cloud of computing resources.

[0274] One or more embodiments may also be assembled as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit that stores data, such as a memory device, etc., and is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), writeable CD (CD-R), rewritable CD (CD-RW), magnetic tape, as well as other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes computer-readable tangible media distributed across a network-coupled computer system such that the computer-readable code is stored and executed in a distributed fashion.

[0275] The method operations are described in a particular order, but in various embodiments, understand that other housekeeping operations may be performed between operations, or the method operations may be adjusted so that they occur at slightly different times, or be distributed within a system that allows for the occurrence of method operations at various intervals, or be performed in an order different from that described above.

[0276] It should also be noted that in one embodiment, one or more features from any embodiment described above may be combined with one or more features from any other embodiment without departing from the scope described in the various embodiments described herein.

[0277] Although the embodiments described above have been described in some detail for the purpose of clarity of understanding, it is clear that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, these embodiments are to be construed as illustrative and not restrictive, and are not limited to the details given herein.

Claims

1. A method for pulsing a radio frequency (RF) coil, The first RF signal is supplied to a first impedance matching circuit coupled to a first RF coil, The second RF signal is supplied to a second impedance matching circuit coupled to a second RF coil, The first RF signal is pulsed between a first parameter level and a second parameter level, A method comprising pulsing the second RF signal between a third parameter level and a fourth parameter level in reverse synchronization with the pulsing of the first RF signal.

2. The method according to claim 1, wherein the second RF signal is pulsed in reverse synchronization with the pulsing of the first RF signal, During the time period in which the first RF signal transitions from the first parameter level to the second parameter level, the second RF signal is transitioned from the third parameter level to the fourth parameter level. This includes, during the time period in which the first RF signal transitions from the second parameter level to the first parameter level, the second RF signal transitions from the fourth parameter level to the third parameter level, A method wherein the first parameter level is different from the third parameter level, and the second parameter level is different from the fourth parameter level.

3. The method according to claim 1, The second RF signal is maintained at the third parameter level for a period of time during which the first RF signal is maintained at the first parameter level. A method further comprising maintaining the second RF signal at the fourth parameter level for a period of time during which the first RF signal is maintained at the second parameter level.

4. The method according to claim 1, wherein the first RF coil and the second RF coil are located above the dielectric window of the plasma chamber.

5. A method according to claim 1, wherein the first parameter level includes one or more parameter values, the second parameter level includes one or more parameter values, and the one or more values ​​of the first parameter level do not include the one or more values ​​of the second parameter level.

6. A method according to claim 1, wherein the third parameter level includes one or more parameter values, the fourth parameter level includes one or more parameter values, and the one or more values ​​of the third parameter level do not include the one or more values ​​of the fourth parameter level.

7. A method according to claim 1, wherein the first RF signal has substantially the same frequency as the second RF signal.

8. A method according to claim 1, wherein each of the first RF signal and the second RF signal has a frequency in the range of 10 kilohertz (kHz) to 100 kHz.

9. A method according to claim 1, wherein the first parameter level of the first RF signal has a duty cycle, the second parameter level has a duty cycle equal to the difference between 100 percent and the duty cycle of the first parameter level of the first RF signal, and the fourth parameter level has a duty cycle equal to the difference.

10. A method according to claim 1, wherein the first parameter level and the second parameter level occur during a cycle of a synchronization signal, and the third parameter level and the fourth parameter level occur during the cycle.

11. The method according to claim 1, Pulsing the first RF signal is performed as follows: During the cycle of the synchronization signal, the first RF signal is transitioned from the first parameter level to the second parameter level, This includes transitioning the first RF signal from the second parameter level to the first parameter level during the cycle of the synchronization signal, Pulsing the second RF signal is performed as follows: During the cycle of the synchronization signal, the second RF signal is transitioned from the third parameter level to the fourth parameter level. A method comprising transitioning the second RF signal from the fourth parameter level to the third parameter level during the cycle of the synchronization signal.

12. The method according to claim 1, A third RF signal is supplied to the third RF coil of the plasma chamber via a third impedance matching circuit. The third RF signal is further pulsed between a fifth parameter level and a sixth parameter level, A method wherein the third RF signal is pulsed in reverse synchronization with the first RF signal and the second RF signal.

13. A method according to claim 1, wherein the method is performed during a semiconductor wafer processing operation to minimize the inclination of a feature portion.

14. A method for reverse pulsing of a radio frequency (RF) coil, Receiving an indication of the multiplexing operation of a first RF generator and a second RF generator, wherein the first RF generator is configured to be coupled to a first RF coil, and the second RF generator is configured to be coupled to a second RF coil, and receiving an indication of the multiplexing operation of a first RF generator and a second RF generator, Receiving a selection indicating that the first RF generator will begin operating in one state, Receiving the duty cycle of the operation of the first RF generator, Controlling the first RF generator to have the duty cycle and to start operating in the one state, A method comprising controlling the second RF generator to operate in reverse synchronous with the first RF generator, wherein the reverse synchronous operation of the first RF generator and the second RF generator causes the first RF generator to generate a first RF signal and the second RF generator to generate a second RF signal, the second RF signal pulsing in reverse synchronous with the first RF signal.

15. A method according to claim 14, wherein the first state has a first parameter level, and controlling the first RF generator to begin operating in the first state includes controlling the first RF generator to begin operating at the first parameter level, and controlling the second RF generator includes controlling the second RF generator to begin operating at a second parameter level, wherein the second parameter level is lower than the first parameter level.

16. The method according to claim 14, wherein the first RF signal has a first parameter level and a second parameter level, the second RF signal has a third parameter level and a fourth parameter level, the first parameter level is different from the third parameter level, and the second parameter level is different from the fourth parameter level, and pulsing in reverse synchronization with the first RF signal, so that when the first RF signal transitions from the first parameter level to the second parameter level, the second RF signal transitions from the third parameter level to the fourth parameter level, and when the first RF signal transitions from the second parameter level to the first parameter level, the second RF signal transitions from the fourth parameter level to the third parameter level.

17. The method according to claim 16, wherein the first parameter level is greater than the second parameter level and the third parameter level, and the fourth parameter level is greater than the third parameter level.

18. A method according to claim 14, wherein, in order to pulsate the first RF signal and the second RF signal in opposite synchronization with each other, the first RF signal has a first parameter level for a first time period of a clock cycle, the second RF signal has a second parameter level for a first time period, the first RF signal has a third parameter level for a second time period of the clock cycle, the second RF signal has a fourth parameter level for a second time period, the first parameter level is different from the third parameter level, and the second parameter level is different from the fourth parameter level.

19. A method according to claim 14, wherein the first RF generator is configured to be coupled to the first RF coil via a first impedance matching circuit, and the second RF generator is configured to be coupled to the second RF coil via a second impedance circuit.

20. A method according to claim 14, wherein the indication of the multiplexing operation, the selection of a single state, and the duty cycle are received by the processor from an input device.

Images