Block-based adaptive resolution management

Abstract

Providing block-based adaptive resolution management [Solution] The method includes receiving a reference frame, determining a scaling constant with respect to the current block, scaling the block of the reference frame according to the scaling constant so that the block of the reference frame corresponds to the current block, and reconstructing the pixel data of the current block using the scaled block of the reference frame. Related apparatus, systems, techniques, and articles are also described.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of priority of U.S. Provisional Patent Application No. 62 / 883,407, filed on August 6, 2019, entitled "BLOCK - BASED ADAPTIVE RESOLUTION MANAGEMENT", which is hereby incorporated by reference in its entirety.

[0002] The present invention generally relates to the field of video compression. In particular, the present invention is directed to block - based adaptive resolution management.

Background Art

[0003] A video codec can include an electronic circuit or software that compresses or decompresses digital video. This can convert uncompressed video to a compressed format and vice versa. In the context of video compression, a device that compresses video (and / or performs certain functions thereof) can typically be called an encoder, and a device that decompresses video (and / or performs certain functions thereof) can be called a decoder.

[0004] The format of the compressed data can conform to standard video compression specifications. Compression can be lossy in that the compressed video may lack some information present in the original video. This can result in the decompressed video having lower quality than the original uncompressed video, since there is insufficient information to accurately reconstruct the original video.

[0005] There can be complex relationships between video quality, the amount of data used to represent the video (e.g., determined by the bitrate), the complexity of the encoding and decoding algorithms, the sensitivity to data loss and errors, the ease of editing, random access, end - to - end latency (e.g., latency), and the like.

[0006] Motion compensation may include an approach to predict a video frame or part thereof, based on reference frames such as the previous and / or future frames, by taking into account the motion of the camera and / or objects in the video. This can be employed in encoding and decoding video data for video compression, for example, in encoding and decoding using the Advanced Video Coding (AVC) standard of the Video Professional Group (MPEG), also known as H.264. Motion compensation allows a picture to be described in terms of the conversion of a reference picture to the current picture. The reference picture may be temporally previous to the current picture, or it may be from the future to the current picture. Compression efficiency can be improved when the image can be accurately synthesized from the image transmitted and / or stored immediately before it. [Overview of the Initiative] [Means for solving the problem]

[0007] In one aspect, the decoder includes a network configured to receive a reference frame, determine a scaling constant with respect to the current block, scale a block in the reference frame that corresponds to the current block according to the scaling constant, and reconstruct the pixel data of the current block using the scaled block of the reference frame.

[0008] In another aspect, the method includes receiving a reference frame, determining a scaling constant with respect to the current block, scaling the block of the reference frame according to the scaling constant so that the block of the reference frame corresponds to the current block, and reconstructing the pixel data of the current block using the scaled block of the reference frame.

[0009] Details of one or more modifications of the subject matter described herein are shown in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be evident from the description and drawings and from the claims. The present invention provides, for example, the following: (Item 1) A decoder comprising a circuit network, The aforementioned network is Receiving the reference frame, For the current block, determine the scaling constant, Scaling the blocks of the reference frame according to the scaling constant, wherein the blocks of the reference frame correspond to the current blocks. Reconstructing the pixel data of the current block using the scaled block of the reference frame A decoder configured to perform the following actions. (Item 2) The decoder, Receiving a bitstream and The scaling constant is determined from the bitstream, wherein the scaling constant is transmitted within the bitstream. A decoder as described in item 1, configured to perform the following actions. (Item 3) The bitstream includes an index for a predetermined scaling constant, as described in item 2. (Item 4) The decoder according to item 1, wherein the decoder is configured to receive the reference frame by accessing the reference frame from memory. (Item 5) The decoder according to item 1, wherein the decoder is configured to scale the blocks of the reference frame by interpolating pixel values. (Item 6) The interpolation of the aforementioned pixel values ​​is performed using a subpixel predictive interpolation filter, as described in item 9 of the decoder. (Item 7) Reconstructing the pixel data comprises processing the current block using an interprediction mode, the reconstruction comprising determining the current block by combining at least a predicted block and a residual, the predicted block being determined using a scaled block of the reference frame, according to item 1. (Item 8) The decoder according to item 1, wherein the decoder is configured to receive a bitstream, the bitstream including a field that characterizes a skip adaptive resolution control mode. (Item 9) The decoder, Processing multiple blocks according to an adaptive resolution control mode, wherein the processing involves: Applying the first filter to the first current block among multiple current blocks, The method involves applying a second filter to a second current block among the plurality of current blocks, wherein the plurality of blocks form part of a frame. including A decoder as described in item 1, configured to perform the following actions. (Item 10) An entropy decoder processor, wherein the entropy decoder processor is configured to receive a bitstream and decode the bitstream into quantized coefficients, An inverse quantization and inverse transform processor, wherein the inverse quantization and inverse transform processor is configured to process the quantized coefficients, including performing an inverse discrete cosine operation; Deblocking filter and Frame buffer and Intra Prediction Processor and The decoder according to item 1, further comprising (Item 11) A method, the method comprising: Receiving a reference frame; Determining a scaling constant for a current block; Scaling a block of the reference frame according to the scaling constant, the block of the reference frame corresponding to the current block; Reconstructing pixel data of the current block using the scaled block of the reference frame And a method comprising (Item 12) Receiving a bitstream; Determining the scaling constant from the bitstream, the scaling constant being signaled within the bitstream; The method according to item 11, further comprising (Item 13) The bitstream includes an index for a predetermined scaling constant, item The method according to 12 (Item 14) Receiving the reference frame includes accessing the reference frame from memory, the method according to item 11 (Item 15) Scaling the block of the reference frame includes interpolating pixel values, the method according to item 11 (Item 16) Interpolating the pixel values is performed using a sub-pixel prediction interpolation filter, the method according to item 20 (Item 17) The method according to item 11, wherein reconstructing the pixel data comprises processing the current block using an interpretation mode, the processing further comprises determining the current block by combining at least a predicted block with a residual, the predicted block being determined using a scaled block of the reference frame. (Item 18) The method according to item 11, further comprising receiving a bitstream, the bitstream including a field characterizing a skip adaptive resolution management mode. (Item 19) The process further includes processing multiple blocks according to the adaptive resolution control mode, Applying the first filter to the first current block among multiple current blocks, The method involves applying a second filter to a second current block among the plurality of current blocks, wherein the plurality of blocks form part of a frame. The method described in item 1, including the method described in item 1. (Item 20) At least one of the receiving, determining, scaling, and reconstructing is performed by the decoder, and the decoder An entropy decoder processor, wherein the entropy decoder processor is configured to receive a bitstream and decode the bitstream into quantized coefficients, An inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor is configured to process the quantized coefficients, including performing an inverse discrete cosine operation, Deblocking filter and Frame buffer and Intra Prediction Processor and The method described in item 1, comprising: [Brief explanation of the drawing]

[0010] For the purpose of illustrating the present invention, the drawings illustrate aspects of one or more embodiments of the invention. However, it should be understood that the invention is not limited to the precise arrangement and means shown in the drawings.

[0011] [Figure 1] Figure 1 shows exemplary reference frames and exemplary prediction frames at various resolution scales.

[0012] [Figure 2] Figure 2 illustrates the exemplary baseline frame, the exemplary rescaled baseline frame, and the exemplary subsequent block prediction process.

[0013] [Figure 3] Figure 3 is a process flow diagram illustrating exemplary processes for several implementations of this subject.

[0014] [Figure 4] Figure 4 is a system block diagram illustrating an exemplary decoder capable of decoding a bitstream according to several implementations of this subject.

[0015] [Figure 5] Figure 5 is a process flow diagram illustrating an exemplary process for encoding video according to several implementations of this subject.

[0016] [Figure 6] Figure 6 is a system block diagram illustrating exemplary video encoders based on several implementations of this subject.

[0017] [Figure 7] Figure 7 is a block diagram of a computing system that may be used to implement any one or more of the methodologies disclosed herein or in any one or more portions thereof.

[0018] Drawings are not necessarily to scale and may be illustrated using imaginary lines, schematic representations, and partial drawings. In some cases, details that are not necessary for understanding the embodiment or that make other details difficult to perceive may be omitted. Similar reference symbols in various drawings indicate similar elements. [Modes for carrying out the invention]

[0019] Detailed explanation In many current state-of-the-art encoders, resolution is managed by recoding and retransmitting entire portions of video known as group of pictures (GOP). This requires transmitting intraframes (I-frames) because those frames involve a large portion of the bits within the GOP, which can incur additional costs.

[0020] Embodiments described herein relate to Adaptive Resolution Management (ARM), a technique that enables additional flexibility for video encoders / decoders, allowing for bitrate savings in various use cases. Generally, ARM involves performing a prediction using a reference frame with a different resolution than the current frame. In current coding standards, the reference frame has the same resolution as the predicted frame. In ARM, the reference frame may have a lower or higher resolution than the predicted frame. This approach can be used to downscale video resolution and thus reduce the bitrate, or to upscale video resolution and thus improve the display characteristics of video playback.

[0021] ARM may be referred to as reference picture resampling (RPR) for the purposes of this disclosure, either as an alternative or equivalent term, and RPR and ARM may be used synonymously.

[0022] Some implementations of this subject may involve using ARM for any number of frames at any position within the GOP, and thus eliminating the requirement for recoding I frames.

[0023] Figure 1 shows reference and predicted frames at various resolution scales. Frame 1 is smaller (lower resolution) than the reference frame, Frame 2 is the same size (same resolution), while Frame 3 is larger (higher resolution). As used in this disclosure, “resolution” is the number of pixels in a picture, frame, subframe, and / or other displayed area or portion thereof used in video playback, compression, or equivalent, where a higher number of pixels corresponds to a higher resolution, and a lower number of pixels corresponds to a lower resolution. Resolution may also be measured in terms of area, for example, by using one or more dimensions of length measured in pixels that define a certain area, for example, but not limited to. For example, a circular subframe or other area may have a resolution defined according to its radius. Alternatively, or in addition, resolution may be defined by the total number of pixels.

[0024] As an example, continuing with reference to Figure 1, if the reference frame and / or subframe have a geometric shape over which the area can be fully defined in terms of two length parameters, such as a triangle, parallelogram, and / or rectangle, then the reference frame and / or subframe may have a resolution W × H (where W and H may represent the number of pixels describing the width (or base) dimension and height dimension of the reference frame and / or subframe, respectively). Each prediction frame may also have a resolution, which can be determined similarly to the resolution of the reference frame. For example, frame 1 may have a lower resolution WS × HS, frame 2 may have the same resolution as the reference frame W × H, and frame 3 may have a higher resolution WL × HL. The width and height of smaller and larger frames can be obtained by multiplying the reference width and height by an arbitrary rescaling constant (Rc), also called a scaling factor and / or constant. For smaller frames, Rc may have a value between 0 and 1. For larger frames, Rc can have a value greater than 1; for example, Rc can have a value between 1 and 4. Other values ​​are also possible. The rescaling constant can differ with respect to one resolution dimension; for example, the rescaling constant Rch may be used to rescale the height, while another rescaling constant Rcw may be used to rescale the width.

[0025] Referring still to Figure 1, ARM may be implemented as a mode. In the case of ARM mode activation at some point during decoding, the decoder may have already received a reference frame at resolution W×H and may rescale the predicted frame using a rescaling constant. In some implementations, the encoder may signal the decoder a rescaling constant for use. This signaling may be done within a sequence parameter set (SPS) corresponding to the GOP containing the current picture, and / or a picture parameter set (PPS) corresponding to the current picture. For example, but not limited to, the encoder may signal the rescaled parameters using fields such as pps_pic_width_in_luma_samples, pps_pic_height_in_luma_samples, pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, pps_scaling_win_bottom_offset, and / or sps_num_subpics_minus1.

[0026] Referring further to Figure 1, the W and H parameters described above can, but are not limited to, be expressed using the variables CurrPicScalWinWidthL and CurrPicScalWinHeightL, respectively, and these variables can be derived from the signal-transmitted parameters described above using one or more mathematical relationships between the signal-transmitted parameters and the variables. For example, but are not limited to, CurrPicScalWinWidthL can be derived according to the following equation. CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset) As a further non-limiting embodiment, CurrPicScalWinHeightL can be derived according to the following equation. CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset)

[0027] Those skilled in the art will recognize, upon examination of the entirety of this disclosure, various alternative calculations that may be used to derive the variables described above. The encoder may, as an alternative or in addition, directly signal one or more such variables Rc, Rch, and / or Rcw within the PPS and / or SPS, for example, but not limited to these.

[0028] Alternatively, or in addition, still referring to Figure 1, the rescaling constants and / or sets of rescaling constants described above may be signaled in the bitstream using stored scaling constants and / or multiple scaling constants, and / or references to indices of frames and / or blocks that were signaled using the scaling constants and / or multiple scaling constants that were signaled immediately before. The references to the indices of stored scaling constants may be explicitly signaled and / or determined from one or more additional parameters that are signaled in the bitstream. For example, but not limited to, the decoder may identify a group of pictures containing a reference frame and / or the current frame, and if the rescaling constants were previously signaled and / or used in such a group of pictures using the reference frame that is signaled so as to be applicable to the current frame and / or the current group of pictures, or equivalents, the decoder may identify those rescaling constants for use as rescaling constants using the current frame.

[0029] In some implementations, continuing with reference to Figure 1, the ARM operation may be performed depending on the block level of the encoded frame. For example, the reference frame may first be rescaled, and then the prediction may be performed as depicted in Figure 2. Figure 2 is a diagram depicting the reference frame, the rescaled reference frame, and the subsequent block prediction process. The block prediction process may be performed on a scaled reference frame (with scaled resolution) rather than the original reference frame. Rescaling the reference frame may include rescaling according to any parameter signaled by the encoder as described above, for example, if the reference frame to be used with the current picture is signaled via a reference to an index value associated with the reference frame or its equivalent, the signaled reference frame may be rescaled prior to the prediction according to any of the rescaling methods described above. The rescaled reference frame may be stored in memory and / or in a buffer, which may include, but not limited to, a buffer that identifies the frames contained therein by index, according to any frame reads that may be performed, and the buffer may include one or more additional buffers implemented by the decoded picture buffer (DCB) and / or decoder. The prediction process may include, for example, interpicture prediction, including motion compensation.

[0030] Some implementations of block-based ARM may allow for the flexibility of applying the optimal filter to each block instead of applying the same filter across the entire frame. In some implementations, skip ARM modes may be considered, such that some blocks (based on, for example, uniformity of pixel and bitrate costs) may be in skip ARM mode (where rescaling would not change the bitrate). Skip ARM modes may be signaled within the bitstream, or, for example, but not limited to, skip ARM modes may be signaled within the PPS parameters. Alternatively, or in addition, the decoder may signal that the skip ARM mode is one set by the decoder and / or signaled within the bitstream. Alternatively, the decision to be active may be based on parameters that are superior to or exceed those parameters. Spatial filters used within block-based ARM may include, but are not limited to, bicubic spatial filters that apply bicubic interpolation, bilinear spatial filters that apply bilinear interpolation, Lanczos filters that use Lanczos filtering, and / or sinc filters, sinc function interpolation, and / or Lanczos resampling that use a combination of signal reconstruction techniques, and a person skilled in the art will recognize a variety of filters that may be used consistently in this disclosure for interpolation, in accordance with a thorough examination of this disclosure.

[0031] Figure 3 is a process flow diagram illustrating an exemplary embodiment of a block-based adaptive resolution management process 300, which can enable additional flexibility for video encoders / decoders, allowing for bitrate savings in various use cases.

[0032] In step 305, still referring to Figure 3, the reference frame is received. The reference frame may be received (and accessed, for example) by memory, and for example, the reference frame may be accessed from a frame buffer. The reference frame may have been decoded immediately before from a bitstream. The bitstream may have been received by a decoder. The bitstream may contain the current block. The current block may be contained within the bitstream received by the decoder. The bitstream may contain data found in a stream of bits, which is the input to the decoder when using data compression, for example, as described in more detail below. The bitstream may contain information necessary to decode the video. Receiving may include extracting and / or parsing blocks and associated signaling information from the bitstream. In some implementations, the current block may contain a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU).

[0033] In step 310, continuing to refer to Figure 3, the scaling constant may be determined with respect to the current block. In some implementations, the scaling constant may be determined from the bitstream. For example, the scaling constant may be signaled directly within the bitstream, and / or the bitstream may contain an index for a given scaling constant.

[0034] In step 315, still referring to Figure 3, the reference frame block may be scaled according to a scaling constant. The reference frame block may correspond to the current block. Scaling the reference frame block may involve interpolating pixel values ​​to determine the pixel values ​​for the scaled block. In some implementations, interpolating pixel values ​​may be performed using a subpixel predictive interpolation filter. The interpolation filter may, in non-limiting embodiments, be used with an upsampling process, which may include a low-pass filter, where pixels between pixels in the block and / or frame immediately preceding the scaling are initialized to zero, and then the output of the low-pass filter may be taken. Alternatively, or in addition, any luminance sample interpolation filtering process may be used. Luminance sample interpolation may involve calculating an interpolated value in a half-sample interpolation filter index corresponding to two consecutive sample values ​​of an unscaled sample array. The calculation of interpolated values ​​may, but are not limited to, be performed by reading coefficients and / or weights from a lookup table, the selection of the lookup table may be performed as a function of the motion model of coding units and / or scaling ratios, for example, using scaling constants as described above. The calculation may, but are not limited to, perform a weighted sum of adjacent pixel values ​​if the weights are read from a lookup table. The calculated values ​​may, alternatively or in addition, be shifted, for example, but are not limited to, the values ​​being shifted by a minimum value (4, i.e., bit depth -8), a maximum value (2, i.e., 14-bit depth), or equivalents. Those skilled in the art will recognize various alternative or additional implementations that may be used for interpolation filters in accordance with a thorough examination of this disclosure.

[0035] In step 320, referring further to Figure 3, the pixel data of the current block may be reconstructed using a scaled block from a reference frame. Reconstructing the pixel data may include processing the current block using an inter-prediction mode, which may include determining the current block by combining a predicted block with residuals. The predicted block may be determined using a scaled block from a reference frame.

[0036] In some implementations, multiple blocks may be processed according to an adaptive resolution management mode. Processing may include applying a first filter to the first current block of multiple current blocks and applying a second filter to the second current block of multiple current blocks. Multiple blocks may form part of a frame. The decoder may use a list of filters predefined and ordered by the initialization, and the encoder may calculate the optimal filter for a given frame and / or part of it and signal the optimal filter to the decoder.

[0037] In some implementations, the bitstream may include fields that characterize the skip adaptive resolution management mode.

[0038] Figure 4 is a system block diagram illustrating an exemplary decoder 400 capable of block-based adaptive resolution management. The decoder 400 may include an entropy decoder processor 404, an inverse quantization and inverse transform processor 408, a deblocking filter 412, a frame buffer 416, a motion compensation processor 420, and / or an intra-prediction processor 424.

[0039] During operation, still referring to Figure 4, the bitstream 428 may be received by the decoder 400 and input to the entropy decoder processor 404, which may entropi-decode a portion of the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 408, which may perform inverse quantization and inverse transform and generate a residual signal, which may be added to the output of the motion compensation processor 420 or the intra-prediction processor 424, depending on the processing mode. The outputs of the motion compensation processor 420 and the intra-prediction processor 424 may include block predictions based on the previously decoded block. The sum of the predictions and residuals may be processed by the deblocking filter 412 and stored in the frame buffer 416.

[0040] Figure 5 is a process flow diagram illustrating an exemplary process 500 for encoding video according to block-based adaptive resolution management, which can enable additional flexibility for video encoders / decoders, allowing for bitrate savings in various use cases. In step 505, video frames may undergo initial block segmentation using a tree-structured macroblock partitioning scheme, which may include, for example, partitioning picture frames into CTUs and CUs.

[0041] In step 510, still referring to Figure 5, block-based adaptive resolution management may be implemented, including resolution scaling of the frame or part thereof.

[0042] In step 515, continuing to refer to Figure 5, the block may be encoded and included in the bitstream. Encoding may include, for example, utilizing inter-prediction mode and intra-prediction mode.

[0043] Figure 6 is a system block diagram illustrating an exemplary video encoder 600 capable of encoding video using rearrangement of fusion candidates based on global motion vectors. The exemplary video encoder 600 may receive an input video 604, which may first be segmented or divided according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree + binary tree). An embodiment of the tree-structured macroblock partitioning scheme may involve partitioning the picture frame into larger block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned once or more times into several subblocks called coding units (CUs). The final result of this partitioning may include a group of subblocks, which may be called prediction units (PUs). Transformation units (TUs) may also be used.

[0044] Still referring to Figure 6, the exemplary video encoder 600 may include an intra-prediction processor 608, which may also be called an inter-prediction processor, capable of constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list; a motion estimation / compensation processor 612; a transform / quantization processor 616; an inverse quantization / inverse transform processor 620; an in-loop filter 624; a decoded picture buffer 628; and / or an entropiccoding processor 632. Bitstream parameters may be input to the entropiccoding processor 632 for inclusion in the output bitstream 636.

[0045] During operation, continuing to refer to Figure 6, for each block of frames in the input video 604, it may be determined whether to process the block via intra-picture prediction or using motion estimation / compensation. The block may be provided to the intra-prediction processor 608 or the motion estimation / compensation processor 612. If the block should be processed via intra-prediction, the intra-prediction processor 608 may perform the processing and output predictors. If the block should be processed via motion estimation / compensation, the motion estimation / compensation processor 612 may perform the processing, including, if applicable, constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list.

[0046] Referring further to Figure 6, the residual may be formed by subtracting the predictor from the input video. The residual may be received by a transform / quantization processor 616, which may perform a transform (e.g., a discrete cosine transform (DCT)) and produce coefficients that can be quantized. The quantized coefficients and any associated signal-transmission information may be provided to an entropic coding processor 632 for entropic encoding and inclusion in the output bitstream 636. The entropic coding processor 632 may assist in encoding the signal-transmission information related to encoding the current block. In addition, the quantized coefficients may be combined with the predictor and provided to an inverse quantization / inverse transform processor 620, which can reconstruct pixels that can be processed by an in-loop filter 624, the output of which may be stored in a decoded picture buffer 628 for use by a motion estimation / compensation processor 612, which can construct a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list.

[0047] Continuing to refer to Figure 6, several variations have been described in detail above, but other modifications or additions are also possible. For example, in some implementations, the current blocks may include any symmetric blocks (8×8, 16×16, 32×32, 64×64, 128×128, and equivalents) as well as any asymmetric blocks (8×4, 16×8, and equivalents).

[0048] In some implementations, still referring to Figure 6, a quadtree-binary decision tree (QTBT) may be implemented. In a QTBT, at the coding tree unit level, the partition parameters of the QTBT may be dynamically derived to fit local characteristics without transmitting any overhead. Subsequently, at the coding unit level, a joint classifier decision tree structure may be used to eliminate unnecessary iterations and control the risk of false predictions. In some implementations, an LTR frameblock update mode may be available as an additional option per leaf node of the QTBT.

[0049] In some implementations, still referring to Figure 6, additional syntactic elements may be signaled at different hierarchical levels of the bitstream. For example, a flag may be enabled throughout the sequence by including an enabled flag coded within the sequence parameter set (SPS). Furthermore, a CTU flag may be coded at the coding tree unit (CTU) level.

[0050] Some embodiments may include a non-transient computer program product (i.e., a physically embodied computer program product) that, when executed by one or more data processors of one or more computing systems, stores instructions causing at least one data processor to perform the operations described herein.

[0051] Embodiments disclosed herein include a decoder, which is configured to receive a reference frame, determine a scaling constant with respect to the current block, scale a block of the reference frame corresponding to the current block according to the scaling constant, and reconstruct the pixel data of the current block using the scaled block of the reference frame.

[0052] The decoder may further be configured to receive a bitstream and determine from the bitstream a scaling constant, which is signaled within the bitstream. The bitstream may include an index for a given scaling constant. The decoder may be configured to receive a reference frame by accessing a reference frame from memory. The decoder may be configured to scale blocks of the reference frame by interpolating pixel values. Interpolating pixel values ​​may be done using a sub-pixel prediction interpolation filter. Reconstructing the pixel data may include processing the current block using an intermediate prediction mode, and the reconstruction includes determining the current block by combining at least a predicted block and a residual, the predicted block being determined using a scaled block of the reference frame. The decoder may be configured to receive a bitstream, which includes fields characterizing a skip adaptive resolution management mode. The decoder may further be configured to process a plurality of blocks according to an adaptive resolution management mode, which includes applying a first filter to a first current block of a plurality of current blocks and applying a second filter to a second current block of a plurality of current blocks, the plurality of blocks forming a portion of a frame. The decoder may include an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra-prediction processor.

[0053] Embodiments disclosed herein may include a method comprising: receiving a reference frame; determining a scaling constant with respect to the current block; scaling the block of the reference frame according to the scaling constant, wherein the block of the reference frame corresponds to the current block; and reconstructing the pixel data of the current block using the scaled block of the reference frame.

[0054] The method may also include receiving a bitstream and determining a scaling constant from the bitstream, wherein the scaling constant is signaled within the bitstream. The bitstream may include an index for a given scaling constant. Receiving a reference frame may include accessing the reference frame from memory. Scaling blocks of the reference frame may include interpolating pixel values. Interpolating pixel values ​​may be performed using a sub-pixel prediction interpolation filter. Reconstructing pixel data includes processing the current block using an intermediate prediction mode, which further includes determining the current block by combining at least a predicted block with a residual, wherein the predicted block is determined using a scaled block of the reference frame. The method may also include receiving a bitstream, which includes a field characterizing a skip adaptive resolution management mode. The method may also include processing a plurality of blocks according to an adaptive resolution management mode, which may include applying a first filter to a first current block of a plurality of current blocks and applying a second filter to a second current block of a plurality of current blocks, wherein the plurality of blocks form a portion of a frame. At least one of receiving, determining, scaling, and reconstructing may be performed by a decoder comprising an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra-prediction processor.

[0055] It should be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic networks, integrated circuit networks, specially designed application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof, so as will be obvious to those skilled in the computer art, and may be realized and / or implemented in one or more machines (e.g., one or more computing devices used as a user computing device for electronic documents, one or more server devices such as a document server, etc.) programmed in accordance with the teachings herein. These various aspects or features may include implementations in one or more computer programs and / or software that are executable and / or interpretable on a programmable system, including at least one programmable processor, which may be for special purpose or general purpose, that receives data and instructions from a storage system, at least one input device, and at least one output device, and is coupled to transmit data and instructions to them. Appropriate software coding can be readily prepared by a skilled programmer based on the teachings of this disclosure, so as to be obvious to those skilled in the software art. The aspects and implementations discussed above, employing software and / or software modules, may also include appropriate hardware to assist in the implementation of machine-executable instructions of the software and / or software modules.

[0056] Such software may be a computer program product employing a machine-readable storage medium. The machine-readable storage medium may be any medium capable of storing and / or encoding a sequence of instructions for execution by a machine (e.g., a computing device), causing the machine to implement any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random access memory "RAM" devices, magnetic cards, optical cards, solid-state memory devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and / or any combination thereof. As used herein, the machine-readable storage medium is intended to include a single medium, as well as a collection of physically separate media, such as a compact disk or a collection of one or more hard disk drives in combination with computer memory. As used herein, the machine-readable storage medium does not include transient forms of signal transmission.

[0057] Such software may also include information (e.g., data) carried as data signals on a data carrier such as a carrier wave. For example, machine-executable information may include data-carry signals embodied in a data carrier, where the signals encode a sequence or part of instructions for execution by a machine (e.g., a computing device), and any related information (e.g., data structures and data) that causes the machine to implement any one of the methodologies and / or embodiments described herein.

[0058] Embodiments of computing devices include, but are not limited to, e-book reading devices, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smartphones, etc.), web devices, network routers, network switches, network bridges, and any machine capable of executing a sequence of instructions that define the actions to be taken by such machines and any combination thereof. In one embodiment, the computing device includes and / or may be contained within a kiosk.

[0059] Figure 7 shows a schematic representation of one embodiment of a computing device in an exemplary form of computer system 700, in which a set of instructions can be executed to cause a control system to implement one or more aspects and / or methodologies of the present disclosure. It is also conceivable that multiple computing devices may be used to implement a specially configured set of instructions for causing one or more of the present devices to implement one or more aspects and / or methodologies of the present disclosure. Computer system 700 includes a processor 704 and memory 708 that communicate with each other and with other components via a bus 712. The bus 712 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of various bus architectures.

[0060] Memory 708 may include, but is not limited to, various components (e.g., machine-readable media), including random-access memory components, read-only components, and any combination thereof. In one embodiment, a basic input / output system 716 (BIOS), which includes basic routines that help transfer information between elements within the computer system 700 during startup, etc., may be stored in memory 708. Memory 708 may also include instructions (e.g., software) 720 (e.g., stored on one or more machine-readable media) that embody one or more aspects and / or methodologies of this disclosure. In another embodiment, memory 708 may further include, but is not limited to, any number of program modules, including an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0061] The computer system 700 may also include a storage device 724. Embodiments of the storage device (e.g., storage device 724) include, but are not limited to, hard disk drives, magnetic disk drives, optical disk drives in combination with optical media, solid-state memory devices, and any combination thereof. The storage device 724 may be connected to the bus 712 by a suitable interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE®), and any combination thereof. In one embodiment, the storage device 724 (or one or more of its components) may be removably interfaced with the computer system 700 (e.g., via an external port connector (not shown)). In particular, the storage device 724 and associated machine-readable media 728 may provide non-volatile and / or volatile storage devices for machine-readable instructions, data structures, program modules, and / or other data for the computer system 700. In one embodiment, the software 720 may reside entirely or partially within a machine-readable medium 728. In another embodiment, the software 720 may reside entirely or partially within a processor 704.

[0062] The computer system 700 may also include an input device 732. In one embodiment, a user of the computer system 700 may input commands and / or other information into the computer system 700 via the input device 732. Embodiments of the input device 732 include, but are not limited to, alphanumeric input devices (e.g., keyboards), pointing devices, joysticks, gamepads, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., mice), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touchscreens, and any combination thereof. The input device 732 may interface to the bus 712 via, but are not limited to, a variety of interfaces (not shown) including serial interfaces, parallel interfaces, game ports, USB interfaces, FIREWIRE® interfaces, direct interfaces to the bus 712, and any combination thereof. The input device 732 may also include a touchscreen interface, which may be part of or separate from the display 736, which will be discussed further below. The input device 732 may be used as a user selection device for selecting one or more graphic representations within a graphical interface as described above.

[0063] The user may also input commands and / or other information to the computer system 700 via a storage device 724 (e.g., a removable disk drive, a flash drive, etc.) and / or a network interface device 740. Network interface devices such as network interface device 740 may be used to connect the computer system 700 to one or more of various networks such as network 744, and one or more remote devices 748 connected thereto. Embodiments of network interface devices include, but are not limited to, network interface cards (e.g., mobile network interface cards, LAN cards), modems, and any combination thereof. Embodiments of networks include, but are not limited to, wide area networks (e.g., the Internet, corporate networks), local area networks (e.g., networks associated with offices, buildings, campuses, or other relatively small geographical spaces), telephone networks, data networks associated with telephone / voice providers (e.g., data and / or voice networks of mobile communication providers), direct connections between two computing devices, and any combination thereof. Networks such as network 744 may employ wired and / or wireless modes of communication. In general, any network topology may be used. Information (e.g., data, software 720, etc.) may be communicated to and / or from the computer system 700 via the network interface device 740.

[0064] The computer system 700 may further include a video display adapter 752 for communicating images that can be displayed on a display device such as a display device 736. Embodiments of the display device include, but are not limited to, liquid crystal displays (LCDs), cathode ray tubes (CRTs), plasma displays, light-emitting diode (LED) displays, and any combination thereof. The display adapter 752 and the display device 736 may be used in combination with a processor 704 to provide a graphic representation of aspects of this disclosure. In addition to the display devices, the computer system 700 may include, but are not limited to, one or more other peripheral output devices, including audio speakers, printers, and any combination thereof. Such peripheral output devices may be connected to the bus 712 via a peripheral interface 756. Embodiments of the peripheral interface include, but are not limited to, serial ports, USB connections, FireWire® connections, parallel connections, and any combination thereof.

[0065] The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions can be made without departing from the spirit and scope of the invention. Each feature of the various embodiments described above can be combined with features of other described embodiments as appropriate to provide a combination of multiple features in the associated new embodiments. Furthermore, the foregoing describes several distinct embodiments, but those described herein are merely illustrative of the application of the principles of the invention. In addition, certain methods described herein may be illustrated and / or described as being carried out in a specific order, but the order is highly variable among those skilled in the art to achieve embodiments such as those disclosed herein. Therefore, this description is intended to be taken only as examples and is not intended to otherwise limit the scope of the invention.

[0066] In the above description and claims, phrases such as “at least one of ~” or “one or more of ~” may occur and be followed by a conjunctive enumeration of elements or features. The term “and / or” may also occur within an enumeration of two or more elements or features. Unless otherwise implicitly or expressly refuted by the context in which such phrase is used, it is intended to mean either of the individually enumerated elements or features, or any of the elements or features cited in combination with any other cited elements or features. For example, the phrases “at least one of A and B,” “one or more of A and B,” and “A and / or B” are intended to mean “A alone, B alone, or A and B together,” respectively. A similar interpretation is also intended for enumerations containing three or more items. For example, the phrases “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, and / or C” are intended to mean “A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B as well as C together,” respectively. In addition, the use of the term “based on” above and within the claims is intended to mean “at least, based on” any feature or element not cited, as is also acceptable.

[0067] The subject matter described herein can be embodied in systems, apparatus, methods, and / or articles, depending on the desired configuration. The implementations described herein do not represent all implementations consistent with the subject matter described herein. Rather, they are merely some examples consistent with aspects related to the subject matter described herein. While some variations are described in detail above, other modifications or additions are also possible. In particular, further features and / or variations may be provided in addition to those described herein. For example, the implementations described above may cover various combinations and subcombinations of the disclosed features and / or combinations and subcombinations of some further features disclosed above. In addition, the logical flows depicted in the accompanying diagrams and / or described herein do not necessarily require a specific order or sequential order shown to achieve the desired result. Other implementations may also be within the scope of the following claims.

Claims

1. An encoder comprising a network configured to encode a video bitstream, the network comprising: A network of circuits configured to receive a source video signal, A network configured to generate an encoded bitstream representing the source video signal, wherein the encoded bitstream includes a current picture and a reference picture, the current block being coded, and the bitstream also includes an index useful for determining a scaling factor, and the bitstream is Determine whether a mode is enabled when the reference picture and the current picture have different resolutions, Using the aforementioned mode, The scaling rate is determined using the information in the bitstream, including the aforementioned index. The scaled predicted block is determined by scaling the block of the reference picture using the aforementioned scaling ratio and by applying a pixel interpolation filter, wherein the pixel interpolation filter is determined specifically for the predicted block. The scaled prediction block is combined with the residual. Reconstructing the current coded block by and A network that can be decoded by a method including, A network configured to transmit the encoded bitstream to a decoder via a channel. An encoder equipped with the following features.

2. The encoder according to claim 1, wherein the scaling factor further includes one of a height scaling constant or a width scaling constant.

3. The encoder according to claim 1, wherein the interpolation filter uses a luminance sample interpolation process.

4. The encoder according to claim 1, wherein the interpolation filter further includes shifting the pixel values.

5. The encoder according to claim 1, wherein the current picture includes a second coded current block, the mode is skipped for the second coded current block, and the decoder reconstructs the second coded current block without using a scaled prediction block of the reference picture.

6. The encoder according to claim 1, wherein the current picture includes a second coded current block, and the mode is used to reconstruct the second coded current block using a second pixel interpolation filter different from the first pixel interpolation filter.

7. A method for transmitting an encoded bitstream, Encoding a video bitstream for decoding by a decoder, wherein the encoded bitstream includes a current picture and a reference picture, the current block being coded, and the bitstream also includes an index useful for determining a scaling factor, the bitstream is Receiving the bitstream, which includes the current picture and a reference picture, which includes the coded current block, and the bitstream, which also includes an index useful for determining the scaling rate, Determine whether a mode is enabled when the reference picture and the current picture have different resolutions, Using the aforementioned mode, The scaling rate is determined using the information in the bitstream, including the aforementioned index. The scaled predicted block is determined by scaling the block of the reference picture using the aforementioned scaling ratio and by applying a pixel interpolation filter, wherein the pixel interpolation filter is determined specifically for the predicted block. The scaled prediction block is combined with the residual. Reconstructing the current coded block by and It is configured to be decodeable by a method including, The encoded bitstream is transmitted to the decoder via the channel. Methods that include...

8. The method according to claim 7, wherein the scaling factor further comprises one of a height scaling constant or a width scaling constant.

9. The method according to claim 7, wherein the interpolation filter uses a luminance sample interpolation process.

10. The method according to claim 9, wherein the interpolation filter further includes shifting the pixel values.

11. The method according to claim 7, wherein the current picture includes a second coded current block, the mode is skipped for the second coded current block, and the decoder reconstructs the second coded current block without using a scaled prediction block of the reference picture.

12. The method according to claim 7, wherein the current picture includes a second coded current block, and the second coded current block is reconstructed using a second pixel interpolation filter different from the first pixel interpolation filter by utilizing the mode.

Images