Indication device

Abstract

It helps to suppress the decline in reliability. [Solution] According to one embodiment, the display device comprises an organic insulating layer arranged over a display area and a peripheral area, an inorganic insulating layer arranged over the display area and the peripheral area and covering the organic insulating layer, a lower electrode arranged on the organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer arranged on the lower electrode and including a light-emitting layer, an upper electrode arranged on the organic layer, a first lower part arranged on the inorganic insulating layer and having conductivity and contacting the upper electrode, a first upper part arranged on the first lower part, a partition wall formed in an overhang shape, a laminated film arranged in the peripheral area and including a thin film made of the same material as the organic layer and the upper electrode, a first sealing layer made of an inorganic insulating material and arranged on the laminated film, and a first resin layer arranged above the first sealing layer, wherein the first edge of the first resin layer is located directly above the first sealing layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for suppressing a decrease in reliability are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of suppressing a decrease in reliability.

Means for Solving the Problems

[0005] According to an embodiment, a display device The device comprises a substrate, an organic insulating layer disposed above the substrate, extending over a display area for displaying an image and a peripheral area outside the display area, an inorganic insulating layer disposed over the display area and the peripheral area and covering the organic insulating layer, a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, a first lower portion disposed on the inorganic insulating layer and having conductivity and contacting the upper electrode, and a first upper portion disposed on the first lower portion, and a partition wall formed in an overhang shape, disposed in the peripheral area and including a thin film made of the same material as the organic layer and the upper electrode, a first sealing layer made of an inorganic insulating material and disposed on the laminated film, and a first resin layer disposed above the first sealing layer, wherein the first edge of the first resin layer is located directly above the first sealing layer.

[0006] According to the embodiment, the display device is A substrate; an organic insulating layer disposed above the substrate, extending over a display area for displaying an image and a peripheral area outside the display area; an inorganic insulating layer disposed over the display area and the peripheral area, covering the organic insulating layer; a lower electrode disposed on the organic insulating layer in the display area, having a peripheral edge covered by the inorganic insulating layer; an organic layer disposed on the lower electrode, including a light-emitting layer; an upper electrode disposed on the organic layer; and a conductive component disposed on the inorganic insulating layer that contacts the upper electrode. The device comprises a partition wall formed in an overhang shape, comprising a first lower part and a first upper part disposed above the first lower part; a laminated film disposed in the peripheral region and including a thin film made of the same material as the organic layer and the upper electrode; a first sealing layer made of an inorganic insulating material and disposed above the laminated film; a first resin layer disposed above the first sealing layer; a second sealing layer covering the first resin layer; and a second resin layer disposed above the second sealing layer, wherein the third edge of the second resin layer is located directly above the first sealing layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX. [Figure 3] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2. [Figure 4A] Figure 4A is a schematic plan view of a display device DSP to illustrate an example configuration of the peripheral region SA. [Figure 4B] Figure 4B is a schematic plan view of a display device DSP to illustrate another example of a peripheral region SA configuration. [Figure 5A] Figure 5A is a schematic cross-sectional view of the display device DSP along the CD line in the peripheral region SA shown in Figure 4A. [Figure 5B] Figure 5B is an enlarged cross-sectional view of the vicinity of edges E1 and E2 shown in Figure 5A. [Figure 5C] Figure 5C illustrates the effect of moisture infiltration near the edge E2. [Figure 6A] Figure 6A is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6B] Figure 6B is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6C] Figure 6C is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6D] Figure 6D is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6E] Figure 6E is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6F] Figure 6F is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6G] Figure 6G is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6H] Figure 6H is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6I]FIG. 6I is a diagram for explaining a method of manufacturing a display device DSP. [Figure 7A] FIG. 7A is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 7B] FIG. 7B is an enlarged cross-sectional view of the vicinity of the edge E3 shown in FIG. 7A. [Figure 8] FIG. 8 is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 9] FIG. 9 is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 10A] FIG. 10A is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 10B] FIG. 10B is an enlarged cross-sectional view of the vicinity of the edges E1 and E2 shown in FIG. 10A. [Figure 11A] FIG. 11A is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 11B] FIG. 11B is an enlarged cross-sectional view of the vicinity of the edges E1 and E2 shown in FIG. 11A. [Figure 12A] FIG. 12A is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 4A. [Figure 12B] FIG. 12B is an enlarged cross-sectional view of the vicinity of the edges E1 and E2 shown in FIG. 12A.

Embodiments for Carrying Out the Invention

[0008] Embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing various elements parallel to the third direction Z is called a plan view. In addition, terms such as "up," "above," "between," and "opposite" refer to the positional relationship between two or more constituent elements, and include not only cases where the two or more constituent elements of an object are in direct contact, but also cases where they are separated from each other by gaps or other constituent elements. The positive direction of the Z axis will be referred to as "up" or "above."

[0010] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] Figure 1 shows an example configuration of a display device DSP.

[0012] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0013] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in plan view. However, the shape of the display area DA in plan view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors from each other. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] Note that the rounded portion RD of the display area DA is a shape that is visible macroscopically, while microscopically it is a shape formed by the arrangement of multiple pixels PX in a stepped pattern.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. In the illustrated example, the scan line GL and power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0020] The display device DSP further includes a terminal section T located in the peripheral region SA. The terminal section T has multiple terminals and is electrically connected to, for example, an IC chip for driving a display element DE or a flexible circuit board.

[0021] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX.

[0022] In the illustrated example, sub-pixels SP2 and SP3 are aligned in the second direction Y. Sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0023] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown.

[0024] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs.

[0025] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the apertures AP1, AP2, and AP3. The partition wall 6, like the inorganic insulating layer 5, can also be said to have apertures OP1, OP2, and OP3 in the sub-pixels SP1, SP2, and SP3, respectively. Aperture OP1 overlaps with aperture AP1, aperture OP2 overlaps with aperture AP2, and aperture OP3 overlaps with aperture AP3. The partition wall 6 is conductive and is electrically connected to the common voltage terminal at the terminal section T shown in Figure 1.

[0026] The sub-pixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively.

[0027] The display element DE1 of the sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, organic layer OR1, and upper electrode UE1 constituting the display element DE1 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view.

[0028] The display element DE2 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, organic layer OR2, and upper electrode UE2 constituting the display element DE2 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view.

[0029] The sub-pixel SP3 display element DE3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, organic layer OR3, and upper electrode UE3 constituting the display element DE3 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view.

[0030] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown may not accurately reflect their actual shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode and are in contact with the partition wall 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0033] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. Note that the relative sizes of the areas of opening AP1, opening AP2, and opening AP3 are not limited to the illustrated example.

[0034] The partition wall 6 has multiple slits ST. In the illustrated example, each slit ST extends in the second direction Y. For example, sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are arranged between two adjacent slits ST in the first direction X. Note that the slits ST may be omitted.

[0035] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2.

[0036] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, various wirings such as scan lines GL, signal lines SL, and power lines PL, and various insulating layers.

[0037] The organic insulating layer 12 is placed on top of the circuit layer 11. The organic insulating layer 12 is formed, for example, to flatten the irregularities caused by the circuit layer 11.

[0038] The lower electrode LE1 of sub-pixel SP1, LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are arranged on the organic insulating layer 12 and spaced apart from each other.

[0039] The inorganic insulating layer 5 is placed on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the aperture AP2 overlaps with the lower electrode LE2, and the aperture AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the organic insulating layer 12. Note that the contact holes of the organic insulating layer 12 are omitted in Figure 3.

[0040] The partition wall 6 is formed in an overhang shape and comprises a conductive lower part 61 placed on the inorganic insulating layer 5 and an upper part 62 placed on the lower part 61.

[0041] In the illustrated example, the lower part 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5, and an axial layer 64 placed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a greater width than the axial layer 64. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0042] The upper section 62 is positioned on top of the axial layer 64. The upper section 62 has a greater width than the axial layer 64. Both ends of the upper section 62 protrude from the sides of the axial layer 64. In this specification, the sides of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper section 62. In the illustrated example, the upper section 62 has a greater width than the bottom layer 63. The bottom layer 63 may also have a greater width than the upper section 62.

[0043] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0044] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0045] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0046] Furthermore, contact between each of the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper part 62.

[0047] In the illustrated example, sub-pixel SP1 has a cap layer CP1 and a sealing layer SE11, sub-pixel SP2 has a cap layer CP2 and a sealing layer SE12, and sub-pixel SP3 has a cap layer CP3 and a sealing layer SE13. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0048] The cap layer CP1 is placed on top of the upper electrode UE1. The cap layer CP2 is placed on top of the upper electrode UE2. The cap layer CP3 is placed on top of the upper electrode UE3.

[0049] The sealing layer SE11 is positioned on top of the cap layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE11 is in contact with the axial layer 64 and upper layer 62 of the partition wall 6 surrounding the display element DE1.

[0050] The sealing layer SE12 is positioned on top of the cap layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE12 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE2.

[0051] The sealing layer SE13 is positioned on top of the cap layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. The sealing layer SE13 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE3.

[0052] In the following explanation, a multilayer structure containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer structure containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer structure containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0053] The ends of the sealing layers SE11, SE12, and SE13 are located on the partition wall 6. In the illustrated example, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the same partition wall 6. Similarly, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the same partition wall 6.

[0054] The laminated films FL1, FL2, and FL3 are not formed on the partition wall 6. Cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0055] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills the cavity formed above the partition wall 6.

[0056] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 is placed on top of the sealing layer SE2.

[0057] The detection electrode DT, which enables the touch sensor function to detect contact or approach of an object to the display area DA, is placed on the sealing layer SE2 and covered with a resin layer RS2. The detection electrode DT is a multilayer body including, for example, an aluminum layer formed of an aluminum-based material and a titanium layer formed of a titanium-based material. The touch sensor function is realized by detecting a change in capacitance of the sensor part composed of the detection electrode DT.

[0058] The inorganic insulating layer 5, sealing layers SE11, SE12, SE13, and sealing layer SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). In one example, the inorganic insulating layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride.

[0059] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is made of a titanium-based material, such as titanium or a titanium compound. The axial layer 64 is made of a different material from the bottom layer 63 and the upper part 62, and is made of an aluminum-based material, such as aluminum or an aluminum compound.

[0060] The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper part 62 is formed of a different material from the lower part 61. For example, the upper part 62 is formed of a titanium-based material such as titanium or a titanium compound, or an oxide conductive material such as indium tin oxide (ITO).

[0061] The lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a transparent layer formed from an oxide conductive material such as indium tin oxide (ITO), and a reflective layer formed from a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a reflective layer between a pair of transparent layers.

[0062] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials. In one example, light-emitting layer EM1 is formed from a material that emits light in the blue wavelength range, light-emitting layer EM2 is formed from a material that emits light in the green wavelength range, and light-emitting layer EM3 is formed from a material that emits light in the red wavelength range. Alternatively, light-emitting layer EM1 may be formed from a material that emits light in the green wavelength range, and light-emitting layer EM2 may be formed from a material that emits light in the blue wavelength range.

[0063] Furthermore, each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, another hole blocking layer, an electron transport layer, and an electron injection layer.

[0064] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0065] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0066] The illustrated circuit layer 11, organic insulating layer 12, inorganic insulating layer 5, and partition wall 6 are arranged across the display area DA and the surrounding area SA.

[0067] Figure 4A is a schematic plan view of a display device DSP to illustrate an example configuration of the peripheral region SA.

[0068] As described above, partition wall 6 is located in the display area DA. Partition walls 6A, 6B, dam section DM1, and dam section DM2 are located in the peripheral area SA, between the display area DA and the edge 10E of the substrate 10.

[0069] Partition wall 6A is formed to surround the display area DA and is electrically connected to partition wall 6. Partition wall 6B is formed to surround partition wall 6A and is spaced apart from partition wall 6A. In the illustrated example, the outer edge 6AE of partition wall 6A facing partition wall 6B, and partition wall 6B are both formed continuously without any breaks. Note that if the outer edge 6AE is formed continuously without any breaks, partition wall 6B may be omitted.

[0070] These partition walls 6, 6A, and 6B all overlap the organic insulating layer 12 in a plan view. The cross-sectional shapes of partition walls 6A and 6B will be described later, but both are formed in an overhang shape similar to that of partition wall 6.

[0071] Both dam sections DM1 and DM2 are formed in an annular shape. Dam section DM1 is formed to surround the display area DA and is spaced apart from the organic insulating layer 12. Dam section DM2 is formed to surround dam section DM1 and is spaced apart from dam section DM1. Note that the shapes of dam sections DM1 and DM2 are not limited to the illustrated examples. Also, there may be one dam section or three or more dam sections.

[0072] The missing portions RP1, RP2, and RP3 that penetrate the organic insulating layer 12 are all formed in annular shape. Missing portion RP1 is located between the organic insulating layer 12 and the dam portion DM1 and surrounds the display area DA, partition walls 6, 6A, and 6B. Missing portion RP2 is located between the dam portions DM1 and DM2 and surrounds missing portion RP1. Missing portion RP3 extends from the dam portion DM2 to the edge portion 10E and surrounds missing portion RP2.

[0073] Figure 4B is a schematic plan view of a display device DSP to illustrate another example of a peripheral region SA configuration.

[0074] The configuration example shown in Figure 4B differs from the configuration example shown in Figure 4A in that the slit ST of partition wall 6 extends to partition wall 6A. Also, the outer edge 6AE of partition wall 6A, which faces partition wall 6B, is formed discontinuously. On the other hand, partition wall 6B is formed continuously without any breaks.

[0075] Although not shown in the diagram, if the outer edge 6AE is formed continuously as shown in Figure 4A, the partition wall 6B may be formed discontinuously. In other words, it is sufficient that at least one of the outer edge 6AE and the partition wall 6B is formed continuously. This makes it possible to block the moisture intrusion path from the surrounding area SA to the display area DA, as will be described later.

[0076] Figure 5A is a schematic cross-sectional view of the display device DSP along the CD line in the peripheral region SA shown in Figure 4A.

[0077] The circuit layer 11 shown in Figure 3 comprises insulating layers 111, 112, 113, and 114, a power supply line CL, and a connecting electrode CN. Although not described in detail, the circuit layer 11 also includes various wirings and electrodes.

[0078] Insulating layer 111 is placed on substrate 10. Insulating layer 112 is placed on insulating layer 111. Insulating layer 113 is placed on insulating layer 112. Insulating layer 114 is placed on insulating layer 113. Insulating layers 111, 112, and 113 are formed of inorganic insulating material, extend to the edge 10E of substrate 10, and are placed directly beneath dam portions DM1 and DM2. Insulating layer 114 is formed of organic insulating material and is covered by organic insulating layer 12.

[0079] The inorganic insulating layer 5 covers the organic insulating layer 12. In the gap RP1 between the organic insulating layer 12 and the dam section DM1, the inorganic insulating layer 5 covers the insulating layer 113. Partition walls 6A and 6B are positioned above the insulating layer 114 and the organic insulating layer 12, and on top of the inorganic insulating layer 5.

[0080] The power supply line CL is wiring for supplying a common voltage to the partition wall 6 and is located between the insulating layer 112 and the insulating layer 113. The connecting electrode CN is located between the insulating layer 114 and the organic insulating layer 12 and is in contact with the power supply line CL through through holes in the insulating layer 113 and the insulating layer 114. The intermediate electrode RL is located between the organic insulating layer 12 and the inorganic insulating layer 5 and is in contact with the connecting electrode CN through through holes in the organic insulating layer 12. Such an intermediate electrode RL is formed of the same material as, for example, the lower electrode LE1 described above. The partition wall 6A is in contact with the intermediate electrode RL through through holes in the inorganic insulating layer 5. As a result, the partition wall 6A and the partition wall 6 of the display area DA are electrically connected to the power supply line CL.

[0081] Each of the dam sections DM1 and DM2 is placed on the insulating layer 113 and covered with an inorganic insulating layer 5. In the gap RP2 between dam section DM1 and dam section DM2, and in the gap RP3 between dam section DM2 and edge section 10E, the inorganic insulating layer 5 covers the insulating layer 113.

[0082] Each of the dam sections DM1 and DM2 comprises a first layer 114A and a second layer 12A. The first layer 114A is formed simultaneously with the insulating layer 114 using the same material as the insulating layer 114 and has the same thickness as the insulating layer 114. The second layer 12A is formed simultaneously with the organic insulating layer 12 using the same material as the organic insulating layer 12 and has the same thickness as the organic insulating layer 12. Here, thickness corresponds to the length along the third direction Z.

[0083] The first layer 114A is placed on top of the insulating layer 113. The second layer 12A covers the first layer 114A and is covered with an inorganic insulating layer 5. Both the first layer 114A and the second layer 12A are made of the same type of organic insulating material, for example, polyimide.

[0084] The multilayer film MF is located above the organic insulating layer 12 in the peripheral region SA, positioned on partition walls 6A and 6B, and positioned on the inorganic insulating layer 5 between partition walls 6A and 6B. Furthermore, the multilayer film MF is not positioned in any of the missing sections RP1, RP2, or RP3, nor on the dam sections DM1 or DM2.

[0085] The multilayer film MF comprises a stacked film FL and a sealing layer SE1 disposed on top of the stacked film FL. The multilayer film FL here refers to one of the multilayer films FL1, FL2, or FL3 shown in Figure 3. For example, if the multilayer film FL is multilayer film FL3, it is formed as a laminate of thin films made of the same material as the organic layer OR3, the upper electrode UE3, and the cap layer CP3. Furthermore, the sealing layer SE1 here is one of the sealing layers SE11, SE12, or SE13 shown in Figure 3. For example, if the multilayer film FL is multilayer film FL3, then sealing layer SE1 is sealing layer SE13.

[0086] The resin layer RS1 is located on top of the multilayer film MF. The edge E1 of the resin layer RS1 is located directly above the multilayer film MF (or the sealing layer SE1). Furthermore, the resin layer RS1 is not located in any of the missing parts RP1, RP2, or RP3, nor is it located on the dam parts DM1 or DM2.

[0087] The edges E1 of the resin layer RS1 and E2 of the multilayer film MF are both located directly above the organic insulating layer 12. In other words, edges E1 and E2 are located between the display area DA and the missing area RP1. Also, edges E1 and E2 are located directly above the partition wall 6B. In the illustrated example, edge E1 is located inside edge E2 (towards the display area DA), but it is possible that edge E1 is located directly above edge E2. However, edge E1 is never located outside edge E2 (towards the edge 10E of the substrate 10). In other words, the resin layer RS1 is never positioned beyond the multilayer film MF.

[0088] Here, the edge E2 of the multilayer film MF corresponds to the edge of the sealing layer SE1 among the thin films that make up the multilayer film MF. The edge of the multilayer film FL does not necessarily coincide with the edge of the sealing layer SE1 in the third direction Z, and may be located inside the edge of the sealing layer SE1.

[0089] The sealing layer SE2 covers the resin layer RS1. The sealing layer SE2 extends outward beyond edges E1 and E2, covers the partition wall 6B, and is in contact with the inorganic insulating layer 5 at the missing portion RP1, the dam portion DM1, and the missing portion RP2. In the illustrated example, edge E4 of the sealing layer SE2 is located inside edge 10E and overlaps the dam portion DM2.

[0090] With this configuration, the resin layer RS1 is surrounded and sealed by the sealing layers SE1 and SE2. This prevents moisture from penetrating the resin layer RS1.

[0091] The resin layer RS2 is placed on top of the sealing layer SE2 and fills the missing portions RP1 and RP2. In the illustrated example, the edge E3 of the resin layer RS2 overlaps with the dam portion DM2 and is located inside the edge E4.

[0092] As shown in the diagram, a display device DSP in which the missing portion RP3 extends to the edge 10E of the substrate 10 can be removed from the motherboard by using laser light to cut the motherboard.

[0093] Figure 5B is an enlarged cross-sectional view of the vicinity of edges E1 and E2 shown in Figure 5A. Note that in Figure 5B, elements below the organic insulating layer 12 have been omitted.

[0094] Each of the partition walls 6A and 6B, like partition wall 6 shown in Figure 3, comprises a lower section 61 and an upper section 62. The lower section 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5 and an axial layer 64 placed between the bottom layer 63 and the upper section 62. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Similarly, both ends of the upper section 62 protrude from the sides of the axial layer 64.

[0095] The multilayer film FL is divided into a portion located on partition wall 6A, a portion located on partition wall 6B, and a portion located on the inorganic insulating layer 5 between partition walls 6A and 6B. Partition wall 6B is electrically connected to partition wall 6A via a thin film of the same material as the upper electrode contained in the multilayer film FL.

[0096] The sealing layer SE1 covers the multilayer film FL above the partition wall 6A and also covers the partition wall 6A. Furthermore, the sealing layer SE1 covers the multilayer film FL between partition walls 6A and 6B. Also, the sealing layer SE1 overlaps the multilayer film FL above partition wall 6B. The edge of the sealing layer SE1, i.e., the edge E2 of the multilayer film MF, is located directly above partition wall 6B. Therefore, the outside of partition wall 6B (opposite to partition wall 6A) is exposed from the sealing layer SE1.

[0097] The resin layer RS1 is positioned on top of the sealing layer SE1 and fills the space between partition walls 6A and 6B. The edge E1 of the resin layer RS1 is located directly above partition wall 6B. Therefore, the outside of partition wall 6B is exposed from the resin layer RS1.

[0098] The sealing layer SE2 covers the resin layer RS1. Furthermore, the sealing layer SE2 contacts edge E2 outside of edge E1, contacts partition wall 6B outside of edge E2, and covers the outside of partition wall 6B.

[0099] Figure 5C illustrates the effect of moisture infiltration near the edge E2.

[0100] The laminated film FLb, positioned on partition wall 6B, is not covered by the sealing layer SE1 and is exposed from the sealing layer SE1 near the edge E2. Therefore, the laminated film FLb may be destroyed by moisture that penetrates from near the edge E2. On the other hand, the laminated film FLa on partition wall 6A and the laminated film FLc positioned between partition walls 6A and 6B are both covered by the sealing layer SE1 and are separated from the laminated film FLb. Therefore, the laminated films FLa and FLc are not damaged by moisture that penetrates from near the edge E2. In other words, the moisture penetration path from near the edge E2 to the display area DA is blocked, and the laminated film FL in the display area DA is protected from moisture.

[0101] Furthermore, as explained with reference to Figures 4A and 4B, at least one of the outer edge 6AE of partition wall 6A and partition wall 6B is formed continuously. Therefore, the laminated film FL is divided by partition walls 6A and 6B around the entire circumference of the display device DSP. This blocks the moisture intrusion path from the peripheral region SA to the display region DA around the entire circumference of the display device DSP. Thus, a decrease in reliability can be suppressed.

[0102] Next, the manufacturing method of the display device DSP will be described. Figures 6A to 6F are cross-sectional views of the processing substrate SUB along the AB line in Figure 2, with elements below the organic insulating layer 12 omitted.

[0103] First, a processing substrate SUB is prepared as shown in Figure 6A. The process of preparing the processing substrate SUB includes the steps of forming the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 on the organic insulating layer 12, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively, and forming a partition wall 6 having a lower part 61 located on the inorganic insulating layer 5 and an upper part 62 located on the lower part 61. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 having openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition wall 6 is formed. In the step of forming the partition wall 6, partition walls 6A and 6B of the peripheral region SA are also formed at the same time.

[0104] Next, the display element DE1 is formed.

[0105] First, as shown in Figure 6B, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The laminated film FL1 has an organic layer OR1 including an emissive layer EM1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed continuously in a vacuum environment in the deposition apparatus. The laminated film FL1 is divided by the overhanging partition wall 6.

[0106] Then, a sealing layer SE11 is formed that continuously covers the laminated film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0107] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and in the display area DA, they are located not only on the sub-pixel SP1 but also on the sub-pixels SP2 and SP3.

[0108] Next, as shown in Figure 6C, a resist RS patterned to a predetermined shape is formed on the sealing layer SE11. The resist RS overlaps the sub-pixel SP1 and a portion of the surrounding partition wall 6.

[0109] Next, as shown in Figure 6D, the sealing layer SE11 and the multilayer film FL1 are patterned using the resist RS as a mask. By performing various etching processes using the resist RS as a mask, the sealing layer SE11 exposed from the resist RS is removed, and then the cap layer CP1, upper electrode UE1, and organic layer OR1 contained in the multilayer film FL1 are sequentially removed.

[0110] This patterning exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3. In addition, the multilayer film FL1 and the sealing layer SE11 are removed in the peripheral region SA.

[0111] Subsequently, the resist RS is removed. This forms the display element DE1 on the sub-pixel SP1. In the illustrated example, the laminated film FL1 stacked on the partition wall 6 is removed during the process from patterning the laminated film FL1 to removing the resist RS. As a result, a cavity GP is formed between the sealing layer SE11 and the partition wall 6.

[0112] Next, as shown in Figure 6E, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL2 is formed on the lower electrode LE2. The multilayer film FL2 has an organic layer OR2 including an emissive layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE12 is formed on the multilayer film FL2. Then, a resist is formed on the sealing layer SE12. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE12 and the multilayer film FL2 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0113] As a result, the display element DE2 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed. Also, in the illustrated example, the laminated film FL2 on top of the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE12 and the partition wall 6.

[0114] Next, as shown in Figure 6F, the display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL3 is formed on the lower electrode LE3. The multilayer film FL3 has an organic layer OR3 including an emissive layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE13 is formed on the multilayer film FL3. Then, a resist is formed on the sealing layer SE13. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE13 and the multilayer film FL3 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0115] As a result, the display element DE3 is formed on the sub-pixel SP3. Also, in the illustrated example, the laminated film FL3 on the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE13 and the partition wall 6.

[0116] In the above manufacturing process, we assumed that the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0117] Next, we will explain focusing on the surrounding region SA. In Figures 6G to 6I, elements below the organic insulating layer 12 have been omitted.

[0118] In the example shown in Figure 6G, the peripheral region SA contains a multilayer film MF consisting of a laminated film FL3 for forming the display element DE3 and a sealing layer SE13. During the patterning of the laminated film FL3 and sealing layer SE13 in the process of forming the display element DE3, at least a portion of the laminated film FL3 on the partition wall 6B is removed. As a result, a cavity GP is formed between the partition wall 6B and the sealing layer SE13. However, the laminated film FL3 on the partition wall 6A, and the laminated film FL3 between partition walls 6A and 6B, are covered with the sealing layer SE13.

[0119] Next, as shown in Figure 6H, an organic insulating material is applied and cured to form a resin layer RS1. At this time, the organic insulating material applied on the sealing layer SE13 remains on the sealing layer SE13 due to its surface tension. Therefore, in this embodiment, it is not necessary to provide multiple dam sections in the surrounding region SA to prevent the spreading of the resin layer RS1. Consequently, the width of the surrounding region SA, that is, the width from the edge of the organic insulating layer 12 to the edge of the substrate 10, can be reduced compared to the case where dam sections are provided to prevent the spreading of the resin layer RS1.

[0120] Furthermore, compared to the case where the resin layer RS1 fills the missing parts, the formation of undesirable depressions or steps caused by insufficient application of the organic insulating material is suppressed. The upper surface of the resin layer RS1 is convex in the surrounding region SA and is formed as a smooth surface with almost no local depressions.

[0121] Next, as shown in Figure 6I, an inorganic insulating material (e.g., silicon nitride) is deposited to form a sealing layer SE2. The sealing layer SE2 is formed beyond the edges E1 of the resin layer RS1 and E2 of the sealing layer SE1, covering the partition wall 6B, contacting the inorganic insulating layer 5, and sealing the resin layer RS1. In addition, near the edge E2, the cavity GP is sealed by the sealing layer SE2.

[0122] Subsequently, a metal layer is formed on the sealing layer SE2, and the detection electrode DT is formed by patterning this metal layer. When forming the detection electrode DT, if a recess is formed in the underlying resin layer RS1, there is a risk of short-circuiting of adjacent detection electrodes DT due to poor patterning of the metal layer formed in the recess.

[0123] In this embodiment, as described above, the resin layer RS1 is formed to have a smooth upper surface. Therefore, patterning defects in the metal layer are suppressed, and abnormal formation of the detection electrode DT is suppressed.

[0124] Subsequently, an organic insulating material is applied, and the resin layer RS2 is formed by curing the organic insulating material. At this time, as shown in Figure 5A, the spread of the resin layer RS2 is dammed by the dam sections DM1 and DM2, and fills the missing sections RP1 and RP2.

[0125] After the above steps, the DSP display device is completed.

[0126] Next, other configuration examples will be described. Note that for elements identical to those in the above configuration examples, the same reference numerals may be used, and detailed explanations may be omitted.

[0127] Figure 7A is a cross-sectional view showing another example of a display device DSP configuration along the CD line of the peripheral region SA shown in Figure 4A.

[0128] The configuration example shown in Figure 7A differs from the configuration example shown in Figure 5A in that the multilayer film MF is placed on top of the dam portion DM1, and the edge E3 of the resin layer RS2 is located directly above this multilayer film MF (or sealing layer SE1). In the illustrated example, one dam portion DM1 is placed in the peripheral region SA, and neither the dam portion DM2 shown in Figure 5A nor the gap RP2 between the dam portions DM1 and DM2 exists. Outside the dam portion DM1, the gap RP3 extends to the edge 10E of the substrate 10.

[0129] As explained with reference to Figure 4A, the dam section DM1 is formed to surround the display area DA and is spaced apart from the organic insulating layer 12. The dam section DM1 is placed on the insulating layer 113 and covered with the inorganic insulating layer 5. The partition walls 6C and 6D are placed above the dam section DM1 and on the inorganic insulating layer 5. Partition wall 6C is formed to surround the missing section RP1. Partition wall 6D is spaced apart from partition wall 6C and is formed to surround partition wall 6C. The cross-sectional shapes of partition walls 6C and 6D will be described later, but both are formed in an overhang shape similar to partition wall 6 described above.

[0130] The multilayer film MF is not provided in the gap RP1 between the organic insulating layer 12 and the dam section DM1. In other words, the multilayer film MF is divided into a portion located above the organic insulating layer 12 and a portion located above the dam section DM1. Above the dam section DM1, the multilayer film MF is located on partition walls 6C and 6D.

[0131] The resin layer RS1 is positioned above the organic insulating layer 12 and on top of the multilayer film MF. The edge E1 of the resin layer RS1 is located directly above the organic insulating layer 12 and also directly above the multilayer film MF. The resin layer RS1 is not located in the missing portions RP1 and RP3, nor is it located on the dam portion DM1.

[0132] The sealing layer SE2 covers the resin layer RS1 and, at the missing portion RP1, contacts the inorganic insulating layer 5, thereby sealing the resin layer RS1. Furthermore, the sealing layer SE2 is positioned above the dam portion DM1, on top of the multilayer film MF, and a portion of the multilayer film MF is exposed.

[0133] The resin layer RS2 is positioned on top of the sealing layer SE2 and fills the missing portion RP1. The resin layer RS2 is also positioned above the dam portion DM1 and is in contact with the multilayer film MF exposed from the sealing layer SE2. The edge E3 of the resin layer RS2 is located directly above the dam portion DM1.

[0134] Figure 7B is an enlarged cross-sectional view of the vicinity of edge E3 shown in Figure 7A. Note that in Figure 7B, elements below the organic insulating layer 12 have been omitted.

[0135] Each of the partition walls 6C and 6D, like partition wall 6 shown in Figure 3, comprises a lower section 61 and an upper section 62. The lower section 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5 and an axial layer 64 placed between the bottom layer 63 and the upper section 62. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Similarly, both ends of the upper section 62 protrude from the sides of the axial layer 64.

[0136] The multilayer film FL is divided into a portion located on partition wall 6C, a portion located on partition wall 6D, and a portion located on the inorganic insulating layer 5 between partition walls 6C and 6D.

[0137] The sealing layer SE1 covers the laminated film FL above the partition wall 6C and also covers the partition wall 6C. Furthermore, the sealing layer SE1 covers the laminated film FL between partition wall 6C and partition wall 6D. In addition, the sealing layer SE1 overlaps the laminated film FL above partition wall 6D.

[0138] The sealing layer SE2 is positioned above the partition wall 6C and on top of the sealing layer SE1. Furthermore, the sealing layer SE2 exposes the sealing layer SE1 between the partition wall 6C and the partition wall 6D. As shown in Figure 7A, the resin layer RS1 is not positioned on the dam section DM1 and is not interposed between the sealing layer SE1 and the edge section E3.

[0139] The resin layer RS2 is positioned above the partition wall 6C and on top of the sealing layer SE2, and also on top of the sealing layer SE1 that is exposed from the sealing layer SE2. Furthermore, the resin layer RS2 fills the space between partition wall 6C and partition wall 6D. Additionally, the resin layer RS2 is positioned above the sealing layer SE1, above partition wall 6D. The edge E3 of the resin layer RS2 is located directly above the sealing layer SE1. In the illustrated example, the edge E3 of the resin layer RS2 is located directly above partition wall 6D.

[0140] Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0141] Furthermore, the resin layer RS2 in the illustrated example configuration is formed by applying an organic insulating material, similar to the example configuration described above. At this time, the organic insulating material applied on the sealing layer SE1 directly above the dam portion DM1 remains on the sealing layer SE1 due to its surface tension. For this reason, in this embodiment, it is not necessary to provide multiple dam portions in the surrounding region SA to prevent the spreading of the resin layer RS2.

[0142] Figure 8 is a cross-sectional view showing another example of a display device DSP configuration along the CD line in the peripheral region SA shown in Figure 4A.

[0143] The configuration example shown in Figure 8 differs from the configuration example shown in Figure 7A in that the dam portion DM1 extends to the edge portion 10E of the substrate 10. In other words, the missing portion RP3 shown in Figure 7A does not exist.

[0144] The bulkhead 6E is positioned above the dam section DM1, on top of the inorganic insulating layer 5. The bulkhead 6E is spaced apart from the bulkhead 6D and is formed to surround the bulkhead 6D. The cross-sectional shape of the bulkhead 6D will not be described in detail, but it is formed in an overhang shape similar to that of the bulkhead 6 described above.

[0145] Above the dam section DM1, the multilayer membrane MF is divided into a portion located above bulkheads 6C and 6D, and a portion located above bulkhead 6E.

[0146] The edge E1 of the resin layer RS1 is located directly above the organic insulating layer 12 and also directly above the multilayer film MF.

[0147] The sealing layer SE2 contacts the inorganic insulating layer 5 at the missing portion RP1, sealing the resin layer RS1. Furthermore, above the dam portion DM1, the sealing layer SE2 exposes a portion of the multilayer film MF located on partition walls 6C and 6D. Additionally, the sealing layer SE2 covers the multilayer film MF located on partition wall 6E.

[0148] The resin layer RS2 is positioned on top of the sealing layer SE2 and fills the missing portion RP1. Above the dam portion DM1, the resin layer RS2 is in contact with the multilayer film MF exposed from the sealing layer SE2. The edge E3 of the resin layer RS2 is located directly above the dam portion DM1 and also directly above the multilayer film MF exposed from the sealing layer SE2.

[0149] Even in this configuration example, the same effects as those described with reference to Figures 7A and 7B can be obtained.

[0150] As shown in the diagram, a DSP display device in which the dam portion DM1 extends to the edge portion 10E of the substrate 10 can be removed from the motherboard by scribing and cutting the motherboard.

[0151] Figure 9 is a cross-sectional view showing another example of a display device DSP configuration along the CD line in the peripheral region SA shown in Figure 4A.

[0152] The configuration example shown in Figure 9 differs from the configuration example shown in Figure 7A in that there is no organic insulating layer 12 between the edge E3 of the resin layer RS2 and the substrate 10. In other words, the missing portion RP1 shown in Figure 7A extends to the edge 10E of the substrate 10, and the dam portion DM1 and the missing portion RP3 do not exist.

[0153] In the missing portion RP1, the inorganic insulating layer 5 covers the insulating layer 113. The partitions 6C and 6D are located on top of the inorganic insulating layer 5. The multilayer film MF is divided into a portion located above the organic insulating layer 12 and a portion located in the missing portion RP1. In the missing portion RP1, the multilayer film MF is located on top of the partitions 6C and 6D.

[0154] The edge E1 of the resin layer RS1 is located directly above the organic insulating layer 12 and also directly above the multilayer film MF.

[0155] The sealing layer SE2 contacts the inorganic insulating layer 5 at the missing portion RP1, sealing the resin layer RS1. Furthermore, the sealing layer SE2 is positioned on top of the multilayer film MF at the missing portion RP1, and a portion of the multilayer film MF is exposed.

[0156] The resin layer RS2 is positioned on top of the sealing layer SE2 and is in contact with the multilayer film MF exposed from the sealing layer SE2 at the missing portion RP1. The edge E3 of the resin layer RS2 is located at the missing portion RP1 and is also located directly above the multilayer film MF exposed from the sealing layer SE2.

[0157] Even in this configuration example, the same effects as those described with reference to Figures 7A and 7B can be obtained.

[0158] Figure 10A is a cross-sectional view showing another example of a display device DSP configuration along the CD line in the peripheral region SA shown in Figure 4A.

[0159] The configuration example shown in Figure 10A differs from the configuration example shown in Figure 5A in that a sealing layer SE3 is placed between the multilayer film MF and the resin layer RS1. The sealing layer SE3 covers the multilayer film MF, covers the partition wall 6B on the outside of the edge E2, and is in contact with the inorganic insulating layer 5. The sealing layer SE2 covers the resin layer RS1, is in contact with the sealing layer SE3 on the outside of the edge E1, and seals the resin layer RS1.

[0160] Figure 10B is an enlarged cross-sectional view of the vicinity of edges E1 and E2 shown in Figure 10A. Note that in Figure 10B, elements below the organic insulating layer 12 have been omitted.

[0161] The multilayer film FL is divided into a portion located on partition wall 6A, a portion located on partition wall 6B, and a portion located on the inorganic insulating layer 5 between partition walls 6A and 6B.

[0162] The sealing layer SE1 covers the laminated film FL above the partition wall 6A and also covers the partition wall 6A. Furthermore, the sealing layer SE1 covers the laminated film FL between partition walls 6A and 6B. Also, the sealing layer SE1 overlaps the laminated film FL above partition wall 6B. The edge E2 of the sealing layer SE1 is located directly above partition wall 6B.

[0163] The sealing layer SE3 covers the sealing layer SE1. Furthermore, the sealing layer SE3 contacts the partition wall 6B outside the edge E2 and covers the outside of the partition wall 6B. Such a sealing layer SE3 is formed of an inorganic insulating material, and in one example, it is formed of silicon nitride.

[0164] The resin layer RS1 is positioned on top of the sealing layer SE1 and fills the space between partition walls 6A and 6B. The edge E1 of the resin layer RS1 is located directly above partition wall 6B and also directly above the sealing layer SE1.

[0165] The sealing layer SE2 covers the resin layer RS1. Furthermore, the sealing layer SE2 is in contact with the sealing layer SE3 outside the edge E1.

[0166] Even in this configuration example, the same effects as in the above configuration example can be obtained. Furthermore, even if the laminated film FL on the partition wall 6B disappears, the cavity formed between the partition wall 6B and the sealing layer SE1 can be sealed by the sealing layer SE3, thereby suppressing moisture intrusion into the cavity.

[0167] Figure 11A is a cross-sectional view showing another example of a display device DSP configuration along the CD line in the peripheral region SA shown in Figure 4A.

[0168] The configuration example shown in Figure 11A differs from the configuration example shown in Figure 5A in that the partition wall 6B above the organic insulating layer 12 is absent, and the edge E2 of the multilayer film MF is located between the partition wall 6A and the missing portion RP1. The edge E1 of the resin layer RS1 is located directly above the organic insulating layer 12 and also directly above the multilayer film MF. The sealing layer SE2 covers the resin layer RS1, contacts the inorganic insulating layer 5 outside the edge E2, and seals the resin layer RS1.

[0169] Figure 11B is an enlarged cross-sectional view of the vicinity of edges E1 and E2 shown in Figure 11A. Note that in Figure 11B, elements below the organic insulating layer 12 have been omitted.

[0170] The multilayer film FL is divided into a portion located on the partition wall 6A and a portion located on the inorganic insulating layer 5 outside the partition wall 6A.

[0171] The sealing layer SE1 covers the laminated film FL above the partition wall 6A and also covers the partition wall 6A. Furthermore, the sealing layer SE1 covers the laminated film FL outside the partition wall 6A. The edge E2 of the sealing layer SE1 is located directly above the inorganic insulating layer 5 outside the partition wall 6A.

[0172] The resin layer RS1 is positioned on top of the sealing layer SE1. The edge E1 of the resin layer RS1 is located directly above the sealing layer SE1 on the outside of the partition wall 6A.

[0173] The sealing layer SE2 covers the resin layer RS1. Furthermore, the sealing layer SE2 is in contact with the sealing layer SE1 outside the edge E1 and in contact with the inorganic insulating layer 5 outside the edge E2.

[0174] Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0175] Figure 12A is a cross-sectional view showing another example of a display device DSP configuration along the CD line in the peripheral region SA shown in Figure 4A.

[0176] The configuration example shown in Figure 12A differs from the configuration example shown in Figure 11A in that a partition wall 6B exists above the organic insulating layer 12, and the edge E2 of the multilayer film MF is located between partition walls 6A and 6B. The edge E1 of the resin layer RS1 is located directly above the organic insulating layer 12 and also directly above the multilayer film MF. The sealing layer SE2 covers the resin layer RS1, contacts the inorganic insulating layer 5 outside the edge E2, and seals the resin layer RS1. The sealing layer SE2 also covers the partition wall 6B.

[0177] Figure 12B is an enlarged cross-sectional view of the vicinity of edges E1 and E2 shown in Figure 12A. Note that in Figure 12B, elements below the organic insulating layer 12 have been omitted.

[0178] The multilayer film FL is divided into a portion located on partition wall 6A and a portion located on the inorganic insulating layer 5 between partition wall 6A and partition wall 6B.

[0179] The sealing layer SE1 covers the laminated film FL above the partition wall 6A and also covers the partition wall 6A. Furthermore, the sealing layer SE1 covers the laminated film FL between partition walls 6A and 6B. The edge E2 of the sealing layer SE1 is located directly above the inorganic insulating layer 5 between partition walls 6A and 6B.

[0180] The resin layer RS1 is positioned on top of the sealing layer SE1. The edge E1 of the resin layer RS1 is located directly above the sealing layer SE1 between partition walls 6A and 6B. Partition wall 6B is exposed from all of the laminated film FL, the sealing layer SE1, and the resin layer RS1.

[0181] The sealing layer SE2 covers the resin layer RS1. Furthermore, the sealing layer SE2 is in contact with the sealing layer SE1 outside the edge E1 and in contact with the inorganic insulating layer 5 outside the edge E2. In addition, the sealing layer SE2 covers the partition wall 6B.

[0182] Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0183] In the above embodiment, for example, sealing layers SE1, SE11, SE12, and SE13 correspond to the first sealing layer, resin layer RS1 corresponds to the first resin layer, sealing layer SE2 corresponds to the second sealing layer, resin layer RS2 corresponds to the second resin layer, and sealing layer SE3 corresponds to the third sealing layer. In the partition wall 6, the lower part 61 corresponds to the first lower part, and the upper part 62 corresponds to the first upper part. The edge E1 of resin layer RS1 corresponds to the first edge of the first resin layer, the edge E2 of sealing layer SE1 (or the edge of the multilayer film MF) corresponds to the second edge of the first sealing layer, and the edge E3 of resin layer RS2 corresponds to the third edge of the second resin layer. Partition wall 6A corresponds to the first partition wall, and partition wall 6B corresponds to the second partition wall.

[0184] As described above, according to this embodiment, it is possible to provide a display device that can suppress a decrease in reliability.

[0185] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0186] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0187] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0188] DSP...Display device DA...Display area SA...Peripheral area DE1, DE2, DE3... Display elements LE1, LE2, LE3...lower electrode OR1, OR2, OR3…Organic layer UE1, UE2, UE3...upper electrode SE11, SE12, SE13, SE1, SE2, SE3...Sealing layer RS1, RS2…Resin layer 5…Inorganic insulating layer 12…Organic insulating layer RP1, RP2, RP3... Missing parts 6, 6A, 6B, 6C, 6D, 6E...Bulkhead 61...Lower 62...Upper FL1, FL2, FL3… Multilayer film MF…Multilayer film DT...Detection electrode

Claims

1. circuit board and An organic insulating layer is arranged above the substrate, extending to a display area for displaying an image, and to a peripheral area outside the display area. An inorganic insulating layer is arranged across the display area and the surrounding area and covers the organic insulating layer, In the display area, a lower electrode is placed on the organic insulating layer and has a peripheral portion covered by the inorganic insulating layer, Displaced on the aforementioned lower electrode, an organic layer including a light-emitting layer, An upper electrode placed on the aforementioned organic layer, A partition wall formed in an overhang shape comprises a first lower portion disposed on the inorganic insulating layer and having conductivity, which contacts the upper electrode, and a first upper portion disposed on the first lower portion. A laminated film comprising a thin film arranged in the peripheral region and formed of the same material as the organic layer and the upper electrode, A first sealing layer formed of an inorganic insulating material and disposed on the laminated film, A first resin layer disposed above the first sealing layer, Equipped with, The first edge of the first resin layer is located directly above the first sealing layer. Display device.

2. The second edge of the first sealing layer is located directly above the organic insulating layer. The display device according to claim 1.

3. In the aforementioned peripheral region, the missing portion that penetrates the organic insulating layer surrounds the display area. The display device according to claim 2.

4. The missing portion extends to the edge of the substrate. The display device according to claim 3.

5. The second edge is located between the display area and the missing portion. The display device according to claim 3.

6. Furthermore, in the aforementioned peripheral region, A first partition wall surrounds the aforementioned display area and is electrically connected to the aforementioned partition wall, The structure comprises a second partition wall that surrounds the first partition wall and is spaced apart from the first partition wall, Each of the first and second partitions is formed in an overhanging manner. The second edge is located directly above the second partition wall. The display device according to claim 5.

7. Furthermore, it includes a second sealing layer formed of an inorganic insulating material, which covers the first resin layer and covers the second partition on the outside of the second edge. The display device according to claim 6.

8. The first resin layer is filled between the first partition and the second partition. The display device according to claim 6.

9. Furthermore, the surrounding area includes a first partition wall that surrounds the display area and is electrically connected to the partition wall, The first partition wall is formed in an overhanging manner, The second edge is located between the first partition and the missing portion. The display device according to claim 5.

10. Furthermore, it includes a second sealing layer formed of an inorganic insulating material, which covers the first resin layer and contacts the inorganic insulating layer on the outside of the second edge. The display device according to claim 9.

11. Furthermore, the surrounding region includes a second partition wall that is spaced apart from the first partition wall, surrounds the first partition wall, and is positioned between the first partition wall and the missing portion. The second partition wall is formed in an overhanging manner, The second edge is located between the first partition and the second partition. The display device according to claim 9.

12. Furthermore, it comprises a second sealing layer formed of an inorganic insulating material, covering the first resin layer, contacting the inorganic insulating layer on the outside of the second edge, and further covering the second partition wall. The display device according to claim 11.

13. The outer edge of the first partition wall facing the second partition wall, and at least one of the second partition walls, are formed continuously without any breaks. The display device according to claim 6 or 11.

14. Furthermore, a second sealing layer formed of an inorganic insulating material and covering the first resin layer, It comprises a third sealing layer formed of an inorganic insulating material, disposed between the first sealing layer and the first resin layer, and covering the first sealing layer, The second sealing layer is in contact with the third sealing layer on the outside of the first edge. The display device according to claim 1.

15. circuit board and An organic insulating layer is arranged above the substrate, extending to a display area for displaying an image, and to a peripheral area outside the display area. An inorganic insulating layer is arranged across the display area and the surrounding area and covers the organic insulating layer, In the display area, a lower electrode is placed on the organic insulating layer and has a peripheral portion covered by the inorganic insulating layer, Displaced on the aforementioned lower electrode, an organic layer including a light-emitting layer, An upper electrode placed on the aforementioned organic layer, A partition wall formed in an overhang shape comprises a first lower portion disposed on the inorganic insulating layer and having conductivity, which contacts the upper electrode, and a first upper portion disposed on the first lower portion. A laminated film comprising a thin film arranged in the peripheral region and formed of the same material as the organic layer and the upper electrode, A first sealing layer formed of an inorganic insulating material and disposed on the laminated film, A first resin layer disposed above the first sealing layer, A second sealing layer covering the first resin layer, A second resin layer disposed on the second sealing layer, Equipped with, The third edge of the second resin layer is located directly above the first sealing layer. Display device.

16. The first resin layer is not interposed between the third edge and the first sealing layer. The display device according to claim 15.

17. Furthermore, it includes a dam section that surrounds the display area and is spaced apart from the organic insulating layer, The third edge is located directly above the dam section. The display device according to claim 16.

18. Outside the dam section, the missing portion that penetrates the organic insulating layer extends to the edge of the substrate. The display device according to claim 17.

19. The dam portion extends to the edge of the substrate. The display device according to claim 17.

20. The organic insulating layer is not interposed between the third edge and the substrate. The display device according to claim 16.

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