Plasma processing apparatus and etching method

Abstract

We provide technology to reduce residue. [Solution] The plasma processing apparatus comprises a chamber, a substrate support section, a gas supply section, an inductively coupled plasma source, a voltage pulse source, a high-frequency power supply, and a control section. The chamber has a dielectric window at the top, and an antenna is positioned above the dielectric window. The substrate support section is positioned inside the chamber and supports the substrate. The control section is configured to control the process when etching the substrate by supplying processing gas from the gas supply section into the chamber, supplying a first high-frequency power from the inductively coupled plasma source to the antenna to plasmaize the processing gas in the chamber, supplying a voltage pulse from the voltage pulse source to the substrate support section, and supplying a second high-frequency power from the high-frequency power supply superimposed on the voltage pulse.

Description

[Technical Field]

[0001] This disclosure relates to a plasma processing apparatus and an etching method. [Background technology]

[0002] Patent Document 1 below describes a first RF generation unit configured to generate a first RF pulse signal including a plurality of pulse cycles, each of the plurality of pulse cycles including a first period, a second period and a third period, the first RF pulse signal having a first power level in the first period, a second power level in the second period and a third power level in the third period, the first period being 30 μs or less, and a second RF generation unit configured to generate a second RF pulse signal including the plurality of pulse cycles, the second R A plasma processing apparatus is disclosed, comprising: a second RF generation unit, the frequency of which of the F pulse signals is lower than the frequency of the first RF pulse signal, and the second RF pulse signal has a fourth power level in the first period and a fifth power level in at least one of the second and third periods; and a third RF generation unit, coupled to the second matching circuit and configured to generate a third RF pulse signal including the plurality of pulse cycles, the frequency of which of the third RF pulse signals is lower than the frequency of the second RF pulse signal, and the third RF pulse signal has a sixth power level in the second period and a seventh power level in at least one of the first and third periods. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-048032 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] This disclosure provides a technology for reducing residue. [Means for solving the problem]

[0005] A plasma processing apparatus according to one aspect of the present disclosure comprises a chamber, a substrate support, a gas supply unit, an inductively coupled plasma source, a voltage pulse source, a high-frequency power supply, and a control unit. The substrate support unit is located inside the chamber and supports the substrate. The chamber has a dielectric window at its top, and an antenna is located above the dielectric window. The gas supply unit is configured to supply a processing gas into the chamber. The inductively coupled plasma source is configured to supply a first high-frequency power to the antenna to plasmaize the processing gas in the chamber. The voltage pulse source is configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support unit. The high-frequency power supply is configured to supply a second high-frequency power to the substrate support unit. The control unit is configured to control the process when etching the substrate by supplying a processing gas from the gas supply unit into the chamber, supplying a first high-frequency power from the inductively coupled plasma source to plasmaize the processing gas in the chamber, supplying a voltage pulse from the voltage pulse source to the substrate support unit, and supplying a second high-frequency power from the high-frequency power supply superimposed on the voltage pulse. [Effects of the Invention]

[0006] According to this disclosure, the amount of residue can be reduced. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a diagram illustrating an example configuration of an inductively coupled plasma processing apparatus. [Figure 2A] Figure 2A shows an example of etching of the substrate W according to the first embodiment. [Figure 2B] Figure 2B shows an example of etching of the substrate W according to the first embodiment. [Figure 3A]Figure 3A shows an example of etching of the substrate W according to the first embodiment. [Figure 3B] Figure 3B shows an example of etching of the substrate W according to the first embodiment. [Figure 4A] Figure 4A shows an example of the change in the potential of the substrate W in the etching method of the first reference example. [Figure 4B] Figure 4B schematically shows the movement of ions and radicals in the plasma during the etching method of the first reference example. [Figure 4C] Figure 4C shows an example of the ion energy distribution in the etching method of the first reference example. [Figure 5A] Figure 5A shows an example of the change in the potential of the substrate W in the etching method of the second reference example. [Figure 5B] Figure 5B schematically shows the movement of ions and radicals in the plasma during the etching method of the second reference example. [Figure 5C] Figure 5C shows an example of the ion energy distribution in the etching method of the second reference example. [Figure 6] Figure 6 shows an example of residue remaining on the etched substrate according to the first embodiment. [Figure 7A] Figure 7A shows an example of the change in the potential of the substrate W in the etching method of the first embodiment. [Figure 7B] Figure 7B shows an example of the ion energy distribution in the etching method of the first embodiment. [Figure 8A] Figure 8A is a diagram illustrating the processing conditions for the etching method of the first reference example during the first verification. [Figure 8B] Figure 8B is a diagram illustrating the processing conditions of the etching method of the first embodiment during the first verification. [Figure 9A] Figure 9A is a diagram illustrating the processing conditions of the etching method of the first embodiment during the second verification. [Figure 9B] Figure 9B is a diagram illustrating the processing conditions for the etching method of the first embodiment during the second verification. [Figure 10A] FIG. 10A is a diagram for explaining the processing conditions of the etching method of the first embodiment at the time of the third verification. [Figure 10B] FIG. 10B is a diagram for explaining the processing conditions of the etching method of the first embodiment at the time of the third verification. [Figure 11] FIG. 11 is a flowchart showing an example of the processing sequence of the etching process according to the first embodiment. [Figure 12A] FIG. 12A is a diagram showing an example of the change in the potential of the substrate W in the etching method of the second embodiment. [Figure 12B] FIG. 12B is a diagram showing an example of the energy distribution of ions in the etching method of the second embodiment. [Figure 13A] FIG. 13A is a diagram for explaining the change in the potential of the substrate W when the amplitude of the bias DC signal is changed. [Figure 13B] FIG. 13B is a diagram for explaining the change in the energy distribution of ions when the amplitude of the bias DC signal is changed. [Figure 14A] FIG. 14A is a diagram for explaining the change in the potential of the substrate W when the on-period of the bias DC signal is changed. [Figure 14B] FIG. 14B is a diagram for explaining the change in the energy distribution of ions when the on-period of the bias DC signal is changed. [Figure 15A] FIG. 15A is a diagram for explaining the change in the potential of the substrate W when the amplitude of the bias RF signal is changed. [Figure 15B] FIG. 15B is a diagram for explaining the change in the energy distribution of ions when the amplitude of the bias RF signal is changed. [Figure 16A] FIG. 16A is a diagram for explaining the change in the potential of the substrate W when the off-period of the bias DC signal is changed. [Figure 16B] FIG. 16B is a diagram for explaining the change in the energy distribution of ions when the off-period of the bias DC signal is changed. [Figure 17] FIG. 17 is a diagram for explaining the change in the potential of the substrate W when the superimposing period for superimposing the bias RF signal is changed. [Figure 18] Figure 18 illustrates the change in the potential of the substrate W when the superposition period of the bias RF signal is changed. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the plasma processing apparatus and etching method disclosed in this application will be described in detail with reference to the drawings. However, these embodiments do not limit the disclosed plasma processing apparatus and etching method.

[0009] A plasma processing apparatus places a substrate on a substrate support unit located within a chamber, generates plasma within the chamber, and performs plasma processing such as etching. High vertical processing performance is required in the manufacturing of semiconductor devices. Therefore, an etching method is known in which a pulsed rectangular wave DC voltage is applied to the substrate support unit to etch the substrate using a plasma processing apparatus. By applying a rectangular wave DC voltage to the substrate support unit when etching the substrate, the verticality of the ions can be improved, and high vertical processing performance can be obtained.

[0010] However, improving the verticality of the ions can sometimes leave residue in the corners of the etched bottom. Therefore, techniques to reduce this residue are highly anticipated.

[0011] [First Embodiment] [Device configuration] An example of the plasma processing apparatus of this disclosure will be described below. In the embodiments described below, the plasma processing apparatus of this disclosure will be described as a plasma processing system with a system configuration.

[0012] The following describes an example of a plasma processing system configuration. Figure 1 is a diagram illustrating an example of an inductively coupled plasma processing system configuration.

[0013] The plasma processing system includes an inductively coupled plasma processing apparatus 1 and a control unit 2. The inductively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing chamber 10 corresponds to the chamber of this disclosure. The plasma processing chamber 10 includes a dielectric window. The plasma processing apparatus 1 also includes a substrate support unit 11, a gas introduction unit, and an antenna 14. The substrate support unit 11 is located inside the plasma processing chamber 10. The antenna 14 is located on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, the side wall 102 of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s, and at least one gas outlet for discharging gas from the plasma processing space. The plasma processing chamber 10 is grounded.

[0014] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a bias electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b placed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may also have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode, which will be coupled to the RF (Radio Frequency) power supply 31 and / or DC (Direct Current) power supply 32 described later, may be placed within the ceramic member 1111a. In this case, at least one RF / DC electrode will function as a bias electrode. Note that the conductive member of the base 1110 and at least one RF / DC electrode may function as multiple bias electrodes. Also, the electrostatic electrode 1111b may function as a bias electrode. Therefore, the substrate support portion 11 includes at least one bias electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0017] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid, such as brine or gas, flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0018] The gas introduction section is configured to introduce at least one processing gas from the gas supply section 20 into the plasma processing space 10s. In one embodiment, the gas introduction section includes a Center Gas Injector (CGI) 13. The Center Gas Injector 13 is located above the substrate support section 11 and is attached to a central opening formed in the dielectric window 101. The Center Gas Injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas inlet 13c. The processing gas supplied to the gas supply port 13a passes through the gas flow path 13b and is introduced into the plasma processing space 10s from the gas inlet 13c. In addition to or instead of the Center Gas Injector 13, the gas introduction section may also include one or more Side Gas Injectors (SGIs) attached to one or more openings formed in the side wall 102.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the gas inlet from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include one or more flow modulation devices that modulate or pulse the flow rate of at least one processing gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one bias electrode and antenna 14. This causes plasma to be formed from at least one processing gas supplied to the plasma processing space 10s. Thus, the RF power supply 31 can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber 10. Furthermore, by supplying a bias RF signal to at least one bias electrode, a bias potential is generated on the substrate W, and ions in the formed plasma can be drawn into the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is coupled to the antenna 14 and configured to generate a source RF signal (source RF power) for plasma generation via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to the antenna 14. The first RF generation unit 31a corresponds to the first high-frequency power supply of this disclosure. The source RF signal also corresponds to the first high-frequency power of this disclosure.

[0022] The second RF generation unit 31b is configured to be coupled to at least one bias electrode via at least one impedance matching circuit and to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal is preferably in the range of 1 MHz to 100 MHz, and more preferably in the range of 13 MHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. One or more generated bias RF signals are supplied to at least one bias electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed. The second RF generation unit 31b corresponds to the second high-frequency power supply of the present disclosure. The bias RF signal corresponds to the second high-frequency power of the present disclosure.

[0023] Furthermore, the power supply 30 may include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a bias DC generation unit 32a. In one embodiment, the bias DC generation unit 32a is connected to at least one bias electrode and configured to generate a bias DC signal. The generated bias DC signal is applied to at least one bias electrode.

[0024] In various embodiments, the bias DC signal may be pulsed. In this case, a sequence of voltage pulses is applied to at least one bias electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or a combination thereof pulse waveform.

[0025] The bias DC generation unit 32a is configured to supply a bias DC signal obtained by pulsed DC voltage. For example, the bias DC generation unit 32a is configured to supply a bias DC signal obtained by periodically switching a negative polarity DC voltage on and off. In one embodiment, the bias DC generation unit 32a is configured to allow the application of a DC voltage of a negative value. By switching the application of the DC voltage on and off at a predetermined period, the bias DC generation unit 32a applies a voltage pulse of a predetermined frequency to the bias electrode of the base 1110 as a bias DC signal. The frequency of the bias DC signal is preferably in the range of 100kHz to 1200kHz, and more preferably in the range of 400Hz to 800Hz. The bias DC generation unit 32a is configured to allow the duty cycle of the bias DC signal to be changed by changing the ratio of the on and off periods during one cycle. The bias DC generation unit 32a corresponds to the voltage pulse source of this disclosure. The bias DC signal also corresponds to the voltage pulse of this disclosure.

[0026] The antenna 14 includes one or more coils. In one embodiment, the antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply 31 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generation unit may be connected to both the outer coil and the inner coil, or separate RF generation units may be connected to the outer coil and the inner coil separately.

[0027] During plasma processing, the plasma processing apparatus 1 supplies a source RF signal for plasma generation from the first RF generation unit 31a to the antenna 14. The plasma processing apparatus 1 also supplies a pulsed bias DC signal from the bias DC generation unit 32a to the lower electrode of the base 1110 during plasma processing. Furthermore, the plasma processing apparatus 1 supplies a bias RF signal from the second RF generation unit 31b, superimposed on the bias DC signal during plasma processing.

[0028] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0029] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described herein. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or it may be obtained via a medium when needed. The obtained program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The memory unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).

[0030] [Plasma Processing Flow] Next, the process of performing plasma processing, such as plasma etching, on a substrate W using the plasma processing system according to the embodiment will be briefly described. The substrate W is transported into the plasma processing chamber 10 via an inlet / outlet (not shown) by a transport mechanism such as a transport arm and placed on the central region 111a of the substrate support section 11. The exhaust system 40 evacuates the plasma processing chamber 10 to a predetermined vacuum level.

[0031] When etching the substrate W, the control unit 2 controls the gas supply unit 20 and supplies processing gas from the gas supply unit 20 into the plasma processing chamber 10. For example, the storage unit 2a2 stores a plasma processing recipe for the substrate. The recipe registers the type of gas and flow rate to be used for etching. For example, the control unit 2 reads the recipe from the storage unit 2a2 and supplies the gas of the registered gas type and flow rate from the gas supply unit 20 into the plasma processing chamber 10.

[0032] The control unit 2 controls the first RF generation unit 31a and supplies a source RF signal from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10. For example, the power of the source RF signal is registered in the recipe. The control unit 2 supplies the source RF signal to the antenna 14 with the power registered in the recipe from the first RF generation unit 31a to generate a magnetic field in the plasma processing chamber 10, plasmaize the processing gas in the plasma processing chamber 10 and generate inductively coupled plasma.

[0033] The control unit 2 controls the bias DC generation unit 32a and supplies a bias DC signal from the bias DC generation unit 32a to the substrate support unit 11. The control unit 2 controls the duty cycle of the bias DC signal by controlling the bias DC generation unit 32a. For example, it is preferable for the control unit 2 to control the duty cycle of the bias DC signal to 10% to 80%, and more preferably to control the duty cycle to 10% to 20%. For example, the duty cycle of the bias DC signal is registered in the recipe. The control unit 2 reads the recipe from the storage unit 2a2 and supplies a bias DC signal with the duty cycle registered in the recipe from the bias DC generation unit 32a.

[0034] The control unit 2 controls the second RF generation unit 31b and supplies a bias RF signal from the second RF generation unit 31b to the substrate support unit 11, superimposed on the bias DC signal. For example, the power of the bias RF signal is registered in the recipe. For example, the control unit 2 reads the recipe from the storage unit 2a2 and supplies the bias RF signal from the second RF generation unit 31b with the power registered in the recipe.

[0035] Here, an example of etching of the substrate W according to the first embodiment will be described. Figures 2A, 2B, 3A, and 3B show an example of etching of the substrate W according to the first embodiment. Figure 2A shows the planar shape of the substrate W viewed from above before etching. Figure 2B shows the cross-sectional shape of the substrate W at the dashed line L1 in Figure 2A before etching. Figure 3A shows the planar shape of the substrate W viewed from above after etching. Figure 3B shows the cross-sectional shape of the substrate W at the dashed line L1 in Figure 3A after etching.

[0036] Before etching, a base layer 50 is formed on the substrate W, and a fin structure 51 having multiple fins 51a is formed on the base layer 50. Then, a gate material 52 is deposited on the fin structure 51 on the substrate W before etching, and a mask 53 is formed on the gate material 52. Note that the fin structure 51 is embedded in the gate material 52 and is therefore not shown in Figures 2A and 2B. The base layer 50 is a stop layer that suppresses etching to the lower layer and is formed of oxide (Ox), such as a silicon oxide film. The base layer 50 may be SiN, an organic film, or a metal film such as a tungsten film. The fin structure 51 is formed, for example, by covering the surface of a silicon layer with oxide. The multiple fins 51a of the fin structure 51 are formed in parallel in one direction. The gate material 52 is formed of polycrystalline silicon (polysilicon: Poly). The mask 53 is constructed, for example, by laminating an oxide layer 53b (Ox) on a SiN layer 53a. The mask 53 is formed with gaps arranged in parallel in a direction intersecting one direction.

[0037] Figures 3A and 3B show the substrate W after etching the gate material 52 to the underlying layer 50 using mask 53 as a mask. An example of the pressure conditions and processing gas for etching the substrate W is shown below. Note that in the following values, 1 sccm is approximately 1.69 × 10⁻⁶. -3 pa·m 3 The value is / s, and 1 mTorr is approximately 0.133 Pa.

[0038] • Pressure conditions Pressure inside plasma processing chamber 10: 50~100 mTorr • Processed gas Cl2 gas: 100-210 sccm HBr gas: 70-150 sccm O2 gas: 30-60 sccm Ar gas: 50-300 sccm

[0039] As a result of etching, as shown in Figures 3A and 3B, the gate material 52 retains a gate portion 52a directly beneath the mask 53, and this remaining gate portion 52a functions as a gate. On the substrate W, each rectangular portion 55 surrounded by the mask 53 and fins 51a reaches the underlying layer 50.

[0040] Next, we will describe an etching method that will serve as a reference example. Note that the differences from the etching method of the first embodiment will be explained below.

[0041] First, the etching method of the first reference example will be described. Conventionally, an etching method is known in which high-frequency power is applied as a bias to the substrate support portion 11 to etch the substrate W. For example, in the etching method of the first reference example, when etching the substrate W, a source RF signal is supplied from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10. Furthermore, in the etching method of the first reference example, a bias DC signal is not supplied from the bias DC generation unit 32a, but a bias RF signal is supplied from the second RF generation unit 31b to the lower electrode of the base 1110.

[0042] Figure 4A shows an example of the change in the potential of the substrate W in the etching method of the first reference example. When a bias RF signal, which is high-frequency power, is supplied to the lower electrode of the base 1110, the potential of the substrate W changes sinusoidally in accordance with the fluctuations of the bias RF signal.

[0043] Figure 4B schematically illustrates the movement of ions and radicals in the plasma during the etching method of the first reference example. In Figure 4B, the side to be etched, such as the substrate W, is shown as the Etch front. Ions and radicals in the plasma are attracted to the substrate W by its potential, and etch the substrate W. In the etching method of the first reference example, the potential of the substrate W changes sinusoidally, causing ions and radicals to scatter and widening the incident angle of ions and radicals incident on the substrate W. In addition, the etching method of the first reference example widens the energy distribution of ions and radicals incident on the substrate W.

[0044] Figure 4C shows an example of the ion energy distribution in the etching method of the first reference example. Figure 4C also shows an example of the results obtained for determining the ion energy distribution function (IEDF) of the etching method of the first reference example. The horizontal axis represents the ion energy [eV], with higher energy to the right. The vertical axis represents the number of ions, with higher ions at the top. Figure 4C also shows the threshold E, which is the minimum ion energy required to etch the gate material 52. th It is shown as the threshold E. th For example, this is 25 eV.

[0045] The etching method in the first reference example is such that the ion energy distribution is at threshold E th Therefore, although the gate material 52 can be etched, a peak occurs on the lower energy side of the energy distribution, and the energy range in which the peak occurs is wide. In the etching method of the first reference example, the energy distribution of ions incident on the substrate W is broad.

[0046] As a result, the etching method of the first reference example has poor vertical processing performance. For example, if the substrate W shown in Figures 2A, 2B, 3A, and 3B is etched using the etching method of the first reference example, the side walls of the gate portion 52a will also be etched, worsening the roughness of the side walls of the gate portion 52a.

[0047] Next, the etching method of the second reference example will be described. High vertical processing performance is required in the manufacturing of semiconductor devices. Therefore, an etching method is known in which a pulsed rectangular wave DC voltage is applied to the substrate support part 11 to etch the substrate. For example, in the etching method of the second reference example, when etching the substrate W, a source RF signal is supplied from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10. Furthermore, in the etching method of the second reference example, a bias DC signal, which is a pulsed negative polarity DC voltage, is supplied from the bias DC generation unit 32a to the lower electrode of the base 1110, without supplying a bias RF signal from the second RF generation unit 31b.

[0048] Figure 5A shows an example of the change in the potential of the substrate W in the etching method of the second reference example. A bias DC signal, which is a pulsed negative polarity DC voltage, is supplied to the lower electrode of the base 1110, so that the potential of the substrate W changes in a rectangular shape in accordance with the fluctuations of the bias DC signal.

[0049] Figure 5B schematically illustrates the movement of ions and radicals in the plasma during the etching method of the second reference example. In Figure 5B, the side to be etched, such as the substrate W, is shown as the Etch front. Ions and radicals in the plasma are attracted to the substrate W by its potential, and etch the substrate W. The etching method of the second reference example improves the perpendicularity of ions and radicals incident on the substrate W by changing the potential of the substrate W in a rectangular shape. In addition, the etching method of the second reference example results in a narrow energy distribution of ions and radicals incident on the substrate W, and a high energy peak.

[0050] Figure 5C shows an example of the ion energy distribution in the etching method of the second reference example. Figure 5C schematically shows the ion energy distribution function (IEDF) of the etching method of the second reference example. The horizontal axis represents the ion energy [eV], with higher energy to the right. The vertical axis represents the number of ions, with higher ions at the top. Figure 5C also shows the threshold ion energy E required for etching the gate material 52. th This indicates that.

[0051] In the etching method of the second reference example, peaks are produced on both the high-energy and low-energy sides. On the low-energy side, the ion energy is at the threshold E. th Therefore, it does not contribute to the etching of the gate material 52. On the high-energy side, the peak is high and the energy width in which the peak occurs is narrow. In other words, the etching method of the second reference example has an energy distribution with a sharp peak on the high-energy side. This improves the perpendicularity of ions and radicals incident on the substrate W.

[0052] The etching method of the second reference example can achieve high vertical processing performance due to the high perpendicularity of ions and radicals. For example, when etching the substrate W shown in Figures 2A, 2B, 3A, and 3B is performed using the etching method of the second reference example, the gate portion 52a can be etched into a vertical shape while suppressing the roughness of the side wall of the gate portion 52a.

[0053] However, in the etching method of the second reference example, due to the improved vertical processing performance of ions, residue of gate material 52 may remain in the corners of the etched bottom. Figure 6 shows an example of residue remaining on the etched substrate W according to the first embodiment. Figure 6 shows the planar shape of the substrate W viewed from above after etching. Residue 56 remains in each rectangular portion 55 of the substrate W after etching.

[0054] Therefore, in the etching method of the first embodiment, when etching the substrate W, a bias DC signal, which is a pulsed negative DC voltage, is supplied from the bias DC generation unit 32a to the lower electrode of the base 1110. In addition, in the etching method of the first embodiment, a bias RF signal is supplied from the second RF generation unit 31b, superimposed on the bias DC signal.

[0055] Figure 7A shows an example of the change in the potential of the substrate W in the etching method of the first embodiment. A bias DC signal and a bias RF signal, which are pulsed negative polarity DC voltages, are superimposed and supplied to the lower electrode of the base 1110. As a result, the potential of the substrate W changes in a rectangular shape in accordance with the fluctuations of the bias DC signal and oscillates in accordance with the bias RF signal.

[0056] Figure 7B shows an example of the ion energy distribution in the etching method of the first embodiment. Figure 7B schematically shows the ion energy distribution function (IEDF) of the etching method of the first embodiment. The horizontal axis represents the ion energy [eV], with higher energy to the right. The vertical axis represents the number of ions, with higher ions at the top. Figure 7B also shows the threshold ion energy E required for etching the gate material 52.th is shown.

[0057] In the etching method of the first embodiment, peaks occur on the high-energy side and the low-energy side, and the energy width at which the peaks occur is wide. In the etching method of the first embodiment, by generating a peak on the high-energy side, high vertical processing performance can be obtained. Also, in the etching method of the first embodiment, the low-energy side also has a threshold value E th or more, and by generating peaks over a wide width, the incident angle of the ions incident on the substrate W can be widened, and the residue 56 can be efficiently removed.

[0058] Next, an example of the verification result obtained by actually etching the substrate W to verify the amount of the residue 56 will be described.

[0059] In the verification, the substrate W was etched using the etching method of the first embodiment and the etching method of the first reference example. The etching method of the first embodiment was divided into two steps, a residue removal step 1 and a residue removal step 2, and the residue removal step 2 was sequentially performed after the residue removal step 1. Regarding the source RF signal, bias RF signal, and bias DC signal in the residue removal step 1 and the residue removal step 2, the common conditions during the verification are as follows.

[0060] (Common conditions for the etching method of the first embodiment) Conditions for the residue removal step 1 Source RF signal: frequency 27 MHz, power 300 W Bias RF signal: frequency 13 MHz, power 400 W Bias DC signal: frequency 400 kHz, -500 V, duty ratio 0 to 80% Conditions for the residue removal step 2 Source RF signal: frequency 27 MHz, power 500 W Bias RF signal: frequency 13 MHz, power 270 W Bias DC signal: frequency​​The duty cycle of the bias DC signal is the ratio of the ON period during one cycle of switching -500V on and off. In the etching method of the first embodiment, a residue removal step 2 is performed after a residue removal step 1, and the duty cycle of the bias DC signal is changed between residue removal step 1 and residue removal step 2.

[0062] First, the results of the first verification will be explained. In the first verification, the substrate W was etched using the etching method of the first reference example and the etching method of the first embodiment, and the amount of residue 56 on the substrate W was compared.

[0063] In the first verification, the source RF signal and bias RF signal for the etching method of the first reference example were set as follows.

[0064] (Conditions for the etching method in the first reference example) Source RF signal: Frequency 27MHz, Power 500W Bias RF signal: Frequency 13MHz, Power 270W

[0065] Furthermore, in the first verification, the duty cycle of the bias DC signal in the residue removal step 1 and residue removal step 2 of the etching method of the first embodiment was set as follows.

[0066] (Conditions for the etching method of the first embodiment) Conditions for residue removal step 1 Bias DC signal: Not applied (duty cycle 0%) Conditions for residue removal step 2 Bias DC signal: Frequency 400kHz, -500V, Duty cycle 80%

[0067] Figure 8A is a diagram illustrating the processing conditions of the etching method of the first reference example during the first verification. To facilitate comparison with the processing conditions of the etching method of the first embodiment shown in Figure 8B, Figure 8A shows the conditions of the source RF signal, bias RF signal, and bias DC signal of the etching method of the first reference example, divided into residue removal step 1 and residue removal step 2. In Figure 8A, the period during which the source RF signal and bias RF signal are supplied during etching is indicated by a diagonal line pattern, corresponding to one period of the bias DC signal with a frequency of 400 kHz. The etching method of the first reference example continuously supplies the source RF signal and bias RF signal during etching. Therefore, the source RF signal and bias RF signal are shown as always on, indicated by the diagonal line pattern during the period of one period of 400 kHz. The source RF signal and bias RF signal are supplied as continuous waves (CW). On the other hand, in the etching method of the first reference example, since no bias DC signal is applied in residue removal step 1 and residue removal step 2, the diagonal line pattern is not shown for the duration of one period of 400 kHz, and is always shown as "off".

[0068] Figure 8B is a diagram illustrating the processing conditions of the etching method of the first embodiment during the first verification. Figure 8A shows the conditions for the source RF signal, bias RF signal, and bias DC signal of the etching method of the first embodiment during the first verification, divided into residue removal step 1 and residue removal step 2. In Figure 8B, the conditions for the source RF signal, bias RF signal, and bias DC signal in residue removal step 1 are the same as in the first reference example. In residue removal step 1, the bias DC signal is not applied, and the source RF signal and bias RF signal are supplied. In residue removal step 2, the source RF signal, bias RF signal, and bias DC signal are supplied during etching. In residue removal step 2, the bias DC signal is supplied at 400 kHz with a duty cycle of 80%. In Figure 8B, the bias RF signal in residue removal step 2 is shown as being ON for 80% of the period of one cycle of 400 kHz, as shown by the diagonal pattern.

[0069] In the first verification, the amount of residue 56 on the substrate W in the etching method of the first reference example was 1.61 [nm], while the amount of residue 56 on the substrate W in the etching method of the first embodiment was 1.45 [nm]. From this, it can be concluded that the etching method of the first embodiment can reduce the amount of residue 56 compared to the etching method of the first reference example.

[0070] Next, the results of the second verification will be explained. In the second verification, the etching method of the first embodiment was performed with the same conditions for residue removal step 1 as in the first reference example, and the duty cycle of the bias DC signal in residue removal step 2 was set to 80% and 10%, respectively, and the amount of residue 56 on the substrate W was compared.

[0071] Figures 9A and 9B illustrate the processing conditions of the etching method of the first embodiment during the second verification. Figures 9A and 9B show the periods during which the source RF signal, bias RF signal, and bias DC signal are supplied for each period of one 400 kHz cycle during etching, divided into residue removal step 1 and residue removal step 2. In the second verification, the duty cycle of the bias DC signal during etching was set to 80% (Figure 9A) and 10% (Figure 9B), respectively, in residue removal step 2. The conditions for residue removal step 1 are the same as in the first reference example.

[0072] In the second verification, the amount of residue 56 on the substrate W was 2.21 nm when the duty cycle was 80% (Figure 9A), and 1.67 nm when the duty cycle was 10% (Figure 9B). This indicates that the etching method of the first embodiment can reduce the amount of residue 56 by lowering the duty cycle of the bias DC signal. The reason why the amount of residue 56 differs between the first and second verifications when the duty cycle is 80% is that the composition of the substrate W is slightly different in the first and second verifications.

[0073] Next, the results of the third verification will be explained. In the etching method of the first embodiment, the duty cycle of the bias DC signal in the residue removal step 2 was set to 10%, and etching of the substrate W was performed in both cases: when no bias DC signal was applied in the residue removal step 1 and when the duty cycle was set to 20%, and the amount of residue 56 was compared.

[0074] Figures 10A and 10B illustrate the processing conditions of the etching method of the first embodiment during the third verification. Figures 10A and 10B show the periods during which the source RF signal, bias RF signal, and bias DC signal are supplied for each period of one 400 kHz cycle during etching, divided into residue removal step 1 and residue removal step 2. In the third verification, the residue removal step 1 was set to either no bias DC signal applied during etching (Figure 10A) or 20% (Figure 10B), respectively. In both cases, the duty cycle for residue removal step 2 was set to 10%.

[0075] In the third verification, the amount of residue 56 on the substrate W was 1.67 nm when no bias DC signal was applied during etching in residue removal step 1 (Figure 10A), and 1.1 nm when the duty cycle was set to 20% (Figure 10B). From this, it can be seen that in the etching method of the first embodiment, applying a bias DC signal even in residue removal step 1 can reduce the amount of residue 56.

[0076] In the verification described above, the etching method of the first embodiment was divided into two steps, residue removal step 1 and residue removal step 2, and the substrate W was etched by performing residue removal step 2 after residue removal step 1. However, the etching method of the first embodiment is not limited to this. The etching method of the first embodiment may be divided into three or more steps. Alternatively, the etching method of the first embodiment may be etched without dividing the steps, while keeping the duty cycle of the bias DC signal constant during etching. The substrate W may be etched using only the steps of the etching method of the first embodiment, or it may be etched in combination with other etching methods.

[0077] [flowchart] This document describes the etching process, including the etching method described herein. Figure 11 is a flowchart showing an example of the etching process sequence according to the first embodiment. The etching process in Figure 11 is performed when etching of the substrate W is initiated.

[0078] The control unit 2 controls the gas supply unit 20 and starts supplying processing gas from the gas supply unit 20, supplying the processing gas into the plasma processing chamber 10 (step S10). The control unit 2 controls the first RF generation unit 31a and starts supplying a source RF signal from the first RF generation unit 31a, plasmaizing the processing gas in the plasma processing chamber 10 (step S11). The control unit 2 controls the bias DC generation unit 32a and starts supplying a bias DC signal from the bias DC generation unit 32a, supplying a bias DC signal to the substrate support unit 11 (step S12). The control unit 2 controls the second RF generation unit 31b and starts supplying a bias RF signal from the second RF generation unit 31b, supplying a bias RF signal superimposed on the bias DC signal to the substrate support unit 11 (step S13). Note that the order of steps S11 to S13 may be changed. Also, some or all of steps S11 to S13 may be executed as a single step.

[0079] The control unit 2 determines whether etching is complete or not (step S14). For example, if the control unit 2 meets the predetermined conditions for terminating etching, it determines that etching is complete. If etching is not complete (step S14: No), the process returns to step S14. If etching is complete (Step S14: Yes), the control unit 2 controls the supply of the processing gas, the source RF signal, the bias DC signal, and the bias RF signal, respectively, to stop the process.

[0080] As a result, the etching process according to the first embodiment can achieve high vertical processing performance. Furthermore, the etching method of the first embodiment can reduce the amount of residue 56.

[0081] Note that the etching process shown in Figure 11 is just one example and is not limited thereto. The etching process may include other steps. Also, the etching process may be performed as part of other processes. For example, if etching involves sequentially executing multiple processes to etch the substrate W down to the stop layer, the etching process shown in Figure 11 may be executed as the etching process that reaches the stop layer of the substrate W. For example, when etching the substrate W as shown in Figures 2A, 2B, 3A, and 3B, the control unit 2 may control the process to perform the etching process shown in Figure 11 when etching the bottom of the rectangular portion 55 that has reached the underlayer 50.

[0082] (Second Embodiment) Next, a second embodiment will be described. The configuration of the plasma processing system according to the second embodiment is the same as that of the plasma processing system according to the first embodiment shown in Figure 1, so a description will be omitted.

[0083] The bias DC generation unit 32a supplies a pulsed bias DC signal by periodically switching a negative polarity DC voltage on and off.

[0084] The second RF generation unit 31b does not supply a bias RF signal during the period when the bias DC signal is ON, and supplies a bias RF signal during the period when it is OFF.

[0085] In the etching method of the second embodiment, the bias RF signal is not superimposed during the ON period when the DC voltage of the bias DC signal is ON, but is superimposed and supplied during the OFF period when the DC voltage of the bias DC signal is OFF.

[0086] Figure 12A shows an example of the change in the potential of the substrate W in the etching method of the second embodiment. During the off period of the bias DC signal, the bias RF signal is superimposed on the bias DC signal and supplied to the lower electrode of the base 1110. As a result, the potential of the substrate W changes in a rectangular shape in accordance with the fluctuations of the bias DC signal and also oscillates in accordance with the bias RF signal during the off period.

[0087] Figure 12B shows an example of the ion energy distribution in the etching method of the second embodiment. Figure 12B schematically shows the ion energy distribution function (IEDF) of the etching method of the second embodiment. The horizontal axis represents the ion energy [eV], with higher energy to the right. The vertical axis represents the number of ions, with a higher number of ions at the top. Figure 12B also shows the threshold ion energy E required for etching the gate material 52. th This indicates that.

[0088] In the etching method of the second embodiment, peaks are generated on both the high-energy and low-energy sides.

[0089] In the etching method of the second embodiment, the bias RF signal is not superimposed during the ON period of the bias DC signal, resulting in a high peak on the high-energy side and a narrow energy width at which the peak occurs. In the etching method of the second embodiment, the high-energy peak has a sharp-angled energy distribution. As a result, the etching method of the second embodiment can achieve high vertical processing performance because the verticality of ions and radicals is increased.

[0090] Furthermore, in the etching method of the second embodiment, the bias RF signal is superimposed during the off period of the bias DC signal, so the threshold E is also at the low energy side. th As a result, a peak is generated over a wide range. This allows the etching method of the second embodiment to widen the incident angle of ions incident on the substrate W, and to efficiently remove the residue 56, thereby reducing the amount of residue 56.

[0091] Furthermore, the etching methods of the first and second embodiments described above allow for independent modification of the peak height and peak energy on the high-energy side, without changing the peak height and peak energy on the low-energy side, by changing the amplitude and on-duration of the bias DC signal.

[0092] Figure 13A illustrates the change in the potential of the substrate W when the amplitude of the bias DC signal is changed. Figure 13A shows the case in the etching method of the second embodiment in which the amplitude of the bias DC signal is changed by changing the negative voltage during the on-period of the bias DC signal. In Figure 13A, the change in the potential of the substrate W during the on-period is larger on the right side, as the negative voltage during the on-period of the bias DC signal is changed larger on the right side. Figure 13B illustrates the change in the energy distribution of ions when the amplitude of the bias DC signal is changed. Figure 13B shows the case in the etching method of the second embodiment in which the amplitude of the bias DC signal is changed by changing the negative voltage during the on-period of the bias DC signal. The energy of ions attracted to the substrate W changes depending on the potential of the substrate W. Therefore, by changing the amplitude of the bias DC signal, the energy range in which the high-energy peak occurs can be changed.

[0093] Figure 14A illustrates the change in substrate potential W when the on-duration of the bias DC signal is changed. Figure 14A shows the etching method of the second embodiment in which the on-duration of the bias DC signal is changed. In Figure 14A, the on-duration of the bias DC signal is changed to be longer on the right, and the period T1 during which the potential of the substrate W is negative is longer on the right. Figure 14B illustrates the change in ion energy distribution when the on-duration of the bias DC signal is changed. Figure 14B shows the etching method of the second embodiment in which the on-duration of the bias DC signal is changed. The longer the period during which the potential of the substrate W is negative, the more ions are attracted to the substrate W. Therefore, by changing the on-duration of the bias DC signal, the height of the high-energy peak can be changed.

[0094] Furthermore, the etching methods of the first and second embodiments described above allow for independent modification of the peak height and the energy range at which the peak occurs on the low-energy side, without changing the peak height and the energy at which the peak occurs on the high-energy side, by changing the amplitude of the bias RF signal and the off-period of the bias DC signal.

[0095] Figure 15A illustrates the change in the potential of the substrate W when the amplitude of the bias RF signal is changed. Figure 15A shows the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. In Figure 15A, the amplitude of the potential oscillation of the substrate W during the off period becomes larger on the right side as the amplitude of the bias RF signal is changed. Figure 15B illustrates the change in the energy distribution of ions when the amplitude of the bias RF signal is changed. Figure 15B shows the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. The energy of ions attracted to the substrate W changes depending on the potential of the substrate W. Therefore, by changing the amplitude of the bias RF signal, the energy range in which the low-energy peak occurs can be changed.

[0096] Figure 16A illustrates the change in substrate potential W when the off-period of the bias DC signal is changed. Figure 16A shows the case where the off-period of the bias DC signal is changed in the etching method of the second embodiment. In Figure 16A, the off-period of the bias DC signal is made longer on the right, and the period T2 during which the substrate W's potential is near 0 is made longer on the right. Figure 16B illustrates the change in ion energy distribution when the off-period of the bias DC signal is changed. Figure 16B shows the case where the off-period of the bias DC signal is changed in the etching method of the second embodiment. The longer the period T2 during which the substrate W's potential is near 0, the more ions are drawn into the substrate W during period T2. Therefore, by changing the off-period of the bias DC signal, the height of the low-energy peak can be changed.

[0097] The on and off periods of the bias DC signal can be changed by changing the period and duty cycle of the bias DC signal. Therefore, the etching methods of the first and second embodiments can adjust the energy distribution of ions incident on the substrate W by changing the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, the etching methods of the first and second embodiments can adjust the height of the low-energy and high-energy peaks and the energy range in which the peaks occur, respectively, by changing the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal.

[0098] The control unit 2 may control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal during etching of the substrate W. For example, in the etching of the substrate W shown in Figures 2A, 2B, 3A, and 3B, a hole surrounded by the mask 53 and the fins 51a is formed in the gate material 52. When forming a hole in the gate material 52 by etching, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the high-energy peak is high and the low-energy peak is low until the bottom of the hole reaches the underlying layer 50. Then, when the bottom of the hole reaches the underlying layer 50, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the low-energy peak is high and the energy range in which the low-energy peak occurs is wide. As a result, the plasma processing apparatus 1 can obtain high vertical processing performance. In addition, the plasma processing apparatus 1 can reduce the residue 56.

[0099] Furthermore, the etching methods of the first and second embodiments described above were explained using the case where the bias RF signal is superimposed over the entire off period of the bias DC signal as an example. However, the method is not limited to this. In the etching methods of the first and second embodiments described above, the bias RF signal may be superimposed over a part of the off period of the bias DC signal. Figure 17 is a diagram illustrating the change in the potential of the substrate W when the superposition period of the bias RF signal is changed. Figure 17 shows that in the etching method of the second embodiment, the height of the low-energy peak can be changed by changing the length of the superposition period T4 in which the bias RF signal is superimposed within the off period T3 of the bias DC signal.

[0100] Furthermore, the etching methods of the first and second embodiments described above were explained using the case where the bias RF signal is superimposed over the entire off period of the bias DC signal as an example. However, the method is not limited to this. In the etching methods of the first and second embodiments described above, if the rectangularity of the bias DC signal is poor, the bias RF signal may not be superimposed during the transient period in which the potential of the substrate W changes in response to the on / off change of the bias DC signal, but rather the bias RF signal may be superimposed after the transient period has elapsed. Figure 18 is a diagram illustrating the change in the potential of the substrate W when the superposition period T4 for superimposing the bias RF signal is changed. A transient period T5 occurs in the potential of the substrate W as it transitions to near 0 after the bias DC signal is turned off. In Figure 18, the bias RF signal is kept off from the time the bias DC signal is turned off until the period T5 has elapsed, and the bias RF signal is not superimposed on the bias DC signal. In the etching methods of the first and second embodiments, when the rectangularity of the bias DC signal is poor, the bias RF signal is not superimposed during the transient period, but rather after the transient period has elapsed, thereby generating separate peaks on the low-energy and high-energy sides.

[0101] Furthermore, the etching methods of the first and second embodiments described above were explained using the case of etching the substrate W shown in Figures 2A and 2B as an example. However, the method is not limited to this. The substrate W only needs to have the target film to be etched formed on the underlying layer. The target film to be etched can be, for example, an oxide film such as a silicon oxide film, or a metal film such as a SiN film, an organic film, or a tungsten film. The underlying layer can be any material that has an etching selectivity ratio with the target film to be etched. The etching methods of the first and second embodiments can be applied to any process of etching holes in the target film of the substrate W that reach the underlying layer.

[0102] (effect) As described above, the plasma processing system (plasma processing apparatus) according to the above embodiment comprises a plasma processing chamber 10, a substrate support section 11, a gas supply section 20, a first RF generation section 31a (first high-frequency power supply), a bias DC generation section 32a (voltage pulse source), a second RF generation section 31b (second high-frequency power supply), and a control section 2. The substrate support section 11 is located inside the plasma processing chamber 10 and supports the substrate W. The gas supply section 20 is configured to supply processing gas into the plasma processing chamber 10. The first RF generation section 31a is configured to supply a source RF signal (first high-frequency power) that plasmaizes the processing gas in the plasma processing chamber 10. The bias DC generation section 32a is configured to supply a bias DC signal (voltage pulse) to the substrate support section 11, which is a pulsed DC voltage. The second RF generation section 31b is configured to supply a bias RF signal (second high-frequency power) to the substrate support section 11. The control unit 2 is configured to control the plasma processing chamber 10 from the gas supply unit 20 when etching the substrate W, to supply a source RF signal from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10, to supply a bias DC signal from the bias DC generation unit 32a to the substrate support unit 11, and to supply a bias RF signal from the second RF generation unit 31b superimposed on the bias DC signal. As a result, the plasma processing system according to this embodiment can reduce residue.

[0103] Furthermore, the bias DC generation unit 32a is configured to periodically switch a negative polarity DC voltage on and off, and to change the duty cycle of the bias DC signal by changing the ratio of the on and off periods within one cycle. The control unit 2 is configured to control the duty cycle of the bias DC signal from 10% to 80%. As a result, the plasma processing system according to this embodiment can reduce residue.

[0104] Furthermore, the control unit 2 is configured to control the duty cycle of the bias DC signal to 10% to 20%. This allows the plasma processing system according to the embodiment to reduce residue.

[0105] Furthermore, the substrate W has a target film to be etched formed on the underlying layer. The control unit 2 is configured to control the duty cycle of the bias DC signal so that it decreases as the bottom of the holes formed in the target film by etching gets closer to the underlying layer. As a result, the plasma processing system according to this embodiment can reduce the residue at the bottom of the holes.

[0106] Furthermore, the bias DC generation unit 32a is configured to supply a bias DC signal by periodically switching a negative polarity DC voltage on and off. The second RF generation unit 31b is configured not to supply a bias RF signal during the ON period, but to supply a bias RF signal during the OFF period. As a result, the plasma processing system according to the embodiment can reduce residue. In addition, the plasma processing system according to the embodiment can achieve high vertical processing performance.

[0107] Furthermore, the substrate W has a target film to be etched formed on the underlying layer. The control unit 2 is configured to perform the above-described control when the bottom of the holes formed in the target film by etching reaches the underlying layer. As a result, the plasma processing system according to this embodiment can reduce the residue at the bottom of the holes.

[0108] Furthermore, the substrate W has, in order, a fin structure 51 having a plurality of fins 51a, a gate material 52 deposited on the fin structure 51, and a mask 53 on the gate material 52 on the underlying layer 50. The control unit 2 is configured to perform the above-described control when etching the gate material 52 deposited between the plurality of fins 51a of the substrate W until the underlying layer 50 is exposed. As a result, the plasma processing system according to the embodiment can reduce the residue 56 at the bottom of the hole (rectangular portion 55) where the underlying layer 50 is exposed.

[0109] Furthermore, the bias DC generation unit 32a is configured to supply a bias DC signal with a frequency of 100 kHz to 1200 kHz. As a result, the plasma processing system according to this embodiment can achieve high vertical processing performance.

[0110] Furthermore, the gate material is polycrystalline silicon. The underlying layer is a silicon oxide film. As a result, the plasma processing system according to the embodiment can reduce the amount of residue at the bottom of the holes where the silicon oxide film formed on the polycrystalline silicon is exposed.

[0111] Furthermore, the control unit 2 is configured to control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal during etching of the substrate W. As a result, the plasma processing system according to this embodiment can adjust the height of the low-energy and high-energy peaks in the ion energy distribution, as well as the energy range in which the peaks occur.

[0112] Furthermore, the substrate W has a target film to be etched formed on the underlying layer. The control unit 2 is configured to control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the high-energy peak and low-energy peak of the energy distribution of ions incident on the substrate W are high until the bottom of the holes formed in the target film by etching reach the underlying layer, and when the bottom of the holes reach the underlying layer, the low-energy peak is high and the energy range in which the low-energy peak occurs is wide. As a result, the plasma processing system according to the embodiment can reduce residue. Furthermore, the plasma processing system according to the embodiment can obtain high vertical processing performance.

[0113] While embodiments have been described above, it should be understood that the embodiments disclosed herein are illustrative and not restrictive in all respects. Indeed, the embodiments described above can be embodied in a variety of forms. Furthermore, the embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the claims.

[0114] For example, in the above embodiment, the case in which a semiconductor wafer is subjected to plasma etching as the substrate W was described as an example, but it is not limited to this. The substrate W may be any other material.

[0115] It should be noted that the embodiments disclosed herein are illustrative and not restrictive in all respects. Indeed, the embodiments described above can be embodied in a variety of forms. Furthermore, the embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended claims.

[0116] Furthermore, the following additional information is disclosed regarding the above embodiments.

[0117] (Note 1) Chamber and, A substrate support portion is arranged within the chamber and supports the substrate, A gas supply unit configured to supply processing gas into the chamber, A first high-frequency power supply configured to supply first high-frequency power for plasma-generating the processing gas in the chamber, A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support portion, A second high-frequency power supply configured to supply a second high-frequency power to the substrate support portion, A control unit is configured to control the etching of the substrate by supplying the processing gas from the gas supply unit into the chamber, supplying the first high-frequency power from the first high-frequency power supply to plasmaize the processing gas in the chamber, supplying the voltage pulse from the voltage pulse source to the substrate support unit, and supplying the second high-frequency power from the second high-frequency power supply superimposed on the voltage pulse, A plasma processing device equipped with the following features.

[0118] (Note 2) The voltage pulse source is configured to periodically switch a negative polarity DC voltage on and off, and to change the duty cycle of the voltage pulse by changing the ratio of the on and off periods within one cycle. The control unit is configured to control the duty cycle of the voltage pulse from 10% to 80%. The plasma processing apparatus described in Appendix 1.

[0119] (Note 3) The control unit is configured to control the duty cycle of the voltage pulse to 10% to 20%. The plasma processing apparatus described in Appendix 2.

[0120] (Note 4) The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to control the duty cycle of the voltage pulse so that it decreases as the bottom of the hole formed in the target film by etching approaches the underlying layer. A plasma processing apparatus as described in Appendix 2 or 3.

[0121] (Note 5) The voltage pulse source is configured to supply the voltage pulse by periodically switching a negative polarity DC voltage on and off. The second high-frequency power supply is configured to not supply the second high-frequency power during the ON period and to supply the second high-frequency power during the OFF period. A plasma processing apparatus as described in any one of the appendices 1 to 4.

[0122] (Note 6) The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to perform the control when the bottom of a hole formed in the target film by etching reaches the underlying layer. A plasma processing apparatus as described in any one of the appendices 1 to 5.

[0123] (Note 7) The substrate has, in order, a fin structure having a plurality of fins on a base layer, a gate material deposited on the fin structure, and a mask on the gate material. The control unit is configured to perform the control when etching the gate material deposited between the plurality of fins of the substrate until the underlying layer is exposed. A plasma processing apparatus as described in any one of the appendices 1 to 6.

[0124] (Note 8) The voltage pulse source is configured to supply voltage pulses with a frequency of 100kHz to 1200kHz. A plasma processing apparatus as described in any one of the appendices 1 to 7.

[0125] (Note 9) The gate material is polycrystalline silicon. The plasma processing apparatus described in Appendix 7.

[0126] (Note 10) The aforementioned underlayer is a silicon oxide film. A plasma processing apparatus as described in Appendix 7 or 9.

[0127] (Note 11) The control unit is configured to control the period, duty cycle, and amplitude of the voltage pulse and the amplitude of the second high-frequency power during etching of the substrate. A plasma processing apparatus as described in any one of the appendices 1 to 10.

[0128] (Note 12) The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the high-energy peak and low-energy peak of the energy distribution of ions incident on the substrate are high until the bottom of the hole formed in the target film by etching reaches the underlying layer, and when the bottom of the hole reaches the underlying layer, the low-energy peak is high and the energy range in which the low-energy peak occurs is wide. A plasma processing apparatus as described in any one of the appendices 1 to 11.

[0129] (Note 13) Chamber and, A substrate support portion is arranged within the chamber and supports the substrate, A gas supply unit configured to supply processing gas into the chamber, A first high-frequency power supply configured to supply first high-frequency power for plasma-generating the processing gas in the chamber, A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support portion, A second high-frequency power supply configured to supply a second high-frequency power to the substrate support portion, An etching method for a plasma processing apparatus comprising: The process involves etching the substrate by supplying the processing gas from the gas supply unit into the chamber, supplying first high-frequency power from the first high-frequency power supply to plasmaize the processing gas in the chamber, supplying the voltage pulse from the voltage pulse source to the substrate support unit, and supplying the second high-frequency power from the second high-frequency power supply superimposed on the voltage pulse. Etching methods including [specific methods]. [Explanation of symbols]

[0130] 1. Plasma processing equipment 2 Control Unit 2a Computer 2a1 Processing Unit 2a2 Storage section 2a3 communication interface 10 Plasma processing chamber 11. Substrate support section 13 Central gas injection section 14 Antennas 20 Gas Supply Department 21 Gas Source 22 Flow controller 30 power supply 31 RF power supply 31a First RF generation unit 31b Second RF generation unit 32 DC power supply 32a Bias DC generation section 40 Exhaust System 50 Base layer 51 fin structure 51a Fin 52 Gate Material 52a Gate section 53 masks 53a SiN layer 53b Oxide layer 55 Rectangular part 56 Residue 101 Dielectric window 102 Side wall 111 Main body 112 Ring Assembly 1111 Electrostatic Chuck W board

Claims

1. A chamber having a dielectric window at the top and an antenna positioned above the dielectric window, A substrate support portion is arranged within the chamber and supports the substrate, A gas supply unit configured to supply processing gas into the chamber, An inductively coupled plasma source configured to supply a first high-frequency power to the antenna for plasmaizing the processing gas in the chamber, A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support portion, A high-frequency power supply configured to supply a second high-frequency power to the substrate support portion, A control unit is configured to control the etching of the substrate by supplying the processing gas from the gas supply unit into the chamber, supplying a first high-frequency power from the inductively coupled plasma source to plasmaize the processing gas in the chamber, supplying the voltage pulse from the voltage pulse source to the substrate support unit, and supplying the second high-frequency power from the high-frequency power supply superimposed on the voltage pulse, A plasma processing device equipped with the following features.

2. The antenna includes an outer coil and an inner coil arranged on the same axis. The plasma processing apparatus according to claim 1.

3. The first high-frequency power is supplied to either the outer coil or the inner coil. The plasma processing apparatus according to claim 2.

4. The same high-frequency power is supplied to both the outer coil and the inner coil as the first high-frequency power, or different high-frequency powers are supplied separately. The plasma processing apparatus according to claim 2.

5. The system further includes a gas introduction unit for introducing the processing gas supplied from the gas supply unit into the chamber, The gas introduction section includes a central gas injection section, which is positioned above the substrate support section and attached to a central opening formed in the dielectric window. It has at least one gas supply port, at least one gas flow path, and at least one gas inlet, and is configured such that the processing gas supplied to the gas supply port is introduced into the plasma processing space through the gas flow path and from the gas inlet. The plasma processing apparatus according to claim 1.

6. The gas introduction section includes, in addition to the central gas injection section, one or more side gas injection sections attached to one or more openings formed in the side wall of the chamber. The plasma processing apparatus according to claim 5.

7. The voltage pulse source is configured to periodically switch a negative polarity DC voltage on and off, and to change the duty cycle of the voltage pulse by changing the ratio of the on and off periods within one cycle. The control unit is configured to control the duty cycle of the voltage pulse to 10% to 80%. The plasma processing apparatus according to claim 1.

8. The control unit is configured to control the duty cycle of the voltage pulse to 10% to 20%. The plasma processing apparatus according to claim 7.

9. The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to control the duty cycle of the voltage pulse so that it decreases as the bottom of the hole formed in the target film by etching approaches the underlying layer. The plasma processing apparatus according to claim 7.

10. The voltage pulse source is configured to supply the voltage pulse by periodically switching a negative polarity DC voltage on and off. The high-frequency power supply is configured to not supply the second high-frequency power during the ON period, and to supply the second high-frequency power during the OFF period. The plasma processing apparatus according to claim 1.

11. The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to perform the control when the bottom of a hole formed in the target film by etching reaches the underlying layer. The plasma processing apparatus according to claim 1.

12. The substrate has, in order, a fin structure having a plurality of fins on a base layer, a gate material deposited on the fin structure, and a mask on the gate material. The control unit is configured to perform the control when etching the gate material deposited between the plurality of fins of the substrate until the underlying layer is exposed. The plasma processing apparatus according to claim 1.

13. The voltage pulse source is configured to supply voltage pulses with frequencies between 100 kHz and 1200 kHz. The plasma processing apparatus according to claim 1.

14. The gate material is polycrystalline silicon. The plasma processing apparatus according to claim 12.

15. The aforementioned underlayer is a silicon oxide film. The plasma processing apparatus according to claim 12.

16. The control unit is configured to control the period, duty cycle, and amplitude of the voltage pulse and the amplitude of the second high-frequency power during etching of the substrate. The plasma processing apparatus according to claim 1.

17. The substrate has a target film to be etched formed on the underlying layer. The control unit is configured to control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the high-energy peak and low-energy peak of the energy distribution of ions incident on the substrate are high until the bottom of the hole formed in the target film by etching reaches the underlying layer, and when the bottom of the hole reaches the underlying layer, the low-energy peak is high and the energy range in which the low-energy peak occurs is wide. The plasma processing apparatus according to claim 1.

18. A chamber having a dielectric window at the top and an antenna positioned above the dielectric window, A substrate support portion is arranged within the chamber and supports the substrate, A gas supply unit configured to supply processing gas into the chamber, An inductively coupled plasma source configured to supply a first high-frequency power to the antenna for plasmaizing the processing gas in the chamber, A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support portion, A high-frequency power supply configured to supply a second high-frequency power to the substrate support portion, An etching method for a plasma processing apparatus comprising: The process involves etching the substrate by supplying the processing gas from the gas supply unit into the chamber, supplying a first high-frequency power from the inductively coupled plasma source to plasmaize the processing gas in the chamber, supplying the voltage pulse from the voltage pulse source to the substrate support unit, and supplying the second high-frequency power from the high-frequency power supply superimposed on the voltage pulse. Etching methods including [specific methods].

Images