Semiconductor chip and method for manufacturing the same

Abstract

To provide a semiconductor chip and a method for manufacturing the same that can achieve cost reduction. [Solution] The semiconductor chip comprises a silicon substrate, an integrated circuit, a first seal ring, a second seal ring, polyimide, a first pad, and a second pad. The integrated circuit is formed on the silicon substrate. The first seal ring is formed on the silicon substrate so as to surround the integrated circuit and is connected to the silicon substrate. The second seal ring is formed on the silicon substrate so as to surround the integrated circuit, is formed inside the first seal ring, and is capacitively coupled to the first seal ring. The polyimide is formed on the silicon substrate so as to cover the integrated circuit, the first seal ring, and the second seal ring. The first pad is formed as part of the integrated circuit and is electrically connected to the first seal ring via a first signal line. The second pad is formed as part of the integrated circuit and is electrically connected to the second seal ring via a second signal line.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor chip and a method for manufacturing the same, and more particularly to a semiconductor chip and a method for manufacturing the same suitable for realizing cost reduction.

Background Art

[0002] When cutting out an integrated circuit formed on a semiconductor wafer and a seal ring formed on the semiconductor wafer so as to surround the integrated circuit as a semiconductor chip along a dicing line formed outside the seal ring, chipping cracks may occur in the semiconductor wafer. If this chipping crack has not reached the seal ring, the cut-out semiconductor chip is judged as a good product, but if the chipping crack reaches the seal ring, the cut-out semiconductor chip is judged as a defective product.

[0003] Here, since cost reduction by miniaturization is required for semiconductor devices, it is desirable that the semiconductor chips used for forming the semiconductor devices be cut out to the smallest possible size. That is, it is desirable that the semiconductor chip be cut out to the smallest possible size within a range where the chipping crack does not reach the seal ring. Techniques related to the cutting out of semiconductor chips are also disclosed in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The seal ring formed on the semiconductor wafer is covered by polyimide along with the integrated circuit surrounded by the seal ring and is therefore not visible. For this reason, related technologies must determine whether or not chipping cracks have reached the seal ring by visual inspection after cutting the semiconductor chip. However, visual inspection may not accurately determine whether or not chipping cracks have reached the seal ring. Therefore, related technologies required a sufficiently large distance between the seal ring and the dicing line to prevent chipping cracks from reaching the seal ring. Consequently, related technologies faced the challenge of being unable to miniaturize semiconductor chips and increasing costs. Other challenges and novel features will become apparent from the description and accompanying drawings of this specification. [Means for solving the problem]

[0006] The semiconductor chip according to this disclosure comprises a silicon substrate, an integrated circuit formed on the silicon substrate, a first seal ring formed on the silicon substrate so as to surround the integrated circuit and connected to the silicon substrate, a second seal ring formed on the silicon substrate so as to surround the integrated circuit, formed inside the first seal ring and capacitively coupled to the first seal ring, a polyimide formed on the silicon substrate so as to cover the integrated circuit, the first seal ring, and the second seal ring, a first pad formed as part of the integrated circuit and electrically connected to the first seal ring via a first signal line, and a second pad formed as part of the integrated circuit and electrically connected to the second seal ring via a second signal line.

[0007] A method for manufacturing a semiconductor chip according to this disclosure comprises the steps of: preparing a semiconductor wafer including a semiconductor chip comprising: a silicon substrate; an integrated circuit formed on the silicon substrate; a first seal ring formed on the silicon substrate so as to surround the integrated circuit and connected to the silicon substrate; a second seal ring formed on the silicon substrate so as to surround the integrated circuit, formed inside the first seal ring and capacitively coupled to the first seal ring; a polyimide formed on the silicon substrate so as to cover the integrated circuit, the first seal ring, and the second seal ring; a first pad formed as part of the integrated circuit and electrically connected to the first seal ring via a first signal line; and a second pad formed as part of the integrated circuit and electrically connected to the second seal ring via a second signal line; cutting the semiconductor chip from the semiconductor wafer; and detecting whether a chipping crack has reached the first seal ring based on the electrical signals of the first pad and the electrical signals of the second pad. [Effects of the Invention]

[0008] This disclosure provides a semiconductor chip and a method for manufacturing the same that can achieve cost reduction. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic plan view showing an example of the configuration of a semiconductor chip according to Embodiment 1. [Figure 2] Figure 2 illustrates the challenges that arise when cutting semiconductor chips from semiconductor wafers. [Figure 3] Figure 3 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 1. [Figure 4] Figure 4 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 2. [Figure 5]Figure 5 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 3. [Figure 6] Figure 6 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 4. [Figure 7] Figure 7 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 5. [Figure 8] Figure 8 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 6. [Figure 9] Figure 9 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 7. [Figure 10] Figure 10 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 8. [Figure 11] Figure 11 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 9. [Figure 12] Figure 12 is a schematic plan view and schematic cross-sectional view showing an enlarged portion of the configuration example of a semiconductor chip according to Embodiment 10. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on their depiction. Furthermore, the same elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0011] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or entire modification example, application example, detailed description, supplementary description, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0012] Furthermore, in the following embodiments, the constituent elements (including operation steps, etc.) are not necessarily essential unless otherwise specified and unless it is clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly considered otherwise in principle, it includes those that are substantially approximate or similar to the shape, etc. This also applies to the above-mentioned numbers, etc. (including the number, numerical value, quantity, range, etc.).

[0013] <Embodiment 1> FIG. 1 is a schematic plan view showing a configuration example of a semiconductor chip 1 according to Embodiment 1. The semiconductor chip 1 is formed by cutting out the semiconductor chip 1 formed on a semiconductor wafer along a dicing line formed outside the seal ring. Note that FIG. 1 shows a portion of the semiconductor chip 1 before being cut out from the semiconductor wafer, and does not show the polyimide covering the integrated circuit IC1 and the reel ring. Hereinafter, the portion of the semiconductor chip 1 before being cut out from the semiconductor wafer will also be simply referred to as the semiconductor chip 1.

[0014] Note that the right-handed XYZ orthogonal coordinates shown in FIG. 1 are for convenience in explaining the positional relationship of the constituent elements. In FIG. 1 and the like, for example, the Z direction is the vertical direction, the XY plane is the horizontal plane, and the X direction, Y direction, and Z direction are common among the drawings. <了

[0015] Specifically, the semiconductor chip 1 includes a silicon substrate 100, an integrated circuit IC1, a seal ring (first seal ring) SR1, and a seal ring (second seal ring) SR2. The seal ring is also called a guard ring.

[0016] The integrated circuit IC1 is formed on the silicon substrate 100. In the integrated circuit IC1, at least pad PD1 and pad PD2 are formed in addition to integrated electronic components (not shown).

[0017] The seal ring SR1 is formed on the silicon substrate 100 so as to surround the integrated circuit IC. Also, the seal ring SR1 is electrically connected to the silicon substrate 100. Specifically, the seal ring SR1 is grounded via the silicon substrate 100.

[0018] The seal ring SR2 is formed on the silicon substrate 100 so as to surround the integrated circuit IC and is formed inside the seal ring SR1. Also, the seal ring SR2 is capacitively coupled to the seal ring SR1.

[0019] The seal ring SR1 is connected to the pad PD1 of the integrated circuit IC1 via the signal line W1. The seal ring SR2 is connected to the pad PD2 of the integrated circuit IC1 via the signal line W2.

[0020] By referring to FIG. 2, for example, when the integrated circuit IC1 formed on the semiconductor wafer and the seal rings SR1 and SR2 formed on the semiconductor wafer so as to surround the integrated circuit IC1 are cut out as the semiconductor chip 1 along the dicing line formed outside the seal rings SR1 and SR2, chipping cracks may occur in the semiconductor wafer. If this chipping crack has not reached the seal ring SR1, the cut-out semiconductor chip 1 is determined to be a good product and is used for the formation of the subsequent semiconductor device. However, if the chipping crack reaches the seal ring SR1, the cut-out semiconductor chip 1 is determined to be a defective product and is not used for the formation of the subsequent semiconductor device.

[0021] Here, since cost reduction through miniaturization is required for semiconductor devices, it is desirable that the semiconductor chip 1 used in the formation of the semiconductor device be cut to the smallest possible size. In other words, it is desirable that the semiconductor chip 1 be cut to the smallest possible size without chipping cracks reaching the seal ring SR1. However, the seal rings SR1 and SR2 are covered with polyimide PI along with the integrated circuit IC1 and are not visible. Therefore, related technologies are forced to determine whether or not chipping cracks have reached the seal rings by visual inspection after cutting the semiconductor chip. However, visual inspection may not be able to accurately determine whether or not chipping cracks have reached the seal rings. Therefore, related technologies had to make the distance between the seal ring and the dicing line sufficiently large so that chipping cracks do not reach the seal ring when viewed from above. As a result, related technologies had the problem that they could not miniaturize the semiconductor chip and the cost of the semiconductor device increased.

[0022] To solve these problems, the semiconductor chip 1 according to Embodiment 1 enables detection of whether or not a chipping crack has reached the seal ring SR1 based on the change in capacitance values ​​of seal rings SR1 and SR2 that occurs when a chipping crack reaches the seal ring SR1. Specifically, the semiconductor chip 1 according to Embodiment 1 enables detection of whether or not a chipping crack has reached the seal ring SR1 by detecting the changes in the electrical signal of pad PD1 connected to seal ring SR1 and the electrical signal of pad PD2 connected to seal ring SR2, respectively, in accordance with the change in capacitance values ​​of the capacitively coupled seal rings SR1 and SR2. Here, the detection circuit that detects whether or not a chipping crack has reached the seal ring SR1 based on the respective electrical signals of pads PD1 and PD2 is mounted on the integrated circuit IC1, for example, but for example, the detection circuit may be located outside the semiconductor wafer. In other words, the detection circuit may be an external device such as a tester that acquires the respective electrical signals of pads PD1 and PD2 by contacting a pair of probes to pads PD1 and PD2.

[0023] As described above, the semiconductor chip 1 according to Embodiment 1 enables detection of whether or not a chipping crack has reached the seal ring SR1 based on electrical signals obtained from the capacitively coupled seal rings SR1 and SR2. This makes it possible to determine whether or not a chipping crack has reached the seal ring SR1 with higher accuracy than with visual inspection, thus reducing the distance between the seal ring and the dicing line. As a result, even when the seal rings SR1 and SR2 are covered with polyimide and cannot be seen, it becomes possible to cut out a small semiconductor chip 1. Therefore, the semiconductor chip 1 according to Embodiment 1 can be miniaturized and thus cost-effective.

[0024] Furthermore, the semiconductor chip 1 according to Embodiment 1 can increase the capacitance values ​​of the seal rings SR1 and SR2, thereby improving the oscillation prevention and decoupling effects.

[0025] (Structure of seal rings SR1 and SR2) Next, the specific structure of the seal rings SR1 and SR2 will be explained using Figure 3. Figure 3 is a schematic plan view and schematic cross-sectional view of a portion of the semiconductor chip 1, magnified. Figure 3 also shows a schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and the area around them in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 3 shows the AA cross-section in region A1 of the semiconductor chip 1 shown in Figure 1 as a schematic cross-sectional view, and the wiring layer M4 as a schematic plan view. The AA cross-section is a cross-section viewed in the Y direction from the ZX plane.

[0026] As shown in Figure 3, in the semiconductor chip 1 according to Embodiment 1, the seal ring SR1 comprises a plurality of wirings M11, M21, M31, M41, M51, M61 and a plurality of vias V11, V21, V31, V41, V51, V61. The plurality of wirings M11, M21, M31, M41, M51, M61 are formed within each of the plurality of wiring layers M1, M2, M3, M4, M5, M6 stacked on the silicon substrate 100. The plurality of vias V11, V21, V31, V41, V51, V61 electrically connect the silicon substrate 100 and the wirings M11, M21, M31, M41, M51, M61.

[0027] Specifically, wiring layer M2 is formed on wiring layer M1. Wiring layer M3 is formed on wiring layer M2. Wiring layer M4 is formed on wiring layer M3. Wiring layer M5 is formed on wiring layer M4. Wiring layer M6 is formed on wiring layer M5. Wiring M11 is formed within wiring layer M1. Wiring M21 is formed within wiring layer M2. Wiring M31 is formed within wiring layer M3. Wiring M41 is formed within wiring layer M4. Wiring M51 is formed within wiring layer M5. Wiring M61 is formed within wiring layer M6. Via V11 connects the silicon substrate 100 to wiring M11. Via V21 connects wiring M11 to wiring M21. Via V31 connects wiring M21 to wiring M31. Via V41 connects wiring M31 to wiring M41. Via V51 connects wire M41 and wire M51. Via V61 connects wire M51 and wire M61.

[0028] The seal ring SR2 comprises multiple wirings M12, M22, M32, and M42, and multiple vias V22, V32, and V42. The multiple wirings M12, M22, M32, and M42 are formed within each of the multiple wiring layers M1, M2, M3, and M4 stacked on the silicon substrate 100. The multiple vias V22, V32, and V42 electrically connect the wirings M12, M22, M32, and M42.

[0029] Specifically, wiring M12 is formed within wiring layer M1. Wiring M22 is formed within wiring layer M2. Wiring M32 is formed within wiring layer M3. Wiring M42 is formed within wiring layer M4. Via V22 connects wiring M12 and wiring M22. Via V32 connects wiring M22 and wiring M32. Via V42 connects wiring M32 and wiring M42.

[0030] In the example in Figure 3, multiple wirings M21, M31, M41, M51, M61, and multiple wirings M22, M22, M32, M42 are formed of aluminum or an alloy containing aluminum. Wirings M11 and M12 are formed of tungsten or an alloy containing tungsten. Multiple wirings M21, M31, M41, M51, M61, and multiple wirings M22, M22, M32, M42 are not limited to being formed of aluminum or an alloy containing aluminum, but may be formed of another metallic material such as copper or an alloy containing copper. Multiple vias V11, V21, V31, V41, V51, V61, and multiple vias V22, V32, V42 are formed of tungsten or an alloy containing tungsten. Multiple vias V11, V21, V31, V41, V51, V61, and multiple vias V22, V32, V42 are not limited to being formed of tungsten or an alloy containing tungsten, but may also be formed of another metallic material such as copper or an alloy containing copper.

[0031] Multiple wirings M21, M31, M41, M51, M61 and multiple wirings M22, M22, M32, M42 are formed in a plate-like or linear shape in the corresponding wiring layer, but are not limited to this and may be formed in any shape. In the example in Figure 3, multiple wirings M11, M21, M31, M41, M51, M61 of the seal ring SR1 are formed extending along the Y direction, and multiple wirings M11, M31, M51 of the multiple wirings M11, M21, M31, M41, M51, M61 are formed in a plate-like shape protruding toward the seal ring SR2 (in the X direction). Furthermore, in the example shown in Figure 3, multiple wirings M12, M22, M32, and M42 of the seal ring SR2 are formed extending along the Y direction, and multiple wirings M22 and M42 of the multiple wirings M12, M22, M32, and M42 are formed in a plate-like shape, protruding toward the seal ring SR1 (in the X direction). In addition, in the example shown in Figure 3, multiple plate-like wirings M11, M22, M31, M42, and M51 overlap alternately in the vertical direction (Z direction). As a result, parasitic capacitances with capacitance value C1 (hereinafter referred to as capacitance C1) are formed between the multiple wirings M11, M22, M31, M42, and M51. The capacitance value of capacitance C1 is, for example, about 0.104 fF / µm².

[0032] Furthermore, a parasitic capacitance (hereinafter referred to as capacitance C2a) with capacitance value C2a is formed between wiring M11 and wiring M12 formed in wiring layer M1. The capacitance value of capacitance C2a is, for example, about 0.075 fF / um. A parasitic capacitance (hereinafter referred to as capacitance C2) with capacitance value C2 is formed between wiring M21 and wiring M22 formed in wiring layer M2. A parasitic capacitance (hereinafter referred to as capacitance C2) with capacitance value C2 is formed between wiring M31 and wiring M32 formed in wiring layer M3. A parasitic capacitance (hereinafter referred to as capacitance C2) with capacitance value C2 is formed between wiring M41 and wiring M42 formed in wiring layer M4. The capacitance value of capacitance C2 is, for example, about 0.079 fF / um. Therefore, if the size of semiconductor chip 1 is 1 mm x 1 mm, the total capacitance value formed in the seal rings SR1 and SR2 will be approximately 6 pF (0.3 fF / µm²).

[0033] For example, when a chipping crack reaches the seal ring SR1, at least one of the capacitance values ​​C1, C2, and C2a between the capacitively coupled seal rings SR1 and SR2 changes due to a break in the seal ring SR1, a crack in the interlayer film, or moisture absorption of the interlayer film. The semiconductor chip 1 according to Embodiment 1 detects whether or not a chipping crack has reached the seal ring SR1 by detecting this change in the capacitance values ​​of the seal rings SR1 and SR2.

[0034] In Embodiment 1, the example described was a case in which the seal ring SR1 is composed of multiple wires formed on all of the wiring layers M1, M2, M3, M4, M5, and M6. However, the invention is not limited to this, and the seal ring SR2 may be composed of wires formed on one or more of the wiring layers M1, M2, M3, M4, M5, and M6. Similarly, in Embodiment 1, the example described was a case in which the seal ring SR2 is composed of multiple wires formed on all of the wiring layers M1, M2, M3, M4, M5, and M6. However, the invention is not limited to this, and the seal ring SR2 may be composed of wires formed on one or more of the wiring layers M1, M2, M3, M4, M5, and M6. Furthermore, in Embodiment 1, the example described was a case in which there are six wiring layers. However, the invention is not limited to this.

[0035] (Manufacturing method for semiconductor chip 1) Next, the manufacturing method of semiconductor chip 1 will be explained. First, a semiconductor wafer containing semiconductor chip 1 as shown in Figure 1 is prepared. Then, before cutting semiconductor chip 1 from the semiconductor wafer, the capacitance values ​​of seal rings SR1 and SR2 are measured based on the electrical signals of pads PD1 and PD2 of semiconductor chip 1. After that, semiconductor chip 1 is cut from the semiconductor wafer along the dicing line. Then, the capacitance values ​​of seal rings SR1 and SR2 are measured based on the electrical signals of pads PD1 and PD2. By comparing the capacitance value of semiconductor chip 1 before cutting with the capacitance value of semiconductor chip 1 after cutting, it is detected whether or not a chipping crack has reached seal ring SR1. If the difference between the capacitance values ​​of seal rings SR1 and SR2 of semiconductor chip 1 before cutting from the semiconductor wafer and the capacitance values ​​of seal rings SR1 and SR2 of semiconductor chip 1 after cutting from the semiconductor wafer is greater than or equal to a predetermined value, it is determined that a chipping crack has reached seal ring SR1. As a result, determining whether or not a chipping crack has reached the seal ring SR1 becomes more accurate than with visual inspection, making it possible to reduce the distance between the seal ring and the dicing line. This makes it possible to cut out a small semiconductor chip 1 even when the seal rings SR1 and SR2 are covered with polyimide and cannot be seen. As a result, the semiconductor chip 1 according to Embodiment 1 can be miniaturized, and thus cost reduction can be achieved.

[0036] Alternatively, instead of measuring the capacitance values ​​of the sealing rings SR1 and SR2 of the semiconductor chip 1 before cutting it from the semiconductor wafer, a standard value for the capacitance may be set in advance. In this case, whether or not a chipping crack has reached the sealing ring SR1 can be detected by comparing the standard value for capacitance with the capacitance values ​​of the sealing rings SR1 and SR2 of the semiconductor chip 1 after it has been cut from the semiconductor wafer. For example, if the difference between the standard value for capacitance and the capacitance values ​​of the sealing rings SR1 and SR2 of the semiconductor chip 1 after it has been cut from the semiconductor wafer is greater than or equal to a predetermined value, it may be determined that a chipping crack has reached the sealing ring SR1.

[0037] <Embodiment 2> Figure 4 is a schematic plan view and schematic cross-sectional view of a portion of the semiconductor chip 1 according to Embodiment 2, with some parts enlarged. Similar to Figure 3, Figure 4 also shows a schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 4 shows not only the AA cross-section but also a portion of the BB cross-section, which is perpendicular to the AA cross-section, as schematic cross-sectional views. The BB cross-section is a cross-section viewed in the X direction from the YZ plane.

[0038] As shown in Figure 4, the semiconductor chip 1 according to Embodiment 2, compared to the semiconductor chip 1 shown in Figure 3, further includes a Metal Insulator Metal (MIM) capacitance element between the wiring M51 of the seal ring SR1 formed in the wiring layer M5 and the wiring M42 of the seal ring SR2 formed in the wiring layer M4. Specifically, an insulating film MI1 is formed on the upper surface of the wiring M42 formed in the wiring layer M4. A film-like additional metal MA1 is formed on the insulating film MI1. The additional metal MA1 is formed of a metal such as aluminum or copper, but may also be formed of titanium nitride. The additional metal MA1 and the wiring M51 formed in the wiring layer M5 are electrically connected to each other by a plurality of additional vias VA1. As a result, a capacitance with capacitance value C3 (hereinafter referred to as capacitance C3) is formed between the additional metal MA1 and the wiring M51. The capacitance value of capacitance C3 is, for example, about 0.8 fF / µm². Therefore, if the size of semiconductor chip 1 is 1 mm x 1 mm, the total capacitance value formed in the seal rings SR1 and SR2 will be approximately 16 pF (0.8 fF / µm²).

[0039] Thus, the semiconductor chip 1 according to Embodiment 2 can increase the capacitance value of the capacitance formed in the seal rings SR1 and SR2 by further forming MIM capacitance elements between adjacent wiring layers. In Embodiment 2, the case in which MIM capacitance elements are formed between wiring layers M4 and M5 was described as an example, but it is not limited to this. One or more MIM capacitance elements may be formed in any one or more of the following locations: between wiring layers M1 and M2, between wiring layers M2 and M3, between wiring layers M3 and M4, and between wiring layers M4 and M5.

[0040] <Embodiment 3> Figure 5 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 3. Similar to Figure 3, Figure 5 also shows an enlarged schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 5 shows not only the AA cross-section but also a portion of the BB cross-section perpendicular to the AA cross-section as a schematic cross-sectional view.

[0041] As shown in Figure 5, the semiconductor chip 1 according to Embodiment 3, compared to the semiconductor chip 1 shown in Figure 3, further includes an MIM capacitance element between the wiring M51 of the seal ring SR1 formed in the wiring layer M5 and the wiring M42 of the seal ring SR2 formed in the wiring layer M4. Specifically, a film-like additional metal MA1 is formed on the upper surface of the wiring M42 formed in the wiring layer M4. An insulating film MI1 is formed on the additional metal MA1. A film-like additional metal MA2 is formed on the insulating film MI1. The additional metal MA1 and additional metal MA2 are formed of a metal such as aluminum or copper, but may also be formed of titanium nitride. The additional metal MA2 and the wiring M51 formed in the wiring layer M5 are electrically connected to each other by a plurality of additional vias VA1. As a result, a capacitance of capacitance value C3 (hereinafter, capacitance C3) is formed between the additional metal MA1 and additional metal MA2.

[0042] Here, the wiring M42 formed within the wiring layer M4 is formed in a comb-like shape when viewed from above (in the Z direction). The stacked additional metal MA1, insulating film MI1, and additional metal MA2 are formed to cover a portion of the surface of the comb-like wiring M42. Specifically, the stacked additional metal MA1, insulating film MI1, and additional metal MA2 are formed to cover a portion of the top and side surfaces of each comb tooth of the comb-like wiring M42. As a result, the opposing area between additional metal MA1 and additional metal MA2 increases, and the capacitance value of capacitance C3 increases. The capacitance value of capacitance C3 at this time is, for example, about 1.6 fF / µm². Therefore, if the size of the semiconductor chip 1 is 1 mm × 1 mm, the total capacitance value formed in the seal rings SR1 and SR2 will be approximately 28 pF (1.4 fF / µm²).

[0043] As described above, the semiconductor chip 1 according to Embodiment 3 can further increase the capacitance value of the capacitance formed in the seal rings SR1 and SR2 by forming the wiring M42 of the wiring layer M4 that supports the MIM capacitance element in a comb-like shape. In Embodiment 3, the case in which the MIM capacitance element is formed between wiring layers M4 and M5 was described as an example, but it is not limited to this. One or more MIM capacitance elements may be formed in any one or more of the following locations: between wiring layer M1 and wiring layer M2, between wiring layer M2 and wiring layer M3, between wiring layer M3 and wiring layer M4, and between wiring layer M4 and wiring layer M5. In this case, the wiring formed in the wiring layer that supports the MIM capacitance element may be formed in a comb-like shape when viewed from above. As a result, the capacitance value of each MIM capacitance element will increase.

[0044] <Embodiment 4> Figure 6 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 4. Similar to Figure 3, Figure 6 also shows an enlarged schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 6 shows not only the AA cross-section but also a portion of the BB cross-section perpendicular to the AA cross-section as schematic cross-sectional views.

[0045] As shown in Figure 6, the semiconductor chip 1 according to Embodiment 4, compared to the semiconductor chip 1 shown in Figure 5, further comprises a Metal Oxide Semiconductor (MOS) capacitive element between the silicon substrate 100 and the lowest layer wiring layer M1. Specifically, a gate oxide film MO1 is formed on the silicon substrate 100. A polysilicon film MA3 is formed on the gate oxide film MO1. The polysilicon film MA3 and the wiring M12 formed on the wiring layer M1 are electrically connected to each other by a plurality of additional vias VA2. As a result, a capacitance value C5 (hereinafter referred to as capacitance C5) is formed between the silicon substrate 100 and the polysilicon film MA3. The capacitance value of capacitance C5 is, for example, about 1.71 fF / µm. In addition, a capacitance value C4 (hereinafter referred to as capacitance C4) is formed between the polysilicon film MA3 and the wiring M11 that is positioned opposite to the polysilicon film MA3 in the wiring layer M1. The capacitance value of capacitance C4 is, for example, about 0.083 fF / µm². Therefore, if the size of semiconductor chip 1 is 1 mm x 1 mm, the total capacitance value formed in the seal rings SR1 and SR2 will be approximately 47 pF (2.4 fF / µm²).

[0046] As described above, the semiconductor chip 1 according to Embodiment 4 can further increase the capacitance value of the capacitance formed in the seal rings SR1 and SR2 by further forming a MOS capacitance element between the silicon substrate 100 and the wiring layer M1. In Embodiment 4, the case in which an MIM capacitance element is formed between the wiring layer M4 and the wiring layer M5, and a MOS capacitance element is formed between the silicon substrate 100 and the wiring layer M1 was described as an example, but it is not limited to this. An MIM capacitance element may not be formed between the wiring layer M4 and the wiring layer M5, and a MOS capacitance element may be formed between the silicon substrate 100 and the wiring layer M1.

[0047] <Embodiment 5> Figure 7 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 5. Similar to Figure 3, Figure 7 also shows an enlarged schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 7 shows not only the AA cross-section but also a portion of the BB cross-section perpendicular to the AA cross-section as a schematic cross-sectional view.

[0048] As shown in Figure 7, in the semiconductor chip 1 according to Embodiment 5, compared to the semiconductor chip 1 shown in Figure 6, a portion of the upper surface of the silicon substrate 100 has an uneven shape. The stacked gate oxide film MO1 and polysilicon film MA3 are formed to cover the upper surface of the uneven silicon substrate 100. As a result, the opposing area between the polysilicon film MA3 and the silicon substrate 100 is increased, and the capacitance value of capacitance C5 increases. The capacitance value of capacitance C5 in this case is, for example, about 3.42 fF / µm. Therefore, if the size of the integrated circuit IC1 is 1 mm × 1 mm, the total capacitance value formed in the seal rings SR1 and SR2 will be about 65 pF (3.3 fF / µm²).

[0049] Thus, the semiconductor chip 1 according to Embodiment 5 can further increase the capacitance value of the capacitance formed in the seal rings SR1 and SR2 by forming an uneven shape on the upper surface of the silicon substrate that supports the MOS capacitance element.

[0050] <Embodiment 6> Figure 8 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 6. Similar to Figure 3, Figure 8 also shows an enlarged schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 8 shows not only the AA cross-section but also a portion of the BB cross-section perpendicular to the AA cross-section as a schematic cross-sectional view.

[0051] As shown in Figure 8, in the semiconductor chip 1 according to Embodiment 6, compared to the semiconductor chip 1 shown in Figure 7, the additional metal MA1, insulating film MI1, and additional metal MA2 stacked on the wiring M42 are formed to further cover the side surfaces of the tip portions T1 of each comb tooth of the comb-shaped wiring M42. That is, the additional metal MA1, insulating film MI1, and additional metal MA2 stacked on the wiring M42 are formed to cover the entire upper and side surfaces of each comb tooth of the comb-shaped wiring M42. As a result, the opposing area between the additional metal MA1 and additional metal MA2 is increased, and the capacitance value of capacitance C3 is further increased.

[0052] As described above, the semiconductor chip 1 according to Embodiment 6 can further increase the capacitance value of the capacitance formed in the seal rings SR1 and SR2 by forming the additional metal MA1, insulating film MI1, and additional metal MA2, which are stacked on the wiring M42 formed in the wiring layer M4, so as to cover the entire upper and side surfaces of the wiring M42. In Embodiment 6, the case in which an MIM capacitance element is formed between wiring layers M4 and M5 was described as an example, but it is not limited to this. One or more MIM capacitance elements may be formed between wiring layers M1 and M2, between wiring layers M2 and M3, between wiring layers M3 and M4, and between wiring layers M4 and M5. In this case, each MIM capacitance element may be formed so as to cover the entire upper and side surfaces of the wiring that supports the MIM capacitance element.

[0053] <Embodiment 7> Figure 9 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 7. Similar to Figure 3, Figure 9 also shows an enlarged schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1. Furthermore, Figure 9 shows not only the AA cross-section but also a portion of the BB cross-section perpendicular to the AA cross-section as a schematic cross-sectional view.

[0054] As shown in Figure 9, in the semiconductor chip 1 according to Embodiment 7, compared to the semiconductor chip 1 shown in Figure 8, the corners of the upper surface of the wiring M42 formed in the wiring layer M4 are further chamfered. As a result, the additional metal MA1, insulating film MI1, and additional metal MA2 located at the chamfered corners of the wiring M42 are rounded. This suppresses the degradation of the additional metal MA1, insulating film MI1, and additional metal MA2 located at the chamfered corners of the wiring M42, thereby improving reliability.

[0055] As described above, the semiconductor chip 1 according to Embodiment 7 can improve reliability by chamfering the corners of the upper surface of the wiring M42 formed in the wiring layer M4, thereby suppressing the degradation of the additional metal MA1, insulating film MI1, and additional metal MA2 located at the chamfered corners of the wiring M42. Although Embodiment 7 describes the case in which an MIM capacitive element is formed between wiring layers M4 and M5, it is not limited to this. One or more MIM capacitive elements may be formed between wiring layers M1 and M2, between wiring layers M2 and M3, between wiring layers M3 and M4, and between wiring layers M4 and M5. In this case, each MIM capacitive element may be formed so as to cover not only the upper surface but also the side surface of the wiring that supports the MIM capacitive element. Furthermore, in this case, the corners of the upper surface of the wiring that indicates each MIM capacitive element may be chamfered.

[0056] <Embodiment 8> Figure 10 is a schematic plan view and schematic cross-sectional view of an enlarged portion of the semiconductor chip 1 according to Embodiment 8. Similar to Figure 3, Figure 10 also shows a schematic plan view and schematic cross-sectional view of the seal rings SR1 and SR2 and their surroundings in region A1 of the semiconductor chip 1 shown in Figure 1.

[0057] As shown in Figure 10, in the semiconductor chip 1 according to Embodiment 8, compared to the semiconductor chip 1 shown in Figure 2, each of the multiple wirings M11, M21, M31, M41, M51, and M61 of the seal ring SR1 is formed in a comb-like shape when viewed from above, and each of the multiple wirings M12, M22, M32, and M42 of the seal ring SR2 is formed in a comb-like shape when viewed from above. Specifically, in the wiring layer M1, the wirings M11 and M12 are formed so that their comb teeth extend in the X direction and overlap alternately when viewed in the Y direction. In the wiring layer M2, the wirings M21 and M22 are formed in a comb-like shape so that their teeth extend in the X direction and overlap alternately when viewed in the X direction. In the wiring layer M3, the wirings M31 and M32 are formed in a comb-like shape so that their teeth extend in the X direction and overlap alternately when viewed in the X direction. In wiring layer M4, wirings M41 and M42 are formed in a comb-like shape, with their teeth extending in the X direction and overlapping alternately when viewed in the X direction. As a result, the opposing area between wirings in each wiring layer is increased, further increasing the capacitance value of capacitance C2.

[0058] Thus, in the semiconductor chip 1 according to Embodiment 6, the capacitance value of the capacitance formed in the seal rings SR1 and SR2 can be further increased by forming the wiring of the seal rings SR1 and SR2 in each wiring layer in a comb-like shape.

[0059] <Embodiment 9> Figure 11 is a schematic plan view showing an example of the configuration of a semiconductor chip 1 according to Embodiment 9. The semiconductor chip 1 according to Embodiment 9 is formed by cutting an integrated circuit IC 1 formed on a semiconductor wafer along a dicing line formed on the outside of a seal ring. Note that Figure 11 shows the portion of the semiconductor wafer before the semiconductor chip 1 is cut from the semiconductor wafer, and the polyimide covering the integrated circuit IC 1 is not shown. Hereinafter, the portion of the semiconductor chip 1 before it is cut from the semiconductor wafer will also be simply referred to as semiconductor chip 1.

[0060] As shown in Figure 11, in the semiconductor chip 1 according to Embodiment 9, compared to the semiconductor chip 1 shown in Figure 1, the seal ring SR2 is further composed of multiple sealing materials that are electrically isolated from each other. In the example of Figure 11, the seal ring SR2 is composed of an L-shaped seal ring SR2a and an L-shaped seal ring SR2b facing the seal ring SR2a. This makes it possible, for example, to adjust the capacitance values ​​of the seal rings SR1 and SR2. The structure of the semiconductor chip 1 shown in Figure 11 may also be applied to the semiconductor chip 1 according to Embodiments 2 to 8.

[0061] <Embodiment 10> Figure 12 is a schematic plan view showing an example of the configuration of a semiconductor chip 1 according to Embodiment 10. The semiconductor chip 1 according to Embodiment 10 is formed by cutting an integrated circuit IC 1 formed on a semiconductor wafer along a dicing line formed on the outside of a seal ring. Note that Figure 12 shows the portion of the semiconductor wafer before the semiconductor chip 1 is cut from the semiconductor wafer, and the polyimide covering the integrated circuit IC 1 is not shown. Hereinafter, the portion of the semiconductor chip 1 before it is cut from the semiconductor wafer will also be simply referred to as semiconductor chip 1.

[0062] As shown in Figure 12, in the semiconductor chip 1 according to Embodiment 10, compared to the semiconductor chip 1 shown in Figure 1, the seal ring SR2 is further composed of multiple sealing materials that are electrically isolated from each other. In the example of Figure 12, the seal ring SR2 is composed of seal rings SR2a, SR2b, SR2c, and SR2d formed along each of the four sides of the rectangular integrated circuit IC1. This makes it possible, for example, to adjust the capacitance values ​​of the seal rings SR1 and SR2. The structure of the semiconductor chip 1 shown in Figure 12 may also be applied to the semiconductor chip 1 according to Embodiments 2 to 8.

[0063] Furthermore, the seal ring SR2 is not limited to the structure shown in Figures 11 and 12, and may be composed of any number of electrically isolated sealing materials. For example, the multiple sealing materials may be formed so as to be symmetrical with respect to a line passing through the center of the integrated circuit IC1 when viewed from above (in the Z direction).

[0064] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]

[0065] 1. Semiconductor chip 100 silicon substrates IC1 Integrated Circuit M11 wiring (1st wiring) M21 Wiring (First Wiring) M31 Wiring (First Wiring) M41 wiring (first wiring) M51 wiring (1st wiring) M61 Wiring (First Wiring) M12 wiring (second wiring) M22 wiring (second wiring) M32 wiring (second wiring) M42 wiring (second wiring) MI1 Insulating Film MA1 Additional Metal MA2 Additional Metal MA3 Polysilicon film MO1 gate oxide film PD1, PD2 pads PI polyimide SR1 seal ring (first seal ring) SR2 seal ring (second seal ring) V11 Via (First Via) V21 Via (Via No. 1) V31 Via (First Via) V41 Via (First Via) V51 Via (First Via) V61 Via (First Via) V22 Via (Second Via) V32 Via (Second Via) V42 Via (Second Via) VA1, VA2 Additional Via W1, W2 signal lines

Claims

1. A silicon substrate and The integrated circuit formed on the silicon substrate, A first seal ring is formed on the silicon substrate so as to surround the integrated circuit and is connected to the silicon substrate, A second seal ring is formed on the silicon substrate so as to surround the integrated circuit, is formed inside the first seal ring, and is capacitively coupled to the first seal ring, The integrated circuit, the first seal ring, and the polyimide formed on the silicon substrate so as to cover the second seal ring, A first pad formed as part of the integrated circuit and electrically connected to the first seal ring via a first signal line, A second pad formed as part of the integrated circuit and electrically connected to the second seal ring via a second signal line, A semiconductor chip equipped with this feature.

2. The first seal ring is Multiple first wirings formed within multiple stacked wiring layers, A plurality of first vias that electrically connect the plurality of first wirings to each other, It has, The second seal ring is Multiple second wirings formed on the stacked multiple wiring layers, A plurality of second vias that electrically connect the plurality of second wirings to each other, It has, In a cross-sectional view, one of the plurality of first wirings is positioned between two of the plurality of second wirings. In a cross-sectional view, one of the plurality of second wirings is positioned between two of the plurality of first wirings. The semiconductor chip according to claim 1.

3. Some or all of the plurality of first wirings and the plurality of second wirings are formed of aluminum or an aluminum-containing alloy. Some or all of the plurality of first vias and the plurality of second vias are formed of tungsten or a tungsten-containing alloy. The semiconductor chip according to claim 2.

4. Some or all of the plurality of first wirings and the plurality of second wirings are formed of copper or a copper-containing alloy. Some or all of the plurality of first vias and the plurality of second vias are formed of copper or a copper-containing alloy. The semiconductor chip according to claim 2.

5. The first wiring layer included in the plurality of wiring layers, One of the first wiring and the second wiring, and a lower wiring formed within the first wiring layer, A second wiring layer is included in the plurality of wiring layers, is in contact with the first wiring layer, and is located on the first wiring layer, The other of the first wiring and the second wiring, and the upper wiring formed within the second wiring layer, An insulating film is disposed between the lower wiring and the upper wiring, and is formed on the lower wiring. A first additional metal formed on the insulating film, A plurality of first additional vias electrically connect the first additional metal and the upper wiring, Furthermore, The semiconductor chip according to claim 2.

6. The first wiring layer included in the plurality of wiring layers, One of the first wiring and the second wiring, and a lower wiring formed within the first wiring layer, A second wiring layer is included in the plurality of wiring layers, is in contact with the first wiring layer, and is located on the first wiring layer, The other of the first wiring and the second wiring, and the upper wiring formed within the second wiring layer, A first additional metal is disposed between the lower wiring and the upper wiring and formed on the lower wiring, An insulating film formed on the first additional metal, A second additional metal formed on the insulating film, Multiple first additional vias electrically connect the second additional metal and the upper wiring, Furthermore, The semiconductor chip according to claim 2.

7. The aforementioned lower wiring is formed in a comb-like shape when viewed from above, The first additional metal, the insulating film, and the second additional metal are formed to cover a portion of the upper and side surfaces of each comb tooth of the comb-shaped lower wiring. The semiconductor chip according to claim 6.

8. The first additional metal, the insulating film, and the second additional metal are formed to further cover the side surfaces of the tips of each tooth of the comb-shaped lower wiring. The semiconductor chip according to claim 7.

9. The corners of the upper surface of the aforementioned lower wiring are chamfered. The semiconductor chip according to claim 7.

10. The second seal ring is The gate oxide film formed on the silicon substrate, A polysilicon film formed on the gate oxide film, A plurality of second additional vias electrically connect the second wiring formed in the lowest wiring layer among the plurality of wiring layers, and the polysilicon film. It further possesses, The semiconductor chip according to claim 2.

11. A portion of the upper surface of the silicon substrate has an uneven shape, The gate oxide film and the polysilicon film are formed to cover the upper surface of the silicon substrate which has an uneven shape. The semiconductor chip according to claim 10.

12. The second seal ring is composed of multiple electrically isolated sealing materials. The semiconductor chip according to claim 1.

13. The plurality of sealing materials are formed such that, when viewed from above, they are symmetrical with respect to a straight line passing through the center of the semiconductor chip. The semiconductor chip according to claim 12.

14. A third seal ring is formed on the silicon substrate so as to surround the integrated circuit, is formed inside the second seal ring, and is connected to the silicon substrate, A fourth seal ring is formed on the silicon substrate so as to surround the integrated circuit, is formed inside the third seal ring, and is capacitively coupled to the third seal ring, Furthermore, The semiconductor chip according to claim 1.

15. The plurality of first wirings of the first seal ring are formed in a comb-like shape when viewed from above, The plurality of second wirings of the second seal ring are formed in a comb-like shape when viewed from above, Of the plurality of first wirings and the plurality of second wirings, the first wirings and the second wirings formed on the same wiring layer are formed such that, in a top view, their comb teeth face each other and their comb teeth are positioned alternately. In a cross-sectional view, one of the plurality of first wirings is positioned between two of the plurality of second wirings. In a cross-sectional view, one of the plurality of second wirings is positioned between two of the plurality of first wirings. The semiconductor chip according to claim 2.

16. The integrated circuit further includes a detection circuit that detects whether a chipping crack has reached the first seal ring based on the electrical signal of the first pad and the electrical signal of the second pad. The semiconductor chip according to claim 1.

17. An external device detects whether a chipping crack has reached the first seal ring based on the electrical signal of the first pad and the electrical signal of the second pad. The semiconductor chip according to claim 1.

18. A step of preparing a semiconductor wafer including a semiconductor chip comprising: a silicon substrate; an integrated circuit formed on the silicon substrate; a first seal ring formed on the silicon substrate so as to surround the integrated circuit and connected to the silicon substrate; a second seal ring formed on the silicon substrate so as to surround the integrated circuit, formed inside the first seal ring and capacitively coupled to the first seal ring; a polyimide formed on the silicon substrate so as to cover the integrated circuit, the first seal ring, and the second seal ring; a first pad formed as part of the integrated circuit and electrically connected to the first seal ring via a first signal line; and a second pad formed as part of the integrated circuit and electrically connected to the second seal ring via a second signal line; A step of cutting out the semiconductor chip from the semiconductor wafer, A step of detecting whether a chipping crack has reached the first seal ring based on the electrical signals of the first pad and the second pad, A method for manufacturing semiconductor chips, comprising the following features.

19. The process further includes, after the step of preparing the semiconductor wafer and before the step of cutting the semiconductor chip from the semiconductor wafer, measuring the capacitance values ​​of the first seal ring and the second seal ring based on the electrical signals of the first pad and the electrical signals of the second pad, In the step of detecting whether or not the chipping crack has reached the first seal ring, Based on the electrical signals of the first pad and the second pad of the semiconductor chip after it has been cut from the semiconductor wafer, the capacitance values ​​of the first seal ring and the second seal ring are measured. By comparing the capacitance value of the semiconductor chip before cutting with the capacitance value of the semiconductor chip after cutting, it is detected whether or not the chipping crack has reached the first seal ring. A method for manufacturing a semiconductor chip according to claim 18.

20. In the step of detecting whether or not the chipping crack has reached the first seal ring, Based on the electrical signals of the first pad and the second pad of the semiconductor chip after it has been cut from the semiconductor wafer, the capacitance values ​​of the first seal ring and the second seal ring are measured. By comparing a preset capacity value with the capacity values ​​of the first and second seal rings, it is detected whether or not a chipping crack has reached the first seal ring. A method for manufacturing a semiconductor chip according to claim 18.

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