Pixel circuits and electronic devices

Abstract

To provide pixel circuits and electronic devices with improved light emission reliability. [Solution] The pixel circuit PXA includes a transistor T1 that generates a drive current based on the voltage of node N1 and has an electrode connected to node N1, an electrode to which a power supply voltage ELVDD is applied, and an electrode connected to node N2; a transistor T2 that provides a data voltage VDATA to transistor T1 in response to a write gate signal GW[n]; a transistor that has an electrode to which a control signal is applied, an electrode connected to node N2, and an electrode connected to node N4; a transistor T4 that responds to a light emission signal EM; a transistor T5 that provides an initialization voltage VINT to node N5 in response to a bias signal EB; and a light-emitting element EE that has an electrode connected to node N5 and an electrode to which a power supply voltage ELVSS is applied, wherein the control signal CB is a DC voltage.

Description

Technical Field

[0001] The present invention relates to a pixel circuit and an electronic device including the pixel circuit, and more particularly, to a pixel circuit with improved light emission reliability and an electronic device including the pixel circuit.

Background Art

[0002] Generally, a display device includes a display panel and a display panel driving unit. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of light emission lines, and a plurality of pixels. The display panel driving unit includes a gate driving unit that provides a gate signal to the plurality of gate lines, a data driving unit that provides a data voltage to the data lines, a light emission driving unit that provides a light emission signal to the light emission lines, and a driving control unit that controls the gate driving unit, the data driving unit, and the light emission driving unit.

[0003] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have been prominent. For this purpose, display devices are required to have a low area and a high integration density. In this case, since the pitch occupied by the pixel circuit becomes narrow, there are restrictions on the number of transistors constituting the pixel circuit and the number of signals applied to the pixel circuit.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a pixel circuit with improved light emission reliability.

[0005] Another object of the present invention is to provide a display device including the pixel circuit.

[0006] Still another object of the present invention is to provide an electronic device including the pixel circuit.

[0007] However, the object of the present invention is not limited to the problems mentioned above, and can be extended in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0008] The pixel circuit according to the present invention includes a drive transistor that generates a drive current based on the voltage of the first node, comprising a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node; a write transistor that applies a data voltage to the drive transistor in response to a write gate signal; a control transistor to which a control signal is applied, comprising a first electrode connected to the second node and a second electrode connected to a fourth node; a light-emitting transistor that connects the fourth node and the fifth node in response to a light-emitting signal; a light-emitting element initializing transistor that applies an initialization voltage to the fifth node in response to a bias signal; and a light-emitting element comprising a first electrode connected to the fifth node and a second electrode to which a second power supply voltage is applied. The control signal is a DC voltage.

[0009] The DC voltage is the voltage that turns on the control transistor.

[0010] The frame interval in which the pixel circuit is driven includes a write interval, a hold interval, and an illumination interval. In the write interval, the write gate signal has an activation level. In the hold interval, the bias signal has an activation level, and the illumination signal has an activation level. In the illumination interval, the drive current is supplied to the fifth node.

[0011] During the holding interval, the control transistor turns on, the light-emitting transistor turns on, and the control transistor turns on.

[0012] The pixel circuit further includes a storage capacitor having a first electrode connected to the first node and a second electrode connected to the third node; a first initialization transistor that provides a reference voltage to the third node in response to an initialization gate signal; a second initialization transistor that provides the reference voltage to the first node in response to a previous stage write gate signal; and a compensation transistor that connects the first node and the second node in response to the write gate signal. The write transistor provides the data voltage to the third node in response to the write gate signal.

[0013] The frame interval in which the pixel circuit is driven includes a first to a fourth interval. In the first interval, the bias signal has an activation level, the light emission signal has a deactivation level, the pre-stage write gate signal has an activation level, and the initialization gate signal has an activation level.

[0014] In the second section following the first section, the bias signal has an activation level, the light emission signal has an inactivation level, the pre-stage write gate signal has an inactivation level, the initialization gate signal has an inactivation level, and the write gate signal has an activation level.

[0015] In the second section, the drive transistor and the compensation transistor are turned on.

[0016] In the third section following the second section, the bias signal has an activation level, the light emission signal has an activation level, and the write gate signal has a deactivation level.

[0017] In the third interval, the light-emitting transistor is turned on, the light-emitting transistor is turned on, and the control transistor is turned on.

[0018] In the fourth section following the third section, the bias signal has a deactivation level, and the light emission signal has an activation level.

[0019] During the first to fourth intervals, the control signal maintains the control voltage.

[0020] The write transistor includes a control electrode to which the write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node. The compensation transistor includes a control electrode to which the write gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node. The light-emitting transistor includes a control electrode to which the light-emitting signal is applied, a first electrode connected to the fourth node, and a second electrode connected to the fifth node. The light-emitting element initializing transistor includes a control electrode to which the bias signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the fifth node. The first initializing transistor includes a control electrode to which the initialization gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the third node. The second initializing transistor includes a control electrode to which the previous stage write gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node. The control transistor includes a control electrode to which the control signal is applied, a first electrode connected to the second node, and a second electrode connected to the fourth node.

[0021] The pixel circuit according to the present invention includes a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, and includes a drive transistor that generates a drive current based on the voltage of the first node, a write transistor that applies a data voltage to the drive transistor in response to a write gate signal, a light-emitting transistor that connects the second node and a fourth node in response to a light-emitting signal, a light-emitting element initializing transistor that applies an initialization voltage to the fourth node in response to a bias signal, and a light-emitting element that includes a first electrode connected to the fourth node and a second electrode to which a second power supply voltage is applied. The light-emitting signal transitions between a first light-emitting voltage and a second light-emitting voltage lower than the first light-emitting voltage. The absolute value of the second light-emitting voltage is smaller than the sum of the voltage of the second electrode of the drive transistor and the second power supply voltage minus the absolute value of the threshold voltage of the light-emitting transistor.

[0022] The frame interval in which the pixel circuit is driven includes a write interval, a hold interval, and an illumination interval. In the write interval, the write gate signal has an activation level. In the hold interval, the bias signal has an activation level, and the illumination signal has an activation level. In the illumination interval, the drive current is supplied to the fourth node.

[0023] In the light-emitting section, the light-emitting signal has a third light-emitting voltage that is lower than the second light-emitting voltage.

[0024] The pixel circuit further includes a storage capacitor having a first electrode connected to the first node and a second electrode connected to the third node; a first initialization transistor that provides a reference voltage to the third node in response to an initialization gate signal; a second initialization transistor that provides the reference voltage to the first node in response to a previous stage write gate signal; and a compensation transistor that connects the first node and the second node in response to the write gate signal. The write transistor provides the data voltage to the third node in response to the write gate signal.

[0025] The frame period during which the pixel circuit is driven includes first to fourth periods. In the first period, the bias signal has an activation level, the light emission signal has a non-activation level, the pre-stage write gate signal has an activation level, and the initialization gate signal has an activation level.

[0026] In the second period after the first period, the bias signal has an activation level, the light emission signal has a non-activation level, the pre-stage write gate signal has a non-activation level, the initialization gate signal has a non-activation level, and the write gate signal has an activation level.

[0027] In the third period after the second period, the bias signal has an activation level, the light emission signal has an activation level, and the write gate signal has a non-activation level.

[0028] In the fourth period after the third period, the bias signal has a non-activation level, and the light emission signal has an activation level.

[0029] The pixel circuit according to the present invention includes a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, and includes a driving transistor that generates a driving current based on the voltage of the first node, a writing transistor that applies a data voltage to the driving transistor in response to a writing gate signal, a light-emitting transistor that connects the second node and a fourth node in response to a light-emitting signal, a light-emitting element initialization transistor that applies an initialization voltage to the fourth node in response to a bias signal, and a light-emitting element including a first electrode connected to a fifth node and a second electrode to which a second power supply voltage is applied. The light-emitting signal transitions between a first light-emitting voltage and a second light-emitting voltage lower than the first light-emitting voltage. The writing gate signal transitions between a first gate voltage and a second gate voltage lower than the first gate voltage. The absolute value of the second light-emitting voltage is lower than the absolute value of the second gate voltage.

[0030] The frame period during which the pixel circuit is driven includes a writing period, a holding period, and a light-emitting period. In the writing period, the writing gate signal has an activation level. In the holding period, the bias signal has an activation level and the light-emitting signal has an activation level. In the light-emitting period, the driving current is applied to the fourth node.

[0031] The pixel circuit further includes a storage capacitor including a first electrode connected to the first node and a second electrode connected to a third node, a first initialization transistor that applies a reference voltage to the third node in response to an initialization gate signal, a second initialization transistor that applies the reference voltage to the first node in response to a previous-stage writing gate signal, and a compensation transistor that connects the first node and the second node in response to the writing gate signal. The writing transistor applies the data voltage to the third node in response to the writing gate signal.

[0032] The display device according to the present invention includes a display panel including a pixel circuit, a gate drive unit that outputs a gate signal to the pixel circuit, a light emission drive unit that outputs a light emission signal to the pixel circuit, a data drive unit that supplies a data voltage to the display panel, a voltage generation unit that supplies a power supply voltage to the display panel, and a drive control unit that controls the gate drive unit, the light emission drive unit, the data drive unit, and the voltage generation unit. The pixel circuit includes a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, and includes a drive transistor that generates a drive current based on the voltage of the first node, a write transistor that applies the data voltage to the drive transistor in response to a write gate signal, a control electrode to which a control signal is applied, a control transistor including a first electrode connected to the second node and a second electrode connected to the fourth node, a light-emitting transistor that connects the fourth node and the fifth node in response to a light-emitting signal, a light-emitting element initializing transistor that applies an initialization voltage to the fifth node in response to a bias signal, and a light-emitting element including a first electrode connected to the fifth node and a second electrode to which a second power supply voltage is applied. The voltage generation unit outputs the control signal. The control signal is a DC voltage.

[0033] The DC voltage is the voltage that turns on the control transistor.

[0034] The frame interval in which the pixel circuit is driven includes a write interval, a hold interval, and an illumination interval. In the write interval, the write gate signal has an activation level. In the hold interval, the bias signal has an activation level, and the illumination signal has an activation level. In the illumination interval, the drive current is supplied to the fifth node.

[0035] During the holding interval, the control transistor turns on, the light-emitting transistor turns on, and the light-emitting element initialization transistor turns on.

[0036] The electronic device according to the present invention includes a display panel including a pixel circuit, a gate drive unit that outputs a gate signal to the pixel circuit, a light-emitting drive unit that outputs a light-emitting signal to the pixel circuit, a data drive unit that supplies a data voltage to the display panel, a voltage generation unit that supplies a power supply voltage to the display panel, a drive control unit that controls the gate drive unit, the light-emitting drive unit, the data drive unit, and the voltage generation unit based on an input control signal, and a processor that outputs the input control signal. The pixel circuit includes a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, and includes a drive transistor that generates a drive current based on the voltage of the first node, a write transistor that applies the data voltage to the drive transistor in response to a write gate signal, a control electrode to which a control signal is applied, a control transistor comprising a first electrode connected to the second node and a second electrode connected to the fourth node, a light-emitting transistor that connects the fourth node and the fifth node in response to the light-emitting signal, a light-emitting element initializing transistor that applies an initialization voltage to the fifth node in response to a bias signal, and a light-emitting element comprising a first electrode connected to the fifth node and a second electrode to which a second power supply voltage is applied. The voltage generation unit outputs the control signal. The control signal is a DC voltage. [Effects of the Invention]

[0037] According to the pixel circuit and display device including the present invention, the light-emitting transistor of the pixel circuit is weakly turned on. Because the light-emitting transistor is weakly turned on, the voltage change at the second node to which the second electrode of the drive transistor is connected is reduced during the light-emitting standby section (e.g., the holding section). Because the voltage change at the second node is reduced during the holding section, the voltage change at the first node to which the control electrode of the drive transistor is connected, due to the coupling of the voltage change at the second node, is reduced. This improves the reliability of the drive current generated by the drive transistor. Because the reliability of the drive current is improved, the light emission reliability of the pixel circuit can be further improved.

[0038] However, the effects of the present invention are not limited to those mentioned above, and can be extended in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawing]

[0039] [Figure 1] Figure 1 is a block diagram of a display device according to one embodiment of the present invention. [Figure 2] Figure 2 is a circuit diagram showing an example of the pixel circuit included in the display device shown in Figure 1. [Figure 3] Figure 3 is a timing diagram showing the input signals applied to the pixel circuit in Figure 2. [Figure 4] Figure 4 is a circuit diagram showing the operation of the pixel circuit in Figure 2 in the first section of Figure 3. [Figure 5] Figure 5 is a circuit diagram showing the operation of the pixel circuit in Figure 2 in the second section of Figure 3. [Figure 6] Figure 6 is a circuit diagram showing the operation of the pixel circuit in Figure 2 in the third section of Figure 3. [Figure 7] Figure 7 is a circuit diagram showing the operation of the pixel circuit in Figure 2 in the fourth section of Figure 3. [Figure 8] Figure 8 is a timing diagram showing the input signals applied to the pixel circuit in Figure 2. [Figure 9] Figure 9 is a circuit diagram showing the operation of the pixel circuit in the third section of Figure 8. [Figure 10] Figure 10 is a circuit diagram showing the operation of the pixel circuit in the fourth section of Figure 8. [Figure 11] Figure 11 is a circuit diagram showing an example of the pixel circuit included in the display device shown in Figure 1. [Figure 12] Figure 12 is a timing diagram showing the input signals applied to the pixel circuit in Figure 11. [Figure 13] Figure 13 is a circuit diagram showing the operation of the pixel circuit in Figure 11 in the first section of Figure 12. [Figure 14] Figure 14 is a circuit diagram showing the operation of the pixel circuit in Figure 11 in the second section of Figure 12. [Figure 15]Figure 15 is a circuit diagram showing the operation of the pixel circuit in Figure 11 in the third section of Figure 12. [Figure 16] Figure 16 is a circuit diagram showing the operation of the pixel circuit in Figure 11 in the fourth section of Figure 12. [Figure 17] Figure 17 is a diagram showing an example of how the pixel circuits included in the display device shown in Figure 1 are arranged on a substrate. [Figure 18] Figure 18 is a block diagram showing an electronic device according to one embodiment of the present invention. [Figure 19] Figure 19 shows an example of how the electronic device in Figure 18 is implemented in a smartphone. [Figure 20] Figure 20 shows an example of the electronic device shown in Figure 18 being realized in a virtual reality display system. [Modes for carrying out the invention]

[0040] The present invention will be described in more detail below with reference to the attached drawings.

[0041] Figure 1 is a block diagram showing a display device 1 according to one embodiment of the present invention.

[0042] As shown in Figure 1, the display device 1 includes a display panel 100 and a display panel drive unit. The display panel drive unit includes a drive control unit 200, a gate drive unit 300, a gamma reference voltage generation unit 400, a data drive unit 500, a light emission drive unit 600, and a voltage generation unit 700.

[0043] The display panel 100 includes a display unit for displaying images and a peripheral unit arranged adjacent to the display unit.

[0044] The display panel 100 includes gate lines (GL), data lines (DL), light-emitting lines (EL), and pixel circuits (PX) electrically connected to the gate lines (GL), data lines (DL), and light-emitting lines (EL). The gate lines (GL) extend in a first direction (D1). The data lines (DL) extend in a second direction (D2) that intersects the first direction (D1). The light-emitting lines (EL) extend in the first direction (D1).

[0045] The drive control unit 200 receives input image data (IMG) and input control signals (CONT) from an external device. For example, the input image data (IMG) includes red image data, green image data, and blue image data. The input image data (IMG) includes white image data. The input image data (IMG) includes magenta image data, yellow image data, and cyan image data. The input control signals (CONT) include a master clock signal and a data enable signal. The input control signals (CONT) further include a vertical synchronization signal and a horizontal synchronization signal.

[0046] The drive control unit 200 generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), a fifth control signal (CONT5), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0047] The drive control unit 200 generates a first control signal (CONT1) for controlling the operation of the gate drive unit 300 based on the input control signal (CONT), and outputs it to the gate drive unit 300. The first control signal (CONT1) includes a vertical start signal and a gate clock signal.

[0048] The drive control unit 200 generates a second control signal (CONT2) for controlling the operation of the data drive unit 500 based on the input control signal (CONT), and outputs it to the data drive unit 500. The second control signal (CONT2) includes a horizontal start signal and a load signal.

[0049] The drive control unit 200 generates a data signal (DATA) based on the input image data (IMG). The drive control unit 200 outputs the data signal (DATA) to the data drive unit 500.

[0050] The drive control unit 200 generates a third control signal (CONT3) to control the operation of the gamma reference voltage generation unit 400 based on the input control signal (CONT), and outputs it to the gamma reference voltage generation unit 400.

[0051] The drive control unit 200 generates a fourth control signal (CONT4) for controlling the operation of the light-emitting drive unit 600 based on the input control signal (CONT), and outputs it to the light-emitting drive unit 600. The fourth control signal (CONT4) includes a vertical start signal and a light-emitting clock signal. In one embodiment, the gate clock signal and the light-emitting clock signal are substantially the same.

[0052] The drive control unit 200 generates a fifth control signal (CONT5) to control the operation of the voltage generation unit 700 based on the input control signal (CONT), and outputs it to the gate drive unit 300.

[0053] The gate drive unit 300 generates a gate signal for driving the gate line (GL) in response to a first control signal (CONT1) input from the drive control unit 200. The gate drive unit 300 generates the gate signal based on the power supply voltage (DV) supplied from the voltage generation unit 700. For example, the gate drive unit 300 generates the gate signal based on the gate high voltage and the gate low voltage. The gate drive unit 300 outputs the gate signal to the gate line (GL). For example, the gate signal includes an initialization gate signal (GI in Figure 2), a write gate signal (GW[n] in Figure 2), a previous stage write gate signal (GW[n-1] in Figure 2), and a bias signal (EB in Figure 2). For example, the gate signal transitions between a first gate voltage and a second gate voltage lower than the first gate voltage. For example, the bias signal (EB) is referred to as the light-emitting element initialization gate signal. For example, the bias signal (EB) is referred to as the bias gate signal.

[0054] In one embodiment, the gate drive unit 300 is integrated into the peripheral part of the display panel 100. In one embodiment, the gate drive unit 300 is mounted on the peripheral part of the display panel 100.

[0055] The gamma reference voltage generation unit 400 generates a gamma reference voltage (VGREF) in response to a third control signal (CONT3) input from the drive control unit 200. The gamma reference voltage generation unit 400 provides the gamma reference voltage (VGREF) to the data drive unit 500. The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0056] For example, the gamma reference voltage generation unit 400 is located within the drive control unit 200 or within the data drive unit 500.

[0057] The data drive unit 500 receives a second control signal (CONT2) and a data signal (DATA) from the drive control unit 200, and a gamma reference voltage (VGREF) from the gamma reference voltage generation unit 400. The data drive unit 500 converts the data signal (DATA) into an analog data voltage (VDATA) using the gamma reference voltage (VGREF). The data drive unit 500 outputs the data voltage (VDATA) to a data line (DL).

[0058] In one embodiment, the data drive unit 500 is integrated into the peripheral part of the display panel 100. In one embodiment, the data drive unit 500 is mounted on the peripheral part of the display panel 100.

[0059] The light-emitting drive unit 600 generates a light-emitting signal (EM in Figure 2) in response to a fourth control signal (CONT4) input from the drive control unit 200. The light-emitting drive unit 600 outputs the light-emitting signal (EM in Figure 2) to the display panel 100. The light-emitting drive unit 600 generates the light-emitting signal (EM in Figure 2) based on the power supply voltage (DV) supplied from the voltage generation unit 700. For example, the light-emitting drive unit 600 generates the light-emitting signal (EM in Figure 2) based on a light-emitting high voltage and a light-emitting low voltage. In one embodiment, the light-emitting low voltage is higher than the gate low voltage. In one embodiment, the activation level of the light-emitting signal (EM in Figure 2) is higher than the activation level of the write gate signal (GW[n] in Figure 2). In one embodiment, the absolute value of the activation level of the light-emitting signal (EM in Figure 2) (e.g., the second light-emitting voltage) is lower than the absolute value of the second gate voltage.

[0060] In one embodiment, the light-emitting drive unit 600 is integrated into the peripheral part of the display panel 100. In one embodiment, the light-emitting drive unit 600 is mounted on the peripheral part of the display panel 100.

[0061] In Figure 1, for the sake of explanation, the gate drive unit 300 is shown to be located on the first side of the display panel 100 and the light-emitting drive unit 600 is shown to be located on the second side of the display panel 100, but the present invention is not limited thereto. For example, the gate drive unit 300 and the light-emitting drive unit 600 may be located on the first side of the display panel 100. For example, the gate drive unit 300 and the light-emitting drive unit 600 may be located on both sides of the display panel 100. For example, the gate drive unit 300 and the light-emitting drive unit 600 may be formed integrally.

[0062] The voltage generation unit 700 outputs a power supply voltage (DV) in response to a fifth control signal (CONT5) input from the drive control unit 200. For example, the power supply voltage (DV) includes a first power supply voltage (ELVDD), a second power supply voltage (ELVSS), a gate high voltage, a gate low voltage, a light emission high voltage, and a light emission low voltage. The voltage generation unit 700 outputs the power supply voltage (DV) to the display panel 100, the gate drive unit 300, and the light emission drive unit 600.

[0063] Figure 2 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 shown in Figure 1.

[0064] As shown in Figures 1 and 2, the pixel circuit (PXA) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a storage capacitor (CST), and a light-emitting element (EE).

[0065] The first transistor (T1) includes a control electrode connected to a first node (N1), a first electrode to which a first power supply voltage (ELVDD) is applied, and a second electrode connected to a second node (N2). The first transistor (T1) generates a drive current based on the voltage at the first node (N1). The first transistor (T1) supplies the drive current to the second node (N2) in response to the voltage at the first node (N1). For example, the first transistor (T1) is referred to as the drive transistor.

[0066] The second transistor (T2) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode to which a data voltage (VDATA) is applied, and a second electrode connected to a third node (N3). The second transistor (T2) applies the data voltage (VDATA) to the third node (N3) in response to the write gate signal (GW[n]). For example, the second transistor (T2) is referred to as the write transistor.

[0067] The third transistor (T3) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode connected to a second node (N2), and a second electrode connected to a first node (N1). In response to the write gate signal (GW[n]), the third transistor (T3) connects the first node (N1) and the second node (N2). In response to the write gate signal (GW[n]), the third transistor (T3) diode-connects the first transistor (T1). For example, the third transistor (T3) is called a compensation transistor.

[0068] The fourth transistor (T4) includes a control electrode to which a light emission signal (EM) is applied, a first electrode connected to the second node (N2), and a second electrode connected to the fourth node (N4). In response to the light emission signal (EM), the fourth transistor (T4) connects the second node (N2) and the fourth node (N4). In response to the light emission signal (EM), the fourth transistor (T4) supplies a drive current to the fourth node (N4). For example, the fourth transistor (T4) is referred to as a light-emitting transistor.

[0069] The fifth transistor (T5) includes a control electrode to which a bias signal (EB) is applied, a first electrode connected to the fourth node (N4), and a second electrode to which an initialization voltage (VINT) is applied. In response to the bias signal (EB), the fifth transistor (T5) applies the initialization voltage (VINT) to the fourth node (N4). For example, the fifth transistor (T5) is referred to as an luminescent-emitting element initialization transistor.

[0070] In one embodiment, the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS). For example, the value of the initialization voltage (VINT) is less than the sum of the second power supply voltage (ELVSS) and the threshold voltage of the light-emitting element (EE), minus the absolute value of the threshold voltage of the fifth transistor (T5). As a result, when the initialization voltage (VINT) is applied to the fourth node (N4), the light-emitting element (EE) does not emit light. For example, when the initialization voltage (VINT) is applied to the fourth node (N4), the pixel circuit (PXA) displays black. Because the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS), the black characteristics of the pixel circuit (PXA) are improved.

[0071] The sixth transistor (T6) includes a control electrode to which an initialization gate signal (GI) is applied, a first electrode to which a reference voltage (VREF) is applied, and a second electrode connected to a third node (N3). In response to the initialization gate signal (GI), the sixth transistor (T6) applies the reference voltage (VREF) to the third node (N3). For example, the sixth transistor (T6) is referred to as the first initialization transistor.

[0072] The seventh transistor (T7) includes a control electrode to which the previous stage write gate signal (GW[n-1]) is applied, a first electrode to which a reference voltage (VREF) is applied, and a second electrode connected to the first node (N1). In response to the previous stage write gate signal (GW[n-1]), the seventh transistor (T7) applies the reference voltage (VREF) to the third node (N3). For example, the seventh transistor (T7) is referred to as the second initialization transistor.

[0073] A storage capacitor (CST) includes a first electrode connected to a third node (N3) and a second electrode connected to a first node (N1). The storage capacitor (CST) stores the difference between the voltage at the first node (N1) and the voltage at the third node (N3). The storage capacitor (CST) couples the voltage change at the third node (N3) and provides the coupled voltage to the first node (N1). For example, the storage capacitor (CST) is referred to as the first storage capacitor.

[0074] The light-emitting element (EE) includes a first electrode connected to a fourth node (N4) and a second electrode to which a second power supply voltage (ELVSS) is applied. In one embodiment, the light-emitting element (EE) is, but is not limited to, an organic light-emitting diode (OLED). In other embodiments, the light-emitting element (EE) is a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0075] Figure 3 is a timing diagram showing the input signals applied to the pixel circuit (PXA) in Figure 2.

[0076] The frame interval in which the pixel circuit (PXA) is driven includes a first interval (TP1A), a second interval (TP2A), a third interval (TP3A), and a fourth interval (TP4A).

[0077] In the first section (TP1A), the bias signal (EB) has an activation level. The light emission signal (EM) has a deactivation level. The previous stage write gate signal (GW[n-1]) has an activation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. For example, the first section (TP1A) is referred to as the initialization section.

[0078] In the second section (TP2A), the bias signal (EB) has an activation level. The light emission signal (EM) has a deactivation level. The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has a deactivation level. The write gate signal (GW[n]) has an activation level. For example, the second section (TP2A) is referred to as the write section.

[0079] In the third interval (TP3A), the bias signal (EB) has an activation level. The light emission signal (EM) has an activation level. The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. For example, the third interval (TP3A) is called the hold interval.

[0080] In the fourth section (TP4A), the bias signal (EB) has an inactivation level. The light emission signal (EM) has an activation level. The previous stage write gate signal (GW[n-1]) has an inactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has an inactivation level. For example, the fourth section (TP4A) is referred to as the light emission section.

[0081] Figure 4 is a circuit diagram showing the operation of the pixel circuit (PXA) in Figure 2 in the first section (TP1A) of Figure 3.

[0082] As shown in Figures 3 and 4, in the first section (TP1A), the sixth transistor (T6) turns on in response to the initialization gate signal (GI). Since the sixth transistor (T6) is turned on, the reference voltage (VREF) is applied to the third node (N3). In response to the previous stage write gate signal (GW[n-1]), the seventh transistor (T7) turns on. Since the seventh transistor (T7) is turned on, the reference voltage (VREF) is applied to the first node (N1). For example, the first node (N1) is initialized to the reference voltage (VREF). For example, the third node (N3) is initialized to the reference voltage (VREF). Since the reference voltage (VREF) is applied to the first node (N1) and the reference voltage (VREF) is applied to the third node (N3), the voltage at the first node (N1) and the voltage at the third node (N3) are substantially the same. This initializes the storage capacitor (CST).

[0083] In the first section (TP1A), the first transistor (T1) is turned on based on the voltage at the first node (N1).

[0084] In the first section (TP1A), the fifth transistor (T5) turns on in response to the bias signal (EB). Because the fifth transistor (T5) is turned on, an initialization voltage (VINT) is applied to the fourth node (N4). Because an initialization voltage (VINT) is applied to the fourth node (N4), the light-emitting element (EE) stops emitting light.

[0085] Figure 5 is a circuit diagram showing the operation of the pixel circuit (PXA) in Figure 2 during the second section (TP2A) of Figure 3.

[0086] As shown in Figures 3 and 5, in the second section (TP2A), the second transistor (T2) turns on in response to the write gate signal (GW[n]). Since the second transistor (T2) is turned on, the data voltage (VDATA) is supplied to the third node (N3).

[0087] In the second section (TP2A), the third transistor (T3) turns on in response to the write gate signal (GW[n]). Because the third transistor (T3) is turned on, the first transistor (T1) is connected in diode mode. Because the first transistor (T1) is connected in diode mode, the voltage obtained by adding the threshold voltage of the first transistor (T1) and the first power supply voltage (ELVDD) is applied to the first node (N1). For example, the voltage obtained by adding the threshold voltage of the first transistor (T1) and the first power supply voltage (ELVDD) is called the compensation voltage. The storage capacitor (CST) stores the difference between the data voltage (VDATA) and the compensation voltage.

[0088] In this embodiment, the first electrode of the first transistor (T1) is the source electrode. Furthermore, the data voltage (VDATA) is not written through the source electrode of the first transistor (T1). The source electrode of the first transistor (T1) is supplied with a first power supply voltage (ELVDD). For example, only the first power supply voltage (ELVDD) can be supplied to the source electrode of the first transistor (T1). As a result, the voltage supplied to the source electrode of the first transistor (T1) remains constant. Since the voltage supplied to the source electrode of the first transistor (T1) remains constant, the threshold voltage of the first transistor (T1) is substantially the same throughout the frame interval. Therefore, the accuracy of the compensation voltage is improved. Because the accuracy of the compensation voltage is improved, the driving reliability and light emission reliability of the pixel circuit (PXA) can be further improved.

[0089] In the second interval (TP2A), the ON state of the fifth transistor (T5) is maintained in response to a bias signal (EB) having an activation level.

[0090] Figure 6 is a circuit diagram showing the operation of the pixel circuit (PXA) in Figure 2 during the third section (TP3A) of Figure 3.

[0091] As shown in Figures 3 and 6, in the third interval (TP3A), the sixth transistor (T6) turns on in response to the initialization gate signal (GI). As the sixth transistor (T6) turns on, a reference voltage (VREF) is applied to the third node (N3). In response to the write gate signal (GW[n]), the third transistor (T3) turns off. As the third transistor (T3) turns off, the first node (N1) becomes floating. The storage capacitor (CST) couples the voltage change at the third node (N3). The storage capacitor (CST) couples the voltage change at the third node (N3) and applies the coupled voltage to the first node (N1). As the coupled voltage is applied to the first node (N1), the first node (N1) can have a voltage that takes into account the compensation voltage and the data voltage (VDATA).

[0092] In the third section (TP3A), the first transistor (T1) generates a drive current based on the voltage at the first node (N1).

[0093] In the third interval (TP3A), the fourth transistor (T4) turns on in response to the light emission signal (EM). Also, the fifth transistor (T5) remains in the ON state in response to the bias signal (EB). As a result, the light-emitting element (EE) does not emit light.

[0094] Figure 7 is a circuit diagram showing the operation of the pixel circuit (PXA) in Figure 2 during the fourth section (TP4A) of Figure 3.

[0095] As shown in Figures 3 and 7, in the fourth section (TP4A), the fifth transistor (T5) is turned off in response to the bias signal (EB). This provides a drive current to the light-emitting element (EE). In the fourth section (TP4A), the light-emitting element (EE) emits light based on the drive current.

[0096] As shown in Figures 1 to 7, in conventional pixel circuits, the reliability of the current supplied to the conventional light-emitting element within the conventional pixel circuit is reduced in the light-emitting section due to the parasitic capacitance of at least one of the transistors included in the conventional pixel circuit. For example, when a conventional pixel circuit must display black, the parasitic capacitance supplies current to the conventional light-emitting element. This allows the conventional light-emitting element to emit light. When a conventional pixel circuit must display black, the conventional light-emitting element emits light, resulting in a decrease in display quality.

[0097] In contrast, the frame interval in which the pixel circuit (PXA) is driven includes a third interval (TP3A). In the third interval (TP3A), current flows along the path formed by the first transistor (T1), the fourth transistor (T4), and the fifth transistor (T5). This reduces the effect of parasitic capacitance in the light-emitting interval. For example, if the pixel circuit (PXA) is to display black, the effect of parasitic capacitance is reduced, and the light-emitting element (EE) does not emit light. This improves the light-emitting reliability of the pixel circuit (PXA). As the light-emitting reliability of the pixel circuit (PXA) is improved, the display quality of the display panel 100 is improved.

[0098] In this embodiment, the deactivation level of the light emission signal (EM) has a first light emission voltage (VEM1), and the activation level of the light emission signal (EM) has a second light emission voltage (VEM2) that is lower than the first light emission voltage (VEM1). For example, the high light emission voltage corresponds to the first light emission voltage (VEM1). For example, the low light emission voltage corresponds to the second light emission voltage (VEM2). The second light emission voltage (VEM2) is set based on the drive voltage of the light-emitting element (EE). The second light emission voltage (VEM2) is set based on the source-drain voltage of the drive transistor. The drive voltage of the light-emitting element (EE) means the voltage applied to the first electrode (e.g., anode) of the light-emitting element (EE) based on the drive current. For example, the second light emission voltage (VEM2) is set to the value obtained by subtracting the threshold voltage of the fourth transistor (T4) from the sum of the second power supply voltage (ELVSS) and the drive voltage. For example, the second light-emitting voltage (VEM2) is set to a voltage higher than the value obtained by subtracting the threshold voltage of the fourth transistor (T4) from the sum of the second power supply voltage (ELVSS) and the drive voltage (e.g., the lower limit voltage). For example, the absolute value of the second light-emitting voltage (VEM2) is smaller than the value obtained by subtracting the absolute value of the threshold voltage of the fourth transistor (T4) from the sum of the voltage at the second electrode of the drive transistor and the second power supply voltage (ELVSS). For example, the second light-emitting voltage (VEM2) is the voltage obtained by subtracting the threshold voltage of the fourth transistor (T4) from the first light-emitting voltage (VEM1). For example, the second light-emitting voltage (VEM2) is set to a voltage lower than the value obtained by subtracting the source / drain voltage of the first transistor (T1) and the threshold voltage of the fourth transistor (T4) from the first power supply voltage (ELVDD) (e.g., the upper limit voltage). For example, the second light emission voltage (VEM2) is set to a voltage between the lower limit voltage and the upper limit voltage.

[0099] As a result, in this embodiment, the control electrode of the fourth transistor (T4) of the pixel circuit (PXA) is subjected to a light emission signal (EM) having a higher activation level than the activation level of the light emission signal applied to the light emission transistor of a conventional pixel circuit. For example, the absolute value of the second light emission voltage (VEM2) of the light emission signal (EM) is lower than the absolute value of the voltage corresponding to the activation level of the light emission signal applied to a conventional light emission transistor. As a result, the fourth transistor (T4) is weakly turned on.

[0100] During the hold interval, the first node (N1), to which the initial voltage (VINT) is applied to the second node (N2), is coupled to the voltage change of the second node (N2). This causes the voltage of the first node (N1) to change. When the voltage of the first node (N1) changes during the hold interval, the reliability of the drive current decreases. When the reliability of the drive current decreases, the light emission reliability of the pixel circuit decreases.

[0101] In this embodiment, the fourth transistor (T4) is weakly turned on, so the voltage change at the second node (N2) is reduced during the holding period. Since the voltage change at the second node (N2) is reduced during the holding period, the voltage change at the first node (N1) due to the coupling of the voltage change at the second node (N2) is reduced. This improves the reliability of the drive current. Since the reliability of the drive current is improved, the light emission reliability of the pixel circuit (PXA) is further improved.

[0102] Figure 8 is a timing diagram showing the input signals applied to the pixel circuit (PXA) in Figure 2. Figure 9 is a circuit diagram showing the operation of the pixel circuit (PXA) in the third section (TP3B) of Figure 8. Figure 10 is a circuit diagram showing the operation of the pixel circuit (PXA) in the fourth section (TP4B) of Figure 8.

[0103] As shown in Figures 1, 2, and 10, the frame interval in which the pixel circuit (PXA) is driven includes a first interval (TP1B), a second interval (TP2B), a third interval (TP3B), and a fourth interval (TP4B).

[0104] In the first interval (TP1B), the bias signal (EB) has an activation level. The light emission signal (EM) has a first light emission voltage (VEM1). The previous stage write gate signal (GW[n-1]) has an activation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. For example, the first interval (TP1B) is referred to as the initialization interval.

[0105] In the second section (TP2B), the bias signal (EB) has an activation level. The light emission signal (EM) has a first light emission voltage (VEM1). The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has a deactivation level. The write gate signal (GW[n]) has an activation level. For example, the second section (TP2B) is referred to as the write section.

[0106] In the third interval (TP3B), the bias signal (EB) has an activation level. The light emission signal (EM) has a second light emission voltage (VEM2). The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. For example, the third interval (TP3B) is referred to as the hold interval.

[0107] In the fourth interval (TP4B), the bias signal (EB) has an inactivation level. The light emission signal (EM) has a third light emission voltage (VEM3). The third light emission voltage (VEM3) is lower than the second light emission voltage (VEM2). The previous stage write gate signal (GW[n-1]) has an inactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has an inactivation level. For example, the fourth interval (TP4B) is referred to as the light emission interval.

[0108] In conventional pixel circuits, the reliability of the current supplied to the conventional light-emitting element is reduced in the light-emitting section due to the parasitic capacitance of at least one of the transistors included in the conventional pixel circuit. For example, when a conventional pixel circuit must display black, the parasitic capacitance supplies current to the conventional light-emitting element. This allows the conventional light-emitting element to emit light. However, when a conventional pixel circuit must display black, the emission of light from the conventional light-emitting element degrades the display quality.

[0109] In contrast, the frame interval in which the pixel circuit (PXA) is driven includes a third interval (TP3B). In the third interval (TP3B), current flows along the path formed by the first transistor (T1), the fourth transistor (T4), and the fifth transistor (T5). This reduces the effect of parasitic capacitance in the light-emitting interval. For example, if the pixel circuit (PXA) is supposed to display black, the effect of parasitic capacitance is reduced, and the light-emitting element (EE) does not emit light. This improves the light-emitting reliability of the pixel circuit (PXB). As the light-emitting reliability of the pixel circuit (PXB) is improved, the display quality of the display panel 100 is improved.

[0110] Furthermore, in the third section (TP3B), if current flows along the path formed by the first transistor (T1), the fourth transistor (T4), and the fifth transistor (T5), and the fifth transistor (T5) is weakly turned on, the leakage current can be further reduced. This further improves the display quality of the display panel 100.

[0111] In this embodiment, the deactivation level of the light emission signal (EM) has a first light emission voltage (VEM1), and the activation level of the light emission signal (EM) has a second light emission voltage (VEM2) that is lower than the first light emission voltage (VEM1). For example, the high light emission voltage corresponds to the first light emission voltage (VEM1). For example, the low light emission voltage corresponds to the second light emission voltage (VEM2). The second light emission voltage (VEM2) is set based on the drive voltage of the light-emitting element (EE). The second light emission voltage (VEM2) is set based on the source-drain voltage of the drive transistor. The drive voltage of the light-emitting element (EE) means the voltage applied to the first electrode (e.g., anode) of the light-emitting element (EE) based on the drive current. For example, the second light emission voltage (VEM2) is set to the value obtained by subtracting the threshold voltage of the fourth transistor (T4) from the sum of the second power supply voltage (ELVSS) and the drive voltage. For example, the second light-emitting voltage (VEM2) is set to a voltage higher than the value obtained by subtracting the threshold voltage of the fourth transistor (T4) from the sum of the second power supply voltage (ELVSS) and the drive voltage (e.g., the lower limit voltage). For example, the absolute value of the second light-emitting voltage (VEM2) is smaller than the value obtained by subtracting the absolute value of the threshold voltage of the fourth transistor (T4) from the sum of the voltage at the second electrode of the drive transistor and the second power supply voltage (ELVSS). For example, the second light-emitting voltage (VEM2) is the voltage obtained by subtracting the threshold voltage of the fourth transistor (T4) from the first light-emitting voltage (VEM1). For example, the second light-emitting voltage (VEM2) is set to a voltage lower than the value obtained by subtracting the source / drain voltage of the first transistor (T1) and the threshold voltage of the fourth transistor (T4) from the first power supply voltage (ELVDD) (e.g., the upper limit voltage). For example, the second light emission voltage (VEM2) is set to a voltage between the lower limit voltage and the upper limit voltage.

[0112] As a result, in this embodiment, the control electrode of the fourth transistor (T4) of the pixel circuit (PXA) is subjected to a light emission signal (EM) having a higher activation level than the activation level of the light emission signal applied to the light emission transistor of a conventional pixel circuit. For example, the absolute value of the second light emission voltage (VEM2) of the light emission signal (EM) is lower than the absolute value of the voltage corresponding to the activation level of the light emission signal applied to a conventional light emission transistor. As a result, the fourth transistor (T4) is weakly turned on.

[0113] During the hold interval, an initialization voltage (VINT) is applied to the second node (N2), causing the first node (N1) to couple with the voltage change of the second node (N2). This changes the voltage of the first node (N1). When the voltage of the first node (N1) changes during the hold interval, the reliability of the drive current decreases. When the reliability of the drive current decreases, the light emission reliability of the pixel circuit (PXA) decreases.

[0114] In this embodiment, the fourth transistor (T4) is weakly turned on during the holding period, so the voltage change at the second node (N2) is reduced during the holding period. Since the voltage change at the second node (N2) is reduced during the holding period, the voltage change at the first node (N1) due to the coupling of the voltage change at the second node (N2) is reduced. This improves the reliability of the drive current. Since the reliability of the drive current is improved, the light emission reliability of the pixel circuit (PXA) is further improved.

[0115] Furthermore, in the fourth section (TP4B), the light emission signal (EM) has a third light emission voltage (VEM3) that is lower than the second light emission voltage (VEM2). Since the light emission signal (EM) has a third light emission voltage (VEM3), the fourth transistor (T4) can be fully turned on. Because the fourth transistor (T4) is fully turned on in the fourth section (TP4B), the reliability of the drive current output in the fourth section (TP4B) is further improved.

[0116] Figure 11 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of Figure 1.

[0117] As shown in Figures 1 and 11, the pixel circuit (PXB) includes a first transistor (T1B), a second transistor (T2), a third transistor (T3), a fourth transistor (T4B), a fifth transistor (T5B), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8B), a storage capacitor (CST), and an light-emitting element (EEB).

[0118] The first transistor (T1B) includes a control electrode connected to a first node (N1), a first electrode to which a first power supply voltage (ELVDD) is applied, and a second electrode connected to a second node (N2B). The first transistor (T1B) generates a drive current based on the voltage at the first node (N1). The first transistor (T1B) supplies the drive current to the second node (N2B) in response to the voltage at the first node (N1). For example, the first transistor (T1B) is referred to as the drive transistor.

[0119] The second transistor (T2) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode to which a data voltage (VDATA) is applied, and a second electrode connected to a third node (N3). The second transistor (T2) applies the data voltage (VDATA) to the third node (N3) in response to the write gate signal (GW[n]). For example, the second transistor (T2) is referred to as the write transistor.

[0120] The third transistor (T3B) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode connected to a second node (N2B), and a second electrode connected to a first node (N1). In response to the write gate signal (GW[n]), the third transistor (T3B) connects the first node (N1) and the second node (N2B). In response to the write gate signal (GW[n]), the third transistor (T3B) diode-connects the first transistor (T1B). For example, the third transistor (T3B) is referred to as a compensation transistor.

[0121] The fourth transistor (T4B) includes a control electrode to which a light emission signal (EM) is applied, a first electrode connected to the fourth node (N4B), and a second electrode connected to the fifth node (N5B). In response to the light emission signal (EM), the fourth transistor (T4B) connects the fourth node (N4B) and the fifth node (N5B). In response to the light emission signal (EM), the fourth transistor (T4B) supplies a drive current to the fifth node (N5B). For example, the fourth transistor (T4B) is referred to as a light-emitting transistor.

[0122] The fifth transistor (T5B) includes a control electrode to which a bias signal (EB) is applied, a first electrode connected to the fifth node (N5B), and a second electrode to which an initialization voltage (VINT) is applied. In response to the bias signal (EB), the fifth transistor (T5B) applies the initialization voltage (VINT) to the fifth node (N5B). For example, the fifth transistor (T5B) is referred to as the light-emitting element initialization transistor.

[0123] In this embodiment, the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS). For example, the value of the initialization voltage (VINT) is less than the value obtained by subtracting the absolute value of the threshold voltage of the fifth transistor (T5) from the sum of the second power supply voltage (ELVSS) and the threshold voltage of the light-emitting element (EE). As a result, when the initialization voltage (VINT) is applied to the fifth node (N5B), the light-emitting element (EE) does not emit light. For example, when the initialization voltage (VINT) is applied to the fifth node (N5B), the pixel circuit (PXB) displays black. Since the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS), the black characteristics of the pixel circuit (PXB) are improved.

[0124] The sixth transistor (T6) includes a control electrode to which an initialization gate signal (GI) is applied, a first electrode to which a reference voltage (VREF) is applied, and a second electrode connected to a third node (N3). In response to the initialization gate signal (GI), the sixth transistor (T6) applies the reference voltage (VREF) to the third node (N3). For example, the sixth transistor (T6) is referred to as the first initialization transistor.

[0125] The seventh transistor (T7) includes a control electrode to which the previous stage write gate signal (GW[n-1]) is applied, a first electrode to which a reference voltage (VREF) is applied, and a second electrode connected to the first node (N1). In response to the previous stage write gate signal (GW[n-1]), the seventh transistor (T7) applies the reference voltage (VREF) to the third node (N3). For example, the seventh transistor (T7) is referred to as the second initialization transistor.

[0126] The eighth transistor (T8B) includes a control electrode to which a control signal (CB) is applied, a first electrode connected to a second node (N2B), and a second electrode connected to a fourth node (N4B). In response to the control signal (CB), the eighth transistor (T8B) connects the second node (N2B) and the fourth node (N4B). For example, the eighth transistor (T8B) is referred to as the control transistor.

[0127] The control signal (CB) is a DC voltage. For example, the control signal (CB) has a control voltage. The control voltage is the voltage that turns on the eighth transistor (T8B). In one embodiment, the control voltage is the voltage that weakly turns on the eighth transistor (T8B).

[0128] A storage capacitor (CST) includes a first electrode connected to a third node (N3) and a second electrode connected to a first node (N1). The storage capacitor (CST) stores the difference between the voltage at the first node (N1) and the voltage at the third node (N3). The storage capacitor (CST) couples the change in voltage at the third node (N3) and provides a coupled voltage to the first node (N1). For example, the storage capacitor (CST) is referred to as the first storage capacitor.

[0129] The light-emitting element (EEB) includes a first electrode connected to a fifth node (N5B) and a second electrode to which a second power supply voltage (ELVSS) is applied. In one embodiment, the light-emitting element (EEB) is, but is not limited to, an organic light-emitting diode (OLED). In other embodiments, the light-emitting element (EEB) is a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0130] Figure 12 is a timing diagram showing the input signals applied to the pixel circuit (PXB) in Figure 11.

[0131] As shown in Figures 1, 11, and 12, the frame interval in which the pixel circuit (PXB) is driven includes a first interval (TP1C), a second interval (TP2C), a third interval (TP3C), and a fourth interval (TP4C).

[0132] In the first section (TP1C), the bias signal (EB) has an activation level. The light emission signal (EM) has a deactivation level. The previous stage write gate signal (GW[n-1]) has an activation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. The control signal (CB) has a control voltage (VCB). For example, the first section (TP1C) is called the initialization section.

[0133] In the second section (TP2C), the bias signal (EB) has an activation level. The light emission signal (EM) has a deactivation level. The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has a deactivation level. The write gate signal (GW[n]) has an activation level. The control signal (CB) has a control voltage (VCB). For example, the second section (TP2C) is referred to as the write section.

[0134] In the third section (TP3C), the bias signal (EB) has an activation level. The light emission signal (EM) has an activation level. The previous stage write gate signal (GW[n-1]) has a deactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has a deactivation level. The control signal (CB) has a control voltage (VCB). For example, the third section (TP3C) is called the hold section.

[0135] In the fourth section (TP4C), the bias signal (EB) has an inactivation level. The light emission signal (EM) has an activation level. The previous stage write gate signal (GW[n-1]) has an inactivation level. The initialization gate signal (GI) has an activation level. The write gate signal (GW[n]) has an inactivation level. The control signal (CB) has a control voltage (VCB). For example, the fourth section (TP4C) is called the light emission section.

[0136] In this embodiment, during the first to fourth intervals (TP1C, TP2C, TP3C, TP4C), the control signal (CB) has a control voltage (VCB). This turns on the eighth transistor (T8B) during the frame interval. In one embodiment, the eighth transistor (T8B) is weakly turned on during the frame interval.

[0137] Figure 13 is a circuit diagram showing the operation of the pixel circuit (PXB) in Figure 11 in the first section (TP1C) of Figure 12.

[0138] As shown in Figures 12 and 13, in the first section (TP1C), the sixth transistor (T6) turns on in response to the initialization gate signal (GI). Since the sixth transistor (T6) is turned on, the reference voltage (VREF) is applied to the third node (N3). In response to the previous stage write gate signal (GW[n-1]), the seventh transistor (T7) turns on. Since the seventh transistor (T7) is turned on, the reference voltage (VREF) is applied to the first node (N1). For example, the first node (N1) is initialized to the reference voltage (VREF). For example, the third node (N3) is initialized to the reference voltage (VREF). Since the first node (N1) and the third node (N3) are given the reference voltage (VREF), the voltages at the first node (N1) and the third node (N3) are substantially the same. This initializes the storage capacitor (CST).

[0139] In the first section (TP1C), the first transistor (T1B) is turned on based on the voltage at the first node (N1).

[0140] In the first section (TP1C), the fifth transistor (T5B) turns on in response to the bias signal (EB). Because the fifth transistor (T5B) is turned on, an initialization voltage (VINT) is applied to the fifth node (N5B). Because an initialization voltage (VINT) is applied to the fifth node (N5B), the light-emitting element (EEB) stops emitting light.

[0141] Figure 14 is a circuit diagram showing the operation of the pixel circuit (PXB) in Figure 11 in the second section (TP2C) of Figure 12.

[0142] As shown in Figures 12 and 14, in the second section (TP2C), the second transistor (T2) turns on in response to the write gate signal (GW[n]). Because the second transistor (T2) is turned on, the data voltage (VDATA) is supplied to the third node (N3).

[0143] In the second section (TP2C), the third transistor (T3B) is turned on in response to the write gate signal (GW[n]). Because the third transistor (T3B) is turned on, the first transistor (T1B) is diode-connected. Because the first transistor (T1B) is diode-connected, the voltage obtained by adding the threshold voltage of the first transistor (T1B) and the first power supply voltage (ELVDD) is applied to the first node (N1). For example, the voltage obtained by adding the threshold voltage of the first transistor (T1B) and the first power supply voltage (ELVDD) is called the compensation voltage. The storage capacitor (CST) can store the difference between the data voltage (VDATA) and the compensation voltage.

[0144] In this embodiment, the first electrode of the first transistor (T1B) is the source electrode. Furthermore, the data voltage (VDATA) is not written through the source electrode of the first transistor (T1B). The source electrode of the first transistor (T1B) is supplied with a first power supply voltage (ELVDD). For example, only the first power supply voltage (ELVDD) can be supplied to the source electrode of the first transistor (T1B). As a result, the voltage supplied to the source electrode of the first transistor (T1B) remains constant. Since the voltage supplied to the source electrode of the first transistor (T1B) remains constant, the threshold voltage of the first transistor (T1B) is substantially the same throughout the frame interval. Therefore, the accuracy of the compensation voltage is improved. Because the accuracy of the compensation voltage is improved, the driving reliability and light emission reliability of the pixel circuit (PXB) are further improved.

[0145] In the second interval (TP2C), the ON state of the fifth transistor (T5B) is maintained in response to a bias signal (EB) having an activation level.

[0146] Figure 15 is a circuit diagram showing the operation of the pixel circuit (PXB) in Figure 11 during the third interval (TP3C) of Figure 12.

[0147] As shown in Figures 12 and 15, in the third interval (TP3C), the sixth transistor (T6) turns on in response to the initialization gate signal (GI). As the sixth transistor (T6) turns on, a reference voltage (VREF) is applied to the third node (N3). In response to the write gate signal (GW[n]), the third transistor (T3B) turns off. As the third transistor (T3B) turns off, the first node (N1) becomes floating. The storage capacitor (CST) couples the voltage change at the third node (N3). The storage capacitor (CST) couples the voltage change at the third node (N3) and applies the coupled voltage to the first node (N1). As the coupled voltage is applied to the first node (N1), the first node (N1) can have a voltage that takes into account the compensation voltage and the data voltage (VDATA).

[0148] In the third section (TP3C), the first transistor (T1B) generates a drive current based on the voltage at the first node (N1).

[0149] In the third interval (TP3C), the fourth transistor (T4B) turns on in response to the light emission signal (EM). Also, the fifth transistor (T5B) remains on in response to the bias signal (EB). Furthermore, the eighth transistor (T8B) can remain on in response to the control signal (CB). As a result, the light-emitting element (EEB) does not emit light.

[0150] Figure 16 is a circuit diagram showing the operation of the pixel circuit (PXB) in Figure 11 in the fourth section (TP4C) of Figure 12.

[0151] As shown in Figures 12 and 16, in the fourth section (TP4C), the fifth transistor (T5B) is turned off in response to the bias signal (EB). This provides a drive current to the light-emitting element (EEB). In the fourth section (TP4C), the light-emitting element (EEB) can emit light based on the drive current.

[0152] As shown in Figures 1 and 11 to 16, in conventional pixel circuits, the reliability of the current supplied to the conventional light-emitting element included in the conventional pixel circuit is reduced in the light-emitting section due to the parasitic capacitance of at least one of the transistors included in the conventional pixel circuit. For example, when a conventional pixel circuit must display black, the parasitic capacitance supplies current to the conventional light-emitting element. This allows the conventional light-emitting element to emit light. When a conventional pixel circuit must display black, the conventional light-emitting element emits light, resulting in a decrease in display quality.

[0153] In contrast, the frame interval in which the pixel circuit (PXB) is driven includes a third interval (TP3C). In the third interval (TP3C), current flows along the path formed by the first transistor (T1B), the eighth transistor (T8B), the fourth transistor (T4B), and the fifth transistor (T5B). This reduces the effect of parasitic capacitance in the light-emitting interval. For example, if the pixel circuit (PXB) must display black, the effect of parasitic capacitance is reduced, and the light-emitting element (EEB) does not emit light. This improves the light-emitting reliability of the pixel circuit (PXB). Because the light-emitting reliability of the pixel circuit (PXB) is improved, the display quality of the display panel 100 can be improved.

[0154] In this embodiment, the pixel circuit (PXB) further includes an eighth transistor (T8B). The eighth transistor (T8B) can remain ON for the duration of a frame interval. In one embodiment, the eighth transistor (T8B) is weakly ON for the duration of a frame interval.

[0155] During the hold interval, an initialization voltage (VINT) is applied to the second node (N2B), causing the first node (N1) to couple with the voltage change of the second node (N2B). This changes the voltage of the first node (N1). When the voltage of the first node (N1) changes during the hold interval, the reliability of the drive current decreases. When the reliability of the drive current decreases, the light emission reliability of the pixel circuit (PXB) decreases.

[0156] The eighth transistor (T8B) can remain ON during the frame interval, thus reducing the voltage change at the second node (N2B) during the hold interval. In one embodiment, the eighth transistor (T8B) is weakly ON, thus reducing the voltage change at the second node (N2B) during the hold interval. Since the voltage change at the second node (N2B) is reduced during the hold interval, the voltage change at the first node (N1) due to the coupling of the voltage change at the second node (N2B) is reduced. This improves the reliability of the drive current. Since the reliability of the drive current is improved, the light emission reliability of the pixel circuit (PXB) is further improved.

[0157] Figure 17 is a diagram showing an example of how the pixel circuits (PX) included in the display device 1 of Figure 1 are arranged on the substrate 101.

[0158] As shown in Figures 1 and 17, the pixel circuit (PX) is arranged on the substrate 101. In one embodiment, the substrate 101 is a silicon-based substrate. In one embodiment, the pixel circuit (PX) is arranged on the silicon-based substrate.

[0159] Silicon-based substrates include single-crystal silicon wafers, polycrystalline silicon wafers, or amorphous silicon wafers. A semiconductor layer is formed on the silicon-based substrate by a semiconductor manufacturing process. For example, a silicon-based substrate on which a semiconductor layer has been formed is a silicon-based semiconductor substrate.

[0160] In one embodiment, the semiconductor layer is formed on a silicon-based substrate by a CMOS (Complementary Metal Oxide Semiconductor) process. The semiconductor layer includes a pixel circuit in CMOS form. For example, the pixel circuit (PX) includes a CMOS circuit containing p-type transistors and n-type transistors. Thus, the display device 1 is a DOS (Display on Silicon) or LEDoS (Light Emitting Diode on Silicon) having a light-emitting structure on a silicon-based semiconductor substrate.

[0161] Since the pixel circuit (PX) is placed on a silicon-based substrate, the voltage level of the input signal supplied to the pixel circuit (PX) can be set more precisely. Also, because the pixel circuit (PX) is placed on a silicon-based substrate, at least one of the transistors included in the pixel circuit (PX) is a MOS (Metal Oxide Semiconductor) transistor. This improves the driving stability of at least one of the transistors. As a result, the driving stability and light emission reliability of the pixel circuit (PX) are improved.

[0162] Figure 18 is a block diagram showing an electronic device 1000 according to an embodiment of the present invention. Figure 19 is a diagram showing an example in which the electronic device 2000 of Figure 18 is implemented in a smartphone.

[0163] As shown in Figure 18, the electronic device 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 is the display device shown in Figure 1. The electronic device 1000 may also further include a number of ports that can communicate with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0164] In one embodiment, as shown in Figure 19, the electronic device 1000 can be embodied in a smartphone. However, this is illustrative, and the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be embodied in a mobile phone, video phone, smart pad, smartwatch, tablet PC, vehicle navigation system, computer monitor, notebook PC, head-mounted display device, etc.

[0165] The processor 1010 can perform specific calculations or tasks. Depending on the embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0166] The processor 1010 outputs input image data (IMG) and input control signal (CONT) to the drive control unit 200 shown in Figure 1.

[0167] The memory device 1020 can store data necessary for the operation of the electronic device 1000. For example, the memory device 1020 includes non-volatile memory devices such as ERPOM (Erasable Programmable Read-Only Memory) devices, EERPOM (Electrically Erasable Programmable Read-Only Memory) devices, flash memory devices, PRAM (Phase Change Random Access Memory) devices, RRAM (Resistance Random Access Memory) devices, NFGM (Nano Floating Gate Memory) devices, PoRAM (Polymer Random Access Memory) devices, MRAM (Magnetic Random Access Memory), FRAM® (Ferroelectric Random Access Memory) devices, and / or volatile memory devices such as DRAM (Dynamic Random Access Memory) devices, SRAM (Static Random Access Memory) devices, and mobile DRAM devices.

[0168] The storage device 1030 includes SSDs (Solid State Drives), HDDs (Hard Disk Drives), CD-ROMs, etc. The input / output device 1040 includes input means such as keyboards, keypads, touchpads, touchscreens, and mice, and output means such as speakers and printers. Depending on the embodiment, the display device 1060 may also be included in the input / output device 1040. The power supply 1050 can supply the power necessary for the operation of the electronic device 1000. The display device 1060 can be connected to other components via a bus or other communication link.

[0169] Figure 19 shows that the electronic device of the present invention is embodied in a smartphone, but the present invention is not limited to this. The electronic device may be a television, monitor, notebook computer, or tablet. Furthermore, the electronic device may be an automobile.

[0170] Figure 20 shows an example of the electronic device 1000 from Figure 18 being realized in a virtual reality display system.

[0171] As shown in Figures 18 and 20, the virtual reality display system includes a lens unit 10, a display device 20, and a housing 30. The display device 20 is positioned adjacent to the lens unit 10. The housing 30 houses the lens unit 10 and the display device 20. Figure 20 shows that the lens unit 10 and the display device 20 are housed on a first side of the housing 30, but the present invention is not limited thereto. For example, the lens unit 10 is housed on a first side of the housing 30, and the display device 20 is housed on a second side of the housing 30 opposite to the first side. When the lens unit 10 and the display device 20 are housed on different sides of the housing 30, the housing 30 has a transmissive portion for transmitting light.

[0172] For example, a virtual reality display system is a head-mounted display system worn on the user's head. Although not shown in the illustration, the virtual reality display system further includes a headband for wearing on the user's head.

[0173] In contrast, virtual reality display systems can also take the form of smart glasses, which are embodied in the shape of eyeglasses.

[0174] Furthermore, electronic devices can be realized in augmented reality display systems or mixed reality display systems. [Industrial applicability]

[0175] The present invention can be applied to display devices and electronic devices including the same. For example, the display device of the present invention can be applied to computers, notebook computers, mobile phones, smartphones, smartpads, smartwatches, PMPs, PDAs, MP3 players, and the like.

[0176] Having been described above with reference to embodiments, a person skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and scope of the invention as set forth in the following claims. [Explanation of symbols]

[0177] 100: Display Panel 200: Drive Control Unit 300: Gate drive unit 400: Gamma Reference Voltage Generation Unit 500: Data-driven unit 600: Light-emitting drive unit 700: Voltage generation unit

Claims

1. A drive transistor comprising a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, which generates a drive current based on the voltage of the first node, A writing transistor that provides a data voltage to the drive transistor in response to a write gate signal, A control transistor comprising a control electrode to which a control signal is applied, a first electrode connected to the second node, and a second electrode connected to the fourth node, A light-emitting transistor connects the fourth node and the fifth node in response to a light-emitting signal, A light-emitting element initialization transistor that provides an initialization voltage to the fifth node in response to a bias signal, The device includes a light-emitting element comprising a first electrode connected to the fifth node and a second electrode to which a second power supply voltage is applied, The pixel circuit is characterized in that the control signal is a DC voltage.

2. The pixel circuit according to claim 1, characterized in that the DC voltage is a voltage that turns on the control transistor.

3. The frame interval in which the pixel circuit is driven includes a write interval, a hold interval, and an illumination interval. In the aforementioned writing section, the write gate signal has an activation level. In the holding section, the bias signal has an activation level, and the light emission signal has an activation level. The pixel circuit according to claim 1, characterized in that the drive current is supplied to the fifth node in the light-emitting section.

4. The pixel circuit according to claim 3, characterized in that during the holding interval, the control transistor turns on, the light-emitting transistor turns on, and the control transistor turns on.

5. A storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node, A first initialization transistor that provides a reference voltage to the third node in response to an initialization gate signal, A second initialization transistor that provides the reference voltage to the first node in response to the previous stage write gate signal, The system further includes a compensation transistor that connects the first node and the second node in response to the write gate signal, The pixel circuit according to claim 1, characterized in that the writing transistor provides the data voltage to the third node in response to the writing gate signal.

6. The frame interval in which the pixel circuit is driven includes the first to fourth intervals, The pixel circuit according to claim 5, characterized in that in the first section, the bias signal has an activation level, the light emission signal has a deactivation level, the pre-stage write gate signal has an activation level, and the initialization gate signal has an activation level.

7. The pixel circuit according to claim 6, characterized in that in the second section following the first section, the bias signal has an activation level, the light emission signal has a deactivation level, the pre-stage write gate signal has a deactivation level, the initialization gate signal has a deactivation level, and the write gate signal has an activation level.

8. The pixel circuit according to claim 7, characterized in that the drive transistor and the compensation transistor are turned on in the second section.

9. The pixel circuit according to claim 7, characterized in that in the third section following the second section, the bias signal has an activation level, the light emission signal has an activation level, and the write gate signal has a deactivation level.

10. The pixel circuit according to claim 9, characterized in that in the third section, the light-emitting initialization transistor is turned on, the light-emitting transistor is turned on, and the control transistor is turned on.

11. The pixel circuit according to claim 9, characterized in that in the fourth section following the third section, the bias signal has a deactivation level and the light emission signal has an activation level.

12. The pixel circuit according to claim 6, characterized in that the control signal maintains a control voltage during the first to fourth intervals.

13. The writing transistor includes a control electrode to which the writing gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node. The compensation transistor includes a control electrode to which the write gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node. The light-emitting transistor includes a control electrode to which the light-emitting signal is applied, a first electrode connected to the fourth node, and a second electrode connected to the fifth node. The light-emitting element initialization transistor includes a control electrode to which the bias signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the fifth node. The first initialization transistor includes a control electrode to which the initialization gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the third node. The second initialization transistor includes a control electrode to which the pre-stage write gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node. The pixel circuit according to claim 5, characterized in that the control transistor includes a control electrode to which the control signal is applied, a first electrode connected to the second node, and a second electrode connected to the fourth node.

14. A drive transistor comprising a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, which generates a drive current based on the voltage of the first node, A writing transistor that provides a data voltage to the drive transistor in response to a write gate signal, A light-emitting transistor connects the second node and the fourth node in response to a light-emitting signal, A light-emitting element initialization transistor that provides an initialization voltage to the fourth node in response to a bias signal, The light-emitting element includes a first electrode connected to the fourth node and a second electrode to which a second power supply voltage is applied, The light emission signal transitions between a first light emission voltage and a second light emission voltage lower than the first light emission voltage. A pixel circuit characterized in that the absolute value of the second light-emitting voltage is smaller than the value obtained by subtracting the absolute value of the threshold voltage of the light-emitting transistor from the sum of the voltage of the second electrode of the driving transistor and the second power supply voltage.

15. The frame interval in which the pixel circuit is driven includes a write interval, a hold interval, and an illumination interval. In the aforementioned writing section, the write gate signal has an activation level. In the holding section, the bias signal has an activation level, and the light emission signal has an activation level. The pixel circuit according to claim 14, characterized in that the drive current is supplied to the fourth node in the light-emitting section.

16. The pixel circuit according to claim 15, characterized in that in the light-emitting section, the light-emitting signal has a third light-emitting voltage that is lower than the second light-emitting voltage.

17. A storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node, A first initialization transistor that provides a reference voltage to the third node in response to an initialization gate signal, A second initialization transistor that provides the reference voltage to the first node in response to the previous stage write gate signal, The system further includes a compensation transistor that connects the first node and the second node in response to the write gate signal, The pixel circuit according to claim 14, characterized in that the writing transistor provides the data voltage to the third node in response to the writing gate signal.

18. The frame interval in which the pixel circuit is driven includes the first to fourth intervals, The pixel circuit according to claim 17, characterized in that in the first section, the bias signal has an activation level, the light emission signal has a deactivation level, the pre-stage write gate signal has an activation level, and the initialization gate signal has an activation level.

19. The pixel circuit according to claim 18, characterized in that in the second section following the first section, the bias signal has an activation level, the light emission signal has a deactivation level, the pre-stage write gate signal has a deactivation level, the initialization gate signal has a deactivation level, and the write gate signal has an activation level.

20. A display panel including a pixel circuit, The aforementioned pixel circuit includes a gate drive unit that outputs a gate signal, A light-emitting drive unit that outputs a light-emitting signal to the pixel circuit, A data drive unit that supplies data voltage to the display panel, A voltage generation unit that supplies power voltage to the aforementioned display panel, A drive control unit controls the gate drive unit, the light emission drive unit, the data drive unit, and the voltage generation unit based on an input control signal, The processor includes the input control signal mentioned above, The aforementioned pixel circuit is A drive transistor comprising a control electrode connected to a first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a second node, which generates a drive current based on the voltage of the first node, A write transistor that provides the data voltage to the drive transistor in response to a write gate signal, A control transistor comprising a control electrode to which a control signal is applied, a first electrode connected to the second node, and a second electrode connected to the fourth node, A light-emitting transistor connects the fourth node and the fifth node in response to the light-emitting signal, A light-emitting element initialization transistor that provides an initialization voltage to the fifth node in response to a bias signal, The device includes a light-emitting element comprising a first electrode connected to the fifth node and a second electrode to which a second power supply voltage is applied, The voltage generation unit outputs the control signal, The electronic device is characterized in that the control signal is a DC voltage.

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