An electronic system for generating multiple power supply output voltages using a single adjustment loop.

Abstract

This provides an electronic system that generates multiple power supply output voltages using only one adjustment loop. [Solution] The electronic system (1) comprises a plurality of subblocks, each of which is required to be supplied with a different power output voltage; a differential amplifier (3) having a plurality of outputs and an input reference voltage (VRF) applied to the first input of the amplifier; a voltage adjustment loop comprising a first transistor (40) and a variable resistor (5) connected to the first output and second input of the amplifier; and a plurality of additional transistors (41, 42, ...) to which each output of the amplifier is connected to one gate or base, and whose drain, source, emitter or collector is connected to one of the subblocks (21, 22, ...).

Description

[Technical Field]

[0001] The present invention relates to the field of power supplies, and more particularly to an electronic system that enables the generation of multiple power supply output voltages using only one adjustment loop. [Background technology]

[0002] Existing electronic circuits are not designed to operate under the same power supply voltage. For example, some digital circuits may require a 1.2V power supply, while flash memory requires a 1.5V power supply.

[0003] As a result, any electronic system requires a power supply capable of outputting the power supply voltage required for the components it contains.

[0004] Figure 1 shows an existing power supply architecture using a capacitorless adjustment loop with NMOS feedback. In such an architecture, a differential amplifier is supplied with an input reference voltage VRF at one of its terminals, and its output VG is connected to the gate of a transistor NFB. The source of this transistor is the voltage VDD_VFB, which is fed back to the other terminal of the amplifier through a variable resistor. The system also includes a second transistor, the gate of which is connected to the amplifier output, and the source of the second transistor is connected to a digital subblock, which is supplied with a voltage VDD that is approximately equal to VDD_VFB. The input reference voltage VRF and the variable resistor can be set so that the VDD voltage is set to any desired value.

[0005] Most electronic systems have numerous sub-blocks that may not all be supplied with the same voltage. Consequently, such systems must include a power supply unit capable of simultaneously delivering multiple different power output voltages.

[0006] The architecture shown in Figure 1 can be duplicated as many times as there are different power supply output voltages required, with each duplicate supplying its required voltage to one system subblock, as shown in Figure 2 for two subblocks. Nevertheless, such a solution cannot be applied to integrated systems with high constraints on available silicon area, such as system-on-a-chip (SOCs).

[0007] As a result, there is a need for an electronic system that includes a power supply capable of outputting multiple different power output voltages to various sub-blocks, with a smaller silicon area and current consumption than existing power supply architectures. [Overview of the project] [Means for solving the problem]

[0008] For this purpose, and according to the first aspect, the present invention therefore: • Multiple sub-blocks, each requiring a different power output voltage, A differential amplifier having multiple outputs, wherein an input reference voltage is applied to the first input of the amplifier, A voltage regulating loop with transistor feedback connected to the first output and second input of an amplifier, wherein the loop comprises a first transistor and a variable resistor, Multiple additional transistors, wherein each output of the amplifier is connected to the gate or base of one of the additional transistors, and the drain, source, emitter, or collector of each additional transistor is connected to one of the subblocks. Equipped with, The input reference voltage and variable resistor are configured such that the first subblock is supplied with its required power supply output voltage by the transistor to which it is connected. The amplifier also relates to an electronic system in which each of its outputs outputs outputs a power reference voltage such that each of the subblocks other than the first subblock outputs the required power supply output voltage, which is supplied by the transistor to which it is connected.

[0009] Such a system allows for the generation of only the number of power output voltages required by the sub-blocks of the system that will be powered up, using only one amplifier and one adjustment loop.

[0010] In one embodiment, the final stage of the amplifier comprises at least one component configured such that when the potential at one of its terminals is set to a first power reference voltage, a second power reference voltage is generated at the other terminal of the component.

[0011] This allows for the easy generation of numerous different voltage outputs from the amplifier, along with reduced silicon area costs and current consumption.

[0012] The aforementioned component may be one of a resistor, a diode, a MOS transistor, or a switched capacitor.

[0013] The subblock may be one of the following: flash memory, digital circuitry, analog circuitry, or input / output interface.

[0014] For example, the first subblock may be a digital circuit to which a first power output voltage equal to 1.2V is supplied, the second subblock may be a flash memory to which a second power output voltage equal to 1.5V is supplied, and the component may be a resistor set to a value equal to 300mV divided by the current flowing through it.

[0015] According to a second aspect, the invention thus also relates to a system-on-chip comprising an electronic system according to the first aspect.

[0016] For the achievement of the foregoing and related objectives, one or more embodiments are fully described hereinafter and include features particularly pointed out within the scope of the claims.

[0017] The following description and the accompanying drawings specify particular illustrative aspects in detail, but show some of the various ways in which the principles of the embodiments can be used. Other advantages and novel features will become apparent from the following detailed description when considered in conjunction with the drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents.

Brief Description of the Drawings

[0018] [Figure 1] Schematic diagram of an existing power architecture using a capacitorless regulation loop with NMOS feedback. [Figure 2] Schematic diagram of a power architecture that generates two power output voltages for two sub-blocks. [Figure 3] Schematic diagram of an electronic system according to the invention using MOS transistors. [Figure 4] Schematic diagram of an electronic system according to the invention using bipolar transistors. [Figure 5] Schematic diagram of an amplifier architecture based on a PMOS transistor differential pair according to an embodiment of the invention.

Modes for Carrying Out the Invention

[0019] According to a first aspect, as shown in Figure 3, the present invention relates to an electronic system 1 comprising a plurality of subblocks 21, 22..., each subblock being required to be supplied with different power supply output voltages VDD1, VDD2.... Such subblocks may be, for example, a flash memory to be supplied with a voltage of 1.5V, a digital circuit to be supplied with a voltage of 1.2V, an analog circuit, or an input / output interface.

[0020] Such electronic systems can be embedded in portable electronic devices. For example, they could be contained within a smart card or within a system-on-a-chip (SOC).

[0021] To generate the voltage to be supplied to the subblock, System 1 also includes a differential amplifier 3. This amplifier has a specific design with multiple outputs. An input reference voltage VRF is applied to the first input of the amplifier. In the example shown in Figure 3, the input reference voltage VRF is applied to the positive input of the amplifier.

[0022] To make the amplifier output a constant voltage equal to a desired value, the system includes a capacitorless voltage regulation loop with transistor feedback. This loop is connected at one end to the second input of the amplifier. In the example in Figure 3, it is connected to the negative input of the amplifier. In Figure 3, all transistors used in the electronic system, including those for feedback, are MOS transistors. Figure 4 presents another example in which all transistors used in the system are bipolar transistors. For the remainder of this application, the description refers to Figure 3 and refers to the transistors used in the system as MOS transistors, but any other type of transistor, such as a bipolar transistor, may be used instead with the same effect.

[0023] The voltage at the second input of the amplifier is denoted as VFB. The loop is connected to the first output of the amplifier at its other end, outputting a power supply reference voltage VG1. This loop includes a first MOS transistor 40 and a variable resistor 5. In the example shown in Figure 3, this transistor is an NMOS transistor. The threshold voltage of the first transistor is denoted as VTH (for a bipolar transistor, the transistor is characterized by its base-emitter voltage VBE instead of the threshold voltage VTH). The architecture of this regulating loop is the same as that shown in Figure 1. The first output of the amplifier is connected to the gate of the first transistor 40 (or its base in the case of a bipolar transistor). The source of the first transistor (or its emitter terminal in the case of a bipolar transistor) is connected to one end terminal of the variable resistor, and the center terminal of the variable resistor is connected to the second input of the amplifier.

[0024] The voltage at the source of the first transistor is denoted as VDD_VFB, and the resistance between the source of the first transistor and the second input of the amplifier is R up It is written that the resistance between the second input of the amplifier and ground is R down It is written as follows: In such a configuration, when the amplifier is assumed to be ideal (VRF=VFB), VDD_VFB and VG1 satisfy the following equation: VDD_VFB=VRF*(R up +R down ) / R down =VG1-VTH

[0025] Finally, to supply various power output voltages to the subblocks of this system, the system includes several additional MOS transistors 41, 42... Each output of the amplifier is connected to the gate of one of these additional MOS transistors, and the drain or source of each additional transistor is connected to one of the subblocks of this system to supply it with the required voltage.

[0026] In the example of FIG. 3, the system includes two sub-blocks and two additional NMOS transistors. The gate of the first additional transistor is connected to the first output of the amplifier at voltage VG1, and its source supplies voltage VDD1 to the first sub-block. The gate of the second additional transistor is connected to the second output of the amplifier at voltage VG2, and its source supplies voltage VDD2 to the second sub-block.

[0027] The first transistor 40 has a gate width W and a gate length L. The first additional transistor 41 has a gate width W1 and a gate length L1. A magnification factor m1 defined by the relationship: W1 / L1 = m1 * W / L will be introduced. If the currents flowing out from the source of the first transistor and the source of the first additional transistor are named IFB and IDD1 respectively, then IFB is proportional to W / L * (VG1 - VDD_FB - VTH) 2 and IDD1 is proportional to W1 / L1 * (VG1 - VDD1 - VTH). 2 For a given value of IDD1 discharged by the first sub-block, the ratio W1 / L1 of the first additional transistor can be set such that IFB * L / W = IDD1 * L1 / W1, that is, for IFB equal to VDD_FB / (Rup + Rdown), m1 = IDD1 / IFB. In such a configuration, the power supply output voltage VDD1 supplied to the first sub-block by the first additional MOS transistor 41 connected to the first output of the amplifier is approximately equal to the voltage VDD_VFB at the source of the first transistor of the adjustment loop that also has a gate connected to the first output of the amplifier, that is, VDD1 = VDD_VFB.

[0028] As a result, in order to supply the required power supply output voltage VDD1 to the first sub-block, the input reference voltage VRF and the variable resistor are configured such that the first sub-block supplies the required power supply output voltage VDD1 as supplied by the MOS transistor to which it is connected. In other words, VRF and R up / (R up +R down ) is VRF*(R up +R down ) / R down =VDD1 It is set to be such that VG1 = VDD1 + VTH.

[0029] Such formulas do not account for voltage fluctuations or offsets, variations in the input reference voltage VRF, etc., resulting from design flaws such as the amplifier not being ideal. To account for such flaws, VDD1 and VG1 can be precisely set by performing a trimming process.

[0030] In addition, for each additional transistor i, the voltage VDDi at its terminal connected to the subblock it supplies, and the power reference voltage VGi supplied by the output of the amplifier to which its gate is connected, satisfy the following equation: VGi = VDDi + VTHi, where VTHi is the threshold voltage of the transistor. For the first additional transistor, as described above, the ratio grid width / grid length (Wi / Li = mi*W / L) of each additional transistor can be set to have a desired current flowing out of the transistor's source toward its subblock.

[0031] To supply all subblocks with their required power output voltages, the amplifier is configured to output different power reference voltages VG1, VG2... at each of its outputs, such that each subblock other than the first subblock is supplied with its required power output voltage (VDD2...) by the MOS transistor to which it is connected. In other words, the amplifier is configured to output a voltage VGi at its output i such that VGi = VDDi + VTHi ensures that the subblock supplied by the i-th additional transistor connected to this output is supplied with its required power output voltage VDDi.

[0032] To generate multiple power supply reference voltages, an additional component that generates voltage offsets may be included in the amplifier. More precisely, the final stage of the amplifier may include at least one component configured such that when the potential at one of its terminals is set to a first power supply reference voltage VG1, a second power supply reference voltage VG2... is generated at the other terminal of the component.

[0033] Such components may include, for example, resistors, diodes, MOS transistors, switched capacitors, etc.

[0034] An example of such an amplifier architecture is shown in Figure 5. In such an example, the amplifier architecture is based on a differential pair of PMOS transistors. It generates a first power supply reference voltage VG1 at the drain of its output transistor NOUT. A resistor Roffset is inserted between transistor NOUT and current source Iref. It generates a voltage offset Voff, which results in a voltage VG2 = VG1 + Voff at its terminal connected to the current source Iref.

[0035] In such an example, when such an amplifier is used in the configuration shown in Figure 3, the first subblock is a digital circuit to which a first power supply output voltage VDD1 equal to 1.2V should be supplied, and the second subblock is flash memory to which a second power supply output voltage VDD2 equal to 1.5V should be supplied. In such a case, the offset that will be generated between VG1 and VG2 is 300mV, and the component is a resistor set to a value equal to 300mV divided by the current flowing through it. When the current Iref is set to 1μA, the resistor is set to 300k ohms.

[0036] When VDDi is lower than VDD1, a negative offset is required. In such cases, the component to be added to the amplifier may be inserted between the amplifier's first output and the output transistor NOUT.

[0037] As a result, the system according to the present invention enables the generation of as many power output voltages as required by the subblocks of the system to be powered up, using only one amplifier and one adjustment loop. Silicon area and power consumption are reduced. Only one trimming process is required to precisely set all power output voltages to their required values.

Claims

1. Multiple subblocks (21, 22, ...) each require a different power output voltage (VDD1, VDD2, ...). A differential amplifier (3) having multiple outputs, wherein an input reference voltage (VRF) is applied to the first input of the amplifier, A voltage regulating loop with transistor feedback connected to the first output and second input of an amplifier, wherein the loop comprises a first transistor (40) and a variable resistor (5), A plurality of additional transistors (41, 42, ...) wherein each output of the amplifier is connected to the gate or base of one of the additional transistors, and the drain, source, emitter, or collector of each additional transistor is connected to one of the subblocks. Equipped with, The input reference voltage (VRF) and variable resistor are configured such that the first subblock (21) is supplied with its required power supply output voltage (VDD1) by the transistor to which it is connected. Furthermore, the amplifier ensures that each subblock other than the first subblock (22, ...) has the required power supply output voltage (VDD) 2. An electronic system (1) configured to output power reference voltages (VG1, VG2, ...) at each of its outputs, such that the power supply is supplied by the transistor to which it is connected.

2. The electronic system according to claim 1, wherein the final stage of the amplifier (3) comprises at least one component configured such that when the potential at one of its terminals is set to a first power supply reference voltage (VG1), a second power supply reference voltage (VG2...) is generated at the other terminal of the component.

3. The electronic system according to claim 2, wherein the component is one of a resistor, a diode, a MOS transistor, or a switched capacitor.

4. The electronic system according to any one of claims 1 to 3, wherein the subblock is one of a flash memory (22), a digital circuit (21), an analog circuit, or an input / output interface.

5. The electronic system according to any one of claims 1 to 4, wherein the first subblock (21) is a digital circuit to be supplied with a first power supply output voltage (VDD1) equal to 1.2V, and the second subblock (22) is a flash memory to be supplied with a second power supply output voltage (VDD2) equal to 1.5V, and the component is a resistor set to a value equal to 300mV divided by the current flowing therethrough.

6. A system-on-a-chip comprising the electronic system (1) according to any one of claims 1 to 5.

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