Imaging device

Abstract

This enables the reading of pixel signals with switched pixel conversion efficiency while suppressing a decrease in frame rate. [Solution] The imaging device comprises a photoelectric conversion unit provided in the pixel, a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, an amplification transistor that outputs a pixel signal corresponding to the charge accumulated in the first floating diffusion, a selection transistor that selects the output from the amplification transistor, a first switching transistor that adds capacitance to the first floating diffusion based on a first switching signal to switch the conversion efficiency when outputting the pixel signal, and a second switching transistor connected in parallel to the first switching transistor that adds capacitance to the first floating diffusion based on a second switching signal to switch the conversion efficiency when outputting the pixel signal.

Description

[Technical Field]

[0001] This technology relates to an imaging device. More specifically, this technology relates to an imaging device capable of switching the pixel conversion efficiency. [Background technology]

[0002] There is a technology that achieves HDR (High Dynamic Range) by switching the conversion efficiency of pixels. For example, a technology has been disclosed that achieves both high-light and low-light image quality by switching between three levels of conversion efficiency for each pixel (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2024 / 0088176 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] However, the conventional technology described above requires six AD conversions per frame: HCG (High Conversion Gain) P-phase / D-phase, LCG (Low Conversion Gain) P-phase / D-phase, and MCG (Middle Conversion Gain) P-phase / D-phase. As a result, there was a risk that the frame rate would drop to about one-third compared to non-HDR mode, which only requires two AD conversions (P-phase / D-phase).

[0005] This technology was developed in light of these circumstances, and its purpose is to enable the reading of pixel signals with switched pixel conversion efficiencies while suppressing a decrease in frame rate. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is an imaging device comprising: a photoelectric conversion unit provided in a pixel; a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion; an amplification transistor that outputs a pixel signal corresponding to the charge accumulated in the first floating diffusion; a selection transistor that selects the output from the amplification transistor; a first switching transistor that adds capacitance to the first floating diffusion based on a first switching signal to switch the conversion efficiency when outputting the pixel signal; and a second switching transistor connected in parallel to the first switching transistor that adds capacitance to the first floating diffusion based on a second switching signal to switch the conversion efficiency when outputting the pixel signal. This results in the setting of the second switching signal based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, and the switching of the conversion efficiency based on the second switching signal.

[0007] Furthermore, in the first aspect, the capacitance may include a second floating diffusion, and the first and second switching transistors may be connected between the first and second floating diffusions. This results in the capacitance of the second floating diffusion being added to the first floating diffusion based on a switching signal.

[0008] Furthermore, in the first aspect, the system may also include a third floating diffusion and a third switching transistor connected between the second floating diffusion and the third floating diffusion, which adds the capacitance of the third floating diffusion to the second floating diffusion based on a third switching signal to switch the conversion efficiency when outputting the pixel signal. This results in the conversion efficiency being switched in three stages based on the switching signal.

[0009] Furthermore, in the first aspect, the conversion efficiency of the pixel may be set to HCG (High Conversion Gain), the P-phase level may be read out, and then the D-phase level may be read out. Based on the determination result of the D-phase level read out from the pixel, the on / off state of the first switching transistor may be controlled to select HCG or MCG (Middle Conversion Gain) as the conversion efficiency of the pixel. The conversion efficiency of the pixel may then be set to the selected HCG or MCG, the D-phase level may be read out, and the second and third switching transistors may be turned on to set the conversion efficiency of the pixel to LCG (Low Conversion Gain), the D-phase level may be read out, and then the P-phase level may be read out. This results in the conversion efficiency being switched in three stages through four AD conversions: the P-phase of HCG, the D-phase of HCG or MCG, the D-phase of LCG, and the P-phase of LCG.

[0010] Furthermore, in the first aspect, by controlling the on / off state of the first switching transistor based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, the HCG or MCG is selected as the conversion efficiency of the pixel, the conversion efficiency of the pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out, and by turning on the second switching transistor and the third switching transistor, the conversion efficiency of the pixel is set to LCG, the D-phase level is read out, and then the P-phase level is read out, and the intermediate potential may be a potential that does not transfer when the charge accumulated in the photoelectric conversion unit is below a certain value. This results in the P-phase level and D-phase level corresponding to the conversion efficiency that is switched based on the determination result of the signal level being read out.

[0011] Furthermore, in the first aspect, a LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion may be provided. This has the effect of suppressing a decrease in frame rate while expanding the dynamic range in HDR.

[0012] Furthermore, in the first aspect, an overflow control transistor may be provided connected between the LOFIC and the photoelectric conversion unit. This suppresses a decrease in frame rate, expands the dynamic range in HDR, and reduces fixed pattern noise caused by dark current.

[0013] Furthermore, in the first aspect, the photoelectric conversion unit may include a first photodiode connected to the transfer transistor and a second photodiode connected to the LOFIC and having lower sensitivity than the first photodiode. This suppresses a decrease in frame rate while expanding the dynamic range in HDR and suppressing afterimages caused by dielectric absorption.

[0014] Furthermore, in the first aspect, a fourth switching transistor may be provided, which is connected in series with the third switching transistor and switches the conversion efficiency when outputting the pixel signal by adding the capacitance of the third floating diffusion to the first floating diffusion based on the first switching signal. This results in the CDS and DDS being performed based on the same conversion efficiency readout level by providing one vertical control line for each column in the switching of HCG and MCG and the switching of MCG and LCG.

[0015] Furthermore, in the first aspect, by controlling the on / off state of the first switching transistor and the fourth switching transistor based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, the HCG or MCG is selected as the conversion efficiency of the pixel, the conversion efficiency of the pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out. By controlling the on / off state of the first switching transistor and the fourth switching transistor based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, the second switching transistor and the third switching transistor are turned on, the MCG or LCG is selected as the conversion efficiency of the pixel, the conversion efficiency of the pixel is set to the selected MCG or LCG, the P-phase level is read out, and then the D-phase level is read out. The intermediate potential may also be a potential that is not transferred to the first floating diffusion when the charge accumulated in the photoelectric conversion unit is below a certain value. This results in CDS and DDS being performed based on the same conversion efficiency readout level during the switching between HCG and MCG, and between MCG and LCG.

[0016] Furthermore, in the first aspect, the system may include a switching control unit that switches the conversion efficiency of the pixels based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion. This eliminates the need for AD conversion of the P-phase level and D-phase level for each switching of the conversion efficiency, while still enabling HDR.

[0017] Also, on the first aspect, when the switching control unit sets the gate potential of the transfer transistor to an intermediate potential, based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, the conversion efficiency of the pixel is switched, and the intermediate potential may be a potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the first floating diffusion when it is below a certain value. As a result, it brings about the effect that the P-phase level and the D-phase level corresponding to the conversion efficiency switched based on the determination result of the signal level are read out.

[0018] Also, on the first aspect, the amplification transistor, the selection transistor, the first switching transistor, the second switching transistor, and the first floating diffusion are shared by a plurality of photoelectric conversion units, and the transfer transistor may be provided for each photoelectric conversion unit. As a result, it brings about the effect that signals can be read out separately from a plurality of pixels while reducing the layout area of the plurality of pixels.

[0019] Also, on the second aspect, an imaging device includes a pixel array unit in which pixels capable of switching conversion efficiency are arranged in a matrix in the row direction and the column direction, and a switching control unit that switches the conversion efficiency of the pixels for each column based on the determination result of the level of the pixel signal read from the pixels. The pixel array unit includes a horizontal control line that transmits a first switching signal for switching the conversion efficiency in the row direction and a vertical control line that transmits a second switching signal for switching the conversion efficiency in the column direction. As a result, it brings about the effect that the conversion efficiency is switched in the row direction and also in the column direction.

[0020] Furthermore, in a second aspect, the vertical control line may include a first vertical control line that transmits a second switching signal for switching the conversion efficiency in the direction of the column, and a second vertical control line that transmits a third switching signal for switching the conversion efficiency in the direction of the column. This results in the reading of P-phase levels and D-phase levels corresponding to the three-stage conversion efficiency, which is switched based on the signal level determination result. [Brief explanation of the drawing]

[0021] [Figure 1] This is a block diagram showing an example configuration of an imaging device according to the first embodiment. [Figure 2] This is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment. [Figure 3] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the first embodiment. [Figure 4] This is a block diagram showing an example configuration of the AD conversion unit according to the first embodiment. [Figure 5] This figure shows an example of a comparator circuit configuration according to the first embodiment. [Figure 6] This figure shows an example of the circuit configuration of the downstream amplifier according to the first embodiment. [Figure 7] This is a timing chart showing the waveforms of each part of the signal readout process according to the first embodiment. [Figure 8] This figure shows an example of the potential readout period of the imaging device according to the first embodiment. [Figure 9] This is a perspective view showing a first example of the stacked structure of a solid-state imaging device according to the first embodiment. [Figure 10] This is a plan view showing a first layout example of a solid-state imaging device according to the first embodiment. [Figure 11] This is a cross-sectional view showing a first configuration example of a solid-state imaging device according to the first embodiment. [Figure 12] This is a perspective view showing a second example of the stacked structure of a solid-state imaging device according to the first embodiment. [Figure 13]This figure shows a first example of the division of the stacked structure of a solid-state imaging device according to the first embodiment. [Figure 14] This is a plan view showing a second layout example of a solid-state imaging device according to the first embodiment. [Figure 15] This is a cross-sectional view showing a second configuration example of a solid-state imaging device according to the first embodiment. [Figure 16] This is a cross-sectional view showing a third configuration example of a solid-state imaging device according to the first embodiment. [Figure 17] This figure shows a second example of the division of the stacked structure of the solid-state imaging device according to the first embodiment. [Figure 18] This is a plan view showing a fourth layout example of a solid-state imaging device according to the first embodiment. [Figure 19] This is a cross-sectional view showing a fourth configuration example of a solid-state imaging device according to the first embodiment. [Figure 20] This is a plan view showing the cutting position in a fourth layout example of a solid-state imaging device according to the first embodiment. [Figure 21] This is a cross-sectional view showing a first configuration example of a cell according to the first embodiment. [Figure 22] This is a cross-sectional view showing a second configuration example of a cell according to the first embodiment. [Figure 23] This is a cross-sectional view showing a third configuration example of a cell according to the first embodiment. [Figure 24] This is a cross-sectional view showing a fourth configuration example of a cell according to the first embodiment. [Figure 25] This is a cross-sectional view showing a fifth configuration example of a cell according to the first embodiment. [Figure 26] This is a plan view showing the cutting position in a fifth layout example of a solid-state imaging device according to the first embodiment. [Figure 27] This is a cross-sectional view showing a sixth configuration example of a cell according to the first embodiment. [Figure 28] This is a cross-sectional view showing a seventh configuration example of a cell according to the first embodiment. [Figure 29]This is a timing chart showing the waveforms of each part of the signal readout process according to the second embodiment. [Figure 30] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the third embodiment. [Figure 31] This is a timing chart showing the waveforms of each part of the signal readout process according to the third embodiment. [Figure 32] This is a plan view showing an example layout of a solid-state imaging device according to the third embodiment. [Figure 33] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the fourth embodiment. [Figure 34] This is a timing chart showing the waveforms of each part of the signal readout process according to the fourth embodiment. [Figure 35] This is a plan view showing an example of the layout of a solid-state imaging device according to the fourth embodiment. [Figure 36] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the fifth embodiment. [Figure 37] This is a timing chart showing the waveforms of each part of the signal readout process according to the fifth embodiment. [Figure 38] This figure shows an example of the division of the stacked structure of a solid-state imaging device according to the fifth embodiment. [Figure 39] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the sixth embodiment. [Figure 40] This is a timing chart showing the waveforms of each part of the signal readout process according to the sixth embodiment. [Figure 41] This is a plan view showing an example layout of a solid-state imaging device according to the sixth embodiment. [Figure 42] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the seventh embodiment. [Figure 43] This is a timing chart showing the waveforms of each part of the signal readout process according to the seventh embodiment. [Figure 44] This is a plan view showing an example of the layout of a solid-state imaging device according to the seventh embodiment. [Figure 45] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the eighth embodiment. [Figure 46] This is a timing chart showing the waveforms of each part of the signal readout process according to the eighth embodiment. [Figure 47] This is a plan view showing an example of the layout of a solid-state imaging device according to the eighth embodiment. [Figure 48] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the ninth embodiment. [Figure 49] This is a timing chart showing the waveforms of each part of the signal readout process according to the ninth embodiment. [Figure 50] This is a plan view showing an example of the layout of a solid-state imaging device according to the ninth embodiment. [Figure 51] This is a block diagram showing an example configuration of the AD conversion unit according to the tenth embodiment. [Figure 52] This figure shows an example of a comparator circuit configuration according to the tenth embodiment. [Figure 53] This is a timing chart showing the waveforms of each part of the signal readout process according to the tenth embodiment. [Figure 54] This figure shows an example of a cell circuit configuration provided in a solid-state imaging device according to the 11th embodiment. [Figure 55] This is a timing chart showing the waveforms of each part of the signal readout process according to the 11th embodiment. [Figure 56] This is a perspective view showing an example of stacking of a solid-state imaging device according to the twelfth embodiment. [Figure 57] This is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 58] This is an explanatory diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0022] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (Example of switching the pixel conversion efficiency based on the determination result of the pixel signal readout level) 2. Second Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential) 3. Third Embodiment (An example in which switching between HCG and MCG and switching between MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential) 4. Fourth Embodiment (An example in which, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion, and the control lines that control the switching of HCG and MCG and the switching of MCG and LCG are made common.) 5. Fifth Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and a LOFIC (Lateral Overflow Integration Capacitor) is provided) 6. Sixth Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and LOFIC and overflow control transistors are provided) 7. Seventh Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and LOFIC is also provided.) 8. Eighth Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and in which LOFIC and overflow control transistors are provided.) 9. A ninth embodiment (an example in which the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided) 10. Tenth Embodiment (An example in which one 4-input comparator is provided for each column, and the AZ level can be set according to the switching of conversion efficiency) 11. Eleventh Embodiment (An example in which the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided.) 12. Twelfth Embodiment (Example of stacked pixel array sections) 13. Examples of applications to mobile devices

[0023] <1. First Embodiment> Figure 1 is a block diagram showing an example configuration of an imaging device according to the first embodiment.

[0024] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging device 100 also includes a drive control unit 109. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, operation unit 107, and drive control unit 109 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0025] The optical system 101 directs light from the subject onto the solid-state imager 102 and forms an optical image on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0026] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. At this time, the solid-state imaging device 102 can output the pixel signal by switching the conversion efficiency of the pixels. For example, the solid-state imaging device 102 may switch the conversion efficiency of the pixels in two stages or in three stages. The solid-state imaging device 102 may also be equipped with multiple floating diffusions to which charge is transferred from the pixels. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0027] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0028] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may also include a processor that performs processing based on software. The image processing unit 104 includes an HDR processing unit 104A.

[0029] The HDR processing unit 104A performs HDR processing based on the pixel signals read from the solid-state imaging device 102. For example, in a dark environment, the HDR processing unit 104A can generate an HDR image based on the combination of the HCG output and MCG output generated by the solid-state imaging device 102. In a bright environment, the HDR processing unit 104A can generate an HDR image based on the combination of the MCG output and LCG output generated by the solid-state imaging device 102. In this case, the HDR processing unit 104A may set an α value (transmittance) and perform α blending.

[0030] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0031] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro-Luminescence) display, or a micro-LED display.

[0032] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0033] The drive control unit 109 controls the drive of the optical system 101 based on the pixel signals read from the solid-state imaging device 102 and the operation information operated by the operation unit 107. For example, the drive control unit 109 can perform manual focusing or control the zoom magnification based on the operation information operated by the operation unit 107.

[0034] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0035] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0036] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0037] The pixel array section 111 comprises a plurality of cells 120. The cells 120 are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). For example, a cell 120 can share n (n is a positive integer) pixels in one floating diffusion. In this case, a photoelectric conversion unit can be provided for each pixel. Note that a cell 120 may share 8 pixels in one floating diffusion, or 4 pixels in one floating diffusion, or it may consist of a single pixel. A cell 120 can configure a source follower with the column readout circuit 113 when reading a signal. Each cell 120 is connected to a horizontal control line 131 in the row direction and to vertical signal lines 132 and vertical control lines 133 in the column direction. The horizontal control line 131 drives each cell 120 horizontally when reading a signal from each cell 120. At this time, the horizontal control line 131 transmits a switching signal to each cell 120 to switch the conversion efficiency of each pixel contained in the cell 120. The vertical signal line 132 transmits the potential based on the current flowing when reading signals from the cell 120 to the column signal processing unit 114 vertically. The vertical control line 133 transmits a switching signal to each cell 120 to switch the conversion efficiency of each pixel contained in the cell 120. The switching signal can, for example, switch the conversion efficiency of the cell 120 between HCG and MCG, or between MCG and LCG.

[0038] Each pixel in cell 120 may form a Bayer array or a quad-Bayer array. The light received by each pixel in each cell 120 may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0039] The vertical scanning circuit 112 scans each pixel in the cell 120 to be read vertically. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may include an address decoder, or it may include a driver that drives the horizontal control line 131 selected via the address decoder row by row.

[0040] The column readout circuit 113 can configure a source follower with each cell 120 when reading a signal from the cell 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the cell 120.

[0041] The column signal processing unit 114 processes signals transmitted vertically from the cell 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted vertically from the cell 120. Furthermore, the column signal processing unit 114 can perform analog-to-digital (AD) conversion processing based on signals transmitted vertically from each cell 120 and output an imaging signal Gout.

[0042] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the cell 120 and the reference signal. Here, the column ADC unit 114A can switch the conversion efficiency of the cell 120 for each column based on the determination result of the level of the pixel signal read from the cell 120. Alternatively, the column ADC unit 114A may switch the conversion efficiency of the cell 120 based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor that transfers the charge accumulated in the photoelectric conversion unit provided in the cell 120 to the floating diffusion is set to an intermediate potential. The intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the floating diffusion when it is below a certain value. Switching the conversion efficiency of the cell 120 based on the determination result of the level of the pixel signal can be performed via the vertical control line 133.

[0043] The horizontal scanning circuit 115 scans each pixel in the cell 120 to be read out in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0044] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0045] Figure 3 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the first embodiment. In this figure, an n-pixel shared cell is used as an example. Furthermore, in this figure, a cell with three levels of conversion efficiency can be set is used as an example.

[0046] In the figure, cell 120 comprises photodiodes PD1 to PDn, transfer transistors TG1 to TGn, reset transistor 121, amplification transistor 122, selection transistor 123, switching transistors 124 to 126, and floating diffusion transistors FD1 to FD3. Transfer transistors TG1 to TGn, reset transistor 121, amplification transistor 122, selection transistor 123, and switching transistors 124 to 126 may be MOS (Metal Oxide Semiconductor) transistors.

[0047] Each photodiode PD1 to PDn performs photoelectric conversion and stores the converted charge. Each photodiode PD1 to PDn can constitute a pixel. Each transfer transistor TG1 to TGn transfers the charge stored in each photodiode PD1 to PDn to the floating diffusion FD1. The reset transistor 121 resets the floating diffusion FD1 to FD3. At this time, the floating diffusion FD2 can be provided between the switching transistors 124 and 125. The floating diffusion FD3 can be provided between the reset transistor 121 and the switching transistor 125. The amplification transistor 122 outputs a signal that follows the potential corresponding to the capacitance of the floating diffusion FD1 to FD3. The selection transistor 123 selects the output of the amplification transistor 122.

[0048] Each switching transistor 124 to 126 switches the conversion efficiency of the amplification transistor 122. At this time, each switching transistor 124 to 126 can switch the capacitance added to the gate of the amplification transistor 122. For example, each switching transistor 124 and 126 adds the capacitance of floating diffusion FD2 to floating diffusion FD1. Switching transistor 126 adds the capacitance of floating diffusion FD3 to floating diffusion FD2.

[0049] Each transfer transistor TG1 through TGn is connected between the cathode of each photodiode PD1 through PDn and the floating diffusion FD1. In this case, the floating diffusion FD1 is shared by the photodiodes PD1 through PDn. The amplification transistor 122 and the selection transistor 123 are connected in series. The drain of the amplification transistor 122 is connected to the power supply potential VDD. The gate of the amplification transistor 122 is connected to the floating diffusion FD1. The source of the selection transistor 123 is connected to the vertical signal line 132.

[0050] The reset transistor 121 is connected between the floating diffusion FD3 and the power supply potential VDD. The switching transistors 124 and 126 are connected in parallel to each other between the floating diffusion FD1 and FD2. The switching transistor 125 is connected between the floating diffusion FD2 and FD3.

[0051] Transfer signals TGL1 to TGLn are applied to the gates of each transfer transistor TG1 to TGn, respectively. A reset signal RST is applied to the gate of reset transistor 121. A selection signal SEL is applied to the gate of selection transistor 123. A switching signal FDG1 is applied to the gate of switching transistor 124. A switching signal FDG2 is applied to the gate of switching transistor 125. The gate of switching transistor 126 is connected to the vertical control line 133. At this time, a switching signal FDGV is applied to the gate of switching transistor 126. Transfer signals TGL1 to TGLn, reset signal RST, selection signal SEL, and switching signals FDG1 and FDG2 can be transmitted to cell 120 via the horizontal control line 131. The switching signal FDGV can be transmitted to cell 120 via the vertical control line 133.

[0052] Figure 4 is a block diagram showing an example configuration of the AD conversion unit according to the first embodiment. Note that this figure shows an example configuration of the AD conversion unit for one column.

[0053] In the figure, the column ADC section 114A includes a comparator CM1, a subsequent amplifier CM2, a latch circuit 151, a multiplexer 152, a counter 153, and a switching control unit 154 for each column. Each comparator CM1 can be configured as a two-input comparator. In this case, the non-inverting input of comparator CM1 is connected to the vertical signal line 132 via input capacitor C2. The inverting input of comparator CM1 is to which a reference signal REF is applied via input capacitor C1. The vertical signal line 132 and the vertical control line 133 are provided for each column.

[0054] Comparator CM1 compares the pixel signal transmitted via the vertical signal line 132 with the reference signal REF. An auto-zero signal AZ is also input to comparator CM1. The auto-zero signal AZ activates the auto-zero operation of comparator CM1 during the auto-zero period. During auto-zero operation, charge can be accumulated in the input capacitors C1 and C2 to balance the non-inverting and inverting inputs of each comparator CM1, respectively.

[0055] The subsequent amplifier CM2 amplifies the output of each comparator CM1 and inputs it to the latch circuit 151 and the multiplexer 152. The latch circuit 151 latches the output of the subsequent amplifier CM2 and inputs it to the multiplexer 152 and the switching control unit 154. The latch circuit 151 can latch the result of determining the magnitude of the D-phase level of the pixel signal. The multiplexer 152 inputs the output of the subsequent amplifier CM2 and the output of the latch circuit 151 as a single signal to the counter 153.

[0056] The switching control unit 154 switches the switching signal FDGV based on the determination result of the magnitude of the D-phase level of the pixel signal latched by the latch circuit 151. For example, if the D-phase level of the pixel signal read out by the HCG is above a threshold level, the switching control unit 154 switches the conversion efficiency of each pixel in the cell 120 to medium or low conversion efficiency. On the other hand, if the D-phase level of the pixel signal read out by the HCG is below a threshold level, the switching control unit 154 switches the conversion efficiency of each pixel in the cell 120 to high conversion efficiency.

[0057] The counter 153 performs a counting operation based on the output timing of the comparison result of each comparator CM1. Then, based on the count value generated by the counting operation, the counter 153 digitizes the pixel signal transmitted via the vertical signal line 132 and outputs the digitized digital signal ADO.

[0058] Figure 5 shows an example of a comparator circuit configuration according to the first embodiment.

[0059] In the figure, comparator CM1 balances comparator inputs DV1 and DV2 based on auto-zero operation and outputs a voltage VC corresponding to the difference between comparator inputs DV1 and DV2. Comparator CM1 comprises PMOS transistors 231 and 232, NMOS transistors 233, 234 and 242, capacitor 238, and switches 236 and 237.

[0060] PMOS transistor 231 and NMOS transistor 233 are connected in series with each other. PMOS transistor 232 and NMOS transistor 234 are also connected in series with each other. The sources of each PMOS transistor 231 and 232 are connected to the power supply potential VDD, and the gates of each PMOS transistor 231 and 232 are connected to the drain of PMOS transistor 231. In this configuration, PMOS transistors 231 and 232 can form a current mirror.

[0061] The gate of NMOS transistor 233 is input to the reference signal REF via input capacitor C1. The gate of NMOS transistor 234 is connected to the potential VSL of the vertical signal line 132 column by column via input capacitor C2.

[0062] A switch 236 is connected between the gate and drain of NMOS transistor 233, and a switch 237 is connected between the gate and drain of NMOS transistor 234. The sources of each NMOS transistor 233 and 234 are connected to ground potential via NMOS transistor 242.

[0063] Switches 236 and 237 are opened and closed based on the auto-zero signal AZ. During the auto-zero period, switches 236 and 237 are turned on based on the auto-zero signal AZ. At this time, current flows through PMOS transistors 231 and 232 based on the current mirror operation of the PMOS transistors 231 and 232. Charge is then accumulated in input capacitors C1 and C2 so that the non-inverting and inverting inputs of comparator CM1 are balanced.

[0064] Capacitor 238 is connected in parallel with PMOS transistor 232. Capacitor 238 can limit the bandwidth. A bias voltage VBN is applied to the gate of NMOS transistor 242. NMOS transistor 242 can operate as a constant current source based on the bias voltage VBN.

[0065] Figure 6 shows an example of the circuit configuration of the downstream amplifier according to the first embodiment.

[0066] In the figure, the subsequent amplifier CM2 includes a PMOS transistor 251, an NMOS transistor 252, a switch 253, and a capacitor 254.

[0067] PMOS transistor 251 and NMOS transistor 252 are connected in series. The source of PMOS transistor 251 is connected to the power supply potential VDD. A switch 253 is connected between the gate and drain of NMOS transistor 252. Switch 253 can be opened and closed based on the auto-zero signal AZ. Capacitor 254 is also connected between the gate of NMOS transistor 252 and ground potential. An input voltage VI is input to the gate of PMOS transistor 251, and an output voltage VO is output from the drain of NMOS transistor 252.

[0068] Figure 7 is a timing chart showing the waveforms of each part of the signal readout process according to the first embodiment. In this figure, an example of the waveform for a 1H period (1 horizontal synchronization period) is shown. The transfer signal TGL is one of the transfer signals TGL1 to TGLn. In this figure, an example of switching between three conversion efficiency levels, including high conversion efficiency (HCG), medium conversion efficiency (MCG), and low conversion efficiency (LCG), is shown. In the digital signal ADO, R() indicates the reset level (P-phase level), and S() indicates the signal level (D-phase level).

[0069] In the figure, this signal readout process includes a high-efficiency P-phase readout period T1, a high-efficiency D-phase settling period T2, a selective-efficiency D-phase readout period T3, a low-efficiency D-phase readout period T4, and a low-efficiency P-phase readout period T5 within a 1H period. A level determination period HK is provided during the high-efficiency D-phase settling period T2. During the selective-efficiency D-phase readout period T3, high or medium conversion efficiency is selected according to the level determination result. During the high-efficiency P-phase readout period T1, the reference signal REF includes the ramp wave RA1. During the level determination period HK, the reference signal REF is set to the threshold level SHL. During the selective-efficiency D-phase readout period T3, the reference signal REF includes the ramp wave RA3. During the low-efficiency D-phase readout period T4, the reference signal REF includes the ramp wave RA4. During the low-efficiency P-phase readout period T5, the reference signal REF includes the ramp wave RA5.

[0070] Before the high-efficiency P-phase readout period T1, the reset signal RST and switching signals FDG1 and FDG2 rise, and the reset transistor 121 and switching transistors 124 and 125 turn on, resetting the floating diffusions FD1 through FD3. Also before the high-efficiency P-phase readout period T1, the auto-zero signal AZ rises, and charge accumulates in the input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively. At this time, auto-zero is taken at the P-phase level, so in the comparison of P-phase levels, the reference signal REF is set according to the auto-zero level.

[0071] Next, during the high-efficiency P-phase readout period T1, the reset signal RST and switching signals FDG1 and FDG2 fall, and the reset transistor 121 and switching transistors 124 and 125 turn off. At this time, the conversion efficiency of cell 120 is set to high conversion efficiency. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0072] Next, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the high conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0073] Next, during the high-efficiency D-phase settling period T2, the transfer signal TGL rises, turning on one of the transfer transistors TG1 through TGn, and transferring the charge accumulated in one of the photodiodes PD1 through PDn to the floating diffusion FD1.

[0074] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122. Then, during the level determination period HK, the high-efficiency D-phase level is compared with the threshold level SHL in the comparator CM1, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0075] Then, when the high conversion efficiency D-phase level is above the threshold level SHL, the switching control unit 154 raises the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to medium conversion efficiency.

[0076] On the other hand, when the high conversion efficiency D-phase level of the switching control unit 154 is below the threshold level SHL, it maintains a low level of the switching signal FDGV and applies it to the cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned off, and the floating diffusion FD1 is disconnected from the floating diffusion FD2. As a result, the conversion efficiency of cell 120 is maintained at high conversion efficiency.

[0077] Next, during the selective conversion efficiency D-phase readout period T3, the transfer signal TGL rises, turning on one of the transfer transistors TG1 to TGn, and the charge accumulated in one of the photodiodes PD1 to PDn is transferred to the floating diffusion FD1.

[0078] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. At this time, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0079] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0080] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0081] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the high conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level.

[0082] Next, during the low-conversion-efficiency D-phase readout period T4, the auto-zero signal AZ rises, and charge accumulates in the input capacitors C1 and C2 so that the non-inverting and inverting inputs of comparator CM1 are balanced, respectively. At this time, auto-zero is taken at the D-phase level, so in the comparison of D-phase levels, the reference signal REF is set according to the auto-zero level. Also, the switching signals FDG1 and FDG2 rise, and the switching transistors 124 and 125 turn on. At this time, the capacitances of floating diffusion transistors FD2 and FD3 are added to floating diffusion transistor FD1, and the conversion efficiency of cell 120 is set to low conversion efficiency. Then, the transfer signal TGL rises, and one of the transfer transistors TG1 to TGn turns on, and the charge accumulated in one of the photodiodes PD1 to PDn is transferred to floating diffusion transistor FD1.

[0083] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-conversion-efficiency D-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0084] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the low conversion efficiency D-phase levels read from cell 120 are AD converted column by column.

[0085] Next, during the low-conversion-efficiency P-phase readout period T5, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusions FD1 through FD3 are reset. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-conversion-efficiency P-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0086] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the low conversion efficiency P-phase level read from cell 120 is AD converted column by column. At this time, DDS (Double Data Sampling) processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0087] Figure 8 shows an example of the readout period potential of the imaging device according to the first embodiment. In Figure 8, a to d show an example of the timing potential of P1 to P4 in Figure 7. Also, in Figure 8, a to d show an example of the potential of the photodiode PD1, transfer transistor TG1, reset transistor 121, switching transistor 126, and floating diffusions FD1, FD2, and FD3.

[0088] In Figure a, at timing P1 in Figure 7, the transfer transistor TG1 and switching transistors 124 to 126 are turned off. At this time, the charge EL1 converted photoelectrically by the photodiode PD1 is stored in the photodiode PD1. In addition, the floating diffusions FD1 and FD2 store the charge EL2 when the reset transistor 121 is turned off, the charge EL3 when the switching transistors 124 and 126 are turned off, and the charge EL4 when the switching transistor 125 is turned off. In addition, the floating diffusion FD3 stores the charge EL2 when the reset transistor 121 is turned off and the charge EL3 when the switching transistor 125 is turned off. At this time, the floating diffusions FD1 and FD2 are set to the reset level RLH in HCG.

[0089] Next, at point b in the same figure, at timing P2 in Figure 7, the charge EL1 accumulated in the photodiode PD1 is transferred to the floating diffusion FD1. At this time, the floating diffusion FD1 is set to the signal level SLH in HCG. Then, during the level determination period HK, the signal level SLH is compared with the threshold level SHL. If the signal level SLH is greater than or equal to the threshold level SHL, the conversion efficiency is switched from HCG to MCG.

[0090] Next, at point c in the same figure, if the signal level SLH is equal to or greater than the threshold level SHL at timing P3 in Figure 7, the switching signal FDGV is activated and the switching transistor 126 is turned on. At this time, the capacitance of floating diffusion FD2 is added to floating diffusion FD1, and the conversion efficiency is switched from HCG to MCG.

[0091] Next, at point d in the same figure, at timing P4 in Figure 7, the switching signal FDGV is brought down, and the switching transistor 126 is turned off. At this time, floating diffusion FD1 is disconnected from floating diffusion FD2. Here, each floating diffusion FD1 and FD2 is set to the sum of the reset level RLM in the MCG and the signal level SLM in the MCG.

[0092] Figure 9 is a perspective view showing a first example of the stacked structure of a solid-state imaging device according to the first embodiment.

[0093] In the figure, in the first example of this stacked structure, a logic board LOB is stacked on a pixel board PXB. Light is incident from the back side of the pixel board PXB.

[0094] Figure 10 is a plan view showing a first layout example of a solid-state imaging device according to the first embodiment. In this figure, an example where n is 4 is shown. Also in this figure, an example is shown in which the cell 120 of Figure 3 is formed on the pixel substrate PXB.

[0095] In the figure, the solid-state imaging device 102 includes a semiconductor layer SUB1. The semiconductor layer SUB1 can be an N-type semiconductor layer. The semiconductor layer SUB1 is provided with an active region AK1, which is isolated by an element isolation region ISA1. The element isolation region ISA1 may be STI (Shallow Trench Isolation). Photodiodes PD1 to PD4, a channel region, and an impurity diffusion layer are formed in the active region AK1. The photodiodes PD1 to PD4 are arranged symmetrically around a floating diffusion FD1. In this case, the photodiodes PD1 to PD4 can be arranged adjacent to each other in the row direction and column direction. The impurity diffusion layer is formed with floating diffusion FD1 to FD3 and the source and drain layers of the pixel transistors. The pixel transistors may include transfer transistors TG1 to TG4, a reset transistor 121, an amplification transistor 122, a selection transistor 123, and switching transistors 124 to 126.

[0096] On the active region AK1, gate electrodes GT1 to GT4 and G1 to G6 are formed. The gate electrodes GT1 to GT4 are arranged symmetrically around the floating diffusion FD1. Each of the gate electrodes GT1 to GT4 can be used as a transfer transistor TG1 to TG4, respectively.

[0097] Tokens G1 to G3 are formed on the active region AK1 adjacent to photodiodes PD2 and PD4. At this time, gates G1 to G3 can be arranged in this order in the column direction. Tokens G4 to G6 are formed on the active region AK1 adjacent to photodiodes PD1 and PD3. At this time, gates G5, G6, and G4 can be arranged in this order in the column direction. Each of the gates G1 to G6 can be used as a reset transistor 121, an amplification transistor 122, a selection transistor 123, and switching transistors 124 to 126, respectively.

[0098] Contact CN1 is placed between gate electrodes G1 and G2. The power supply potential VDD is applied to contact CN1. Contact CN2 is placed adjacent to gate electrode G3. The potential VSL of the vertical signal line 132 is applied to contact CN2. Contact CN3 is placed in active region AK1, which is separated in the column direction from active region AK1 where gate electrodes G5, G6, and G4 are located. The ground potential is applied to contact CN3.

[0099] The material for the semiconductor layer SUB1 may be Si, InGaAs, InP, InSb, HgCdTe, etc. For the gate electrodes GT1 to GT4 and G1 to G6, polycrystalline silicon can be used, for example. For the element isolation region ISA1, an insulator such as SiO2 can be used.

[0100] Figure 11 is a cross-sectional view showing a first configuration example of a solid-state imaging device according to the first embodiment.

[0101] In the figure, a semiconductor layer SUB1 is provided on the pixel substrate PXB. A polycrystalline silicon layer PS1 is formed on the semiconductor layer SUB1 via a gate insulating film GZ1. The polycrystalline silicon layer PS1 can be used for gate electrodes GT1 to GT4 and G1 to G6. A channel region can be formed beneath the polycrystalline silicon layer PS1. An impurity diffusion layer FK1 is also formed on the semiconductor layer SUB1. The impurity diffusion layer FK1 may be N-type or P-type. An insulating layer ZF1 is formed on the semiconductor layer SUB1 such that the polycrystalline silicon layer PS1 is embedded within it. A wiring layer HA1 is embedded within the insulating layer ZF1.

[0102] A semiconductor layer SUB3 is provided on the logic substrate LOB. A polycrystalline silicon layer PS3 is formed on the semiconductor layer SUB3 via a gate insulating film GZ3. The polycrystalline silicon layer PS3 can be used as the gate electrode of a logic circuit. The logic circuit may include, for example, a comparator CM1, a subsequent amplifier CM2, a latch circuit 151, a multiplexer 152, a counter 153, and a switching control unit 154. A channel region can be formed beneath the polycrystalline silicon layer PS3. An impurity diffusion layer FK3 is also formed on the semiconductor layer SUB3. The impurity diffusion layer FK3 may be N-type or P-type. An insulating layer ZF3 is formed on the semiconductor layer SUB3 such that the polycrystalline silicon layer PS3 is embedded within it. A wiring layer HA3 is embedded within the insulating layer ZF3.

[0103] Figure 12 is a perspective view showing a second example of the stacked structure of a solid-state imaging device according to the first embodiment.

[0104] In the figure, in this second example of the stacked structure, a pixel substrate PXB2 is stacked on a pixel substrate PXB1, and a logic substrate LOB is stacked on top of the pixel substrate PXB2. Light is incident from the back side of the pixel substrate PXB1.

[0105] Figure 13 shows a first example of the division of the stacked structure of the solid-state imaging device according to the first embodiment.

[0106] In the figure, the photodiodes PD1 to PDn, transfer transistors TG1 to TGn, amplification transistor 122, and switching transistors 124 and 126 are formed on the pixel substrate PXB1. The reset transistor 121, selection transistor 123, and switching transistor 125 are formed on the pixel substrate PXB2.

[0107] Figure 14 is a plan view showing a second layout example of a solid-state imaging device according to the first embodiment. In this figure, an example is shown in which the photodiodes PD1 to PD4, transfer transistors TG1 to TGn, amplification transistor 122, and switching transistors 124 and 126 of Figure 13 are formed on the pixel substrate PXB1.

[0108] In the figure, the semiconductor layer SUB1 is provided with an active region AK2, and the active region AK2 is isolated by the device isolation region ISA2.

[0109] Photodiodes PD1 to PD4 are formed in the active region AK2. Additionally, gate electrodes GT1 to GT4, G2, G4, and G6 are formed on the active region AK2. The gate electrodes GT1 to GT4 are arranged symmetrically around the floating diffusion FD1.

[0110] Tokens G2, G4, and G6 are formed on the active region AK2 adjacent to the photodiodes PD1 and PD3. At this time, the gates G2, G6, and G4 can be arranged in this order in the column direction. A contact CN3 is placed in the active region AK2 separated in the column direction from the active region AK2 where the gates G2, G4, and G6 are located. A ground potential is applied to the contact CN3. The source and drain layers on both sides of the channel region beneath the gate G2 are connected to the pixel substrate PXB2.

[0111] In this layout, it is no longer necessary to form gate electrodes G1, G3, and G5 on the pixel substrate PXB1. Therefore, the planar size of photodiodes PD1 to PD4 can be increased compared to the layout in Figure 10, and sensitivity can be improved.

[0112] Figure 15 is a cross-sectional view showing a second configuration example of a solid-state imaging device according to the first embodiment.

[0113] In the figure, a semiconductor layer SUB1 is provided on the pixel substrate PXB1. A polycrystalline silicon layer PS1 is formed on the semiconductor layer SUB1 via a gate insulating film GZ1. The polycrystalline silicon layer PS1 can be used for gate electrodes GT1 to GT4, G2, G4, and G6. A channel region can be formed beneath the polycrystalline silicon layer PS1. An impurity diffusion layer FK1 is also formed on the semiconductor layer SUB1. The impurity diffusion layer FK1 may be N-type or P-type. An insulating layer ZF1 is formed on the semiconductor layer SUB1 such that the polycrystalline silicon layer PS1 is embedded within it. A wiring layer HA1 is embedded within the insulating layer ZF1.

[0114] A semiconductor layer SUB2 is provided on the pixel substrate PXB2. A polycrystalline silicon layer PS2 is formed on the semiconductor layer SUB2 via a gate insulating film GZ2. The polycrystalline silicon layer PS2 can be used for gate electrodes G1, G3, and G5. A channel region can be formed beneath the polycrystalline silicon layer PS2. An impurity diffusion layer FK2 is also formed on the semiconductor layer SUB2. The impurity diffusion layer FK2 may be N-type or P-type. An insulating layer ZF2 is formed on the semiconductor layer SUB2 so as to embed the polycrystalline silicon layer PS2. A wiring layer HA2 is embedded in the insulating layer ZF2. A through-electrode THD is also formed on the pixel substrate PXB2. The through-electrode THD penetrates the semiconductor layer SUB2 and connects the wiring layers HA1 and HA2. An insulating layer can be formed around the through-electrode THD to insulate it from the semiconductor layer SUB2.

[0115] A semiconductor layer SUB3 is provided on the logic substrate LOB. A polycrystalline silicon layer PS3 is formed on the semiconductor layer SUB3 via a gate insulating film GZ3. The polycrystalline silicon layer PS3 can be used as the gate electrode of a logic circuit. A channel region can be formed beneath the polycrystalline silicon layer PS3. An impurity diffusion layer FK3 is also formed on the semiconductor layer SUB3. The impurity diffusion layer FK3 may be N-type or P-type. An insulating layer ZF3 is formed on the semiconductor layer SUB3 such that the polycrystalline silicon layer PS3 is embedded within it. A wiring layer HA3 is embedded within the insulating layer ZF3.

[0116] Here, the pixel substrate PXB2 and the logic substrate LOB are directly bonded. At this time, a bonding electrode PXD is formed on the pixel substrate PXB2, and a bonding electrode LOD is formed on the logic substrate LOB. The bonding electrode PXD is exposed from the surface of the insulating layer ZF2, and the bonding electrode LOD is exposed from the surface of the insulating layer ZF3. At this time, the bonding electrodes PXD and LOD can be positioned facing each other. The material for each bonding electrode PXD and LOD can be Cu. The bonding electrodes PXD and LOD can then be electrically connected based on Cu-Cu connections. At this time, the pixel substrate PXB2 and the logic substrate LOB can be connected face to face.

[0117] Figure 16 is a cross-sectional view showing a third configuration example of the solid-state imaging device according to the first embodiment. The layout of this third configuration example is the same as the layout of the second configuration example in Figure 14.

[0118] In the same figure, this third configuration example includes a semiconductor layer SUB12 instead of the semiconductor layer SUB2 in the second configuration example of Figure 15. A polycrystalline silicon layer PS2 is formed on the semiconductor layer SUB12 via a gate insulating film GZ2. An impurity diffusion layer FK2 is also formed on the semiconductor layer SUB12. The semiconductor layer SUB2, the polycrystalline silicon layer PS2, and the wiring layer HA2 are embedded in the insulating layer ZF2.

[0119] Here, the pixel substrate PXB2 is directly bonded to the pixel substrate PXB1 and the logic substrate LOB. In this configuration, to directly bond the pixel substrates PXB1 and PXB2 to each other, a bonding electrode PXD1 is formed on the pixel substrate PXB1, and a bonding electrode PXD2 is formed on the pixel substrate PXB2. The bonding electrode PXD1 is exposed from the surface of the insulating layer ZF1, and the bonding electrode PXD2 is exposed from the surface of the insulating layer ZF2. In this configuration, the bonding electrodes PXD1 and PXD2 can be positioned facing each other. The material for each bonding electrode PXD1 and PXD2 can be Cu. The bonding electrodes PXD1 and PXD2 can be electrically connected based on Cu-Cu connections. In this configuration, the pixel substrates PXB1 and PXB2 can be connected face-to-bottom. The bonding electrode PXD1 is connected to the wiring layer HA1 via THD1, and the bonding electrode PXD2 is connected to the wiring layer HA2 via THD2. In this configuration, an opening for the via THD2 can be formed in the semiconductor layer SUB12.

[0120] Figure 17 shows a second example of the division of the stacked structure of the solid-state imaging device according to the first embodiment.

[0121] In the figure, the photodiodes PD1 to PDn and the transfer transistors TG1 to TGn are formed on the pixel substrate PXB1. The reset transistor 121, the amplification transistor 122, the selection transistor 123, and the switching transistors 124 to 126 are formed on the pixel substrate PXB2.

[0122] Figure 18 is a plan view showing a fourth layout example of a solid-state imaging device according to the first embodiment. In this figure, an example is shown in which photodiodes PD1 to PD4 are formed on the pixel substrate PXB1.

[0123] In the figure, the semiconductor layer SUB1 is provided with an active region AK4, and the active region AK4 is isolated by the device isolation region ISA4.

[0124] Photodiodes PD1 to PD4 are formed in the active region AK4. Guard gates GT1 to GT4 are also formed on the active region AK4. The guard gates GT1 to GT4 are arranged symmetrically around the floating diffusion FD1.

[0125] In this layout, it is no longer necessary to form gate electrodes G1 to G6 on the pixel substrate PXB1. Therefore, the planar size of photodiodes PD1 to PD4 can be increased compared to the layout in Figure 14, and sensitivity can be improved.

[0126] Figure 19 is a cross-sectional view showing a fourth configuration example of a solid-state imaging device according to the first embodiment.

[0127] In this figure, the fourth configuration example is obtained by reversing the semiconductor layer SUB12 and the wiring layer HA2 vertically compared to the third configuration example in Figure 16. In this case, the pixel substrates PXB1 and PXB2 can be connected face to face. The pixel substrate PXB2 and the logic substrate LOB can be connected face to bottom. The other configurations of the fourth configuration example are the same as those of the third configuration example in Figure 16.

[0128] Figure 20 is a plan view showing the cutting position in a fourth layout example of the solid-state imaging device according to the first embodiment, and Figure 21 is a cross-sectional view showing a first configuration example of the cell according to the first embodiment. In Figure 21, a configuration example cut along the line A1-A2 in Figure 20 is shown.

[0129] In Figure 21, the semiconductor layer SUB1 is separated into cells 120 at each pixel isolation region 161. The pixel isolation region 161 may be, for example, FFTI (Full-thickness Front deep Trench Isolation). In this case, the pixel isolation region 161 can penetrate the semiconductor layer SUB1 in the depth direction. The pixel isolation region 161 can be placed at the boundary of the cells 120.

[0130] On the back side of the semiconductor layer SUB1, color filters 163 are formed for each photodiode PD1 to PD4. A light-shielding film 162 is formed between the color filters 163. On the light-shielding film 162 and the color filters 163, on-chip lenses 164 are formed for each photodiode PD1 to PD4. The materials for the color filters 163 and on-chip lenses 164 can be, for example, insulating films such as SiO2, SiN, or SiCN, or transparent resins such as acrylic or polycarbonate. The color filters 163 may contain pigments. The color filters 163 may form a Bayer array or a quad Bayer array, for example. The color filters 163 may include RGB filters, complementary color filters, or white filters. The material for the light-shielding film 162 may be black resin. The light-shielding film 162 may contain carbon black or black pigment.

[0131] An N-type impurity diffusion layer 186 is formed in the semiconductor layer SUB1. The N-type impurity diffusion layer 186 can be positioned at the locations of photodiodes PD1 to PD4. Around the pixel separation region 161, P + A type impurity diffusion layer 181 is formed. At the position surrounded by photodiodes PD1 to PD4, N + A type impurity diffusion layer 183 is formed. + The impurity diffusion layer 183 can be used in floating diffusion FD1. + Around the type impurity diffusion layer 183, a polycrystalline silicon layer PS1 is formed, separated for each photodiode PD1 to PD4. In this case, the polycrystalline silicon layer PS1 can be used for gate electrodes GT1 to GT4.

[0132] N + Below the type impurity diffusion layer 183, P + A type impurity diffusion layer 187 is formed. + The type impurity diffusion layer 187 can form a potential barrier that separates the N-type impurity diffusion layer 186 from photodiode PD1 to PD4. +The P-type impurity diffusion layer 187 can be arranged in a plug shape at the boundary positions of the photodiodes PD1 to PD4.

[0133] Also, in the semiconductor layer SUB1, an N + -type impurity diffusion layer 185 is formed adjacent to the N + -type impurity diffusion layer 183. The depth of the N + -type impurity diffusion layer 185 can be made deeper than the depth of the N + -type impurity diffusion layer 183. The N + -type impurity diffusion layer 185 can be arranged under the polycrystalline silicon layer PS1.

[0134] N + An embedded transfer gate 171 is embedded in the -type impurity diffusion layer 185. The embedded transfer gate 171 is connected to the polycrystalline silicon layer PS1. At this time, the polycrystalline silicon layer PS1 and the embedded transfer gate 171 can be integrally used as gate electrodes GT1 to GT4. Here, by providing the embedded transfer gate 171, the transfer efficiency can be improved. The polycrystalline silicon layer PS1 is connected to the wiring layer HA1 via the via THD1.

[0135] Also, in the semiconductor layer SUB1, a P + -type impurity diffusion layer 184 is formed adjacent to the N + -type impurity diffusion layer 185. The P + -type impurity diffusion layer 184 can be extended to the position of the pixel isolation region 161. The P + -type impurity diffusion layer 184 can form a potential gradient for easily transferring the charges accumulated in the photodiodes PD1 to PD4 to the floating diffusion FD1.

[0136] FIG. 22 is a cross-sectional view showing a second configuration example of the cell according to the first embodiment.

[0137] In the same figure, this second configuration example includes pixel separation regions 191 and 192 in place of the pixel separation region 161 of the first configuration example in Figure 21. The other configurations of this second configuration example are the same as those of the first configuration example in Figure 21.

[0138] The semiconductor layer SUB1 is separated into cell 120 units by pixel isolation regions 191 and 192. Pixel isolation region 191 may be, for example, RDTI (Rear Deep Trench Isolation). Pixel isolation region 192 may be STI or LOCOS (Local Oxidation of Silicon). In this case, pixel isolation region 191 can penetrate in the depth direction from the back side of the semiconductor layer SUB1. Pixel isolation regions 191 and 192 can be placed at the boundaries of cell 120. Furthermore, pixel isolation region 191 is P + It can be embedded in the type impurity diffusion layer 187.

[0139] Figure 23 is a cross-sectional view showing a third configuration example of a cell according to the first embodiment.

[0140] In the same figure, this third configuration example is the same as the first configuration example in Figure 21, but with the embedded transfer gate 171 removed. The other configurations of this third configuration example are the same as those of the first configuration example in Figure 21.

[0141] Figure 24 is a cross-sectional view showing a fourth configuration example of a cell according to the first embodiment.

[0142] In the same figure, this fourth configuration example includes an on-chip lens 164' in place of the on-chip lens 164 in the first configuration example of Figure 21. The other configurations of this fourth configuration example are the same as those of the first configuration example of Figure 21.

[0143] The on-chip lens 164' is provided in common for photodiodes PD1 to PD4. The on-chip lens 164' is positioned on the light-shielding film 162 and the color filter 163.

[0144] Figure 25 is a cross-sectional view showing a fifth configuration example of a cell according to the first embodiment.

[0145] In the same figure, this fifth configuration example includes a light-shielding film 162' instead of the light-shielding film 162 in the fourth configuration example of Figure 24. The other configurations of this fifth configuration example are the same as those of the fourth configuration example of Figure 24.

[0146] The light-shielding film 162' is placed between photodiodes PD1 to PD4, and is also placed in place of one of the color filters 163 on photodiodes PD1 to PD4. In this case, photodiodes PD1 to PD4 can be used not only as imaging pixels but also as image plane phase-difference pixels.

[0147] Figure 26 is a plan view showing the cutting position in a fifth layout example of the solid-state imaging device according to the first embodiment.

[0148] In the same figure, this layout example includes an element isolation region ISA4' in place of the element isolation region ISA4 in the fourth layout example of Figure 20. The other configurations of this layout example are the same as those of the fourth layout example of Figure 20.

[0149] The element isolation region ISA4' separates the floating diffusion FD1 for each photodiode PD1 to PD4 in the semiconductor layer SUB1. By separating the floating diffusion FD1 for each photodiode PD1 to PD4, it is possible to reduce crosstalk between pixels and increase the signal strength.

[0150] Figure 27 is a cross-sectional view showing a sixth configuration example of the cell according to the first embodiment. Note that Figure 27 shows a configuration example cut along the line A1-A2 in Figure 26.

[0151] In the same figure, this sixth configuration example is the first configuration example in Figure 21 with the addition of a pixel separation region 161'. The other configurations of this sixth configuration example are the same as those of the first configuration example in Figure 21.

[0152] The pixel isolation region 161' may be, for example, FFTI. In this case, the pixel isolation region 161' can penetrate the semiconductor layer SUB1 in the depth direction. The pixel isolation region 161' is N + The type impurity diffusion layer 183 is separated for each photodiode PD1 to PD4. At this time, the pixel separation region 161' is N + It can penetrate the type impurity diffusion layers 183 and 187. N separated for each photodiode PD1 to PD4. + The impurity diffusion layers 183 can be connected to each other via the wiring layer HA1.

[0153] Figure 28 is a cross-sectional view showing a seventh configuration example of a cell according to the first embodiment.

[0154] In the same figure, this seventh configuration example is the same as the sixth configuration example in Figure 27, but with the embedded transfer gate 171 removed. The other configurations of this seventh configuration example are the same as those of the sixth configuration example in Figure 27.

[0155] As described above, in the first embodiment, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level. This makes it possible to acquire data with three levels of conversion efficiency through four AD conversions: the P phase of HCG, the D phase of HCG or MCG, the D phase of LCG, and the P phase of LCG. Therefore, it becomes possible to achieve HDR while suppressing a decrease in frame rate.

[0156] <2. Second Embodiment> In the first embodiment described above, the pixel conversion efficiency was switched based on the determination result of the readout level of the pixel signal. In this second embodiment, the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor is set to an intermediate potential. The intermediate potential is the potential at which no charge is transferred to the floating diffusion FD1 when the charge accumulated in any of the photodiodes PD1 to PDn is below a certain value.

[0157] Figure 29 is a timing chart showing the waveforms of each part of the signal readout process according to the second embodiment. Note that the cells in the second embodiment are the same as the cells in the first embodiment described above.

[0158] In the figure, this signal readout process provides a determination level setting period T11, a selective conversion efficiency P-phase readout period T12, and a selective conversion efficiency D-phase readout period T13, instead of the high conversion efficiency P-phase readout period T1, high conversion efficiency D-phase settling period T2, and selective conversion efficiency D-phase readout period T3 of the first embodiment described above. The determination level setting period T11 includes a level determination period HK. In the selective conversion efficiency P-phase readout period T12 and the selective conversion efficiency D-phase readout period T13, high conversion efficiency or medium conversion efficiency is selected according to the level determination result. In the level determination period HK, the reference signal REF is set to the threshold level SHB. The threshold level SHB is set to a value that allows determination of whether or not charge has been transferred to the floating diffusion FD1 when a charge exceeding a certain value is accumulated in cell 120. In the selective conversion efficiency P-phase readout period T12, the reference signal REF includes the ramp wave RA1. During the selective conversion efficiency P-phase readout period T13, the reference signal REF includes the ramp wave RA3.

[0159] Before the judgment level setting period T11, the reset signal RST and switching signals FDG1, FDG2, and FDGV rise, and the reset transistor 121 and switching transistors 124, 125, and 126 turn on, resetting floating diffusions FD1 through FD3. Also before the judgment level setting period T11, the auto-zero signal AZ rises, and charge accumulates in the input capacitors C1 and C2 of the comparator CM1 so that the non-inverting and inverting inputs are balanced, respectively.

[0160] Next, during the judgment level setting period T11, if the transfer signal TGL rises to an intermediate potential, and any of the transfer transistors TG1 to TGn are half-on, and a charge exceeding a certain value is accumulated in any of the photodiodes PD1 to PDn, that charge is transferred to the floating diffusion FD1. If the charge accumulated in any of the photodiodes PD1 to PDn is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0161] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplification transistor 122. During the level determination period HK, the level corresponding to the presence or absence of charge in the floating diffusion FD1 is compared with the threshold level SHB in the comparator CM1, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0162] Then, when the level of the presence or absence of charge in the floating diffusion FD1 is above the threshold level SHB, the switching control unit 154 raises the switching signal FDGV and applies it to the cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to medium conversion efficiency.

[0163] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, falls below the threshold level SHB, the switching control unit 154 maintains a low level of the switching signal FDGV and applies it to the cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned off, and the floating diffusion FD1 is disconnected from the floating diffusion FD2. As a result, the conversion efficiency of the cell 120 is maintained at a high conversion efficiency.

[0164] Next, during the selective conversion efficiency P-phase readout period T12, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0165] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0166] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0167] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the high conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0168] Subsequently, the transfer signal TGL rises, turning on either the transfer transistor TG1 through TGn, and transferring the charge stored in either the photodiode PD1 through PDn to the floating diffusion FD1. Then, when the transfer signal TGL falls, the transfer transistors TG1 through TGn turn off.

[0169] Next, during the selective conversion efficiency D-phase readout period T13, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0170] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0171] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0172] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the high conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level.

[0173] Next, similar to the first embodiment described above, the system transitions to a low-conversion-efficiency D-phase readout period T4, followed by a low-conversion-efficiency P-phase readout period T5.

[0174] Thus, in the second embodiment described above, the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor is set to an intermediate potential. This makes it possible to determine the signal level without reading out the high conversion efficiency D-phase level. Therefore, the P-phase level and D-phase level corresponding to the conversion efficiency switched based on the signal level determination result can be read out, and CDS can be performed based on the readout level at the same conversion efficiency. As a result, it becomes possible to achieve HDR with reduced S / N step at the junction between HCG and MCG while suppressing a decrease in frame rate.

[0175] <3. Third Embodiment> In the second embodiment described above, the pixel conversion efficiency was switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor was set to an intermediate potential. In this third embodiment, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor was set to an intermediate potential.

[0176] Figure 30 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the third embodiment.

[0177] In the figure, cell 320 has switching transistors 311 and 312 added to cell 120 of the first embodiment described above. Also, cell 320 has the switching transistor 124 removed from cell 120 of the first embodiment described above. Furthermore, cell 320 has vertical control lines 133A and 133B instead of the vertical control line 133 of the first embodiment described above. The other configurations of cell 320 are the same as those of cell 120 of the first embodiment described above.

[0178] Each switching transistor 311 and 312 switches the conversion efficiency of the amplification transistor 122. At this time, each switching transistor 311 and 312 can switch the capacitance added to the gate of the amplification transistor 122. For example, each switching transistor 311 adds the capacitance of floating diffusion FD2 to floating diffusion FD1. Switching transistor 312 adds the capacitance of floating diffusion FD3 to floating diffusion FD2.

[0179] Switching transistor 311 is connected between floating diffusion transistors FD1 and FD2. Switching transistor 312 is connected between floating diffusion transistor FD2 and switching transistor 311. At this time, switching transistors 311, 125, 312 and reset transistor 121 are connected in series in this order.

[0180] The gate of switching transistor 311 is connected to vertical control line 133A. At this time, switching signal FDGV1 is applied to the gate of switching transistor 311. The gate of switching transistor 312 is connected to vertical control line 133B. At this time, switching signal FDGV2 is applied to the gate of switching transistor 312.

[0181] Figure 31 is a timing chart showing the waveforms of each part of the signal readout process according to the third embodiment.

[0182] In the figure, this signal readout process includes a determination level setting period T31, a first selective conversion efficiency P-phase readout period T32, a first selective conversion efficiency D-phase readout period T33, a second selective conversion efficiency D-phase readout period T34, and a second selective conversion efficiency P-phase readout period T35, all within a 1H period. The determination level setting period T31 includes a level determination period HK. During the first selective conversion efficiency P-phase readout period T32 and the first selective conversion efficiency D-phase readout period T33, high or medium conversion efficiency is selected according to the level determination result. During the second selective conversion efficiency D-phase readout period T34 and the second selective conversion efficiency P-phase readout period T35, medium or low conversion efficiency is selected according to the level determination result. During the level determination period HK, the reference signal REF is set to the threshold level SHB. During the first selective conversion efficiency P-phase readout period T32, the reference signal REF includes the ramp wave RA1. During the first selective conversion efficiency D-phase readout period T33, the reference signal REF includes the ramp wave RA3. During the second selective conversion efficiency D-phase readout period T34, the reference signal REF includes the ramp wave RA4. During the second selective conversion efficiency P-phase readout period T35, the reference signal REF includes the ramp wave RA5.

[0183] Before the judgment level setting period T31, the reset signal RST and switching signals FDG2, FDGV1, and FDGV2 rise, and the reset transistor 121 and switching transistors 125, 311, and 312 turn on, resetting the floating diffusion transistors FD1 through FD3. Also before the judgment level setting period T31, the auto-zero signal AZ rises, and charge accumulates in the respective input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively.

[0184] Next, during the judgment level setting period T31, if the transfer signal TGL rises to an intermediate potential, and any of the transfer transistors TG1 to TGn are half-on, and a charge exceeding a certain value is accumulated in any of the photodiodes PD1 to PDn, that charge is transferred to the floating diffusion FD1. If the charge accumulated in any of the photodiodes PD1 to PDn is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0185] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplification transistor 122. During the level determination period HK, the level corresponding to the presence or absence of charge in the floating diffusion FD1 is compared with the threshold level SHB in the comparator CM1, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0186] Then, when the level of the presence or absence of charge in the floating diffusion FD1 is above the threshold level SHB, the switching control unit 154 raises the switching signal FDGV1 and applies it to the cell 120 via the vertical control line 133A. At this time, the switching transistor 311 is turned on, and the capacitance of the floating diffusion FD2 is added to the floating diffusion FD1. As a result, the conversion efficiency of the cell 120 switches to medium conversion efficiency.

[0187] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, falls below the threshold level SHB, the switching control unit 154 maintains a low level of the switching signal FDGV1 and applies it to cell 120 via the vertical control line 133A. At this time, the switching transistor 311 is turned off, and the floating diffusion FD1 is disconnected from the floating diffusion FD2. As a result, the conversion efficiency of cell 120 is maintained at a high conversion efficiency.

[0188] Next, during the first selective conversion efficiency P-phase readout period T32, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0189] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0190] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0191] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the high conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0192] Subsequently, the transfer signal TGL rises, turning on either the transfer transistor TG1 through TGn, and transferring the charge stored in either the photodiode PD1 through PDn to the floating diffusion FD1. Then, when the transfer signal TGL falls, the transfer transistors TG1 through TGn turn off.

[0193] Next, during the first selective conversion efficiency D-phase readout period T33, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0194] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0195] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0196] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the high conversion efficiency D-phase level read from cell 120 is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level.

[0197] Next, during the second selective conversion efficiency D-phase readout period T34, the auto-zero signal AZ rises, and charge accumulates in the input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively. Also, the switching signal FDGV1 is set to a high level and applied to cell 120 via the vertical control line 133A. At this time, the switching transistor 311 turns on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. Also, the switching signal FDG2 rises, and the switching transistor 125 turns on. At this time, floating diffusion FD2 is connected to switching transistor 312.

[0198] Furthermore, during the determination level setting period T31, if the level corresponding to the presence or absence of charge in floating diffusion FD1 is equal to or greater than the threshold level SHB, the switching control unit 154 raises the switching signal FDGV2 and applies it to cell 120 via the vertical control line 133B. At this time, the switching transistor 312 turns on, and the capacitance of floating diffusion FD3 is added to floating diffusion FD2. As a result, the conversion efficiency of cell 120 switches to low conversion efficiency.

[0199] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, falls below the threshold level SHB, the switching control unit 154 maintains the low level of the switching signal FDGV2 and applies it to cell 120 via the vertical control line 133B. At this time, the switching transistor 312 is turned off, and the floating diffusion FD2 is disconnected from the floating diffusion FD3. As a result, the conversion efficiency of cell 120 is maintained at a medium conversion efficiency.

[0200] Then, the transfer signal TGL rises, turning on one of the transfer transistors TG1 through TGn, and the charge accumulated in one of the photodiodes PD1 through PDn is transferred to the floating diffusion diode FD1.

[0201] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, if a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0202] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the low conversion efficiency D-phase levels read from cell 120 are AD converted column by column.

[0203] On the other hand, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0204] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column.

[0205] Next, during the second selective conversion efficiency P-phase readout period T35, the reset signal RST and the switching signal FDGV2 rise, turning on the reset transistor 121 and the switching transistor 312, and resetting the floating diffusions FD1 to FD3. Then, the reset signal RST falls, and the reset transistor 121 turns off. Also, the level of the switching signal FDGV2 is set based on the determination result of the level determination period HK, and the switching transistor 312 turns on or off according to that level. Here, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0206] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column. At this time, DDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0207] On the other hand, if a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0208] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the low conversion efficiency P-phase level read from cell 120 is AD converted column by column. At this time, DDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0209] Figure 32 is a plan view showing an example of the layout of a solid-state imaging device according to the third embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 320 of Figure 30 is formed on the pixel substrate PXB.

[0210] In the figure, an active region AK31 is provided in the semiconductor layer SUB1, and the active region AK31 is isolated by an element isolation region ISA31. On the active region AK31, gate electrodes GT1 to GT4, G1 to G3, G5, G31, and G32 are formed.

[0211] Token gates G4, G31, and G32 are formed on the active region AK1 adjacent to the photodiodes PD1 and PD3. At this time, the gate gates G32, G5, and G31 can be arranged in this order in the column direction. Each gate gate G31 and G32 can be used for the switching transistors 311 and 312, respectively. The other configurations of the layout example according to the third embodiment are the same as those of the layout example in Figure 10.

[0212] Thus, in the third embodiment described above, when the gate potential of the transfer transistor is set to an intermediate potential, the switching between HCG and MCG and the switching between MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1. This makes it possible to perform CDS and DDS based on the same conversion efficiency readout level in the switching between HCG and MCG and the switching between MCG and LCG. As a result, it becomes possible to achieve HDR with reduced S / N steps at the transitions between HCG and MCG and between MCG and LCG while suppressing a decrease in frame rate.

[0213] <4. Fourth Embodiment> In the third embodiment described above, when the gate potential of the transfer transistor was set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG were performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1. In this fourth embodiment, when the gate potential of the transfer transistor was set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG were performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1, and the vertical control lines that control the switching of HCG and MCG and the switching of MCG and LCG were made common.

[0214] Figure 33 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the fourth embodiment.

[0215] In the figure, cell 420 has a switching transistor 411 added to cell 120 of the first embodiment described above. The other configurations of cell 420 are the same as those of cell 120 of the first embodiment described above.

[0216] The switching transistor 411 switches the conversion efficiency of the amplification transistor 122. At this time, the switching transistor 411 can switch the capacitance added to the gate of the amplification transistor 122. For example, the switching transistor 411 adds the capacitance of floating diffusion FD3 to floating diffusion FD2.

[0217] The switching transistor 411 is connected between the switching transistor 125 and the floating diffusion FD3. At this time, the switching transistors 125, 411, and reset transistor 121 are connected in series in this order.

[0218] The gate of switching transistor 411 is connected to the vertical control line 133. At this time, the switching signal FDGV is applied to the gate of switching transistor 411. In addition, the switching signals FDGH are applied to the gates of switching transistors 124 and 125.

[0219] Figure 34 is a timing chart showing the waveforms of each part of the signal readout process according to the fourth embodiment.

[0220] In the figure, this signal readout process provides selective conversion efficiency D-phase readout periods T44 and P-phase readout periods T45, instead of the low conversion efficiency D-phase readout periods T4 and P-phase readout periods T5 of the second embodiment described above. In selective conversion efficiency D-phase readout periods T44 and P-phase readout periods T45, medium or low conversion efficiency is selected according to the level determination result. In selective conversion efficiency D-phase readout period T44, the reference signal REF includes ramp wave RA4. In selective conversion efficiency P-phase readout period T45, the reference signal REF includes ramp wave RA5.

[0221] During the selective conversion efficiency D-phase readout period T44, the switching signal FDGH rises, and switching transistors 124 and 125 turn on. At this time, the capacitance of floating diffusion FD2 is added to floating diffusion FD1, and floating diffusion FD2 is connected to switching transistor 411.

[0222] Furthermore, during the level determination period HK, if the switching control unit 154 determines that the level corresponding to the presence or absence of charge in the floating diffusion FD1 is equal to or greater than the threshold level SHB, it raises the switching signal FDGV and applies it to the cell 120 via the vertical control line 133. At this time, the switching transistor 411 is turned on, and the capacitance of floating diffusion FD3 is added to floating diffusion FD2. As a result, the conversion efficiency of cell 120 switches to low conversion efficiency.

[0223] On the other hand, when the switching control unit 154 determines that the level of the charge in floating diffusion FD1 is below the threshold level SHB, it maintains the low level of the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, the switching transistor 411 is turned off, and floating diffusion FD2 is disconnected from floating diffusion FD3. As a result, the conversion efficiency of cell 120 is maintained at a medium conversion efficiency.

[0224] Then, the transfer signal TGL rises, turning on one of the transfer transistors TG1 through TGn, and the charge accumulated in one of the photodiodes PD1 through PDn is transferred to the floating diffusion diode FD1.

[0225] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, if a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0226] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the low conversion efficiency D-phase levels read from cell 120 are AD converted column by column.

[0227] On the other hand, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0228] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column.

[0229] Next, during the selective conversion efficiency P-phase readout period T45, the reset signal RST and the switching signal FDGV rise, turning on the reset transistor 121 and the switching transistor 411, and resetting the floating diffusions FD1 to FD3. Then, the reset signal RST falls, and the reset transistor 121 turns off. Also, the level of the switching signal FDGV is set based on the determination result of the level determination period HK, and the switching transistor 411 turns on or off according to that level. Here, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0230] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column. At this time, DDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0231] On the other hand, if a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0232] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the low conversion efficiency P-phase level read from cell 120 is AD converted column by column. At this time, DDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0233] Note that the MCGs for low-light and high-light applications have different FD capacities (conversion efficiency), but this is not a problem as long as they can receive the desired charge. Also, the readout methods for DDS and CDS already differ.

[0234] Figure 35 is a plan view showing an example of the layout of a solid-state imaging device according to the fourth embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 420 of Figure 33 is formed on the pixel substrate PXB.

[0235] In the figure, an active region AK41 is provided in the semiconductor layer SUB1, and the active region AK41 is isolated by an element isolation region ISA41. On the active region AK41, gate electrodes GT1 to GT4, G1 to G6, and G41 are formed.

[0236] On the active region AK1 adjacent to the photodiodes PD1 and PD3, gate electrodes G4 to G6 and G41 are formed. At this time, gate electrodes G41, G5, G4, and G6 can be arranged in this order in the column direction. Gate electrode G41 can be used for the switching transistor 411. The other configurations of the layout example according to the fourth embodiment are the same as those of the layout example in Figure 10.

[0237] Thus, in the fourth embodiment described above, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1, and the vertical control line 133 that controls the switching of HCG and MCG and the switching of MCG and LCG is made common. As a result, by providing one vertical control line 133 for each column in the switching of HCG and MCG and the switching of MCG and LCG, CDS and DDS can be performed based on the readout level with the same conversion efficiency. Therefore, it is possible to realize HDR with reduced S / N step differences at the connection between HCG and MCG and between MCG and LCG while suppressing an increase in circuit size, and it is also possible to suppress a decrease in frame rate.

[0238] <5. Fifth Embodiment> In the first embodiment described above, the pixel conversion efficiency was switched based on the determination result of the pixel signal readout level. In this fifth embodiment, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and LOFIC is also provided.

[0239] Figure 36 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the fifth embodiment.

[0240] In the figure, cell 520 has a capacity CF added to cell 120 of the first embodiment described above. The other configurations of cell 520 are the same as those of cell 120 of the first embodiment described above.

[0241] The capacitance CF can be used as a LOFIC. The capacitance CF is connected between the control voltage FVD and the floating diffusion FD3. The capacitance CF may be a MIM (Metal Insulator Metal) capacitance, a MOM (Metal Oxide Metal) capacitance, or a MOS (Metal Oxide Semiconductor) capacitance. At this time, the capacitance CF can achieve a saturation capacitance about 50 to 100 times the saturation capacitance of each photodiode PD1 to PDn. The control voltage FVD can pulse-drive the capacitance CF. By pulse-driving the capacitance CF, the dark current can be reduced. Here, the capacitance CF can accumulate the charges overflowing from each photodiode PD1 to PDn, and can expand the dynamic range.

[0242] A switching signal FDG is applied to the gate of the switching transistor 124. A switching signal FCG is applied to the gate of the switching transistor 125.

[0243] FIG. 37 is a timing chart showing waveforms of each part of the signal readout process according to the fifth embodiment.

[0244] In the figure, the signal readout process of the fifth embodiment includes a high conversion efficiency P-phase readout period T51 instead of the high conversion efficiency P-phase readout period T1 of the above-described first embodiment. Also, instead of the switching signal FDG1, the switching signal FDG is applied to the gate of the switching transistor 124, and instead of the switching signal FDG2, the switching signal FCG is applied to the gate of the switching transistor 125. Other points are the same as the signal readout process of the above-described first embodiment.

[0245] Before the high-efficiency P-phase readout period T51, the switching signals FCG and FDG rise, and the switching transistors 124 and 125 turn on. As a result, the charge overflowing from each photodiode PD1 to PDn is stored in the capacitance CF via the floating diffusion FD1 to FD3. Also, the reset signal RST remains at a low level, and the reset transistor 121 turns off. Therefore, the charge overflowing from each photodiode PD1 to PDn to the floating diffusion FD1 to FD3 is prevented from being reset.

[0246] Furthermore, a capacitance CF is added to the floating diffusion FD3. Therefore, when the switching transistor 125 is turned on during the low-conversion-efficiency D-phase readout period T4 and the low-conversion-efficiency P-phase readout period T5, the conversion efficiency decreases by the amount of the added capacitance CF.

[0247] The layout and cross-sectional structure of the fifth embodiment may be, for example, the layout and cross-sectional structure shown in Figures 9 to 11. In this case, the capacitance CF may be formed in the wiring layer HA1 or in the wiring layer HA3.

[0248] Figure 38 shows an example of the division of the stacked structure of a solid-state imaging device according to the fifth embodiment.

[0249] In the figure, the capacitance CF is formed on the pixel substrate PXB1. At this time, the capacitance CF can be formed on the wiring layer HA1. The capacitance CF may be formed on the pixel substrate PXB1 or on the logic substrate LOB. The photodiodes PD1 to PDn, transfer transistors TG1 to TGn, reset transistor 121, amplification transistor 122, selection transistor 123, and switching transistors 124 to 126 are formed on the pixel substrate PXB2.

[0250] Thus, in the fifth embodiment described above, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and LOFIC is also provided. This makes it possible to expand the dynamic range in HDR while suppressing a decrease in frame rate.

[0251] <6. Sixth Embodiment> In the fifth embodiment described above, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and an overflow control transistor is provided. In this sixth embodiment, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and an overflow control transistor and an overflow control transistor are provided.

[0252] Figure 39 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the sixth embodiment.

[0253] In the figure, cell 620 is the same as cell 520 of the fifth embodiment described above, with the addition of overflow control transistors FG1 through FGn. Also, the source connection destination of the reset transistor 121 is changed from floating diffusion FD3 to floating diffusion FD2. The other configurations of cell 620 are the same as those of cell 520 of the fifth embodiment described above.

[0254] Each overflow control transistor FG1 to FGn controls the overflow from each photodiode PD1 to PDn, respectively. The source of each overflow control transistor FG1 to FGn is connected to the cathode of each photodiode PD1 to PDn, respectively. The drain of each overflow control transistor FG1 to FGn is connected to capacitance CF. Here, the charge overflowing from each photodiode PD1 to PDn is stored in capacitance CF via each overflow control transistor FG1 to FGn, respectively. Therefore, the charge overflowing from each photodiode PD1 to PDn can be prevented from accumulating in capacitance CF via floating diffusions FD1 and FD2. As a result, floating diffusions FD1 and FD2 can be reset during readout, and fixed pattern noise caused by dark current can be reduced.

[0255] Overflow control signals OFG1 to OFGn are applied to the gates of each overflow control transistor FG1 to FGn, respectively. Each overflow control signal OFG1 to OFGn may be a fixed voltage.

[0256] Figure 40 is a timing chart showing the waveforms of each part of the signal readout process according to the sixth embodiment.

[0257] In the figure, in the signal readout process of the sixth embodiment, the switching signal FDG is applied to the gate of the switching transistor 124 instead of the switching signal FDG1, and the switching signal FCG is applied to the gate of the switching transistor 125 instead of the switching signal FDG2. Also, before the high conversion efficiency P-phase readout period T1, the switching signal FCG is maintained at a low level, and the switching transistor 125 is turned off. Other aspects of the signal readout process according to the sixth embodiment are the same as those of the signal readout process of the first embodiment described above.

[0258] Here, before the high-efficiency P-phase readout period T1, the reset signal RST and the switching signal FDG rise, the reset transistor 121 and the switching transistor 124 turn on, and the floating diffusions FD1 and FD2 are reset. Therefore, compared to the fifth embodiment described above, fixed pattern noise caused by dark current can be reduced.

[0259] Furthermore, the charge that overflows from each photodiode PD1 to PDn is stored in the capacitance CF via each overflow control transistor FG1 to FGn and floating diffusion FD3. Therefore, by changing the connection destination of the reset transistor 121 from floating diffusion FD3 to floating diffusion FD2, it is possible to reset each floating diffusion FD1 and FD2 while preventing the charge that overflows from each photodiode PD1 to PDn to floating diffusion FD3 from being reset.

[0260] Figure 41 is a plan view showing an example of the layout of a solid-state imaging device according to the sixth embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 620 of Figure 39 is formed on the pixel substrate PXB.

[0261] In the figure, an active region AK61 is provided in the semiconductor layer SUB1, and the active region AK61 is isolated by an element isolation region ISA61. On the active region AK61, gate electrodes GT1 to GT4, G1 to G6, GF1, and GF2 are formed.

[0262] A gate electrode GF1 is formed on the active region AK1 adjacent to photodiodes PD1 and PD2. A gate electrode GF2 is formed on the active region AK1 adjacent to photodiodes PD3 and PD4. Each gate electrode GF1 and GF2 can be used for overflow control transistors FG1 to FG4. The other configurations of the layout example according to the sixth embodiment are the same as those of the layout example in Figure 10.

[0263] Thus, in the sixth embodiment described above, based on the determination result of the read level of the pixel signal, the conversion efficiency of the pixel is switched, and LOFIC and overflow control transistors FG1 to FGn are provided. Thereby, while suppressing the decrease in the frame rate, it becomes possible to expand the dynamic range in HDR and reduce the fixed pattern noise caused by dark current.

[0264] <7. The Seventh Embodiment> In the fourth embodiment described above, based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor is set to the intermediate potential, the switching between HCG and MCG and the switching between MCG and LCG are performed. At this time, the vertical control line 133 that controls the switching between HCG and MCG and the switching between MCG and LCG is shared. In this seventh embodiment, based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor is set to the intermediate potential, the switching between HCG and MCG and the switching between MCG and LCG are performed. At this time, the vertical control line 133 that controls the switching between HCG and MCG and the switching between MCG and LCG is shared, and LOFIC is provided.

[0265] FIG. 42 is a diagram showing an example of the circuit configuration of a cell provided in the solid-state imaging device according to the seventh embodiment.

[0266] In the figure, a capacitor CF is added to the cell 420 of the fourth embodiment described above in this cell 720. The other configuration of the cell 720 is the same as the configuration of the cell 420 of the fourth embodiment described above.

[0267] Capacitor CF can be used as LOFIC. Capacitor CF is connected between the control voltage FVD and the floating diffusion FD3. Capacitor CF can store the charge overflowing from each photodiode PD1 to PDn, thereby expanding the dynamic range.

[0268] Figure 43 is a timing chart showing the waveforms of each part of the signal readout process according to the seventh embodiment.

[0269] In the figure, the signal readout process of the seventh embodiment includes a determination level setting period T71 instead of the determination level setting period T11 of the fourth embodiment described above. Also, the switching signal FDG is applied to the gate of the switching transistor 124 instead of the switching signal FDG1, and the switching signal FCG is applied to the gate of the switching transistor 125 instead of the switching signal FDG2. In all other respects, it is the same as the signal readout process of the fourth embodiment described above.

[0270] Before the judgment level setting period T71, the switching signal FDGH rises, and switching transistors 124 and 125 turn on. As a result, the charge overflowing from each photodiode PD1 to PDn is stored in the capacitance CF via the floating diffusion FD1 to FD3. Also, the reset signal RST remains at a low level, and the reset transistor 121 turns off. Therefore, the charge overflowing from each photodiode PD1 to PDn to the floating diffusion FD1 to FD3 is prevented from being reset.

[0271] Furthermore, a capacitance CF is added to the floating diffusion FD3. Therefore, when the switching transistor 411 is turned on during the selective conversion efficiency D-phase readout period T44 and the selective conversion efficiency P-phase readout period T45, the conversion efficiency decreases by the amount of the added capacitance CF compared to the signal readout process of the fourth embodiment described above.

[0272] Note that the MCGs for low-light and high-light applications have different FD capacities (conversion efficiency), but this is not a problem as long as they can receive the desired charge. Also, the readout methods for DDS and CDS already differ.

[0273] Figure 44 is a plan view showing an example of the layout of a solid-state imaging device according to the seventh embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 720 of Figure 42 is formed on the pixel substrate PXB.

[0274] In the figure, an active region AK71 is provided in the semiconductor layer SUB1, and the active region AK71 is isolated by an element isolation region ISA71. On the active region AK71, gate electrodes GT1 to GT4, G1 to G6, and G41 are formed.

[0275] On the active region AK1 adjacent to the photodiodes PD1 and PD3, gate electrodes G4 through G6 and G41 are formed. At this time, gate electrodes G41, G5, G6 and G4 can be arranged in this order in the column direction. The other configurations of the layout example according to the seventh embodiment are the same as those of the layout example in Figure 35.

[0276] Thus, in the seventh embodiment described above, the pixel conversion efficiency is switched and LOFIC is provided based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor is set to an intermediate potential. This makes it possible to expand the dynamic range in HDR by reducing the S / N step difference at the junction between HCG and MCG and the junction between MCG and LCG, while suppressing a decrease in the frame rate.

[0277] <8. Eighth Embodiment> In the seventh embodiment described above, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1. At this time, the vertical control line 133 that controls the switching of HCG and MCG and the switching of MCG and LCG is made common, and LOFIC is provided. In this eighth embodiment, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1. At this time, the vertical control line 133 that controls the switching of HCG and MCG and the switching of MCG and LCG is made common, and LOFIC and overflow control transistors FG1 to FGn are provided.

[0278] Figure 45 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the eighth embodiment.

[0279] In the figure, cell 820 is the same as cell 720 of the seventh embodiment described above, with the addition of overflow control transistors FG1 through FGn. Also, the source connection of the reset transistor 121 is changed from floating diffusion FD3 to floating diffusion FD2. The other configurations of cell 820 are the same as those of cell 720 of the seventh embodiment described above.

[0280] Each overflow control transistor FG1 to FGn controls the overflow from each photodiode PD1 to PDn, respectively. Here, the charge overflowing from each photodiode PD1 to PDn is stored in the capacitance CF via each overflow control transistor FG1 to FGn. Therefore, the charge overflowing from each photodiode PD1 to PDn can be prevented from accumulating in the capacitance CF via the floating diffusion transistors FD1 and FD2. As a result, the floating diffusion transistors FD1 and FD2 can be reset during readout, and fixed pattern noise caused by dark current can be reduced.

[0281] Figure 46 is a timing chart showing the waveforms of each part of the signal readout process according to the eighth embodiment.

[0282] In the figure, in the signal readout process of the eighth embodiment, the switching signal FCGH is maintained at a low level before the determination level setting period T11, and the switching transistor 125 is turned off. Furthermore, the signal readout process of the eighth embodiment includes the determination level setting period T11 of the second embodiment described above, instead of the determination level setting period T71 of the seventh embodiment described above. All other aspects of the signal readout process according to the eighth embodiment are the same as those of the signal readout process of the seventh embodiment described above.

[0283] Figure 47 is a plan view showing an example of the layout of a solid-state imaging device according to the eighth embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 820 of Figure 45 is formed on the pixel substrate PXB.

[0284] In the figure, an active region AK81 is provided in the semiconductor layer SUB1, and the active region AK81 is isolated by an element isolation region ISA81. On the active region AK81, gate electrodes GT1 to GT4, G1 to G6, and G41 are formed.

[0285] A gate electrode GF1 is formed on the active region AK1 adjacent to photodiodes PD1 and PD2. A gate electrode GF2 is formed on the active region AK1 adjacent to photodiodes PD3 and PD4. The other configurations of the layout example according to the eighth embodiment are the same as those of the layout example in Figure 44.

[0286] Note that the MCGs for low-light and high-light applications have different FD capacities (conversion efficiency), but this is not a problem as long as they can receive the desired charge. Also, the readout methods for DDS and CDS already differ.

[0287] As described above, in the eighth embodiment, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1. At this time, the vertical control line 133 that controls the switching of HCG and MCG and the switching of MCG and LCG is made common, and FGn is provided from LOFIC and overflow control transistor FG1. This makes it possible to expand the dynamic range in HDR by reducing the S / N step difference at the connection between HCG and MCG and the connection between MCG and LCG, while suppressing a decrease in frame rate, and also reduces fixed pattern noise caused by dark current.

[0288] <9. The ninth embodiment> In the seventh embodiment described above, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and LOFIC is provided. In this ninth embodiment, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided.

[0289] Figure 48 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the ninth embodiment.

[0290] In the figure, cell 920 replaces the photodiodes PD1 to PDn and transfer transistors TG1 to TGn of the fifth embodiment described above with photodiodes LPD, SPD and transfer transistor TG. Also, the source connection destination of the reset transistor 121 is changed from floating diffusion FD3 to floating diffusion FD2. The other configurations of cell 920 are the same as those of cell 520 in the fifth embodiment described above.

[0291] Each photodiode LPD and SPD performs photoelectric conversion and stores the converted charge. The sensitivity of the photodiode SPD can be made smaller than that of the photodiode LPD. For example, the planar size of the photodiode SPD can be made smaller than that of the photodiode LPD. The cathode of the photodiode SPD is connected to the floating diffusion FD3. By making the sensitivity of the photodiode SPD smaller than that of the photodiode LPD, the saturation signal amount can be increased even if the capacitance value of the capacitance CF is reduced. The dielectric constant of the capacitance CF can be reduced, and afterimages caused by dielectric absorption can be reduced.

[0292] The transfer transistor TG transfers the charge stored in the photodiode LPD to the floating diffusion FD1. The transfer transistor TG is connected between the cathode of the photodiode LPD and the floating diffusion FD1. A transfer signal TGL is applied to the gate of the transfer transistor TG.

[0293] Figure 49 is a timing chart showing the waveforms of each part of the signal readout process according to the ninth embodiment.

[0294] In the figure, this signal readout process includes a high conversion efficiency, high sensitivity P-phase readout period T91, a high conversion efficiency, high sensitivity D-phase settling period T92, a selective conversion efficiency, high sensitivity D-phase readout period T93, a low conversion efficiency, low sensitivity D-phase readout period T94, and a low conversion efficiency, low sensitivity P-phase readout period T95 within a 1H period. A level determination period HK is provided during the high conversion efficiency, high sensitivity D-phase settling period T92. During the selective conversion efficiency, high sensitivity D-phase readout period T93, high or medium conversion efficiency is selected in the photodiode LPD according to the level determination result. During the high conversion efficiency, high sensitivity P-phase readout period T91, the reference signal REF includes the ramp wave RA1. During the level determination period HK, the reference signal REF is set to the threshold level SHL. During the selective conversion efficiency, high sensitivity D-phase readout period T93, the reference signal REF includes the ramp wave RA3. During the low conversion efficiency and low sensitivity D-phase readout period T94, the reference signal REF includes the ramp wave RA4. During the low conversion efficiency and low sensitivity P-phase readout period T95, the reference signal REF includes the ramp wave RA5.

[0295] Before the high-efficiency, high-sensitivity P-phase readout period T91, the reset signal RST and the switching signal FDG rise up, turning on the reset transistor 121 and the switching transistor 124, and resetting the floating diffusion transistors FD1 and FD2. Also before the high-efficiency P-phase readout period T91, the auto-zero signal AZ rises up, and charge accumulates in the respective input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively.

[0296] Next, during the high-conversion-efficiency, high-sensitivity P-phase readout period T91, the reset signal RST and the switching signal FDG fall, and the reset transistor 121 and the switching transistor 124 turn off. At this time, the conversion efficiency of cell 120 is set to high conversion efficiency. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-conversion-efficiency, high-sensitivity P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0297] Next, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency and high sensitivity P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the high conversion efficiency and high sensitivity P-phase levels read from cell 120 are AD converted column by column.

[0298] Next, during the high-conversion-efficiency, high-sensitivity D-phase settling period T92, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode LPD is transferred to the floating diffusion FD1.

[0299] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-conversion-efficiency, high-sensitivity D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122. Then, during the level determination period HK, the high-conversion-efficiency, high-sensitivity D-phase level is compared with the threshold level SHL in the comparator CM1, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0300] Then, when the high-efficiency, high-sensitivity D-phase level is above the threshold level SHL, the switching control unit 154 raises the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to medium conversion efficiency.

[0301] On the other hand, when the high-conversion-efficiency, high-sensitivity D-phase level is below the threshold level SHL, the switching control unit 154 maintains a low level of the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, the switching transistor 126 is turned off, and the floating diffusion FD1 is disconnected from the floating diffusion FD2. As a result, the conversion efficiency of cell 120 is maintained at high conversion efficiency.

[0302] Next, during the selective conversion efficiency high-sensitivity D-phase readout period T93, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode LPD is transferred to the floating diffusion FD1.

[0303] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. At this time, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency high-sensitivity D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0304] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency, high sensitivity D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency, high sensitivity D-phase level read from the photodiode LPD is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency, high sensitivity P-phase level and the medium conversion efficiency, high sensitivity D-phase level.

[0305] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency, high sensitivity D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0306] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency, high sensitivity D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the high conversion efficiency, high sensitivity D-phase level read from the photodiode LPD is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency, high sensitivity P-phase level and the high conversion efficiency, high sensitivity D-phase level.

[0307] Next, immediately before the low-conversion-efficiency, low-sensitivity D-phase readout period T94, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 121 and the switching transistor 124, and resetting the floating diffusion transistors FD1 and FD2. At this time, the charge transferred from the photodiode LPD to the floating diffusion transistors FD1 and FD2 can be reset. Also, the auto-zero signal AZ rises, and charge is accumulated in the respective input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively.

[0308] Next, during the low-conversion-efficiency, low-sensitivity D-phase readout period T94, the reset signal RST falls, and the reset transistor 121 turns off. At the same time, the switching signal FCG rises, and the switching transistor 125 turns on. At this time, the capacitances of floating diffusions FD2 and FD3 are added to floating diffusion FD1, and the conversion efficiency of cell 120 is set to low conversion efficiency. Also, the charge accumulated in the photodiode SPD is transferred to floating diffusions FD1 and FD2 via switching transistors 124 and 125. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-conversion-efficiency, low-sensitivity D-phase levels of floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0309] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency, low sensitivity D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the low conversion efficiency, low sensitivity D-phase levels read from the photodiode SPD are AD converted column by column.

[0310] Next, during the low-conversion-efficiency, low-sensitivity P-phase readout period T95, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusions FD1 through FD3 are reset. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-conversion-efficiency, low-sensitivity P-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0311] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency, low sensitivity P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the low sensitivity, low conversion efficiency P-phase levels read from cell 120 are AD converted column by column. At this time, DDS processing can be performed based on the low conversion efficiency, low sensitivity P-phase level and the low conversion efficiency, low sensitivity D-phase level.

[0312] Figure 50 is a plan view showing an example of the layout of a solid-state imaging device according to the ninth embodiment. In this figure, an example is shown where n is 4. Also in this figure, an example is shown in which the cell 920 of Figure 48 is formed on the pixel substrate PXB.

[0313] In the figure, an active region AK91 is provided in the semiconductor layer SUB1, and the active region AK91 is isolated by an element isolation region ISA91. A photodiode LPD, SPD, channel region, and impurity diffusion layer are formed in the active region AK91. Guard gates GT, G1 to G6 are formed on the active region AK91.

[0314] The photodiode SPD is positioned at one corner of the photodiode LPD. A gate electrode GT is formed on the active region AK1 where the photodiode LPD is formed. Gates G4 to G6 are formed on the active region AK1 connected to the photodiode LPD via gate electrode GT. At this time, gate electrodes G5, G6, and G4 can be arranged in this order in the column direction. A floating diffusion FD1 is formed between gate electrodes G4 and G6. A floating diffusion FD2 is formed between gate electrodes G5 and G6. A floating diffusion FD3 is formed on one side of gate electrode G5. The active region AK1 where the floating diffusion FD3 is formed is connected to the photodiode SPD. The other configurations of the layout example according to the ninth embodiment are the same as those of the layout example in Figure 10.

[0315] Thus, in the ninth embodiment described above, the pixel conversion efficiency is switched based on the determination result of the pixel signal readout level, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided. This makes it possible to expand the dynamic range in HDR while suppressing a decrease in frame rate, and to suppress afterimages caused by dielectric absorption.

[0316] In the first embodiment described above, variations in the layout and cross-sectional configuration of cell 120 are shown in Figures 9 to 28. The variations in layout and cross-sectional configuration shown in Figures 9 to 28 may be applied not only to the first embodiment described above, but also to the second to ninth embodiments described above.

[0317] <10. Tenth Embodiment> In the first embodiment described above, the pixel conversion efficiency was switched based on the determination result of the readout level of the pixel signal. In this tenth embodiment, one 4-input comparator is provided for each column, making it possible to set the AZ level according to the switching of the conversion efficiency.

[0318] Figure 51 is a block diagram showing an example configuration of the AD conversion unit according to the tenth embodiment. Note that this figure shows an example configuration of the AD conversion unit for one column.

[0319] In the figure, the column ADC unit 114A of the tenth embodiment includes comparator CM11, switching control unit 1054, and input capacitors CH1, CL1, CH2, CL2 instead of comparator CM1, switching control unit 154, and input capacitors C1, C2 of the first embodiment described above. Furthermore, the column ADC unit 114A of the tenth embodiment has switches WH1, WL1, WH2, WL2 added to the column ADC unit 114A of the first embodiment described above. The other configurations of the column ADC unit 114A of the tenth embodiment are the same as those of the column ADC unit 114A of the first embodiment described above.

[0320] Comparator CM11 can be configured as a 4-input comparator. The two non-inverting inputs of comparator CM11 are connected to vertical signal line 132 via switches WH2 and WL2 and input capacitors CH2 and CL2, respectively. Switch WH2 and input capacitor CH2 are connected in series with each other. Switch WL2 and input capacitor CL2 are connected in series with each other. The two inverting inputs of comparator CM11 are to which the reference signal REF is applied via switches WH1 and WL1 and input capacitors CH1 and CL1, respectively. Switch WH1 and input capacitor CH1 are connected in series with each other. Switch WL1 and input capacitor CL1 are connected in series with each other.

[0321] Comparator CM11 compares the pixel signal transmitted via the vertical signal line 132 with the reference signal REF. At this time, the non-inverting and inverting inputs of comparator CM11 are switched according to the conversion efficiency of cell 420, and auto-zero operation is performed. Then, charge is accumulated in input capacitors CH1, CL1, CH2, and CL2 so that the non-inverting and inverting inputs of comparator CM11 are balanced according to the conversion efficiency of cell 420.

[0322] For example, the conversion efficiency of cell 420 is switched to HCG or MCG based on the determination result of the pixel signal readout level. At this time, when switches WH1 and WH2 are turned on, charge is accumulated in input capacitors CH1 and CH2 so that the non-inverting and inverting inputs of comparator CM11 are balanced. Also, the conversion efficiency of cell 420 is switched to MCG or LCG based on the determination result of the pixel signal readout level. At this time, when switches WL1 and WL2 are turned on, charge is accumulated in input capacitors CL1 and CL2 so that the non-inverting and inverting inputs of comparator CM11 are balanced.

[0323] The switching control unit 1054 switches the switching signal FDGV based on the determination result of the D-phase level of the pixel signal latched by the latch circuit 151. The switching control unit 1054 also switches switches WH1, WL1, WH2, and WL2 based on the determination result of the D-phase level of the pixel signal latched by the latch circuit 151, and selects two inputs via input capacitors CL1 and CL2 or two inputs via input capacitors CH1 and CH2 as comparison targets.

[0324] Figure 52 shows an example of a comparator circuit configuration according to the tenth embodiment.

[0325] In the figure, comparator CM11 balances comparator inputs DVH1 and DVH2 based on auto-zero operation according to the conversion efficiency of cell 420, and then outputs a voltage CPO corresponding to the difference between comparator inputs DVH1 and DVH2. Comparator CM11 also balances comparator inputs DVL1 and DVL2 based on auto-zero operation according to the conversion efficiency of cell 420, and then outputs a voltage CPO corresponding to the difference between comparator inputs DVL1 and DVL2. Comparator CM11 comprises PMOS transistors 261 and 262, NMOS transistors 263, 264, 269, 273, and 274, capacitor 268, and switches 271, 272, 281, and 282.

[0326] PMOS transistor 261 and NMOS transistor 263 are connected in series with each other. PMOS transistor 262 and NMOS transistor 264 are also connected in series with each other. The sources of each PMOS transistor 261 and 262 are connected to the power supply potential VDD, and the gates of each PMOS transistor 261 and 262 are connected to the drain of PMOS transistor 261. In this configuration, PMOS transistors 261 and 262 can form a current mirror.

[0327] NMOS transistor 273 is connected in parallel to NMOS transistor 263. NMOS transistor 274 is connected in parallel to NMOS transistor 264. The drains of each NMOS transistor 263 and 273 are connected to the drain of PMOS transistor 261 via switches 281 and 271, respectively. The drains of each NMOS transistor 264 and 274 are connected to the drain of PMOS transistor 262 via switches 282 and 272, respectively.

[0328] The gate of NMOS transistor 263 is input with reference signal REF via switch WL1 and input capacitor CL1. The gate of NMOS transistor 273 is input with reference signal REF via switch WH1 and input capacitor CH1. The gate of NMOS transistor 264 is connected to the potential VSL of vertical signal line 132 column by column via switch WL2 and input capacitor CL2. The gate of NMOS transistor 274 is connected to the potential VSL of vertical signal line 132 column by column via switch WH2 and input capacitor CH2.

[0329] A switch 266 is connected between the gate and drain of NMOS transistor 263, and a switch 267 is connected between the gate and drain of NMOS transistor 264. A switch 276 is connected between the gate and drain of NMOS transistor 273, and a switch 277 is connected between the gate and drain of NMOS transistor 274. The sources of each NMOS transistor 263, 264, 273, and 274 are connected to ground potential via NMOS transistor 269.

[0330] Switches 266, 267, 276, and 277 are opened and closed based on the auto-zero signal AZ. During the auto-zero period, switches 266, 267, 276, and 277 are turned on based on the auto-zero signal AZ. At this time, current flows through PMOS transistors 261 and 262 based on the current mirror operation of the PMOS transistors 261 and 262. Charge is then accumulated in the input capacitors CH1, CH2, CL1, and CL2 so that the non-inverting and inverting inputs of comparator CM11 are balanced according to the conversion efficiency of cell 420.

[0331] Capacitor 268 is connected in parallel with PMOS transistor 262. Capacitor 268 can limit the bandwidth.

[0332] Switches WL1, WL2, 281, and 282 are subjected to a switching signal SCM. When switches WL1, WL2, 281, and 282 are turned on based on the switching signal SCM, the inputs of the reference signal REF and the potential VSL of the vertical signal line 132 are activated via input capacitors CL1 and CL2. Switches WH1, WH2, 271, and 272 are subjected to a switching inversion signal SCB. When switches WH1, WH2, and switches 271 and 272 are turned on based on the switching inversion signal SCB, the inputs of the reference signal REF and the potential VSL of the vertical signal line 132 are activated via input capacitors CH1 and CH2. The switching inversion signal SCB is the inverted version of the switching signal SCM.

[0333] A bias voltage VBN is applied to the gate of the NMOS transistor 269. Based on the bias voltage VBN, the NMOS transistor 269 can operate as a constant current source.

[0334] Figure 53 is a timing chart showing the waveforms of each part of the signal readout process according to the tenth embodiment. Note that the cells in the tenth embodiment are the same as the cells in the fourth embodiment described above.

[0335] In the figure, this signal readout process includes a determination level setting period T101, a first selective conversion efficiency P-phase readout period T102, a second selective conversion efficiency P-phase readout period T103, a first selective conversion efficiency D-phase readout period T104, and a second selective conversion efficiency D-phase readout period T105, all within a 1H period. The determination level setting period T101 includes a level determination period HK. During the first selective conversion efficiency P-phase readout period T102 and the second selective conversion efficiency D-phase readout period T105, either medium or low conversion efficiency is selected according to the level determination result. During the second selective conversion efficiency P-phase readout period T103 and the first selective conversion efficiency D-phase readout period T104, either high or medium conversion efficiency is selected according to the level determination result. During the level determination period HK, the reference signal REF is set to the threshold level SHB. During the first selective conversion efficiency P-phase readout period T102, the reference signal REF includes the ramp wave RA12. During the second selective conversion efficiency P-phase readout period T103, the reference signal REF includes the ramp wave RA13. During the first selective conversion efficiency D-phase readout period T104, the reference signal REF includes the ramp wave RA14. During the second selective conversion efficiency D-phase readout period T105, the reference signal REF includes the ramp wave RA15.

[0336] Before the judgment level setting period T101, the reset signal RST and switching signals FDG1, FDG2, and FDGV rise, and the reset transistor 121 and switching transistors 124, 125, 126, and 411 turn on, resetting the floating diffusion FD1 through FD3.

[0337] Furthermore, before the judgment level setting period T101, the switching signal SCM rises, and switches WL1, WL2, 281, and 282 are turned on. As a result, NMOS transistor 263 is connected to PMOS transistor 261, and NMOS transistor 264 is connected to PMOS transistor 262. Also, the reference signal REF is applied to input capacitor CL1, and the potential VSL of the vertical signal line 132 is applied to input capacitor CL2. Then, the auto-zero signal AZ rises, and charge is accumulated in each input capacitor CL1 and CL2 so that the non-inverting and inverting inputs of comparator CM11 are balanced, respectively.

[0338] Next, during the judgment level setting period T101, the reset signal RST and switching signals FDG1, FDG2, and FDGV fall, and the reset transistor 121 and switching transistors 124, 125, 126, and 411 turn off. Subsequently, the transfer signal TGL rises to an intermediate potential, and any of the transfer transistors TG1 to TGn are half-on. If a charge exceeding a certain value is accumulated in any of the photodiodes PD1 to PDn, that charge is transferred to the floating diffusion FD1. If the charge accumulated in any of the photodiodes PD1 to PDn is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0339] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when a level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplification transistor 122. During the level determination period HK, the level corresponding to the presence or absence of charge in the floating diffusion FD1 is compared with the threshold level SHB in the comparator CM11, and the comparison result is input to the switching control unit 1054 via the latch circuit 151.

[0340] Next, during the selective conversion efficiency P-phase readout period T102, switching signals FDG1 and FDG2 rise, and switching transistors 124 and 125 turn on. At this time, floating diffusion FD1 is connected to switching transistor 411 via switching transistors 124 and 125. Then, when the level of the presence or absence of charge in floating diffusion FD1 is above the threshold level SHB, the switching control unit 1054 raises the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, switching transistor 126 turns on, and the capacitances of floating diffusions FD2 and FD3 are added to floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to low conversion efficiency.

[0341] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, falls below the threshold level SHB, the switching control unit 1054 maintains the low level of the switching signal FDGV and applies it to cell 120 via the vertical control line 133. At this time, the switching transistor 411 is turned off, and the floating diffusion FD2 is disconnected from the floating diffusion FD3. As a result, the conversion efficiency of cell 120 switches to medium conversion efficiency.

[0342] Then, when a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0343] Then, in comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave RA11, and the timing when the level of the ramp wave RA12 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA12 matches the potential VSL of the vertical signal line 132, the low conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0344] On the other hand, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0345] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA12, and the timing when the level of the ramp wave RA12 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA12 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0346] Subsequently, the switching signals FDG1 and FDG2 fall, and switching transistors 124 and 125 turn off. At this time, the floating diffusion FD1 is disconnected from switching transistor 411.

[0347] Next, during the second selective conversion efficiency P-phase readout period T103, the switching signal SCM falls, and switches WH1, WH2, 271, and 272 are turned on. As a result, NMOS transistor 273 is connected to PMOS transistor 261, and NMOS transistor 274 is connected to PMOS transistor 262. The reference signal REF is applied to input capacitor CH1, and the potential VSL of the vertical signal line 132 is applied to input capacitor CH2. Then, the auto-zero signal AZ rises, and charge is accumulated in each input capacitor CH1 and CH2 so that the non-inverting and inverting inputs of comparator CM11 are balanced, respectively.

[0348] Then, during the level determination period HK, if the level of floating diffusion FD1, based on the presence or absence of charge, is determined to be above the threshold level SHB, floating diffusion FD2 and FD3 are separated from floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to high conversion efficiency.

[0349] On the other hand, if, during the level determination period HK, the level determined by the presence or absence of charge in floating diffusion FD1 is found to be below the threshold level SHB, the capacity of floating diffusion FD2 is added to floating diffusion FD1. As a result, the conversion efficiency of cell 120 switches to medium conversion efficiency.

[0350] Then, when high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0351] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RA13, and the timing when the level of the ramp wave RA13 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA13 matches the potential VSL of the vertical signal line 132, the high conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0352] On the other hand, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0353] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA13, and the timing when the level of the ramp wave RA13 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA13 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0354] Next, during the first selective conversion efficiency D-phase readout period T104, the transfer signal TGL rises, turning on either the transfer transistor TG1 to TGn, and transferring the charge stored in either the photodiode PD1 to PDn to the floating diffusion FD1. Then, when the transfer signal TGL falls, the transfer transistors TG1 to TGn turn off.

[0355] Then, when high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0356] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RA14, and the timing when the level of the ramp wave RA14 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA14 matches the potential VSL of the vertical signal line 132, the high conversion efficiency D-phase level read from cell 120 is AD converted column by column. Here, CDS processing can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level.

[0357] On the other hand, if a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0358] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA14, and the timing when the level of the ramp wave RA14 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA14 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column. Here, CDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0359] Next, during the second selective conversion efficiency D-phase readout period T105, the switching signal SCM rises, and switches WL1, WL2, 281, and 282 are turned on. As a result, NMOS transistor 263 is connected to PMOS transistor 261, and NMOS transistor 264 is connected to PMOS transistor 262. In addition, the reference signal REF is applied to input capacitor CL1, and the potential VSL of the vertical signal line 132 is applied to input capacitor CL2.

[0360] Furthermore, when the switching signals FDG1 and FDG2 rise, the switching transistors 124 and 125 turn on. At this time, the floating diffusion FD1 is connected to the switching transistor 411 via the switching transistors 124 and 125.

[0361] Then, the transfer signal TGL rises, turning on one of the transfer transistors TG1 through TGn, and transferring the charge stored in one of the photodiodes PD1 through PDn to the floating diffusion diode FD1. When the transfer signal TGL falls, the transfer transistors TG1 through TGn turn off.

[0362] Then, when a medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0363] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA15, and the timing when the level of the ramp wave RA15 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA15 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 120 is AD converted column by column. Here, CDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0364] On the other hand, if a low conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusions FD1, FD2, and FD3 are applied to the gate of the amplification transistor 122.

[0365] Then, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave RA15, and the timing when the level of the ramp wave RA15 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA15 matches the potential VSL of the vertical signal line 132, the low conversion efficiency D-phase level read from cell 120 is AD converted column by column. Here, CDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0366] Thus, in the tenth embodiment described above, when the gate potential of the transfer transistor is set to an intermediate potential, the switching of HCG and MCG and the switching of MCG and LCG are performed based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion FD1, and the AZ level can be set according to the switching of the conversion efficiency. As a result, CDS can be performed based on the read level at the same conversion efficiency when switching between HCG and MCG and when switching between MCG and LCG. Therefore, it is possible to realize HDR with reduced S / N step differences at the junction between HCG and MCG and between MCG and LCG, and it is possible to suppress a decrease in the frame rate.

[0367] <11. Eleventh Embodiment> In the ninth embodiment described above, the pixel conversion efficiency is switched based on the determination result of the readout level of the pixel signal, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided. In this eleventh embodiment, the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided.

[0368] Figure 54 shows an example of a cell circuit configuration provided in a solid-state imaging device according to the 11th embodiment.

[0369] In the figure, cell 1120 has a switching transistor 1125 added to cell 920 of the ninth embodiment described above. The other configurations of cell 1120 are the same as those of cell 920 of the ninth embodiment described above.

[0370] Switching transistor 1125 is connected in series with switching transistor 125. At this time, the series circuit of switching transistors 125 and 1125 is connected between floating diffusions FD2 and FD3. The gate of switching transistor 1125 is connected to vertical control line 133A. At this time, the switching signal FDGV is applied to the gate of switching transistor 1125. Also, the gates of switching transistors 124 and 125 are connected to vertical control line 133B. At this time, the switching signal FCGV is applied to the gates of switching transistors 124 and 125.

[0371] Figure 55 is a timing chart showing the waveforms of each part of the signal readout process according to the 11th embodiment.

[0372] In the figure, this signal readout process includes a determination level setting period T111, a first selective conversion efficiency P-phase readout period T112, a first selective conversion efficiency D-phase readout period T113, a second selective conversion efficiency D-phase readout period T114, and a second selective conversion efficiency P-phase readout period T115, all within a 1H period. The determination level setting period T111 includes a level determination period HK. During the first selective conversion efficiency P-phase readout period T112 and the first selective conversion efficiency D-phase readout period T113, high conversion efficiency or medium conversion efficiency is selected for the photodiode LPD according to the level determination result. During the second selective conversion efficiency D-phase readout period T114 and the second selective conversion efficiency P-phase readout period T115, high conversion efficiency or SPD is selected for the photodiode LPD according to the level determination result. During the level determination period HK, the reference signal REF is set to the threshold level SHB. During the first selective conversion efficiency P-phase readout period T112, the reference signal REF includes ramp wave RA1. During the first selective conversion efficiency D-phase readout period T113, the reference signal REF includes ramp wave RA3. During the second selective conversion efficiency D-phase readout period T114, the reference signal REF includes ramp wave RA4. During the second selective conversion efficiency P-phase readout period T115, the reference signal REF includes ramp wave RA5.

[0373] Before the judgment level setting period T111, the reset signal RST and the switching signal FDGV rise, turning on the reset transistor 121 and the switching transistor 126, and resetting the floating diffusion transistors FD1 and FD2. Also before the judgment level setting period T111, the auto-zero signal AZ rises, and charge accumulates in the respective input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively.

[0374] Next, during the judgment level setting period T111, if the transfer signal TGL rises to an intermediate potential, and any of the transfer transistors TG1 to TGn are half-on, and a charge exceeding a certain value is accumulated in any of the photodiodes PD1 to PDn, that charge is transferred to the floating diffusion FD1. If the charge accumulated in any of the photodiodes PD1 to PDn is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0375] Next, when the transfer signal TGL falls, TGn is turned off from the transfer transistor TG1. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplification transistor 122. During the level determination period HK, the level corresponding to the presence or absence of charge in the floating diffusion FD1 is compared with the threshold level SHB in the comparator CM1, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0376] Then, when the level of the charge in floating diffusion FD1 is above the threshold level SHB, the switching control unit 154 raises the switching signal FCGV and applies it to cell 1120 via the vertical control line 133B. At this time, the switching transistor 124 turns on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. As a result, the conversion efficiency of cell 1120 switches to medium conversion efficiency.

[0377] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, falls below the threshold level SHB, the switching control unit 154 maintains a low level of the switching signal FCGV and applies it to cell 1120 via the vertical control line 133B. At this time, the switching transistor 124 is turned off, and floating diffusion FD1 is disconnected from floating diffusion FD2. As a result, the conversion efficiency of cell 1120 is maintained at a high conversion efficiency.

[0378] Next, during the first selective conversion efficiency P-phase readout period T112, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0379] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0380] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0381] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RA1, and the timing when the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA1 matches the potential VSL of the vertical signal line 132, the high conversion efficiency P-phase levels read from cell 120 are AD converted column by column.

[0382] Subsequently, the transfer signal TGL rises, turning on either the transfer transistor TG1 through TGn, and transferring the charge stored in either the photodiode PD1 through PDn to the floating diffusion FD1. Then, when the transfer signal TGL falls, the transfer transistors TG1 through TGn turn off.

[0383] Next, during the first selective conversion efficiency D-phase readout period T113, if the medium conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0384] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the medium conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the medium conversion efficiency D-phase level read from cell 1120 is AD converted column by column. At this time, CDS processing can be performed based on the medium conversion efficiency P-phase level and the medium conversion efficiency D-phase level.

[0385] On the other hand, if high conversion efficiency is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.

[0386] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RA3, and the timing when the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA3 matches the potential VSL of the vertical signal line 132, the high conversion efficiency D-phase level read from cell 1120 is AD converted column by column. At this time, CDS processing can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level.

[0387] Next, during the second selective conversion efficiency D-phase readout period T114, the auto-zero signal AZ rises, and charge accumulates in the input capacitors C1 and C2 so that the non-inverting and inverting inputs of the comparator CM1 are balanced, respectively. The switching control unit 154 sets the switching signal FCGV to a high level and applies it to the cell 1120 via the vertical control line 133B. At this time, the switching transistors 124 and 125 turn on, and floating diffusion FD1 is connected to floating diffusion FD2, and floating diffusion FD2 is connected to floating diffusion FD3 via switching transistor 1125.

[0388] Furthermore, during the determination level setting period T111, if the level corresponding to the presence or absence of charge in floating diffusion FD1 is equal to or greater than the threshold level SHB, the switching control unit 154 raises the switching signal FDGV and applies it to cell 1120 via the vertical control line 133A. At this time, the switching transistors 126 and 1125 are turned on, and the capacitance of floating diffusion FD3 is added to floating diffusion FD2. Therefore, reading from photodiode SPD is selected.

[0389] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, is below the threshold level SHB, the switching control unit 154 maintains the low level of the switching signal FDGV and applies it to cell 120 via the vertical control line 133A. At this time, the switching transistors 126 and 1125 are turned off, and the floating diffusion FD2 is disconnected from the floating diffusion FD3. Therefore, the conversion efficiency of cell 120 is selected to be the medium conversion efficiency read from the photodiode LPD.

[0390] Then, when reading from the photodiode SPD is selected during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-sensitivity D-phase level of the photodiode SPD is applied to the gate of the amplification transistor 122.

[0391] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low-sensitivity D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the low-sensitivity D-phase levels read from cell 120 are AD converted column by column.

[0392] On the other hand, when a medium conversion efficiency is selected from the readout from the photodiode LPD during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-sensitivity medium conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0393] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high-sensitivity medium-conversion efficiency D-phase level is compared with the ramp wave RA4, and the timing when the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA4 matches the potential VSL of the vertical signal line 132, the high-sensitivity medium-conversion efficiency D-phase level read from cell 1120 is AD converted column by column.

[0394] Next, during the second selective conversion efficiency P-phase readout period T115, the reset signal RST rises, and the reset transistor 121 turns on. At this time, if reading from the photodiode SPD is selected, floating diffusions FD1 to FD3 are reset. On the other hand, if the medium conversion efficiency of reading from the photodiode LPD is selected, floating diffusions FD1 and FD2 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. Here, during the level determination period HK, if reading from the photodiode SPD is selected, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low-sensitivity P-phase level of the photodiode SPD is applied to the gate of the amplification transistor 122.

[0395] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the low-sensitivity P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the low-sensitivity P-phase levels read from cell 1120 are AD converted column by column.

[0396] On the other hand, when a medium conversion efficiency is selected from the readout from the photodiode LPD during the level determination period HK, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-sensitivity medium conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 122.

[0397] Then, in comparator CM1, the potential VSL of the vertical signal line 132 corresponding to the high-sensitivity medium-conversion efficiency P-phase level is compared with the ramp wave RA5, and the timing when the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the level of the ramp wave RA5 matches the potential VSL of the vertical signal line 132, the high-sensitivity medium-conversion efficiency P-phase level read from cell 120 is AD converted column by column.

[0398] Thus, in the 11th embodiment described above, the pixel conversion efficiency is switched based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and a high-sensitivity photodiode, a low-sensitivity photodiode, and LOFIC are provided. This makes it possible to expand the dynamic range in HDR by reducing the S / N step at the junction between HCG and MCG while suppressing a decrease in frame rate, and to suppress afterimages caused by dielectric absorption.

[0399] <12. Twelfth Embodiment> In the first embodiment described above, the pixel conversion efficiency was switched based on the determination result of the pixel signal readout level. In this twelfth embodiment, semiconductor chips are stacked, each having a pixel array section in which pixels are arranged in a matrix.

[0400] Figure 56 is a perspective view showing an example of stacking of pixel arrays according to the twelfth embodiment.

[0401] In the figure, the solid-state imaging device comprises semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

[0402] A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. The pixels 931 may be provided with cells 120, 320 to 920 of any of the first to ninth embodiments described above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0403] Peripheral circuits 924 are formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.

[0404] The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of semiconductor chips 921 and 922. In this case, semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0405] Thus, in the twelfth embodiment described above, the semiconductor chip 922 on which the pixel array 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0406] <13. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0407] Figure 57 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0408] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 57, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0409] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0410] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0411] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0412] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0413] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0414] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0415] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0416] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0417] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 57, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0418] Figure 58 shows an example of the installation position of the imaging unit 12031.

[0419] In Figure 58, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0420] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0421] Figure 58 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0422] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0423] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0424] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0425] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0426] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology described herein to the vehicle control system 12000, it is possible to expand the dynamic range while suppressing a decrease in frame rate.

[0427] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0428] Furthermore, this technology can also be configured as follows. (1) A photoelectric conversion unit provided in the pixel, A transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the first floating diffusion, An amplifying transistor that outputs a pixel signal corresponding to the charge accumulated in the first floating diffusion, A selection transistor that selects the output from the aforementioned amplification transistor, A first switching transistor that adds capacitance to the first floating diffusion based on a first switching signal to switch the conversion efficiency when outputting the pixel signal, A second switching transistor is connected in parallel to the first switching transistor and adds capacitance to the first floating diffusion based on a second switching signal to switch the conversion efficiency when outputting the pixel signal. An imaging device equipped with the following features. (2) The capacity is provided with a second floating diffusion, The first switching transistor and the second switching transistor are connected between the first floating diffusion and the second floating diffusion. The imaging device described in (1) above. (3) Third floating diffusion, A third switching transistor is connected between the second floating diffusion and the third floating diffusion, and switches the conversion efficiency when outputting the pixel signal by adding the capacitance of the third floating diffusion to the second floating diffusion based on a third switching signal. The imaging apparatus according to (2) above, comprising: (4) Set the conversion efficiency of the pixel to HCG (High Conversion Gain), read out the P-phase level, and then read out the D-phase level. By controlling the on / off state of the first switching transistor based on the determination result of the D-phase level read from the pixel, the conversion efficiency of the pixel is selected as either HCG or MCG (Middle Conversion Gain). The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, and the D-phase level is read out. By turning on the second and third switching transistors, the conversion efficiency of the pixel is set to LCG (Low Conversion Gain), the D-phase level is read out, and then the P-phase level is read out. The imaging device described in (3) above. (5) When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor is controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, thereby selecting HCG or MCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out. By turning on the second switching transistor and the third switching transistor, the conversion efficiency of the pixel is set to LCG, the D-phase level is read out, and then the P-phase level is read out. The aforementioned intermediate potential is the potential at which no charge is transferred when the charge accumulated in the photoelectric conversion unit falls below a certain value. The imaging device described in (3) above. (6) LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion An imaging device according to any one of (3) to (5) above, comprising: (7) Overflow control transistor connected between the LOFIC and the photoelectric conversion unit The imaging apparatus according to (6) above, comprising: (8) The photoelectric conversion unit is A first photodiode connected to the transfer transistor, A second photodiode, which is connected to the LOFIC and has lower sensitivity than the first photodiode, The imaging apparatus according to (6) above, comprising: (9) A fourth switching transistor connected in series with the third switching transistor, which adds the capacitance of the third floating diffusion to the first floating diffusion based on the first switching signal to switch the conversion efficiency when outputting the pixel signal. The imaging apparatus according to (3) above, comprising: (10) When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor and the fourth switching transistor are controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, thereby selecting HCG or MCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out. When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor and the fourth switching transistor is controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, and the second switching transistor and the third switching transistor are turned on to select MCG or LCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected MCG or LCG, the P-phase level is read out, and then the D-phase level is read out. The aforementioned intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the first floating diffusion unit when the charge is below a certain value. The imaging device described in (9) above. (11) A switching control unit is provided that switches the conversion efficiency of the pixel based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion. The imaging device described in any of (1) to (10) above. (12) The switching control unit, When the gate potential of the transfer transistor is set to an intermediate potential, the conversion efficiency of the pixel is switched based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion. The aforementioned intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the first floating diffusion unit when the charge is below a certain value. The imaging device described in (11) above. (13) The amplification transistor, the selection transistor, the first switching transistor, the second switching transistor, and the first floating diffusion are shared by a plurality of photoelectric conversion units, The transfer transistor is provided for each of the photoelectric conversion units. An imaging device as described in any of (1) to (12) above. (14) A pixel array section in which pixels with switchable conversion efficiency are arranged in a matrix in the row direction and column direction, The system includes a switching control unit that switches the conversion efficiency of each pixel column based on the determination result of the level of the pixel signal read from the pixel, The aforementioned pixel array section is A horizontal control line that transmits a first switching signal for switching the conversion efficiency in the row direction, A vertical control line transmits a second switching signal for switching the conversion efficiency in the direction of the column. An imaging device equipped with the following features. (15) The vertical control line is A first vertical control line transmits a second switching signal for switching the conversion efficiency in the direction of the column, A second vertical control line transmits a third switching signal for switching the conversion efficiency in the direction of the column. The imaging apparatus according to (14) above, comprising: [Explanation of Symbols]

[0429] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image Processing Unit 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel Array Section 112 Vertical scanning circuit 113 Column Readout Circuit 114 Column Signal Processing Unit 115 Horizontal scanning circuit 116 Control circuits 120 cells 131 Horizontal control line 132 Vertical signal line 133 Vertical control lines C1, C2 Input Capacitance CM1 Comparator CM2 Post-stage Amplifier 151 Latch Circuit 152 Multiplexer 153 counter 154 Switching Control Unit

Claims

1. A photoelectric conversion unit provided in the pixel, A transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the first floating diffusion, An amplifying transistor that outputs a pixel signal corresponding to the charge accumulated in the first floating diffusion, A selection transistor that selects the output from the aforementioned amplification transistor, A first switching transistor that adds capacitance to the first floating diffusion based on a first switching signal to switch the conversion efficiency when outputting the pixel signal, A second switching transistor is connected in parallel to the first switching transistor and adds capacitance to the first floating diffusion based on a second switching signal to switch the conversion efficiency when outputting the pixel signal. An imaging device equipped with the following features.

2. The aforementioned capacity includes a second floating diffusion, The first switching transistor and the second switching transistor are connected between the first floating diffusion and the second floating diffusion. The imaging apparatus according to claim 1.

3. The third floating diffusion, A third switching transistor is connected between the second floating diffusion and the third floating diffusion, and switches the conversion efficiency when outputting the pixel signal by adding the capacitance of the third floating diffusion to the second floating diffusion based on a third switching signal. The imaging device according to claim 2, comprising:

4. The conversion efficiency of the aforementioned pixel is set to HCG (High Conversion Gain), the P-phase level is read out, and then the D-phase level is read out. By controlling the on / off state of the first switching transistor based on the determination result of the D-phase level read from the pixel, the HCG or MCG (Middle Conversion Gain) is selected as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, and the D-phase level is read out. By turning on the second and third switching transistors, the conversion efficiency of the pixels is set to LCG (Low Conversion Gain), the D-phase level is read out, and then the P-phase level is read out. The imaging device according to claim 3.

5. When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor is controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, thereby selecting HCG or MCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out. By turning on the second switching transistor and the third switching transistor, the conversion efficiency of the pixel is set to LCG, the D-phase level is read out, and then the P-phase level is read out. The aforementioned intermediate potential is the potential at which no charge is transferred when the charge accumulated in the photoelectric conversion unit falls below a certain value. The imaging device according to claim 3.

6. LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion The imaging device according to claim 3, comprising:

7. Overflow control transistor connected between the LOFIC and the photoelectric conversion unit The imaging device according to claim 6, comprising:

8. The aforementioned photoelectric conversion unit is A first photodiode connected to the transfer transistor, A second photodiode, which is connected to the LOFIC and has lower sensitivity than the first photodiode, The imaging device according to claim 6, comprising:

9. A fourth switching transistor is connected in series with the third switching transistor and switches the conversion efficiency when outputting the pixel signal by adding the capacitance of the third floating diffusion to the first floating diffusion based on the first switching signal. The imaging device according to claim 3, comprising:

10. When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor and the fourth switching transistor are controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, thereby selecting HCG or MCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected HCG or MCG, the P-phase level is read out, and then the D-phase level is read out. When the gate potential of the transfer transistor is set to an intermediate potential, the on / off state of the first switching transistor and the fourth switching transistor is controlled based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion, and the second switching transistor and the third switching transistor are turned on to select MCG or LCG as the conversion efficiency of the pixel. The conversion efficiency of the aforementioned pixel is set to the selected MCG or LCG, the P-phase level is read out, and then the D-phase level is read out. The aforementioned intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the first floating diffusion unit when the charge is below a certain value. The imaging device according to claim 9.

11. The system includes a switching control unit that switches the conversion efficiency of the pixel based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion. The imaging apparatus according to claim 1.

12. The switching control unit described above is When the gate potential of the transfer transistor is set to an intermediate potential, the conversion efficiency of the pixel is switched based on the determination result of the signal level corresponding to the charge transferred to the first floating diffusion. The aforementioned intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the first floating diffusion unit when the charge is below a certain value. The imaging apparatus according to claim 11.

13. The amplification transistor, the selection transistor, the first switching transistor, the second switching transistor, and the first floating diffusion are shared by multiple photoelectric conversion units. The transfer transistor is provided for each of the photoelectric conversion units. The imaging apparatus according to claim 1.

14. A pixel array section in which pixels with switchable conversion efficiency are arranged in a matrix in the row direction and column direction, The system includes a switching control unit that switches the conversion efficiency of each pixel column based on the determination result of the level of the pixel signal read from the pixel, The aforementioned pixel array section is A horizontal control line that transmits a first switching signal for switching the conversion efficiency in the row direction, A vertical control line transmits a second switching signal in the column direction to switch the conversion efficiency. An imaging device equipped with the following features.

15. The aforementioned vertical control line is A first vertical control line transmits a second switching signal for switching the conversion efficiency in the direction of the column, A second vertical control line transmits a third switching signal for switching the conversion efficiency in the direction of the column. The imaging device according to claim 14, comprising:

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