semiconductor element

Abstract

The present invention provides a power transistor that effectively suppresses voltage surges generated during switching, protects the gate oxide layer, and prevents damage. [Solution] In the power transistor 100, the transistor 1 and the buffer circuit 2 are installed on a substrate 10. The buffer circuit is electrically connected to the transistor. The buffer circuit has a polysilicon layer 90 and an interlayer dielectric layer 80 installed adjacent to each other and electrically connected. The polysilicon layer is electrically connected to the source 40 of the transistor by the source metal 60. The dielectric layer 80 is electrically connected to the substrate of the transistor and to the drain metal 70 through the epitaxial layer 20. The dielectric layer and the polysilicon layer function as a capacitor and resistor in the buffer circuit, forming a resistor-capacitor buffer circuit.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of suppressing surges. [Background technology]

[0002] Parasitic inductance exists in application circuits for power transistors. These parasitic inductances cause large voltage surges and ringing phenomena when the power transistor is turned off. This not only causes electromagnetic interference (EMI) in the application circuit, but if the surge exceeds the device's rating, it can damage the power transistor and other electronic components in the circuit.

[0003] A common method for dissipating surge energy is to add a buffer circuit (snubber circuit) to the circuit. Adding a buffer circuit is especially essential in high-speed switching, high-current circuits. Among various types of buffers, the resistor-capacitor buffer (RC snubber) is the most commonly used. However, adding an RC buffer circuit to a power transistor application circuit adds an additional cost to the overall circuit. Generally speaking, voltage surges and ringing phenomena caused by parasitic inductance when a power transistor is turned off are significant problems. External RC buffer circuits can effectively solve this problem, but they increase additional cost and circuit design complexity. Therefore, effectively suppressing power transistor surges without significantly increasing the cost of the components is a challenge that the industry urgently needs to address. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The main objective of this invention is to provide an innovative semiconductor device. Because this device integrates an RC buffer circuit into the semiconductor structure design of the power transistor itself, there is no need to add an external buffer in the application circuit. Such a design effectively suppresses voltage surges generated by the power transistor during switching, protecting the gate oxide layer of the power transistor and preventing damage. [Means for solving the problem]

[0005] To achieve the above objective, the present invention provides a semiconductor device comprising a substrate, a transistor, and a buffer circuit. The transistor and the buffer circuit are mounted on the substrate. The buffer circuit is electrically connected to the transistor. The buffer circuit has a polysilicon layer and a dielectric layer that are mounted adjacent to each other and electrically connected. The polysilicon layer is electrically connected to the source of the transistor. The dielectric layer is electrically connected to the drain of the transistor. As a result, the polysilicon layer acts as a resistor, the dielectric layer acts as a capacitor, and the buffer circuit becomes a resistor-capacitor buffer circuit.

[0006] In an embodiment of the semiconductor device of the present invention, the substrate is a silicon carbide substrate.

[0007] In an embodiment of the semiconductor element of the present invention, the semiconductor element further includes an epitaxial layer placed on a substrate, and the dielectric layer is placed on the epitaxial layer.

[0008] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a drain metal placed on the back side of the substrate as a drain, and the polysilicon layer between the source metal and the drain metal, the epitaxial layer, and the substrate have the aforementioned resistance.

[0009] In embodiments of the semiconductor device of the present invention, the semiconductor device further includes a source metal, the source metal is placed above the epitaxial layer and electrically connected to the source and the polysilicon layer.

[0010] To achieve the above objective, the present invention provides a semiconductor device comprising a substrate, a transistor, and a buffer circuit. The transistor and buffer circuit are mounted on the substrate, and the buffer circuit is electrically connected to the transistor. The buffer circuit has a polysilicon layer and a dielectric layer mounted adjacent to each other and electrically connected, the polysilicon layer being electrically connected to the gate of the transistor and the dielectric layer being electrically connected to the source of the transistor, thereby the polysilicon layer acting as a resistor and the dielectric layer acting as a capacitor.

[0011] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an epitaxial layer and an interlayer dielectric layer, wherein the epitaxial layer is placed on a substrate, the interlayer dielectric layer is placed on the epitaxial layer, and the polysilicon layer is placed on the interlayer dielectric layer.

[0012] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a gate metal placed on an interlayer dielectric layer and electrically connected to the gate, and the resistor is located between the polysilicon layer and the gate metal.

[0013] In an embodiment of the semiconductor element of the present invention, the semiconductor element further includes a source metal that is placed above the interlayer dielectric layer and electrically connected to the source and dielectric layer.

[0014] To achieve the above object, the present invention provides a semiconductor device including a substrate, a transistor, a first buffer circuit, and a second buffer circuit. The transistor, the first buffer circuit, and the second buffer circuit are installed on the substrate. The first buffer circuit and the second buffer circuit are electrically connected to the transistor. The first buffer circuit has a first polysilicon layer and a first dielectric layer that are installed adjacent to each other and electrically connected. The second buffer circuit has a second polysilicon layer and a second dielectric layer that are installed adjacent to each other and electrically connected. The first polysilicon layer is electrically connected to the source of the transistor, and the first dielectric layer is electrically connected to the drain of the transistor. Thus, the first polysilicon layer becomes a first resistor, and the first dielectric layer becomes a first capacitor. The second polysilicon layer is electrically connected to the gate of the transistor, and the second dielectric layer is electrically connected to the source of the transistor. Thus, the second polysilicon layer becomes a second resistor, and the second dielectric layer becomes a second capacitor.

[0015] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an epitaxial layer installed on the substrate, and the first dielectric layer is installed on the epitaxial layer.

[0016] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an interlayer dielectric layer installed on the epitaxial layer, and the second polysilicon layer is installed on the interlayer dielectric layer.

[0017] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a gate metal installed on the interlayer dielectric layer and electrically connected to the gate, and there is a second resistor between the second polysilicon layer and the gate metal.

[0018] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a source metal installed above the interlayer dielectric layer, and the source metal is electrically connected to the source, the first polysilicon layer, and the second dielectric layer.

[0019] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a drain metal placed on the back side of the substrate as a drain, and a first polysilicon layer, an epitaxial layer, and a substrate between the source metal and the drain metal have a first resistor.

[0020] Those skilled in the art will be able to understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described later. [Brief explanation of the drawing]

[0021] [Figure 1] Schematic circuit diagram of the power transistor element according to the first embodiment of the present invention [Figure 2] Schematic cross-sectional view of a power transistor element according to the first embodiment of the present invention. [Figure 3] Schematic circuit diagram of a power transistor element according to the second embodiment of the present invention [Figure 4] Schematic cross-sectional view of a power transistor element according to the second embodiment of the present invention. [Figure 5] Schematic circuit diagram of a power transistor element according to the third embodiment of the present invention. [Figure 6] Schematic cross-sectional view of a power transistor element according to the third embodiment of the present invention. [Modes for carrying out the invention]

[0022] The present invention will be described below through examples. These examples illustrate the embodiments of the present invention and are not intended to limit the invention to any particular environment, application, or specific configuration described therein. Therefore, while the examples illustrate the present invention, they do not limit it. Components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships of the components in the drawings are for ease of understanding and do not limit the actual dimensions.

[0023] Figure 1 is a schematic circuit diagram of a semiconductor device in a first embodiment of the present invention, particularly a schematic circuit diagram of a power transistor device. This power transistor device not only has the same transistor 1 as conventional devices, but also includes a buffer circuit 2 built into the device simultaneously with the transistor 1. With this design, the power transistor device of this embodiment has the ability to suppress voltage surges and protect the oxide dielectric layer of the transistor's gate G from damage, thus eliminating the need to add other surge protection circuits externally. Specifically, as shown in Figure 1, the buffer circuit 2 of this embodiment is a resistor-capacitor type RC buffer circuit, connected between the source S and drain D of the transistor 1.

[0024] Figure 2 is a schematic cross-sectional view of the power transistor element of the first embodiment of the present invention shown in Figure 1. As shown in the figure, the power transistor element 100 of the present invention integrates the transistor 1 and the buffer circuit 2 on the substrate inside the element structure. Details are as follows. This power transistor element 100 has a substrate 10. Specifically, the substrate 10 is a silicon carbide substrate with high concentration N-type doping, but is not limited to this. An epitaxial layer 20 is present on the substrate 10. Similarly, this epitaxial layer 20 is a silicon carbide epitaxial layer with low concentration N-type doping. Next, a patterned dielectric layer and a patterned polysilicon layer are sequentially formed on the epitaxial layer 20. The dielectric layer is a silicon dioxide layer or a silicon nitride layer. Then, a portion of the patterned dielectric layer and the patterned polysilicon layer function as the gate 30 of the transistor 1 structure. The other portion of the patterned dielectric layer 80 and the patterned polysilicon layer 90 function as a capacitor and resistor in the buffer circuit 2, and are placed adjacent to each other and electrically connected. Further details will be described later.

[0025] As shown in Figure 2, the gate 30 is then used as a mask to sequentially form the P-type well region 22 of the transistor 1 and the N-type high-concentration doping source 40 of the transistor 1 on the surface region of the epitaxial layer 20. Next, an interlayer dielectric layer 50 is formed on the epitaxial layer 20. The interlayer dielectric layer 50 covers the gate 30 and the dielectric layer 80 and polysilicon layer 90 within the buffer circuit 2. Finally, a metallization internal wiring process is performed to form the gate metal (not shown), source metal 60, and drain metal 70. The source metal 60 is electrically connected not only to the source 40 of transistor 1 but also to the polysilicon layer 90 within the buffer circuit 2. The drain metal 70 is electrically connected to the dielectric layer 80 within the buffer circuit 2 through the substrate 10 and the epitaxial layer 20.

[0026] As shown in the figure, the power transistor element 100 of the present invention integrates a transistor 1 and a buffer circuit 2 within its structure. In the buffer circuit 2, the capacitance value can be adjusted by selecting an insulating material with an appropriate dielectric constant and adjusting the size of the dielectric layer 80 (film thickness, length, width, etc.). Furthermore, the resistance value of the polysilicon layer 90 of the buffer circuit 2 can be adjusted by adjusting the doping concentration of the polysilicon doping substance and the size of the polysilicon thin film (film thickness, length, width, etc.). With this design, the overall resistance value of the polysilicon layer 90 between the source metal 60 and the drain metal 70, the epitaxial layer 20 and the substrate 10 can be determined for the entire buffer circuit 2. When the power transistor element 100 of the present invention is actually applied to a circuit, during the process of the switch switching from a conductive state to a turn-off state, the current due to the high-voltage surge flows through the circuit formed by the buffer circuit 2 and the switch. The capacitor C in the buffer circuit blocks the DC portion of the surge current. The resistor R in the buffer circuit dissipates the AC portion of the surge current passing through the capacitor C. With this design, the surge voltage peak value sensed at the load end can be reduced and the gate dielectric layer of the transistor in the power transistor element can be protected.

[0027] Figure 3 is a schematic circuit diagram of a power transistor element in a second embodiment of the present invention. Similar to the above embodiment, this power transistor element not only has the same transistor 1 as conventional devices, but also includes a buffer circuit 2 integrated into the element at the same time as the transistor 1. Specifically, as shown in Figure 3, in this second embodiment, the buffer circuit 2 is a resistor-capacitor type RC buffer circuit and is connected between the source S and gate G of the transistor 1.

[0028] Figure 4 is a schematic cross-sectional view of the power transistor element 100 of the second embodiment of the present invention shown in Figure 3. As shown in the figure, the power transistor element 100 of the present invention integrates the transistor 1 and the buffer circuit 2 within the element structure. Details are as follows. Similar to the previously described embodiment, this power transistor element 100 has a substrate 10. An epitaxial layer 20 is present on the substrate 10. Next, a gate 30 is formed on the epitaxial layer 20, and a P-type well region 22 and a source 40 are formed on the surface region of the epitaxial layer 20. Next, an interlayer dielectric layer 50 covering the gate 30 is formed on the epitaxial layer 20. Next, a dielectric layer 80 and a polysilicon layer 90 of the buffer circuit 2 are formed above the interlayer dielectric layer 50. The dielectric layer 80 and the polysilicon layer 90 are placed adjacent to each other and electrically connected. Finally, a metallization internal wiring process is performed to form the gate metal 35, source metal 60, and drain metal 70. The source metal 60 is electrically connected to the source 40 of transistor 1 and the dielectric layer 80 of buffer circuit 2. The gate metal 35 is electrically connected to the polysilicon layer 90 of buffer circuit 2.

[0029] As shown in Figures 3 and 4, the power transistor element 100 of the present invention integrates the transistor 1 and the buffer circuit 2 on the same substrate 10. Similar to the embodiments described above, the capacitor value of the buffer circuit 2 can be adjusted by selecting an insulating material with an appropriate dielectric constant and adjusting the size of the dielectric layer 80. Furthermore, the resistance value of the polysilicon layer 90 can be adjusted by adjusting the doping concentration of the polysilicon doping substance and the size of the polysilicon thin film. When the power transistor element 100 of the present invention is actually applied to a circuit, during the process of the switch switching from a conductive state to a turn-off state, the current due to the high-voltage surge flows through the circuit formed by the buffer circuit 2 and the switch. Within the buffer circuit, the capacitor C (i.e., the dielectric layer 80) blocks the DC portion of the surge current. The resistor R (i.e., the polysilicon layer 90) dissipates the AC portion of the surge current passing through the capacitor C. This design reduces the surge voltage peak value sensed at the load end and protects the gate dielectric layer of the transistor within the power transistor element.

[0030] Figure 5 is a schematic circuit diagram of a power transistor element in the third embodiment of the present invention. The third embodiment is an embodiment that combines the first and second embodiments. This power transistor element integrates two buffer circuits into a conventional transistor 1. Specifically, as shown in Figure 5, buffer circuit A is an RC buffer circuit connected between the source S and drain D of transistor 1. Buffer circuit B is an RC buffer circuit connected between the source S and gate G of transistor 1.

[0031] Figure 6 is a schematic cross-sectional view of the power transistor element 100 of the third embodiment of the present invention shown in Figure 5. As shown in the figure, the power transistor element 100 of the present invention integrates the transistor 1, buffer circuit A, and buffer circuit B within a single element structure. Details are as follows. Similar to the foregoing embodiments, this power transistor element 100 has an epitaxial layer 20 on the substrate 10. On the epitaxial layer 20, there are a gate 30 and a first dielectric layer 80 of buffer circuit A A and a first polysilicon layer 90 A There is. In the surface region of the epitaxial layer 20, there are a P-type well region 22 and a source 40. Also, an interlayer dielectric layer 50 is formed on the epitaxial layer 20. The interlayer dielectric layer 50 is the first dielectric layer 80 of the gate 30 and buffer circuit A A and a first polysilicon layer 90 A covering. Above the interlayer dielectric layer 50, there are a second dielectric layer 80 of buffer circuit B B and a second polysilicon layer 90 B Finally, the metallization internal wiring includes a gate metal 35, a source metal 60, and a drain metal 70. The source metal 60 is the source 40 of transistor 1, the first polysilicon layer 90 of buffer circuit A A , and the second dielectric layer 80 of buffer circuit B B electrically connected to. Note that the gate metal 35 is electrically connected to the second polysilicon layer 90 of buffer circuit B B . The drain metal 70 is electrically connected to the first dielectric layer 80 of buffer circuit A through the substrate 10 and the epitaxial layer 20 A .

[0032] As shown in FIGS. 5 and 6, inside the structure of the power transistor element 100 of the third embodiment, transistor 1, buffer circuit A, and buffer circuit B are integrated. Buffer circuit A is an RC buffer circuit having a resistor R A and a capacitor C A . The resistor R A is the overall resistance composed of the first polysilicon layer 90 between the source metal 60 and the drain metal 70 A , the epitaxial layer 20, and the substrate 10. The capacitor C A is determined by the first dielectric layer 80 A . Buffer circuit B has a resistor R B and a capacitor C BThis is an RC buffer circuit having a resistor R. B The second polysilicon layer 90 B It exists between the capacitor C and the gate metal 35. B is the second dielectric layer 80 B This is determined by the following. Buffer circuits A and B provide a perfect high-voltage surge suppression effect using power transistor elements, thereby protecting the gate dielectric layer of the transistors within the power transistor elements.

[0033] The above-described embodiments illustrate embodiments of the present invention and describe characteristic configurations of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that are easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the scope of the patent application. [Explanation of Symbols]

[0034] 1 transistor 2 Buffer Circuit 10 circuit boards 20 Epitaxial Layer 22 P-type well region Gate 30 35 Gate Metal 40 Sources 50 Interlayer Dielectric Layers 60 Source Metal 70 Drain metal 80 Dielectric layer 80 A First dielectric layer 80 B Second dielectric layer 90 Polysilicon layer 90 A First polysilicon layer 90 B Second polysilicon layer 100 Power Transistor Elements A Buffer circuit B Buffer circuit C Capacitor C A Capacitor C B Capacitor D Drain G Gate R resistance R A resistance R B resistance S Sauce

Claims

1. A semiconductor device, circuit board and A transistor (MOSFET) is installed on the aforementioned substrate, The buffer circuit (Snubber) is installed on the substrate, electrically connected to the transistor, and has a polysilicon layer and a dielectric layer installed adjacent to it and electrically connected, The polysilicon layer is electrically connected to the source of the transistor, and the dielectric layer is electrically connected to the drain of the transistor, so that the polysilicon layer acts as a resistor and the dielectric layer acts as a capacitor. Semiconductor element.

2. The semiconductor device according to claim 1, characterized in that the substrate is a silicon carbide substrate.

3. The substrate further includes an epitaxial layer, The semiconductor element according to claim 1, characterized in that the dielectric layer is placed on the epitaxial layer.

4. The source metal further contains, The semiconductor element according to claim 3, characterized in that the source metal is placed above the epitaxial layer and electrically connected to the source and the polysilicon layer.

5. The drain further includes a drain metal installed on the back side of the substrate, The semiconductor element according to claim 4, characterized in that the polysilicon layer between the source metal and the drain metal, the epitaxial layer, and the substrate have the resistance.

6. A semiconductor device, circuit board and A transistor installed on the aforementioned substrate, The buffer circuit includes a polysilicon layer and a dielectric layer that are installed adjacent to the substrate, electrically connected to the transistor, and electrically connected, The polysilicon layer is electrically connected to the gate of the transistor, and the dielectric layer is electrically connected to the source of the transistor, so that the polysilicon layer acts as a resistor and the dielectric layer acts as a capacitor. Semiconductor element.

7. The semiconductor device according to claim 6, characterized in that the substrate is a silicon carbide substrate.

8. Further comprising an epitaxial layer and an interlayer dielectric layer, The epitaxial layer is installed on the substrate, The interlayer dielectric layer is placed on the epitaxial layer, The semiconductor element according to claim 6, characterized in that the polysilicon layer is installed on the interlayer dielectric layer.

9. The present invention further includes a gate metal that is placed on the interlayer dielectric layer and electrically connected to the gate, The semiconductor element according to claim 8, characterized in that the resistor is located between the polysilicon layer and the gate metal.

10. The semiconductor element according to claim 8, further comprising a source metal that is placed on the interlayer dielectric layer and electrically connected to the source and the dielectric layer.

11. A semiconductor device, circuit board and A transistor installed on the aforementioned substrate, A first buffer circuit having a first polysilicon layer and a first dielectric layer, which are installed on the substrate, electrically connected to the transistor, and adjacent to each other and electrically connected, The circuit includes a second buffer circuit having a second polysilicon layer and a second dielectric layer, which are installed on the substrate, electrically connected to the transistor, and adjacent to each other and electrically connected, The first polysilicon layer is electrically connected to the source of the transistor, and the first dielectric layer is electrically connected to the drain of the transistor, thereby the first polysilicon layer becoming a first resistor and the first dielectric layer becoming a first capacitor. The second polysilicon layer is electrically connected to the gate of the transistor, and the second dielectric layer is electrically connected to the source of the transistor, thereby the second polysilicon layer becoming a second resistor and the second dielectric layer becoming a second capacitor. Semiconductor element.

12. The semiconductor device according to claim 11, characterized in that the substrate is a silicon carbide substrate.

13. The substrate further includes an epitaxial layer, The semiconductor element according to claim 11, characterized in that the first dielectric layer is placed on the epitaxial layer.

14. The present invention further includes an interlayer dielectric layer placed on the epitaxial layer, The semiconductor element according to claim 13, characterized in that the second polysilicon layer is installed on the interlayer dielectric layer.

15. The present invention further includes a gate metal that is placed on the interlayer dielectric layer and electrically connected to the gate, The semiconductor element according to claim 14, characterized in that the second resistor is located between the second polysilicon layer and the gate metal.

16. The semiconductor element according to claim 14, further comprising a source metal placed on the interlayer dielectric layer and electrically connected to the source, the first polysilicon layer, and the second dielectric layer.

17. The drain further includes a drain metal installed on the back side of the substrate, The semiconductor element according to claim 16, characterized in that the first polysilicon layer between the source metal and the drain metal, the epitaxial layer, and the substrate have a first resistor.

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