Normally-on gallium nitride-based transistor with p-type gate

Abstract

The semiconductor device (100) includes a gallium nitride-based low-threshold depletion-mode transistor (GaN FET) (102) having a threshold potential of -10 volts to -0.5 volts. The GaN FET (102) has a channel layer (108) of a gallium and nitrogen-containing III-N semiconductor material supporting a two-dimensional electron gas (2DEG) (114). The GaN FET (102) has a barrier layer (112) of an aluminum and nitrogen-containing III-N semiconductor material above the channel layer (108). The GaN FET (102) further has a p-type gate (124) of a gallium and nitrogen-containing III-N semiconductor material. The bottom surface (136) of the gate (124) adjacent to the barrier layer (112) does not extend beyond the top surface (138) of the barrier layer (112) located on the opposite side from the channel layer (108). In the GaN FET (102), there is no dielectric layer between the gate (124) and the barrier layer (112).

Description

[Technical Field]

[0001] This description relates to the field of semiconductor devices. More specifically, this description relates to, but is not limited to, gallium nitride transistors in semiconductor devices. [Background technology]

[0002] Normally-on gallium nitride-based field-effect transistors (GaN FETs) can be used for power switching applications. Normally-on GaN FETs are also known as depletion-mode GaN FETs. Depletion-mode GaN FETs generally have a gate insulating film made of a dielectric material such as silicon nitride, silicon dioxide, and / or aluminum oxide between the gate and a barrier layer to reduce gate leakage and ensure product reliability. In power switching applications, normally-off operation, also known as enhancement-mode operation, is desired. To operate in normally-off mode, normally-on GaN FETs can be paired with low-voltage silicon transistors in a cascode circuit. In a cascode circuit, the GaN FET and the silicon transistor are connected in series. The threshold potential of a GaN FET to turn it on (i.e., the bias potential on the gate relative to the source) is generally a negative voltage greater than 10 volts. The size of a Si transistor is primarily determined by the magnitude of the threshold voltage of a normally-on GaN FET; a higher threshold potential requires a larger silicon transistor, which leads to higher costs, increased overall on-resistance contribution, and reduced available space for the GaN transistor within a given package. [Overview of the project]

[0003] This document describes semiconductor devices, including GaN FETs, which are gallium nitride-based low-threshold depletion-mode transistors. A GaN FET has a channel layer of a gallium- and nitrogen-containing III-N semiconductor material supporting a two-dimensional electron layer, commonly known as a two-dimensional electron gas (2DEG). Above the channel layer, the GaN FET has a barrier layer of an aluminum- and nitrogen-containing III-N semiconductor material. The GaN FET further has a p-type gate of a gallium- and nitrogen-containing III-N semiconductor material. The bottom surface of the gate adjacent to the barrier layer does not extend beyond the top surface of the barrier layer located on the opposite side of the channel layer. The GaN FET has no dielectric layer between the gate and the barrier layer. [Brief explanation of the drawing]

[0004] [Figure 1A] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1B] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1C] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1D] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1E] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1F] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1G]This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1H] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1I] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1J] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation. [Figure 1K] This is a cross-sectional view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor, as depicted at a certain stage of formation.

[0005] [Figure 2] This is a top view of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor and a silicon metal oxide semiconductor field-effect transistor.

[0006] [Figure 3] This is a schematic circuit diagram of an exemplary semiconductor device, including a low-threshold depletion-mode gallium nitride field-effect transistor and a silicon metal oxide semiconductor field-effect transistor. [Modes for carrying out the invention]

[0007] This description will be explained with reference to the attached drawings. The drawings are not drawn to a specific scale and are provided solely for illustrative purposes. Several aspects of this description are described below in relation to illustrative applications. Many specific details, relationships, and methods are described to aid in understanding this description. Since some actions may be performed in different orders and / or simultaneously with other actions or events, this description is not limited to the order of actions or events shown. Furthermore, not all actions or events shown are required to implement the methodology described herein.

[0008] Furthermore, some of the embodiments described herein are shown in two-dimensional views with various regions having depth and width, but these regions are only illustrative of parts of the device, which is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions have three dimensions, including length, width, and depth. Also, the present invention is illustrated by embodiments relating to active devices, but these examples are not limiting to the scope or availability of the present invention. Active devices of the present invention are not limited to the illustrated physical structures. These structures are included to demonstrate the usefulness and application of the present invention to currently preferred embodiments.

[0009] Semiconductor devices include GaN FETs, which are gallium nitride-based low-threshold depletion-mode transistors. A GaN FET has a channel layer of III-N semiconductor material containing gallium and nitrogen, supporting a two-dimensional electron layer commonly called a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material containing aluminum and nitrogen above the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material containing gallium and nitrogen. The bottom surface of the gate adjacent to the barrier layer does not extend beyond the top surface of the barrier layer located on the opposite side of the channel layer. There is no dielectric layer between the gate and the barrier layer. A GaN FET has a gate-source threshold potential (referred to as the threshold potential in this description) of -10 volts to -0.1 volts.

[0010] For the purposes of this document, the term "III-N" refers to a semiconductor material in which Group III elements (e.g., aluminum, gallium, and indium, and possibly boron) provide some of the atoms in the semiconductor material, and nitrogen atoms provide another portion of the atoms in the semiconductor material. Examples of III-N semiconductor materials are gallium nitride, gallium boron nitride, gallium aluminum nitride, indium nitride, and indium aluminum gallium nitride. The terminology used to describe the compositional formula of a material does not imply a specific stoichiometry of the elements. For example, gallium aluminum nitride can be written as AlGaN, which encompasses a certain range of relative ratios of aluminum and gallium.

[0011] Note that terms such as top, bottom, above, above, and below may be used in this description. These terms do not limit the position or orientation of a particular structure or element, but rather provide spatial relationships between structures or elements. The terms "lateral" and "lateral" refer to the direction parallel to the plane of the top surface of the channel layer.

[0012] Figures 1A to 1K are cross-sectional views of an exemplary semiconductor device 100, which in this example includes a low-threshold depletion-mode gallium nitride field-effect transistor 102, referred to as a GaN FET 102, and are shown at various stages of formation. Referring to Figure 1A, the semiconductor device 100 may be formed on a substrate 104 such as a silicon wafer, sapphire wafer, or silicon carbide wafer.

[0013] A buffer layer 106 of one or more layers of III-N semiconductor material may be formed on the substrate 104. In this example version where the substrate 104 is mounted as a silicon or sapphire wafer, the buffer layer 106 may include a nucleation layer with a stoichiometric content containing aluminum to match the lattice constant of the substrate 104. The buffer layer 106 may further include a sublayer of gallium aluminum nitride with reduced aluminum content, resulting in the formation of an unintentionally doped gallium nitride layer. The buffer layer 106 on silicon or sapphire may be 1 to several microns thick. In this example version where the substrate 104 is mounted as a silicon carbide wafer, the buffer layer 106 may be thinner due to the closer lattice constant match between gallium nitride and silicon carbide. The buffer layer 106 may be formed by a buffered metal-organic vapor-phase epitaxy (MOVPE) process, which involves several operations to form the nucleation layer and sublayer. The buffer layer 106 overlaps with the area for the GaN FET 102.

[0014] Referring to FIG. 1B, a channel layer 108 of a III-N semiconductor material is formed on a buffer layer 106. The channel layer 108 contains gallium and nitrogen and may mainly contain gallium nitride along with any trace amounts of other group III elements such as aluminum or indium. The channel layer 108 can be formed by a channel MOVPE process using gallium-containing gas reagents and nitrogen-containing gas reagents labeled as "Ga reagent" and "N reagent" respectively in FIG. 1B. The substrate 104 can be heated to 900°C to 1100°C during the channel MOVPE process. The gallium-containing gas reagent can be implemented, for example, as trimethylgallium or triethylgallium. The nitrogen-containing gas reagent can be implemented, for example, as ammonia, hydrazine, or 1,1-dimethylhydrazine. The channel MOVPE process uses a carrier gas labeled as "H2 carrier" in FIG. 1B. The carrier gas can mainly contain hydrogen gas and may contain hydrogen together with another gas such as nitrogen. The channel layer 108 can, as an example, have a thickness of 1 nanometer to 10 nanometers. In an alternative version of this example, the channel layer 108 can be formed as the last part of the buffer layer 106. During the operation of the GaN FET 102, the channel layer supports a 2DEG.

[0015] Referring to FIG. 1C, an optional high bandgap sublayer 110 of a III-N semiconductor material can be formed on the channel layer 108. The high bandgap sublayer 110 mainly contains aluminum and nitrogen in order to provide a higher bandgap than the barrier layer 112 formed later, as shown in FIG. 1D. In some versions of this example, the high bandgap sublayer 110 consists essentially of aluminum nitride and may consist of trace amounts of other group III elements, such as gallium.

[0016] The high bandgap sublayer 110 can be formed by a high bandgap MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent, labeled as "Al reagent" and "N reagent", respectively, in FIG. 1C. The aluminum-containing gas reagent can be implemented, for example, as trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent can be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with respect to the formation of the channel layer 108. The substrate 104 can be heated to 900° C. to 1100° C. during the high bandgap MOVPE process. The high bandgap MOVPE process uses a carrier gas labeled as "H2 carrier" in FIG. 1C. The carrier gas can mainly include hydrogen gas or can include hydrogen together with other gases such as nitrogen. The high bandgap sublayer 110 can, as an example, have a thickness of 0.5 nanometers to 3 nanometers. When formed, any high bandgap sublayer 110 can improve charge confinement in the subsequently formed 2DEG 114, shown in FIG. 1D, by providing a deeper quantum well within the channel layer 108 and, advantageously, provides an increased free charge carrier density within the 2DEG 114.

[0017] Referring to FIG. 1D, the barrier layer 112 of the III-N semiconductor material is formed over the channel layer 108 and, if present, over any high bandgap sublayer 110. The barrier layer 112 contains aluminum and nitrogen. In one version of this example, the barrier layer 112 can contain gallium at an atomic percentage lower than that of aluminum. In another version of this example, the barrier layer 112 can have a stoichiometry of Al.83In.17N within a few atomic percent and provides lattice matching close to that of gallium nitride. In a further version, the barrier layer 112 can contain gallium and indium, and the gallium can improve the uniformity of indium within the barrier layer 112. The barrier layer 112 can have a thickness of 1 nanometer to 60 nanometers.

[0018] The barrier layer 112 can be formed by a barrier MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent, labeled "Al reagent" and "N reagent" respectively in Figure 1D. The aluminum-containing gas reagent may be implemented as, for example, trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent may be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described in relation to the formation of the channel layer 108.

[0019] In this example version in which barrier layer 112 contains gallium, the barrier MOVPE process uses a gallium-containing gas reagent labeled "Ga reagent" in Figure 1D. The gallium-containing gas reagent may be implemented as trimethylgallium or triethylgallium, as described with respect to the formation of channel layer 108. In this example version in which barrier layer 112 contains indium, the barrier MOVPE process uses an indium-containing gas reagent labeled "In reagent" in Figure 1D. The indium-containing gas reagent may be implemented as, for example, trimethylindium or triethylindium. The barrier MOVPE process uses a carrier gas labeled "H2 carrier" in Figure 1D. The carrier gas may mainly consist of hydrogen gas, or may consist of hydrogen together with other gases such as nitrogen. The substrate 104 may be heated to 900°C to 1100°C during the barrier MOVPE process.

[0020] The barrier layer 112 induces 2DEG114 within the channel layer 108 adjacent to the barrier layer 112. The stoichiometry and thickness of the barrier layer 112 are set to 3 × 10 to provide the desired on-state resistance for the GaN FET 102. 12 cm -2 ~2×10 13 cm -2 This can provide a free charge carrier density.

[0021] Referring to Figure 1E, any etch-stopping layer 116 can be formed on the barrier layer 112. The etch-stopping layer 116 has a higher aluminum content than the barrier layer 112. The etch-stopping layer 116 may mainly consist of aluminum nitride. The etch-stopping layer 116 may have a thickness of 0.5 nanometers to 3 nanometers and may be formed by an etch-stopping MOVPE process similar to the high-bandgap MOVPE process used to form the high-bandgap sublayer 110. The etch-stopping layer 116 can advantageously reduce or eliminate etching of the barrier layer 112 during subsequent gate etching processes.

[0022] Referring to Figure 1F, a gate layer 118 of the p-type III-N semiconductor material is formed on the barrier layer 112, and on any etch-stopping layer 116, if present. The gate layer 118 may mainly consist of gallium nitride, along with a magnesium dopant to provide p-type conductivity. In some versions of this example, the gate layer 118 may contain other group III elements such as aluminum or indium in amounts of less than 10 atomic percent.

[0023] The gate layer 118 can be formed by a gate MOVPE process using a gallium-containing gas reagent, a nitrogen-containing gas reagent, and a p-type dopant gas reagent, which are labeled “Ga reagent,” “N reagent,” and “Mg reagent” in Figure 1F, respectively. The gallium-containing gas reagent may be implemented as, for example, trimethylgallium or triethylgallium. The nitrogen-containing gas reagent may be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with respect to the formation of the channel layer 108. The p-type dopant gas reagent may be implemented as, for example, bis(cyclopentadienyl)magnesium. Other sources of magnesium-containing gas reagents are also within the scope of this example. Other implementations of p-type dopant gases to provide p-type dopants other than magnesium are also within the scope of this example. In this version of the example in which the p-type dopant is implemented as magnesium, the magnesium concentration in the gate layer 118 is 1 × 10⁻¹⁶ to provide the desired threshold potential for the GaN FET 102. 17 cm-3 ~1 × 10 20 cm -3 It is possible.

[0024] In this example version in which the gate layer 118 contains aluminum, the gate MOVPE process uses an aluminum-containing gas reagent labeled "Al reagent" in Figure 1F. The aluminum-containing gas reagent may be implemented as trimethylaluminum or triethylaluminum, as described in relation to the formation of the barrier layer 112. In this example version in which the gate layer 118 contains indium, the gate MOVPE process uses an indium-containing gas reagent labeled "In reagent" in Figure 1F. The indium-containing gas reagent may be implemented as trimethylindium or triethylindium, as described in relation to the formation of the barrier layer 112. The barrier MOVPE process uses a carrier gas labeled "H2 carrier" in Figure 1F. The carrier gas may mainly consist of hydrogen gas, or may consist of hydrogen together with other gases such as nitrogen. The substrate 104 may be heated to 900°C to 1100°C during the gate MOVPE process.

[0025] The gate layer 118 can be 5 to 500 nanometers thick to provide a desired threshold potential to the GaN FET 102. The gate layer 118 reduces the free charge carrier density in 2DEG114 by 25 to 99 percent as a result of the work function of the gate layer 118 reducing the quantum wells in the channel layer 108. 2DEG114 retains a finite free charge carrier density of electrons after the gate layer 118 is formed.

[0026] Referring to Figure 1G, a gate mask 120 is formed on the gate layer 118. The gate mask covers an area of ​​the gate layer 118 for a gate 124 that will be formed later, as shown in Figure 1H. In one version of this example, the gate mask 120 may include a photoresist formed directly by the photolithography process. The gate mask 120 may include an organic anti-reflective material, such as a bottom anti-reflective coating (BARC) layer, beneath the photoresist. The BARC layer may be patterned after the photolithography process is complete. In another version of this example, the gate mask 120 may include an inorganic hard mask material, such as silicon dioxide or silicon nitride. In a further version, the gate mask 120 may include a metallic hard mask material, such as nickel. The hard mask material, inorganic material, or metal may be patterned by forming a photoresist pattern on the hard mask material, followed by etching the hard mask material using a reactive ion etching (RTE) process or ion milling process with fluorine radicals. The hard mask material within the gate mask 120 can provide improved control over the lateral dimensions of the gate 124.

[0027] Referring to Figure 1H, the gate etching process 122 removes the gate layer 118 exposed by the gate mask 120, leaving the gate layer 118 beneath the gate mask 120 to form the gate 124. The gate etching process 122 may be performed in an inductively coupled plasma (ICP) etching apparatus that generates a plasma containing chemically reactive neutral species, ions, and electrons. The gate etching process 122 includes chemical etchant species, physical etchant species, and aluminum deactivating species. The chemical etchant species may be implemented, for example, as a chlorine radical labeled "Cl" in Figure 1H, or as a bromine radical. The chlorine radical may be provided by chlorine gas, silicon tetrachloride, boron trichloride, or a combination thereof. The bromine radical may be provided, for example, by boron tribromide.

[0028] A physical etchant species can be implemented by one or more ionic species. Examples of physical etchant species include fluoride ions, argon ions, helium ions, and other noble gas ions, as well as oxygen ions. Other ionic species within the physical etchant species are also within the scope in this example. Fluoride ions can be provided, for example, by silicon hexafluoride, carbon tetrafluoride, or nitrogen trifluoride. Noble gas ions can be provided by argon gas or helium gas. Oxygen ions can be provided, for example, by oxygen gas or carbon monoxide gas. A physical etchant species is denoted as "P" in Figure 1H to indicate a physical etchant species and may include multiple ionic species.

[0029] The aluminum deactivating species can be implemented as an oxygen radical, labeled "O" in Figure 1H, or as a fluorine radical. The oxygen radical can be provided by oxygen gas. The fluorine radical can be provided, for example, by silicon hexafluoride, carbon tetrafluoride, or nitrogen trifluoride.

[0030] Chemical etchant species bond to gallium and nitrogen atoms in the gate layer 118. Physical etchant species collide with the gate layer 118, providing sufficient energy to facilitate the separation of gallium and nitrogen atoms bonded to the chemical etchant species from the gate layer 118. The gallium and nitrogen atoms separated from the gate layer 118 are removed by an ICP etching apparatus. The ICP etching apparatus has a first power supply for forming a plasma that generates chemical etchant species, physical etchant species, and aluminum deactivation species, and a second power supply for independently controlling the potential difference between the plasma and the substrate 104. The first power supply may operate at 250 to 500 watts for a 150 mm wafer, for example. The second power supply may be adjusted to initially operate at 20 to 100 watts to provide sufficient impact energy for physical etchant species to facilitate the separation of gallium and nitrogen atoms from the gate layer 118. As the gate etching process 122 nears completion, the power level of the second power supply may be reduced to 20-50 watts to reduce the power supply for the chemical reaction, which significantly reduces the removal of aluminum compared to the removal of gallium, and thus provides etching selectivity. Thus, reducing the power level of the second power supply can reduce the etching rate of the etch stop layer 116, if present, or the barrier layer 112, if the etch stop layer 116 is absent, relative to the gate layer 118, as the gate layer 118 contains more gallium and less aluminum than the etch stop layer 116 and barrier layer 112.

[0031] The gate etching process 122 may be carried out at a pressure of 10 millitorl to 50 millitorl to improve the etching selectivity. Aluminum deactivating species further improve the etching selectivity by preferentially combining with aluminum in the etch stop layer 116 if present, or in the barrier layer 112 if the etch stop layer 116 is absent, minimizing the sites available for chemical etchant species to react with gallium and nitrogen. Thus, the gate etching process 122 can completely remove the gate layer 118 at locations exposed by the gate mask 120 without removing a significant amount of the etch stop layer 116 or barrier layer 112. Figure 1H shows the gate etching process 122 in progress to completion.

[0032] 2DEG114 includes a channel region 126 beneath the gate 124. Since the thickness of the gate layer 118 remains constant within the gate 124, when the gate layer 118 is removed, the free charge carrier density in the channel region remains at the low value described with reference to Figure 1F.

[0033] 2DEG114 includes an access region 128 adjacent to the channel region 126. Since the thickness of the gate layer 118 decreases outside the gate 124, when the gate layer 118 is removed, the free charge carrier density of 2DEG114 increases in the access region 128.

[0034] 2DEG114 includes a source region 130 in the area for the source of the GaN FET 102. The source region 130 is laterally separated from the channel region 126 by one of the access regions 128. 2DEG114 also includes a drain region 132 in the area for the drain of the GaN FET 102. The drain region 132 is laterally separated from the channel region 126 by another of the access regions 128 and is located on the opposite side from the source region 130.

[0035] Referring to FIG. 1I, the gate etching process 122 can continue in an over-etch process after the gate layer 118 is removed outside the gate 124. Reducing the power level of the second power supply and providing aluminum passivation species advantageously allows the complete elimination of the gate layer 118 across the substrate 104 without removing a significant amount of the etch stop layer 116 or the barrier layer 112, despite variations in the thickness of the gate layer 118 across the substrate 104.

[0036] The free charge carrier density of the 2DEG 114 in the access region 128 can increase to a value comparable to the free charge carrier density before the gate layer 118 is formed. The free charge carrier density of the 2DEG 114 in the access region 128 can be from 3×10 12 cm -2 ~2×10 13 cm -2 and can provide the desired on-state resistance for the GaN FET 102. The channel region 12 of the 2DEG 114 retains a non-zero electron density of 1 percent to 75 percent of the free charge carrier density of the 2DEG 114 in the access region 128.

[0037] Thereafter, the gate mask 120 is removed. The photoresist and other organic materials in the gate mask 120 can be removed by an oxygen plasma process, a wet etching process, or a combination of both. The inorganic hard mask material in the gate mask 120 can be removed by, for example, an RIE process or a wet etching process using an aqueous solution of hydrofluoric acid and using fluorine radicals. The metal in the gate mask 120 can be removed by a wet etching process using a combination of nitric acid, acetic acid, and sulfuric acid, or a solution of ferric chloride.

[0038] The gate etching process 122 and the removal of the gate mask 120 may remove a small amount from the gate 124 from the gate layer 118, or may not remove the gate layer 118 from the gate 124, such that the gate 124 can have a thickness of 5 nanometers to 500 nanometers.

[0039] Referring to Figure 1J, a dielectric layer 134 may be formed on the barrier layer 112 adjacent to the gate 124. The dielectric layer 134 may include one or more sublayers of silicon dioxide, silicon nitride, aluminum oxide, or any combination thereof. The dielectric film 134 may be formed, for example, by one or more low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical deposition (PECVD), high-density plasma (HDP), or atomic layer deposition (ALD) processes. The dielectric layer 134 may also advantageously protect the barrier layer 112 from physical or chemical degradation. The dielectric layer 134 may extend over the gate 124, as shown in Figure 1J.

[0040] The bottom surface 136 of the gate 124 adjacent to the barrier layer 112 does not extend beyond the top surface 138 of the barrier layer 112 located on the opposite side of the channel layer 108, which is advantageous as it allows for the formation of the GaN FET 102 without gate recess etching, which increases manufacturing cost and complexity. The GaN FET does not contain any dielectric material between the gate 124 and the barrier layer 112, which is advantageous as it allows for the formation of the GaN FET 102 without forming a gate dielectric layer, which also increases manufacturing cost and complexity. The GaN FET does not contain III-N semiconductor material adjacent to the gate 124, which extends above the bottom surface 136 of the gate 124, which is advantageous as it allows for the formation of the GaN FET 102 without forming a barrier regrowth layer, which further increases manufacturing cost and complexity.

[0041] Referring to Figure 1K, the gate contact 140 is formed in contact with the gate 124 via the dielectric layer 134. The gate contact 140 may be aligned with the opening via the dielectric layer 134 as shown in Figure 1K, or it may extend partway over the dielectric layer 134 around the opening. The source contact 142 is formed via the dielectric layer 134 and the barrier layer 112 and is in contact with 2DEG114 in the source region 130. The drain contact 144 is formed via the dielectric layer 134 and the barrier layer 112 and is in contact with 2DEG114 in the drain region 132. The gate contact 140, source contact 142, and drain contact 144 are conductive and may contain one or more metals such as titanium, tungsten, or aluminum, or other conductive materials such as carbon nanotubes or graphene.

[0042] During the operation of the GaN FET 102, a positive voltage bias is applied to the drain contact 144 relative to the source contact 142, while a negative voltage bias is applied to the gate contact 140 relative to the source contact 142. The negative voltage bias applied to the gate contact 140 is sufficiently negative so that the free charge carrier density of electrons in the channel region 126 of the 2DEG114 is essentially zero. For example, the free charge carrier density of electrons in the channel region 126 is at least four orders of magnitude smaller than the free charge carrier density of electrons in the access region 128 of the 2DEG114. The gate 124 is said to be biased below the threshold. Since the free charge carrier density of electrons in the channel region 126 is essentially zero, there is essentially no current flowing from the drain contact 144 through the GaN FET 102 to the source contact 142 (e.g., less than 10 microamperes per micron of the width of the channel region 126). The GaN FET 102 is in the off state when the gate 124 is biased below the threshold.

[0043] During the operation of the GaN FET 102, the voltage bias applied to the gate contact 140 increases above a threshold potential of -10 volts to -0.1 volts, causing electrons to accumulate in the channel region 126. The gate 124 is said to be biased above the threshold. When a positive voltage bias is applied to the drain contact 144 relative to the source contact 142, while the gate 124 is biased above the threshold, this results in a current flowing from the drain contact 144 through the GaN FET 102 to the source contact 142. The GaN FET 102 is in the ON state when the gate 124 is biased above the threshold. Having a threshold potential of -10 volts to -0.1 volts is advantageous in that it may be possible to use a smaller driver to apply the bias voltage to the gate contact 140 compared to the driver required for a GaN FET with a threshold potential of, for example, -50 volts to -20 volts.

[0044] Figure 2 is a top view, and Figure 3 is a schematic of an exemplary semiconductor device 200, which includes a low-threshold depletion-mode gallium nitride field-effect transistor 202, referred to in this example as a GaN FET 202, and a silicon metal oxide semiconductor field-effect transistor (MOSFET) 246 connected in series with the GaN FET 202. The semiconductor device 200 may optionally include a driver integrated circuit (IC) 248 connected to the GaN FET 202 and MOSFET 246. As shown in Figure 2, the semiconductor device 200 may be in a quad flatpack no-lead (QFN) package, or it may be packaged in another package type. The encapsulant 250 is removed from the GaN FET 202, MOSFET 246, and driver IC in Figure 3. The semiconductor device 200 has external leads 252 that provide connections to external components not shown. The drain contact 244 of the GaN FET 202 is connected to the drain lead 252a of the external lead 252 by a wire bond 254. The source contact 242 of the GaN FET 202 is connected to the drain terminal 256 of the MOSFET 246 by an additional wire bond 254. The source terminal 258 of the MOSFET 246 is connected to the source lead 252b of the external lead 252 by a further wire bond 254. In this example, the driver IC 248 may be connected to the gate contact 240 of the GaN FET 202 and the gate terminal 260 of the MOSFET 246. Alternatively, the gate terminal 260 of the MOSFET 246 may be connected to one of the external leads 252. The input terminal 262 of the driver IC 248 is connected to the control lead 252c of the external lead 252 by a further wire bond 254.

[0045] The GaN FET 202 has the structure shown in Figure 1K and has a threshold potential of -10 volts to -0.5 volts. During the operation of semiconductor device 200, MOSFET 246 operates at a drain-source potential difference corresponding to the magnitude of the threshold potential of GaN FET 202. Having a threshold potential of -10 volts to -0.5 volts allows for a smaller size of MOSFET 246 compared to an equivalent semiconductor device having a GaN FET with a threshold potential of -50 volts to -20 volts. For example, MOSFET 246 can be 2 to 5 times smaller than the MOSFET required for a GaN FET with a threshold potential of -30 volts. Reducing the size of MOSFET 246 can also advantageously lower the cost of semiconductor device 200.

[0046] While various embodiments have been described above, they are merely examples and not limiting. Numerous modifications to the embodiments described can be made in accordance with this description without departing from the spirit or scope of this description. Therefore, the breadth and scope of the present invention are not limited by any of the embodiments described above. Rather, the scope of the description is defined by the following claims and their equivalents.

Claims

1. It is a semiconductor device, It includes a depletion-mode gallium nitride field-effect transistor (GaN FET), wherein the GaN FET is A channel layer of a III-N semiconductor material, comprising the channel layer containing gallium and nitrogen, A barrier layer of III-N semiconductor material on the channel layer, comprising aluminum and nitrogen, The gate of the III-N semiconductor material on the barrier layer, which is p-type and contains gallium and nitrogen, A source adjacent to the channel layer, A drain in contact with the channel layer, Includes, The bottom surface of the gate adjacent to the barrier layer does not extend beyond the top surface of the barrier layer, and the top surface is located on the opposite side from the channel layer. The GaN FET does not include a dielectric layer between the gate and the barrier layer. The GaN FET is a semiconductor device having a gate-source threshold potential of -10 volts to -0.5 volts.

2. A semiconductor device according to claim 1, A semiconductor device in which the barrier layer has a thickness of 1 nanometer to 60 nanometers.

3. A semiconductor device according to claim 1, A semiconductor device in which the barrier layer contains gallium.

4. A semiconductor device according to claim 1, A semiconductor device in which the barrier layer contains indium.

5. A semiconductor device according to claim 1, The channel layer is 3 × 10 １２ cm －２ ~2 x 10 １３ cm －２ A semiconductor device having a two-dimensional electron gas (2DEG) with a free charge carrier density of .

6. A semiconductor device according to claim 1, A semiconductor device in which the gate has a thickness of 5 nanometers to 500 nanometers.

7. A semiconductor device according to claim 1, The gate is 1 x 10 １７ cm －３ ~1 x 10 ２０ cm －３ A semiconductor device having a magnesium concentration of [value].

8. A semiconductor device according to claim 1, A semiconductor device wherein the GaN FET further includes a high-bandgap sublayer between the channel layer and the barrier layer, the high-bandgap sublayer mainly comprises aluminum and nitrogen, and the high-bandgap sublayer has a thickness of 0.5 nanometers to 3 nanometers.

9. A semiconductor device according to claim 1, A semiconductor device wherein the GaN FET further includes an etch-stopping layer between the barrier layer and the gate, the etch-stopping layer having a higher aluminum content than the barrier layer, and the etch-stopping layer having a thickness of 0.5 nanometers to 3 nanometers.

10. A semiconductor device according to claim 1, A semiconductor device wherein the GaN FET further includes a dielectric layer on the barrier layer between the gate and the source, and between the gate and the drain.

11. A method for forming a semiconductor device, Forming a channel layer of a III-N semiconductor material for a depletion-mode gallium nitride field-effect transistor (GaN FET), wherein the channel layer contains gallium and nitrogen. Forming a barrier layer of III-N semiconductor material on the channel layer, wherein the barrier layer contains aluminum and nitrogen, The gate layer of a III-N semiconductor material is formed on the barrier layer, wherein the gate layer is p-type, contains gallium and nitrogen, the bottom surface of the gate layer adjacent to the barrier layer does not extend beyond the top surface of the barrier layer, the top surface is located on the opposite side from the channel layer, and the GaN FET does not include a dielectric layer between the gate layer and the barrier layer. A gate mask is formed on the gate layer, covering the gate area over the area for the gate of the GaN FET. To form the gate, the gate layer exposed by the gate mask is removed, Removing the aforementioned gate mask, Methods that include...

12. The method according to claim 11, A method wherein the barrier layer has a thickness of 1 nanometer to 60 nanometers.

13. The method according to claim 11, A method for forming the barrier layer, comprising using a gallium-containing gas reagent, wherein the barrier layer contains gallium.

14. The method according to claim 11, A method for forming the barrier layer, comprising using an indium-containing gas reagent, wherein the barrier layer contains indium.

15. The method according to claim 11, A method wherein the gate layer has a thickness of 5 nanometers to 500 nanometers.

16. The method according to claim 11, Forming the gate layer includes using a magnesium-containing gas reagent, so that the gate has a magnesium concentration of 1×10 １７ cm －３ to 1×10 ２０ cm －３ . The method

17. The method according to claim 11, A method wherein the gate layer exposed by the gate mask is removed using an inductively coupled plasma (ICP) process with chloride ions and argon ions.

18. The method according to claim 17, A method for the ICP process that uses oxygen ions.

19. The method according to claim 11, A method further comprising forming an etch-stopping layer on the barrier layer before forming the gate layer, wherein the etch-stopping layer has a higher aluminum content than the barrier layer and the etch-stopping layer has a thickness of 0.5 nanometers to 3 nanometers.

20. The method according to claim 11, A method further comprising, after removing the gate mask, forming a dielectric layer adjacent to the gate on the top surface of the barrier layer.

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