Image sensor and imaging device

Abstract

Reduces damage to capacitive elements placed in pixels. [Solution] The image sensor has a plurality of pixels and a capacitive element. Each pixel is formed on a semiconductor substrate and includes a photoelectric conversion unit that performs photoelectric conversion of incident light to generate an electric charge and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge. Each capacitive element is arranged for each pixel and includes a lower electrode positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate, an insulating film configured to cover the lower electrode, an upper electrode configured to face the lower electrode through the insulating film at the opening, and a lower electrode protection unit positioned adjacent to the upper end of the lower electrode to protect the lower electrode.

Description

Technical Field

[0001] The present disclosure relates to an image pickup device and an imaging apparatus.

Background Art

[0002] Among image pickup devices that generate an image signal based on light from a subject, a CMOS (Complementary Metal Oxide Semiconductor) type image pickup device includes a plurality of pixels arranged in a two-dimensional matrix. These pixels are provided with a photoelectric conversion unit that performs photoelectric conversion of incident light, a charge holding unit that holds the charge generated by the photoelectric conversion unit, and a signal generation unit that generates a signal corresponding to the charge held in the charge holding unit. The photoelectric conversion unit performs photoelectric conversion during an exposure period to accumulate charge. This charge is transferred to and held in the charge holding unit after the exposure period. Then, the signal generation unit generates a signal based on the charge held in the charge holding unit and outputs it as an image signal.

[0003] As this charge holding unit, a floating diffusion region (FD), which is a semiconductor region formed in a semiconductor substrate, is used. When the charge holding capacity in this FD is insufficient or when it is applied for use in switching the charge holding capacity, an auxiliary charge holding unit is added to the pixel. As such an additional charge holding unit, an optical detection element (image pickup device) using a MIM (Metal Insulator Metal) capacitor element has been proposed (see, for example, Patent Document 1). This MIM capacitor element is arranged in an insulating layer in a wiring region adjacent to the semiconductor substrate, and is composed of a lower electrode arranged on the side wall of a trench formed in the insulating layer, an insulating film, and an upper electrode. This lower electrode is configured in a film shape covering the side wall of the trench and is arranged only inside the trench. Also, the insulating film is configured in a shape covering the surface including the upper end portion of the lower electrode. The upper electrode facing the lower electrode is arranged via this insulating film.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] International Publication No. 2024 / 053372 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] However, in the conventional technology described above, the upper end of the lower electrode formed inside the trench is exposed during the manufacturing process of the image sensor, which leads to a problem where the upper end of the lower electrode is damaged in subsequent processes. This results in a decrease in the performance of the capacitive element.

[0006] Therefore, this disclosure proposes an image sensor and imaging device that reduce damage to capacitive elements arranged in pixels. [Means for solving the problem]

[0007] The image sensor according to this disclosure comprises a plurality of pixels, each having a photoelectric conversion unit formed on a semiconductor substrate and generating an electric charge by photoelectric conversion of incident light and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge; a lower electrode arranged for each pixel and positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film configured to cover the lower electrode; an upper electrode configured to face the lower electrode through the insulating film in the opening; and a lower electrode protection unit positioned adjacent to the upper end of the lower electrode to protect the lower electrode. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example of the configuration of an image sensor according to the present disclosure. [Figure 2] This figure shows an example of the pixel configuration according to the embodiment of this disclosure. [Figure 3] This is a cross-sectional view showing an example of the pixel configuration according to the first embodiment of this disclosure. [Figure 4] This figure shows an example of the configuration of a second charge-holding unit according to the first embodiment of the present disclosure. [Figure 5] This figure shows an example of the pixel configuration according to the first embodiment of this disclosure. [Figure 6A] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6B] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6C] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6D] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6E] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6F] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6G] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6H] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6I] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 6J] This figure shows an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. [Figure 7A] This figure illustrates the effect of the lower electrode protection portion according to the first embodiment of this disclosure. [Figure 7B] This figure illustrates the effect of the lower electrode protection portion according to the first embodiment of this disclosure. [Figure 8] This figure shows an example of the pixel configuration according to the second embodiment of this disclosure. [Figure 9] This figure shows an example of the configuration of a second charge-holding unit according to a second embodiment of the present disclosure. [Figure 10A] This figure shows an example of a method for manufacturing an image sensor according to the second embodiment of this disclosure. [Figure 10B]It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10C] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10D] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10E] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10F] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10G] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 10H] It is a diagram showing an example of a method for manufacturing an image pickup device according to a second embodiment of the present disclosure. [Figure 11] It is a diagram showing another configuration example of a second charge holding portion according to a second embodiment of the present disclosure. [Figure 12] It is a diagram showing a configuration example of a capacitor element according to a third embodiment of the present disclosure. [Figure 13] It is a diagram showing another configuration example of a capacitor element according to a third embodiment of the present disclosure. [Figure 14] It is a diagram showing another configuration example of a capacitor element according to a third embodiment of the present disclosure. [Figure 15] It is a diagram showing another configuration example of a capacitor element according to a third embodiment of the present disclosure. [Figure 16] It is a diagram showing another configuration example of a capacitor element according to a third embodiment of the present disclosure. [Figure 17] It is a diagram showing a configuration example of an image pickup device according to a third embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. The description will be made in the following order. In each of the following embodiments, the same parts are denoted by the same reference numerals, and redundant descriptions are omitted. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment

[0010] (1. First Embodiment) <Image sensor configuration> Figure 1 is a diagram showing an example configuration of an image sensor according to the present disclosure. The same figure is a block diagram representing an example configuration of the image sensor 1. The image sensor 1 is a semiconductor element that generates image data of a subject. The image sensor 1 comprises a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0011] The pixel array section 10 is composed of multiple pixels 100 arranged together. In this pixel array section 10, the multiple pixels 100 are arranged in the shape of a two-dimensional matrix. Here, each pixel 100 is composed of a photoelectric conversion section that performs photoelectric conversion of incident light and a charge holding section (a first charge holding section 105, described later) that holds the charge generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion section. In addition, a signal generation section (a signal generation section 110, described later) is provided for each pixel 100. This signal generation section 110 generates an image signal based on the charge held in the first charge holding section 105 of the pixel 100.

[0012] Each pixel 100 is wired with a signal line 11. The pixel 100 is controlled by a control signal transmitted by the signal line 11. Additionally, each pixel 100 is wired with a signal line 12. The image signal from the signal generation unit 110 is output to this signal line 12. The signal lines 11 are arranged in rows of a two-dimensional matrix and are wired in common to multiple pixels 100 arranged in one row. The signal lines 12 are arranged in columns of a two-dimensional matrix and are wired in common to multiple pixels 100 arranged in one column.

[0013] The vertical drive unit 20 generates the control signals for the pixels 100 described above. The vertical drive unit 20 in the figure generates control signals for each row of the two-dimensional matrix of the pixel array unit 10 and outputs them sequentially via the signal line 11.

[0014] The column signal processing unit 30 processes the image signals generated by the pixels 100. The column signal processing unit 30 in the figure simultaneously processes image signals from multiple pixels 100 arranged in one row of the pixel array unit 10, transmitted via the signal line 12. This processing can include, for example, analog-to-digital conversion, which converts the analog image signals generated by the pixels 100 into digital image signals, and correlated double sampling (CDS), which removes offset errors in the image signals. The processed image signals are output to external circuits, etc., of the image sensor 1.

[0015] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. The control unit 40 in the figure controls the vertical drive unit 20 and the column signal processing unit 30 by outputting control signals via signal lines 41 and 42, respectively.

[0016] The image sensor 1 is an example of the "imaging device" in this disclosure. The column signal processing unit 30 is an example of the "processing circuit" in this disclosure.

[0017] <Pixel configuration> Figure 2 is a diagram showing an example of the configuration of a pixel according to the present disclosure. The same figure is a circuit diagram showing an example of the configuration of pixel 100.

[0018] Pixel 100 comprises a photoelectric conversion unit 101, a charge transfer unit 102, a first charge holding unit 105, a reset unit 104, a coupling transistor 103, a second charge holding unit 106, and a signal generation unit 110. The signal generation unit 110 also comprises an amplification transistor 111 and a selection transistor 112.

[0019] The charge transfer unit 102, coupling transistor 103, reset unit 104, amplification transistor 111, and selection transistor 112 can be composed of n-channel MOS transistors. Furthermore, the first charge holding unit 105 can be composed of a semiconductor region similar to that of the FD described above.

[0020] As mentioned above, signal lines 11 to 12 are wired to pixel 100. Signal line 11 in the figure includes signal lines TG, FDG, RST, and SEL. Signal line 12 includes signal line VSL. In addition, power lines VDD and MIMVDD are wired to pixel 100. MIMVDD is the wire that supplies the applied voltage to the second charge holding unit 106.

[0021] The anode of the photoelectric conversion unit 101 is connected to a common ground line, and its cathode is connected to the source of the charge transfer unit 102. The drain of the charge transfer unit 102 is connected to the gate of the amplification transistor 111, the drain of the coupling transistor 103, and one end of the first charge holding unit 105. The other end of the first charge holding unit 105 is connected to a common ground line. The drain of the reset unit 104 and the drain of the amplification transistor 111 are connected to the power line VDD. The source of the reset unit 104 is connected to the drain of the coupling transistor 103 and one end of the second charge holding unit 106. The other end of the second charge holding unit 106 is connected to MIMVDD. The source of the amplification transistor 111 is connected to the drain of the selection transistor 112, and the source of the selection transistor 112 is connected to the signal line VSL.

[0022] The gate of the charge transfer unit 102 is connected to the signal line TG. The gate of the reset unit 104 is connected to the signal line RST. The gate of the coupling transistor 103 is connected to the signal line FDG. The gate of the selection transistor 112 is connected to the signal line SEL.

[0023] The reset unit 104 resets the first charge holding unit 105 and the second charge holding unit 106. This reset can be performed by discharging the charge from the first charge holding unit 105, etc., to the power line VDD. The control signal from the reset unit 104 is transmitted via the signal line RST.

[0024] The amplification transistor 111 amplifies the voltage of the first charge holding unit 105. The gate of the amplification transistor 111 is connected to the first charge holding unit 105. Therefore, an image signal of a voltage corresponding to the charge held in the first charge holding unit 105 is generated at the source of the amplification transistor 111. Furthermore, by conducting the selection transistor 112, this image signal can be output to the signal line VSL. The control signal of the selection transistor 112 is transmitted via the signal line SEL.

[0025] The second charge-holding unit 106 is a capacitor coupled to the first charge-holding unit 105. By coupling this second charge-holding unit 106 to the first charge-holding unit 105, the charge-holding capacitance of the pixel 100 can be adjusted. That is, by coupling the second charge-holding unit 106 to the first charge-holding unit 105, the charge-holding capacitance of the pixel 100 can be increased. This allows the sensitivity of the pixel 100 to be adjusted. When the second charge-holding unit 106 is not coupled to the first charge-holding unit 105, a high-sensitivity mode is achieved. On the other hand, when the second charge-holding unit 106 is coupled to the first charge-holding unit 105, a low-sensitivity mode is achieved.

[0026] The coupling transistor 103 connects the second charge holding portion 106 to the first charge holding portion 105.

[0027] [Composition of pixel cross-section] Figure 3 is a cross-sectional view showing an example of the configuration of a pixel according to the first embodiment of the present disclosure. The figure is a cross-sectional view showing an example of the configuration of a pixel 100. The pixel 100 comprises a semiconductor substrate 120, a wiring region 140, a color filter 192, and an on-chip lens 193.

[0028] The semiconductor substrate 120 is a semiconductor substrate on which the diffusion layer of the semiconductor element of the pixel 100 is arranged. The semiconductor substrate 120 can be made of, for example, silicon (Si). The semiconductor elements are arranged in well regions formed on the semiconductor substrate 120. For convenience, the semiconductor substrate 120 in the figure is assumed to be made up of p-type well regions. Semiconductor elements can be formed by arranging n-type or p-type semiconductor regions in these p-type well regions. An insulating film 139 is arranged on the front surface of the semiconductor substrate 120. For example, silicon oxide (SiO2) or silicon nitride (SiN) can be used for this insulating film 139.

[0029] The semiconductor substrate 120 in the figure shows a photoelectric conversion unit 101, a first charge holding unit 105, a charge transfer unit 102, and an amplifying transistor 111. The photoelectric conversion unit 101 is composed of an n-type semiconductor region 121. Specifically, the photodiode consisting of a pn junction at the interface between the n-type semiconductor region 121 and the surrounding p-type well region corresponds to the photoelectric conversion unit 101. The semiconductor region 121 is configured such that a portion of it protrudes near the surface on the front side of the semiconductor substrate 120.

[0030] The first charge-holding portion 105 is composed of a semiconductor region 122. This semiconductor region 122 is an n-type semiconductor region with a relatively high impurity concentration. The semiconductor region 122 corresponds to the aforementioned FD.

[0031] The charge transfer section 102 is composed of a MOS transistor having semiconductor regions 121 and 122 and a gate electrode 131. Semiconductor region 121 corresponds to the source region, and semiconductor region 122 corresponds to the drain region. The insulating film 139 directly beneath the gate electrode 131 corresponds to the gate insulating film.

[0032] Note that only the gate electrode of the amplification transistor 111 is shown. This gate electrode is connected to the semiconductor region 122 of the first charge holding section 105 by wiring 151 and contact plug 153, which will be described later. An isolation section 129 is placed on the semiconductor substrate 120 near the amplification transistor 111 to isolate it from other elements. This isolation section 129 can be constructed using STI (Shallow Trench Isolation).

[0033] The wiring region 140 is an area located on the front surface of the semiconductor substrate 120 where the wiring of the element is formed. This wiring region 140 comprises wiring 151, via plugs 152, contact plugs 153, and an insulating layer 141. The wiring 151 is a conductor that transmits signals to the element on the semiconductor substrate 120. This wiring 151 can be made of a metal such as copper (Cu) or tungsten (W). The insulating layer 141 insulates the wiring 151 and the like. This insulating layer 141 can be made of SiO2, for example. As shown in the figure, the wiring can be made in multiple layers. In this case, the insulating film is also made in multiple layers. The insulating layer placed between layers is also called an interlayer insulating film. The via plugs 152 connect wiring 151 located in different layers. This via plug 152 can be made of a columnar metal, for example. The contact plug 153 connects the elements of the semiconductor substrate 120 to the wiring 151.

[0034] Furthermore, a separation portion 138 is arranged on the semiconductor substrate 120. This separation portion 138 is positioned at the boundary of the pixels 100 on the semiconductor substrate 120 to electrically and optically separate the pixels 100. This separation portion 138 can be made of an insulator embedded in the semiconductor substrate 120. The separation portion 138 can be formed, for example, by placing an insulator such as SiO2 in a groove that penetrates the semiconductor substrate 120 and is formed at the boundary of the pixels 100.

[0035] Furthermore, a protective film 191 is placed on the back surface of the semiconductor substrate 120. This protective film 191 is a film that protects the back surface of the semiconductor substrate 120. This protective film 191 can be made of an insulating material such as SiO2.

[0036] The color filter 192 is an optical filter that transmits incident light of a predetermined wavelength. For example, a color filter that transmits red light, green light, and blue light can be used for this color filter 192. In this case, one color filter 192 corresponding to red light, green light, or blue light is placed in the pixel 100. This pixel 100 generates an image signal of incident light of the wavelength corresponding to the color filter 192.

[0037] The on-chip lens 193 has a hemispherical cross-section and focuses incident light onto the photoelectric conversion unit 101. This on-chip lens 193 can be made of organic materials such as acrylic resin or inorganic materials such as SiN.

[0038] A second charge-holding unit 106 is located in the wiring region 140 of the figure. Unlike the first charge-holding unit 105 described above, this second charge-holding unit 106 is composed of a capacitive element 160. The details of the configuration of the second charge-holding unit 106 will be explained using Figure 4.

[0039] [Configuration of the second charge-holding section] Figure 4 is a diagram showing an example of the configuration of a second charge holding part according to the first embodiment of the present disclosure. The figure is a schematic cross-sectional view showing an example of the configuration of the second charge holding part 106. The wiring region 140 in the figure is composed of multiple insulating layers stacked on top of each other. The figure shows insulating layers 141 to 143. Wiring is formed between these insulating layers. An insulating film 149 is placed between insulating layers 141 and 142. This insulating film 149 is called a block film and can be made of SiN or silicon carbide nitride (SiCN). An insulating film 148 is placed between insulating layers 142 and 143. This insulating film 148 can be made of, for example, SiN or SiCN.

[0040] As described above, the second charge holding section 106 is composed of a capacitive element 160. The capacitive element 160 in the figure is formed in the insulating layer 142. The capacitive element 160 comprises a lower electrode 162, an insulating film 163, and an upper electrode 164.

[0041] The lower electrode 162 is an electrode positioned adjacent to the inner wall of the opening 161 formed in the insulating layer 142. This lower electrode 162 can be made of, for example, a metal or a metal compound. For example, the lower electrode 162 can be made of a metal (e.g., Ti, Ta, W, Mo, Al, Cu, Co, Ni, and Ru) or a compound containing the above metals (e.g., TiN, TaN, WN, and MoN). It is preferable that the lower electrode 162 be made of a material with a lower selectivity ratio during etching than the insulating layer 142.

[0042] The insulating film 163 is an insulating film configured to cover the lower electrode 162. This insulating film 163 can be made of oxides or nitrides. In addition, materials with a high dielectric constant, known as High-k materials, such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2), can also be used for the insulating film 163. Furthermore, the insulating film 163 can be constructed by laminating these materials.

[0043] The upper electrode 164 is an electrode configured to face the lower electrode 162 via an insulating film 163 in the opening 161. This upper electrode 164 can be made of the same material as the lower electrode 162. The second charge holding section 106 can be made of a plurality of capacitive elements 160. The upper electrode 164 can be configured to have a plurality of protrusions that are placed in the opening 161 of each capacitive element 160. The upper electrode 164 can also be considered as an electrode portion placed in the opening 161. In this case, the second charge holding section 107 in the figure can be considered to have an electrode structure in which a plurality of upper electrodes 164, each placed in a plurality of openings 161, are connected by a common electrode.

[0044] The lower electrode 162 is connected to the lower layer wiring 155, which is wiring located in the lower layer of the wiring area 140. The upper electrode 164 is connected to the upper layer wiring 156, which is wiring located in the upper layer of the wiring area 140. The upper layer wiring 156 in the figure is connected to the upper electrode 164 via a via plug 157. The upper layer wiring 156 is also connected to wiring 154 located in the insulating layer 141 via a via plug 158.

[0045] The second charge holding unit 106 can also be configured with a single capacitive element 160.

[0046] As shown in the figure, the lower electrode 162 is positioned only inside the opening 161. Furthermore, since the end of the lower electrode 162 is covered by the insulating film 163, it is shaped to be separated from the end of the upper electrode 164. This improves the electrical resistance between the lower electrode 162 and the upper electrode 164, thereby reducing leakage current.

[0047] As described above, an insulating film 148 is placed on top of the insulating layer 142. This insulating film 148 is made of a material with a lower selectivity ratio during etching than the insulating layer 142. Specifically, when SiO2 is applied to the insulating layer 142, SiN can be applied to the insulating film 148. Furthermore, the insulating film 148 near the capacitive element 160 is configured such that its end protrudes over the upper part of the lower electrode 162. That is, the end of the insulating film 148 is positioned adjacent to the upper end of the lower electrode 162. This region of the insulating film 148 positioned adjacent to the upper end of the lower electrode 162 is referred to as the lower electrode protection portion 165. This lower electrode protection portion 165 protects the lower electrode 162. Note that the insulating film 148 is an example of the "second insulating film" of this disclosure.

[0048] <Configuration of the pixel and the second charge-holding unit> Figure 5 is a diagram showing an example of the configuration of a pixel according to the first embodiment of the present disclosure. The figure is a plan view showing an example of the configuration of a pixel 100. As described above, a second charge holding portion 106 is arranged in the pixel 100. Capacitive elements 160 are arranged in this second charge holding portion 106. The dashed circles in the figure represent the openings 161 of the capacitive elements 160. The second charge holding portion 106 in the figure shows an example in which there are 16 capacitive elements 160 arranged in a 4x4 grid. By arranging multiple capacitive elements 160, the capacitance of the second charge holding portion 106 can be increased. The figure also shows lower wiring 155, upper electrode 164, upper wiring 156, and via plugs 157 and 158. The dashed circles in the figure represent via plugs 157 and 158. The upper wiring 156 is connected to, for example, MIMVDD in Figure 2. Furthermore, the lower wiring 155 is connected to, for example, the reset unit 104 in Figure 2.

[0049] <Manufacturing method for image sensors> Figures 6A-6J show an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. The figure shows an example of the manufacturing process for the capacitive element 160 portion of the image sensor 1.

[0050] First, an insulating layer 141 of the wiring region 140 is formed on the semiconductor substrate 120, and the underlying wiring 155 and wiring 154 are placed thereon. Next, insulating film 149, insulating layer 142, and insulating film 148 are laminated (Figure 6A). The insulating layer 141, insulating film 149, and insulating layer 142 can be formed, for example, by CVD (Chemical Vapor Deposition).

[0051] Next, an opening 400 is formed in the insulating film 148 and the insulating layer 142 at the position where the capacitive element 160 will be placed. This opening 400 is configured such that its lower end is in contact with the lower layer wiring 155 (Figure 6B). The opening 400 can be formed, for example, by dry etching.

[0052] Next, the insulating layer 142 in the opening 400 is etched to form the opening 161. At this time, the side surface of the insulating layer 142 in the opening 400 is ground, and a region of the insulating film 148 protruding toward the opening 400 is formed. This region constitutes the lower electrode protection portion 165 (Figure 6C). The etching of the insulating layer 142 can be performed, for example, by ALE (Atomic Layer Etching).

[0053] Next, the material film 401 of the lower electrode 162 is placed on the surface of the insulating film 148 including the opening 161 (Figure 6D). The material film 401 can be formed by sputtering, CVD, ALD, and plating.

[0054] Next, the material film 401 on the top and side surfaces of the insulating film 148 is removed to form the lower electrode 162 (Figure 6E). The material film 401 can be removed by dry etching.

[0055] Next, insulating film 163 is placed on the upper surface of insulating film 148 and on the side surface of the lower electrode 162 (Figure 6F). The insulating film 163 can be formed, for example, by CVD.

[0056] Next, the upper electrode 164 is formed (Figure 6G). This can be done, for example, by placing the material film of the upper electrode 164 on the surface of the insulating film 163, which includes the opening 161, and removing the unnecessary portion. In this process, unnecessary portions are also removed from the insulating film 163. This allows the capacitive element 160 to be formed.

[0057] Next, an insulating layer 143 is placed on top of the upper electrode 164 (Figure 6H). Then, a via plug 158 is formed (Figure 6I). Next, insulating layers are stacked to form a via plug 157 and upper wiring 156 (Figure 6J).

[0058] <Effects> Figures 7A and 7B illustrate the effects of the lower electrode protection portion according to the first embodiment of this disclosure. Figure 7A shows a capacitive element 160 without the lower electrode protection portion 165, as described as a comparative example. As shown in the figure, the lower electrode 162 is configured such that its upper end is exposed inside the opening 161. Therefore, the upper end of the lower electrode 162 is damaged by the CVD plasma during the formation of the upper electrode 164. The arrows in the figure represent the trajectory of the plasma. In addition, the corners may be shaved off during the etching process when forming the lower electrode 162, forming protrusions. The white arrows in the figure represent these protrusions. The electric field concentrates at such protrusions, causing damage.

[0059] Figure 7B shows a capacitive element 160 having a lower electrode protection portion 165. The upper end of the lower electrode 162 is covered and protected by the lower electrode protection portion 165.

[0060] Thus, in the first embodiment of the present disclosure, the image sensor 1 has a lower electrode protection portion 165 arranged on the capacitive element 160. This prevents damage to the upper end of the lower electrode 162 during the manufacturing process of the capacitive element 160.

[0061] (2. Second Embodiment) In the first embodiment described above, the image sensor 1 had an insulating film 163 and an upper electrode 164 arranged inside the lower electrode 162. In contrast, the image sensor 1 of the second embodiment of this disclosure differs from the first embodiment in that it has an insulating film 163 and an upper electrode 164 that sandwich the lower electrode 162.

[0062] <Configuration of the imaging device> Figure 8 is a diagram showing an example of the configuration of a pixel according to the second embodiment of this disclosure. Similar to Figure 5, this figure is a plan view showing an example of the configuration of a pixel 100. The second charge holding section 106 in this figure shows an example in which there are 16 capacitive elements 160 arranged in 4 rows and 4 columns. Note that the upper wiring 156 and via plugs 157 and 158 are omitted in this figure. The capacitive elements 160 in this figure are arranged in a capacitive element region 170. A capacitive element region separation section 171 is arranged at the boundary of the capacitive element region 170. The area of ​​the dashed line in this figure represents the capacitive element region separation section 171. As shown in this figure, the capacitive elements 160 are arranged inside the capacitive element region separation section 171.

[0063] [Configuration of the second charge-holding section] Figure 9 is a diagram showing an example configuration of a second charge holding portion according to a second embodiment of the present disclosure. Similar to Figure 4, this figure is a schematic cross-sectional view showing an example configuration of the second charge holding portion 106. The capacitive element 160 in this figure comprises an insulating film 163 arranged on both sides of the lower electrode 162 and an upper electrode 164 configured to sandwich the lower electrode 162 via the insulating film 163.

[0064] Furthermore, the capacitive element 160 is placed in the capacitive element region 170. A capacitive element region separation section 171 is placed at the boundary of the capacitive element region 170. This capacitive element region separation section 171 separates the insulating layer 142 inside the capacitive element region 170. The capacitive element region separation section 171 in the figure represents an example composed of an annular capacitive element. Specifically, the capacitive element region separation section 171 is composed of a lower electrode (lower electrode 173), an insulating film, and an upper electrode, which are placed in an annular groove-shaped opening 172 formed in the insulating layer 142. Note that the lower electrode 173 of the capacitive element region separation section 171 is configured so as not to come into contact with the lower layer wiring 155.

[0065] In the capacitive element 160 shown in the figure, the upper electrodes 164 are positioned on both sides of the lower electrode 162, thereby improving the capacitance of the capacitive element 160. Furthermore, in the capacitive element 160 shown in the figure, the lower electrode protection part 165 is also provided, which prevents damage to the upper end of the lower electrode 162 during the manufacturing process.

[0066] <Manufacturing method for image sensors> Figures 10A-10H show an example of a method for manufacturing an image sensor according to the second embodiment of this disclosure. These figures show an example of the manufacturing process for the capacitive element 160 portion of the image sensor 1.

[0067] First, as in Figure 6A, an insulating layer 141 of the wiring region 140 is formed on the semiconductor substrate 120, and the underlying wiring 155 is placed. Next, the insulating film 149, insulating layer 142, and insulating film 148 are laminated (Figure 10A).

[0068] Next, an opening 400 is formed at the position where the capacitive elements 160 of the insulating film 148 and the insulating layer 142 will be placed. Additionally, an opening 402 is formed at the position where the capacitive element region separation portion 171 of the insulating film 148 and the insulating layer 142 will be placed. The opening 402 is formed to a depth where its bottom is in contact with the insulating film 149 (Figure 10B).

[0069] Next, the insulating layer 142 in opening 400 is etched to form opening 161. Then, the insulating layer 142 in opening 402 is etched to form opening 172. At this time, the lower electrode protection portion 165 is formed (Figure 10C).

[0070] Next, the lower electrode 162 is placed in the opening 161. The lower electrode 173 is then placed in the opening 172 (Figure 10D).

[0071] Next, openings 403 are formed in the insulating film 148 and insulating layer 142 between the capacitive elements 160 in the capacitive element region 170 (Figure 10E).

[0072] Next, etching of the insulating layer 142 is performed through the opening 403. Due to the action of the lower electrode 173 of the capacitive element region isolation section 171, the etched area is limited to the inside of the capacitive element region 170 (Figure 10F).

[0073] Next, insulating film 163 is placed on both sides of the lower electrode 162 (Figure 10G).

[0074] Next, an upper electrode 164 is formed on the capacitive element 160 and the capacitive element region separation section 171 (Figure 10H). Through these steps, the capacitive element 160 can be manufactured.

[0075] [Other components of the second charge-holding section] Figure 11 is a diagram showing another example of the configuration of the second charge holding portion according to the second embodiment of the present disclosure. This figure, like Figure 9, is a schematic cross-sectional view showing an example of the configuration of the second charge holding portion 106. The second charge holding portion 106 in this figure differs from the second charge holding portion 106 in Figure 9 in that a capacitive element region isolation portion 179 is arranged instead of the capacitive element region isolation portion 171.

[0076] The capacitive element region isolation section 179 is composed of an insulating member or metal embedded in the insulating layer 142. Specifically, the capacitive element region isolation section 179 can be composed of an insulating member or metal placed in the opening 172 of the insulating layer 142.

[0077] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0078] Thus, the image sensor 1 of the second embodiment of this disclosure includes a capacitive element 160 having an upper electrode 164 that sandwiches the lower electrode 173. This makes it possible to improve the capacitance of the capacitive element 160.

[0079] (3. Third Embodiment) A variation of the image sensor 1 in the first embodiment described above will now be explained.

[0080] Figure 12 is a diagram showing an example configuration of a capacitive element according to the third embodiment of the present disclosure. The figure is a schematic cross-sectional view showing an example configuration of a capacitive element 160. The capacitive element 160 in the figure is shown as an example formed on a plurality of stacked insulating layers. Specifically, the capacitive element 160 in the figure is formed on a stacked insulating layer 142, insulating film 147, and insulating layer 146 in that order. The insulating film 147 can be made of the same material as the insulating film 148. The insulating layer 146 can also be made of the same material as the insulating layer 142. By configuring the capacitive element 160 to penetrate the plurality of insulating layers, the capacitance of the capacitive element 160 can be improved.

[0081] Figure 13 is a diagram showing another example configuration of a capacitive element according to the third embodiment of this disclosure. The figure is a schematic cross-sectional view showing an example configuration of the capacitive element 160. Note that only the upper part of the capacitive element 160 is shown in the figure. The insulating film 148 adjacent to the capacitive element 160 in the figure has a cross-section with arc-shaped corners. This makes it easy to embed the insulating film 163 and the upper electrode 164 into the opening 161.

[0082] Figure 14 is a diagram showing another example configuration of a capacitive element according to the third embodiment of this disclosure. The figure is a schematic cross-sectional view showing an example configuration of the capacitive element 160. Note that only the upper part of the capacitive element 160 is shown in the figure. The lower electrode 162 of the capacitive element 160 in the figure is formed on a side surface where irregularities are formed. As a result, irregularities are also formed on the upper electrode 164 facing the lower electrode 162. This makes it possible to improve the capacitance of the capacitive element 160.

[0083] Figure 15 shows another example of the configuration of a capacitive element according to the third embodiment of this disclosure. This figure shows an example that includes a capacitive element 160 and a capacitive element region isolation section 171 similar to those in Figure 9. The capacitive element region isolation section 171 in this figure differs from the capacitive element region isolation section 171 in Figure 9 in that the lower electrode 173 is connected to the lower layer wiring 155. By using the capacitive element region isolation section 171 as a capacitive element, the capacitance of the second charge holding section 106 equipped with the capacitive element can be improved.

[0084] Figure 16 shows another example of the configuration of a capacitive element according to the third embodiment of the present disclosure. This figure shows an example comprising a capacitive element 160 similar to that in Figure 4. The via plug 158 in this figure is shown as being configured at approximately the same height as the upper electrode 164. The via plug 158 in this figure is connected to the upper wiring 156 via a via plug 159.

[0085] Figure 17 is a diagram showing an example configuration of an image sensor according to a third embodiment of the present disclosure. The same figure is a cross-sectional view showing another example configuration of the image sensor 1. The image sensor 1 in the same figure differs from the image sensor 1 in Figure 2 in that the pixel array portion 10 is divided and arranged on two semiconductor substrates 120 and 220 on which the pixel array portion 10 is stacked.

[0086] The image sensor 1 in the figure is constructed by joining a wiring region 140 of a semiconductor substrate 120 and a wiring region 240 of a semiconductor substrate 220. A so-called Cu-Cu connection is applied to the joining of the wiring region 140 and the wiring region 240. The second charge holding portion 106 is located in the wiring region 240. In addition, a light-shielding film 195 is placed in place of the color filter 192 in the area outside the pixel array portion 10 of the semiconductor substrate 120. Furthermore, an opening 196 for wire bonding is located at the edge of the semiconductor substrate 120. This opening 196 is shaped to extend from the back side of the semiconductor substrate 120 to the wiring region 140. A pad 197 for wire bonding is located at the bottom of this opening 196.

[0087] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0088] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0089] Furthermore, this technology can also be configured as follows. (1) A plurality of pixels, each comprising a photoelectric conversion unit formed on a semiconductor substrate and generating an electric charge by photoelectric conversion of incident light, and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge, A capacitive element comprising: a lower electrode arranged for each pixel and positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film configured to cover the lower electrode; an upper electrode configured to face the lower electrode through the insulating film in the opening; and a lower electrode protection portion positioned adjacent to the upper end of the lower electrode to protect the lower electrode. A standard image sensor. (2) The image sensor according to (1), wherein a plurality of the capacitive elements are arranged for each pixel. (3) The lower electrode protection portion is comprised of a region in which a second insulating film laminated on the insulating layer protrudes toward the opening, as described in (1) above. (4) The image sensor according to (3), wherein the second insulating film is made of a different material from the insulating layer. (5) The insulating layer is made of silicon oxide, The second insulating film is composed of silicon nitride. The image sensor described in (4) above. (6) The image sensor according to any one of (1) to (5), wherein the capacitive element comprises the lower electrode, the insulating film disposed on both sides of the lower electrode, the upper electrode configured to sandwich the lower electrode via the insulating film, and the lower electrode protection portion. (7) The image sensor according to (6), further comprising a capacitive element region separation portion disposed at the boundary of the capacitive element region, which is the region in the insulating layer where the capacitive element is arranged. (8) The image sensor according to (7), wherein the capacitive element region separation portion is composed of annular capacitive elements formed at the boundary of the capacitive element region. (9) The image sensor according to (7), wherein the capacitive element region separation portion is composed of an insulating member embedded in the insulating layer. (10) The image sensor according to (7), wherein the capacitive element region separation portion is made of metal embedded in the insulating layer. (11) The capacitive element region is the image sensor according to (7) in which a plurality of the capacitive elements are arranged. (12) The aforementioned capacitive element is A step of forming the insulating layer in the wiring region of the semiconductor substrate, A step of laminating a second insulating film onto the insulating layer, The process involves forming openings in the second insulating film and the insulating layer, The steps include forming the lower electrode protection portion on the second insulating film of the opening, A step of forming a material film for the lower electrode on the surface of the insulating layer including the opening and the second insulating film, A step of forming the lower electrode by grinding the material film of the lower electrode near the surface of the second insulating film, The process of forming the insulating film, The process of forming the upper electrode and An image sensor according to any one of (1) to (11) above, formed by the above. (13) The image sensor according to (12), wherein the step of forming the lower electrode protection portion is a step of grinding the side surface of the insulating layer in the opening to form a region in which the second insulating film protrudes toward the opening. (14) A plurality of pixels, each comprising a photoelectric conversion unit formed on a semiconductor substrate and generating an electric charge by photoelectric conversion of incident light, and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge, A capacitive element comprising: a lower electrode arranged for each pixel and positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film configured to cover the lower electrode; an upper electrode configured to face the lower electrode through the insulating film in the opening; and a lower electrode protection portion positioned adjacent to the upper end of the lower electrode to protect the lower electrode; A processing circuit for processing the aforementioned pixel signal and An imaging device having [Explanation of symbols]

[0090] 1 Image sensor 10 Pixel array section 30-column signal processing unit 100 pixels 101 Photoelectric conversion unit 105 First charge holding part 106 Second charge holding part 110 Signal generation unit 120, 220 semiconductor substrates 140, 240 wiring area 141-143, 146 Insulating layer 147-149, 163 Insulating film 160 Capacitive elements 161, 172 Openings 162 Lower electrode 164 Upper electrode 165 Lower electrode protection part 170 Capacitive element region 171, 179 Capacitive element region separation section

Claims

1. A plurality of pixels, each comprising a photoelectric conversion unit formed on a semiconductor substrate and generating an electric charge by photoelectric conversion of incident light, and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge, A capacitive element comprising: a lower electrode arranged for each pixel and positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film configured to cover the lower electrode; an upper electrode configured to face the lower electrode through the insulating film in the opening; and a lower electrode protection portion positioned adjacent to the upper end of the lower electrode to protect the lower electrode. A standard image sensor.

2. The image sensor according to claim 1, wherein a plurality of capacitive elements are arranged for each pixel.

3. The image sensor according to claim 1, wherein the lower electrode protection portion is comprised of a region in which a second insulating film laminated on the insulating layer protrudes toward the opening.

4. The image sensor according to claim 3, wherein the second insulating film is made of a different material from the insulating layer.

5. The insulating layer is made of silicon oxide, The second insulating film is composed of silicon nitride. The image sensor according to claim 4.

6. The image sensor according to claim 1, wherein the capacitive element comprises the lower electrode, the insulating film disposed on both sides of the lower electrode, the upper electrode configured to sandwich the lower electrode via the insulating film, and the lower electrode protection portion.

7. The image sensor according to claim 6, further comprising a capacitive element region separation portion disposed at the boundary of the capacitive element region, which is the region in the insulating layer where the capacitive element is arranged.

8. The image sensor according to claim 7, wherein the capacitive element region separation portion is composed of an annular capacitive element formed at the boundary of the capacitive element region.

9. The image sensor according to claim 7, wherein the capacitive element region separation portion is composed of an insulating member embedded in the insulating layer.

10. The image sensor according to claim 7, wherein the capacitive element region isolation portion is made of metal embedded in the insulating layer.

11. The image sensor according to claim 7, wherein the capacitive element region is an image sensor in which a plurality of the capacitive elements are arranged.

12. The aforementioned capacitive element is A step of forming the insulating layer in the wiring region of the semiconductor substrate, A step of laminating a second insulating film onto the insulating layer, The steps include forming openings in the second insulating film and the insulating layer, The steps include forming the lower electrode protection portion on the second insulating film of the opening, A step of forming a material film for the lower electrode on the surface of the insulating layer including the opening and the second insulating film, A step of forming the lower electrode by grinding the material film of the lower electrode near the surface of the second insulating film, The process of forming the insulating film, The process of forming the upper electrode and The image sensor according to claim 1, formed by the above.

13. The image sensor according to claim 12, wherein the step of forming the lower electrode protection portion is a step of grinding the side surface of the insulating layer in the opening to form a region in which the second insulating film protrudes toward the opening.

14. A plurality of pixels, each comprising a photoelectric conversion unit formed on a semiconductor substrate and generating an electric charge by photoelectric conversion of incident light, and a signal generation unit that generates a pixel signal which is a signal based on the generated electric charge, A capacitive element comprising: a lower electrode arranged for each pixel and positioned adjacent to the inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film configured to cover the lower electrode; an upper electrode configured to face the lower electrode through the insulating film in the opening; and a lower electrode protection portion positioned adjacent to the upper end of the lower electrode to protect the lower electrode; A processing circuit for processing the aforementioned pixel signal and An imaging device having

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