Manufacturing method for semiconductor devices

Abstract

The present invention provides a method for manufacturing semiconductor devices that can efficiently consume semiconductor wafers. [Solution] n having a first impurity concentration + The process involves preparing an n-type SiC semiconductor wafer source, forming an n-type SiC epitaxial layer having a second impurity concentration lower than a first impurity concentration on a first main surface, forming a semiconductor element on the surface side of the n-type SiC epitaxial layer, and, after forming the semiconductor element, attaching a first main surface support member made of SiC to the surface side of the n-type SiC epitaxial layer, and n + A step of forming a modified layer extending along a horizontal direction parallel to the first main surface at the thickness position of the middle portion of a type SiC semiconductor wafer source, and along the modified layer n + A manufacturing method comprising the steps of separating a type SiC semiconductor wafer source into an element-forming wafer having semiconductor elements supported by a first main surface side support member and an element-unforming wafer.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes the steps of thinning a semiconductor wafer by grinding and cutting out a plurality of semiconductor chips (semiconductor devices) from the thinned semiconductor wafer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2010-016188 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In recent years, advancements in semiconductor device manufacturing technology have led to the thinning of semiconductor devices. Conversely, advancements in semiconductor wafer manufacturing technology have resulted in the increasing diameter of semiconductor wafers. The thickness of semiconductor wafers increases in proportion to their diameter to suppress deflection due to their own weight. In other words, semiconductor wafer manufacturing technology is moving in the direction of increasing the thickness of semiconductor wafers, contrary to the trend towards thinning semiconductor devices.

[0005] For example, in the conventional manufacturing method disclosed in Patent Document 1, a thick semiconductor wafer is thinned by grinding, and then multiple semiconductor devices are cut out. With such a manufacturing method, semiconductor devices with a desired thickness can be manufactured regardless of the thickness of the semiconductor wafer.

[0006] However, with conventional manufacturing methods, as semiconductor wafers become thicker, the portion that needs to be removed by grinding increases. In other words, with conventional manufacturing methods, for large-diameter and thick semiconductor wafers, the grinding time required to thin the semiconductor device increases compared to small-diameter and thin semiconductor wafers, and at the same time, the number of semiconductor devices that can be obtained per unit volume decreases relatively. Therefore, semiconductor wafers cannot be consumed efficiently.

[0007] One embodiment of the present invention provides a method for manufacturing a semiconductor device that can efficiently consume semiconductor wafers. [Means for solving the problem]

[0008] One embodiment of the present invention is an n having a first impurity concentration, a first main surface on one side and a second main surface on the other side. + The process involves: preparing a type SiC semiconductor wafer source; forming an n-type SiC epitaxial layer having a second impurity concentration lower than a first impurity concentration on the first main surface; forming a semiconductor element on the surface side of the n-type SiC epitaxial layer opposite to the second main surface; and, after forming the semiconductor element, attaching a first main surface support member made of SiC to the surface side of the n-type SiC epitaxial layer, and the n + A step of forming a modified layer extending along a horizontal direction parallel to the first main surface at the thickness position of the intermediate portion of the type SiC semiconductor wafer source, and along the modified layer the n + The present invention provides a method for manufacturing a semiconductor device, which includes the steps of separating a type SiC semiconductor wafer source into an element-forming wafer having semiconductor elements supported by the first main surface side support member and an element-unforming wafer.

[0009] This semiconductor device manufacturing method allows for the extraction of multiple semiconductor devices from a wafer with pre-formed elements, while simultaneously enabling the reuse of unformed wafers as a new semiconductor wafer source. This reduces manufacturing delays and prevents excessive consumption of semiconductor wafer sources. Therefore, it provides a semiconductor device manufacturing method that efficiently utilizes semiconductor wafer sources.

[0010] The above-mentioned, or further, objectives, features, and effects of the present invention will be made clearer by the following description of embodiments with reference to the accompanying drawings. [Brief explanation of the drawing]

[0011] [Figure 1A] Figure 1A is a perspective view illustrating one example of a semiconductor wafer source that may be applied to a method for manufacturing a semiconductor device according to the first embodiment of the present invention. [Figure 1B] Figure 1B is a perspective view illustrating one example of a wafer attachment structure that may be applied to a semiconductor device manufacturing method according to the first embodiment of the present invention. [Figure 2A] Figure 2A is a process diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. [Figure 2B] Figure 2B is a process diagram illustrating the process performed on the element-formed wafer obtained from the process shown in Figure 2A. [Figure 3A] Figure 3A is a schematic cross-sectional view illustrating the manufacturing method shown in Figures 2A and 2B. [Figure 3B] Figure 3B is a cross-sectional view illustrating the process after Figure 3A. [Figure 3C] Figure 3C is a cross-sectional view illustrating a process that follows Figure 3B. [Figure 3D] Figure 3D is a cross-sectional view illustrating a process that follows Figure 3C. [Figure 3E] Figure 3E is a cross-sectional view illustrating a process that follows Figure 3D. [Figure 3F] Figure 3F is a cross-sectional view illustrating the process after Figure 3E. [Figure 3G] Figure 3G is a cross-sectional view illustrating the process after Figure 3F. [Figure 3H] Figure 3H is a cross-sectional view illustrating the process after Figure 3G. [Figure 3I] Figure 3I is a cross-sectional view illustrating the process after Figure 3H. [Figure 3J] FIG. 3J is a cross-sectional view for explaining a process after FIG. 3I. [Figure 3K] FIG. 3K is a cross-sectional view for explaining a process after FIG. 3J. [Figure 4] FIG. 4 is a process diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5] FIG. 5 is a process diagram for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6A] FIG. 6A is a process diagram for explaining a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. [Figure 6B] FIG. 6B is a process diagram for explaining a process performed on an element formation wafer obtained from the process shown in FIG. 6A. [Figure 7A] FIG. 7A is a schematic cross-sectional view for explaining the manufacturing method shown in FIGS. 6A and 6B. [Figure 7B] FIG. 7B is a cross-sectional view for explaining a process after FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view for explaining a process after FIG. 7B. [Figure 7D] FIG. 7D is a cross-sectional view for explaining a process after FIG. 7C. [Figure 7E] FIG. 7E is a cross-sectional view for explaining a process after FIG. 7D. [Figure 7F] FIG. 7F is a cross-sectional view for explaining a process after FIG. 7E. [Figure 7G] FIG. 7G is a cross-sectional view for explaining a process after FIG. 7F. [Figure 8A] FIG. 8A is a process diagram for explaining a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. [Figure 8B] FIG. 8B is a process diagram for explaining a process performed on an element formation wafer obtained from the process shown in FIG. 8A. [Figure 9A] FIG. 9A is a schematic cross-sectional view for explaining the manufacturing method shown in FIGS. 8A and 8B. [Figure 9B] Figure 9B is a cross-sectional view illustrating the process following Figure 9A. [Figure 9C] Figure 9C is a cross-sectional view illustrating a process that follows Figure 9B. [Figure 9D] Figure 9D is a cross-sectional view illustrating a process that follows Figure 9C. [Figure 9E] Figure 9E is a cross-sectional view illustrating a process that follows Figure 9D. [Figure 9F] Figure 9F is a cross-sectional view illustrating the process after Figure 9E. [Figure 9G] Figure 9G is a cross-sectional view illustrating a process that follows Figure 9F. [Figure 9H] Figure 9H is a cross-sectional view illustrating a process that follows Figure 9G. [Figure 9I] Figure 9I is a cross-sectional view illustrating the process after Figure 9H. [Figure 9J] Figure 9J is a cross-sectional view illustrating a process that follows Figure 9I. [Figure 9K] Figure 9K is a cross-sectional view illustrating a subsequent process to Figure 9J. [Figure 9L] Figure 9L is a cross-sectional view illustrating a process that follows Figure 9K. [Figure 9M] Figure 9M is a cross-sectional view illustrating a process that follows Figure 9L. [Figure 10] Figure 10 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention. [Figure 11A] Figure 11A is a process diagram illustrating a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. [Figure 11B] Figure 11B is a process diagram illustrating the process performed on the element formation wafer obtained from the process shown in Figure 11A. [Figure 12A] Figure 12A is a schematic cross-sectional view illustrating the manufacturing method shown in Figures 11A and 11B, applied to the semiconductor device manufacturing method shown in Figure 10. [Figure 12B]Figure 12B is a cross-sectional view illustrating the process following Figure 12A. [Figure 12C] Figure 12C is a cross-sectional view illustrating a process that follows Figure 12B. [Figure 12D] Figure 12D is a cross-sectional view illustrating a process that follows Figure 12C. [Figure 12E] Figure 12E is a cross-sectional view illustrating a subsequent process to Figure 12D. [Figure 12F] Figure 12F is a cross-sectional view illustrating the process after Figure 12E. [Figure 12G] Figure 12G is a cross-sectional view illustrating a process that follows Figure 12F. [Figure 12H] Figure 12H is a cross-sectional view illustrating a process that follows Figure 12G. [Figure 12I] Figure 12I is a cross-sectional view illustrating a subsequent process to Figure 12H. [Figure 13] Figure 13 is a cross-sectional view showing a first modified example of the wafer-bonded structure. [Figure 14] Figure 14 is a perspective view showing a second modified example of the wafer-bonded structure. [Modes for carrying out the invention]

[0012] Figure 1A is a perspective view illustrating one example of a semiconductor wafer source 1 that can be applied to a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0013] Referring to Figure 1A, a disc-shaped semiconductor wafer source 1 may be applied to the manufacture of a semiconductor device. In this embodiment, the semiconductor wafer source 1 contains SiC (silicon carbide). More specifically, the semiconductor wafer source 1 consists of a semiconductor wafer made of a SiC single crystal.

[0014] The semiconductor wafer source 1 has a first main surface 2 on one side, a second main surface 3 on the other side, and a side wall 4 connecting the first main surface 2 and the second main surface 3. The first main surface 2 of the semiconductor wafer source 1 is the element formation surface on which semiconductor elements are formed.

[0015] The semiconductor wafer source 1 has a thickness T1 that can be cut along a horizontal direction parallel to the first main surface 2 from a point midway in the thickness direction. The thickness T1 of the semiconductor wafer source 1 exceeds the thickness of the semiconductor substrate of the semiconductor device (semiconductor chip) to be obtained. The thickness T1 of the semiconductor wafer source 1 may be 100 μm or more and 1000 μm or less. The thickness T1 of the semiconductor wafer source 1 may be 250 μm or more and 500 μm or less.

[0016] The semiconductor wafer source 1 includes a first wafer edge 5 and a second wafer edge 6. The first wafer edge 5 connects the first main surface 2 and the side wall 4. More specifically, the first wafer edge 5 connects the first main surface 2 and the side wall 4 at a right angle. In other words, the first wafer edge 5 is not chamfered.

[0017] The second wafer edge 6 connects the second main surface 3 and the side wall 4. More specifically, the second wafer edge 6 connects the second main surface 3 and the side wall 4 at a right angle. In other words, the second wafer edge 6 is not chamfered. In the semiconductor wafer source 1, it is preferable that at least the second wafer edge 6 is not chamfered.

[0018] The semiconductor wafer source 1 has a first orientation flat 7 (first marker) formed on it that indicates the crystal orientation, etc. The first orientation flat 7 includes a notch formed on the periphery of the semiconductor wafer source 1. The first orientation flat 7 extends linearly along the periphery of the semiconductor wafer source 1.

[0019] Multiple element formation regions 10 (chip formation regions) are set on the first main surface 2 of the semiconductor wafer source 1. Semiconductor elements 11 are formed in each of the multiple element formation regions 10. The multiple element formation regions 10 may be set in a matrix with spacing between them. Each element formation region 10 may be set in a rectangular shape in a plan view as seen from the normal direction of the first main surface 2.

[0020] The semiconductor element 11 may include semiconductor materials and various functional elements formed using the properties of semiconductor materials. The semiconductor element 11 may include at least one of the following: a semiconductor rectifier, a semiconductor switching element, or a semiconductor passive element.

[0021] The semiconductor rectifier element may include various diode elements such as pn junction diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. The semiconductor switching element may include various transistor elements such as bipolar transistors, MISFETs (Metal Insulator Semiconductor Field Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors). The semiconductor passive element may include various passive elements such as capacitors, resistors, and inductors.

[0022] The semiconductor element 11 may include a circuit network in which any two or more elements selected from semiconductor rectifier elements, semiconductor switching elements, and semiconductor passive elements are selectively combined. The circuit network may form part or all of an integrated circuit.

[0023] Integrated circuits may include SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), or ULSI (Ultra-Very Large Scale Integration).

[0024] Dicing lines 12 are demarcated in the boundary regions between multiple element formation regions 10. Multiple semiconductor devices are cut out by cutting the semiconductor wafer source 1 along the dicing lines 12.

[0025] Figure 1B is a perspective view illustrating one example of a wafer attachment structure 101 that can be applied to a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0026] Referring to Figure 1B, a disc-shaped wafer attachment structure 101 may be applied to the manufacture of a semiconductor device. The wafer attachment structure 101 has a laminated structure including a semiconductor wafer source 1 and a first support member 21. The semiconductor wafer source 1 is attached to the first support member 21.

[0027] According to the wafer attachment structure 101, the semiconductor wafer source 1 and the first support member 21 are handled integrally. This improves the convenience of handling the semiconductor wafer source 1. In this specification, the term "handling" includes not only loading and unloading to and from manufacturing equipment for manufacturing semiconductor devices, but also distribution to the market. In other words, the wafer attachment structure 101 can be traded in the market.

[0028] The first support member 21 is made of a disc-shaped substrate (wafer) and supports the semiconductor wafer source 1 from the second main surface 3 side. The first support member 21 has a first support main surface 22 on one side, a second support main surface 23 on the other side, and a support side wall 24 connecting the first support main surface 22 and the second support main surface 23.

[0029] The first support member 21 includes a first support edge 25 and a second support edge 26. The first support edge 25 connects the first support main surface 22 and the support side wall 24. The first support edge 25 includes a chamfered portion. The first support edge 25 may be C-chamfered. The first support edge 25 may be R-chamfered. In this case, the first support edge 25 may include a chamfered portion that is convex or nearly convex.

[0030] The first support edge 25 may be chamfered by at least one of the following methods: wire sawing, dicing blade processing, or etching. Chamfering the first support edge 25 can improve the handling convenience of the wafer attachment structure 101.

[0031] The second support edge 26 connects the second support main surface 23 and the support side wall 24. The second support edge 26 includes a chamfered portion. The second support edge 26 may be chamfered with a C-shape. The second support edge 26 may be chamfered with an R-shape. In this case, the second support edge 26 may include a chamfered portion that is convex or nearly convex.

[0032] The second support edge 26 may be chamfered by at least one of the following methods: wire sawing, dicing blade processing, or etching. Chamfering the second support edge 26 can improve the handling convenience of the wafer attachment structure 101.

[0033] The first support member 21 supports the semiconductor wafer source 1 from the second main surface 3 side. In other words, the semiconductor wafer source 1 is positioned on the first support main surface 22 of the first support member 21 with the second main surface 3 facing the first support main surface 22 of the first support member 21. The first support main surface 22 of the first support member 21 is attached to the second main surface 3 of the semiconductor wafer source 1.

[0034] In this configuration, the planar area of ​​the first support member 21 is greater than or equal to the planar area of ​​the semiconductor wafer source 1. This improves the convenience of handling the wafer attachment structure 101. When the semiconductor wafer source 1 is supported in the center of the first support member 21, the distance D between the periphery of the semiconductor wafer source 1 and the periphery of the first support member 21 may be 0 mm or more and 10 mm or less.

[0035] Various materials can be used for the first support member 21, as long as they can stably support the semiconductor wafer source 1. It is preferable that the first support member 21 has physical properties relatively similar to those of the semiconductor wafer source 1, given its purpose of supporting the semiconductor wafer source 1. These physical properties include, for example, the coefficient of thermal expansion and the melting point.

[0036] The ratio of the thermal expansion coefficient of the first support member 21 to the thermal expansion coefficient of the semiconductor wafer source 1 may be 0.5 or more and 1.5 or less. Preferably, the thermal expansion coefficient ratio is 0.8 or more and 1.2 or less. The melting point of the first support member 21 may be equal to or higher than the melting point of the semiconductor wafer source 1. The melting point of the first support member 21 may be 1600°C or higher.

[0037] The first support member 21 preferably contains the same material species as the semiconductor wafer source 1. In other words, the first support member 21 preferably contains SiC (silicon carbide). It is even more preferable that the first support member 21 is made of a semiconductor wafer made of SiC single crystal. This makes the physical properties of the first support member 21 approximately equal to the physical properties of the semiconductor wafer source 1.

[0038] The thickness T2 of the first support member 21 may be 100 μm or more and 1000 μm or less. The thickness T2 of the first support member 21 may be 250 μm or more and 500 μm or less. The thickness T2 of the first support member 21 may be equal to the thickness T1 of the semiconductor wafer source 1.

[0039] In the method for manufacturing a semiconductor device, laser light may be irradiated onto the semiconductor wafer source 1 via the first support member 21. In this case, it is preferable that the first support member 21 is light-transmitting. It is preferable that the first support member 21 is a light-transmitting wafer that suppresses the attenuation of the laser light irradiated onto the semiconductor wafer source 1. Light-transmitting wafers may include translucent wafers and transparent wafers.

[0040] The first support member 21 is preferably a single-crystal semiconductor wafer (a semiconductor wafer made of SiC single crystal) with no impurities or a low impurity concentration. In this case, absorption (attenuation) of laser light by the first support member 21 is suppressed.

[0041] If the first support member 21 contains impurities, the impurity concentration of the first support member 21 is preferably 1.0 × 10¹⁸ cm⁻³ or less. It should be noted that laser light having a wavelength of 390 μm or less tends to be absorbed (attenuated) by the first support member 21, which is made of a SiC single crystal semiconductor wafer, regardless of whether or not impurities are added.

[0042] The first support member 21 may be a vanadium-doped single-crystal semiconductor wafer (a semiconductor wafer made of SiC single crystal). The first support member 21 may be a p-type impurity-doped single-crystal semiconductor wafer (a semiconductor wafer made of SiC single crystal). The first support member 21 may be an n-type impurity-doped single-crystal semiconductor wafer (a semiconductor wafer made of SiC single crystal).

[0043] The first support member 21 may be a single-crystal semiconductor wafer (a semiconductor wafer made of SiC single crystal) to which p-type and n-type impurities have been added. The concentrations of p-type and n-type impurities may be approximately the same. In addition, the first support member 21 may be made of various materials depending on the physical properties of the semiconductor wafer source 1 and the wavelength of the laser light.

[0044] The first support member 21 has a second orientation flat 27 (second marker) formed on it that indicates the crystal orientation, etc. The second orientation flat 27 includes a notch formed on the periphery of the first support member 21. The second orientation flat 27 extends linearly along the periphery of the first support member 21.

[0045] The second orientation flat 27 of the first support member 21 may have the same crystal orientation as the first orientation flat 7 of the semiconductor wafer source 1. This allows the semiconductor wafer source 1 to be attached to the first support member 21 while knowing its crystal orientation.

[0046] The second orientation flat 27 of the first support member 21 may be positionally aligned with the first orientation flat 7 of the semiconductor wafer source 1. In other words, the second orientation flat 27 may extend parallel to the first orientation flat 7 at a position close to the first orientation flat 7.

[0047] As a result, the crystal orientation of the semiconductor wafer source 1 and the crystal orientation of the first support member 21 coincide, making it easy to determine the crystal orientation of the semiconductor wafer source 1. This improves the convenience of handling the wafer attachment structure 101.

[0048] Figure 2A is a process diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Figure 2B is a process diagram illustrating a process performed on the element-formed wafer 41 (new semiconductor wafer source 51, element-formed wafer) obtained from the process shown in Figure 2A.

[0049] Figures 3A to 3K are schematic cross-sectional views illustrating the manufacturing method shown in Figures 2A and 2B. For ease of explanation, the structure of the semiconductor wafer source 1 and the structure of the first support member 21 are simplified in Figures 3A to 3K.

[0050] First, referring to Figure 3A, the semiconductor wafer source 1 is prepared (step S1 in Figure 2A). Also, the first support member 21 is prepared.

[0051] Next, referring to Figure 3B, the semiconductor wafer source 1 is attached to the first support member 21 (step S2 in Figure 2A). The semiconductor wafer source 1 is attached to the first support member 21 in a position where the second main surface 3 faces the first support main surface 22 of the first support member 21. This forms the wafer attachment structure 101.

[0052] The semiconductor wafer source 1 may be attached to the first support member 21 by an adhesive. If the semiconductor wafer source 1 and the first support member 21 are made of the same material (SiC), the semiconductor wafer source 1 may be bonded to the first support member 21 by a direct wafer bonding method. The direct wafer bonding method may include a room temperature bonding method, a hydroxyl group bonding method, or a plasma bonding method.

[0053] In the room-temperature bonding method, first, an ion beam is irradiated onto the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21, respectively. As a result, atoms with bonding bonds are formed on the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21, respectively. Subsequently, the second main surface 3 of the semiconductor wafer source 1 is attached to the first support main surface 22 of the first support member 21.

[0054] In the hydroxyl group bonding method, first, the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21 are subjected to a hydrophilization treatment. An oxidizing chemical solution such as sulfuric acid hydrogen peroxide may be used for the hydrophilization treatment. This introduces hydroxyl groups to the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21. Subsequently, the second main surface 3 of the semiconductor wafer source 1 is attached to the first support main surface 22 of the first support member 21.

[0055] In the plasma bonding method, first, the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21 are subjected to oxygen plasma treatment, respectively. This forms active regions on the second main surface 3 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21, respectively. The active regions may contain atoms having hydroxyl groups and / or bonding bonds. Subsequently, the second main surface 3 of the semiconductor wafer source 1 is attached to the first support main surface 22 of the first support member 21.

[0056] In the wafer direct bonding method, heat treatment and pressurization steps may be performed as needed to increase the bonding strength between the semiconductor wafer source 1 and the first support member 21.

[0057] The wafer bonding structure 101 may include a bonding layer 28 that bonds the semiconductor wafer source 1 and the first support member 21 in the boundary region between the semiconductor wafer source 1 and the first support member 21. If the semiconductor wafer source 1 and the first support member 21 are bonded together by an adhesive, the bonding layer 28 may include the adhesive.

[0058] When the semiconductor wafer source 1 and the first support member 21 are bonded by a direct wafer bonding method, the bonding layer 28 may include a semiconductor bonding layer. The semiconductor bonding layer may have a different crystalline state from that of the semiconductor wafer source 1 and / or the first support member 21. The semiconductor bonding layer may include an amorphous layer. The amorphous layer may have the material of the semiconductor wafer source 1 and / or the material of the first support member 21.

[0059] Next, referring to Figure 3C, the semiconductor elements 11 are fabricated in each of the multiple element formation regions 10 set on the first main surface 2 of the semiconductor wafer source 1 (step S3 in Figure 2A).

[0060] The semiconductor device 11 formation process may include a step of polishing the first main surface 2 of the semiconductor wafer source 1. The semiconductor device 11 formation process may also include a step of forming an epitaxial layer 29 on the first main surface 2 of the semiconductor wafer source 1.

[0061] The semiconductor device 11 formation process may include a step of selectively introducing n-type impurities and / or p-type impurities into the epitaxial layer 29, depending on the properties of the semiconductor device 11. The semiconductor device 11 formation process may also include a step of forming a first main surface electrode 30 on the epitaxial layer 29.

[0062] In the polishing process, the first main surface 2 of the semiconductor wafer source 1 may be polished until the arithmetic mean roughness Ra is 1 nm or less. The polishing process may be carried out by the CMP (Chemical Mechanical Polishing) method.

[0063] In the process of forming the epitaxial layer 29, SiC is epitaxially grown from the first main surface 2 of the semiconductor wafer source 1. After the polishing process, the epitaxial layer 29 can be properly formed on the first main surface 2 of the semiconductor wafer source 1. This allows the semiconductor element 11 to be properly fabricated on the first main surface 2 of the semiconductor wafer source 1.

[0064] In the process of forming the first main surface electrode 30, the first main surface electrode 30, which is electrically connected to the element formation region 10, is formed in each of the multiple element formation regions 10.

[0065] Next, referring to Figure 3D, the second support member 31 is attached to the semiconductor wafer source 1 (step S4 in Figure 2A). The wafer attachment structure 101 may be handled with the second support member 31 attached.

[0066] The second support member 31 supports the semiconductor wafer source 1 from the first main surface 2 side of the semiconductor wafer source 1. The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0067] Various materials can be used for the second support member 31, as long as it can support the semiconductor wafer source 1. For example, a member having a structure similar to that of the first support member 21 may be used as the second support member 31. In this case, the description of the first support member 21 will apply mutatis mutandis to the description of the second support member 31.

[0068] The second support member 31 may be a disc-shaped glass plate. The glass plate may have an outer shape similar to that of the first support member 21. The second support member 31 may be directly attached to the semiconductor wafer source 1 without using the tape 32. In this case, the second support member 31 may be a single-sided adhesive tape.

[0069] The planar area of ​​the second support member 31 may be set to be greater than or equal to the planar area of ​​the semiconductor wafer source 1 for ease of handling. In this case, the wafer attachment structure 101 has a structure in which the semiconductor wafer source 1 is housed in opposing regions where the first support member 21 and the second support member 31 face each other.

[0070] As a result, the first support member 21 and the second support member 31 can adequately protect the semiconductor wafer source 1 from external forces, etc. Of course, the planar area of ​​the second support member 31 may be less than or equal to the planar area of ​​the semiconductor wafer source 1.

[0071] Next, referring to Figure 3E, laser light is irradiated from the laser light irradiation device 33 toward the semiconductor wafer source 1 (step S5 in Figure 2A). The laser light is irradiated toward the semiconductor wafer source 1 while the semiconductor wafer source 1 is supported by the second support member 31. The laser light is irradiated toward the semiconductor wafer source 1 from the second main surface 3 side of the semiconductor wafer source 1 via the first support member 21.

[0072] The focal point of the laser beam is set midway along the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the focal point of the laser beam is set according to the thickness of the semiconductor device to be acquired. The distance W1 may be between 50 μm and 100 μm.

[0073] The irradiation position of the laser beam onto the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first altered layer 34 is formed in a portion of the semiconductor wafer source 1 in the thickness direction, in which the crystalline state has been altered to properties different from other regions.

[0074] The first altered layer 34 is formed horizontally along the middle of the thickness direction of the semiconductor wafer source 1. The first altered layer 34 is a laser processing mark formed by irradiation with laser light. The first altered layer 34 is also a layer in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have become different from those of other regions due to the alteration.

[0075] The first altered layer 34 may include at least one of the following layers: a melt-re-hardened layer, a defect layer, a breakdown layer, or a refractive index change layer. The melt-re-hardened layer is a layer formed when a portion of the semiconductor wafer source 1 is melted and then re-hardened. The defect layer is a layer containing voids, cracks, etc. The breakdown layer is a layer formed by breakdown. The refractive index change layer is a layer having a different refractive index than other regions.

[0076] Next, referring to Figure 3F, the semiconductor wafer source 1 is cut along a horizontal direction parallel to the first main surface 2 from a point midway in the thickness direction (step S6 in Figure 2A). More specifically, the semiconductor wafer source 1 is cleaved along a horizontal direction starting from the first altered layer 34. The cleavage of the semiconductor wafer source 1 is carried out while the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31.

[0077] As a result, the semiconductor wafer source 1 is separated into an element-forming wafer 41 having semiconductor elements 11 and an unforming wafer 42 without semiconductor elements 11. The element-forming wafer 41 includes a first main surface 2 on one side and a first cross-section 43 on the other side. The element-forming wafer 41 has a thickness Ta. The unforming wafer 42 includes a second cross-section 44 on one side and a second main surface 3 on the other side. The unforming wafer 42 has a thickness Tb.

[0078] Referring to Figure 3G, after the separation process of the semiconductor wafer source 1, the first cross-section 43 of the element formation wafer 41 is ground (step S11 in Figure 2B). The grinding process of the first cross-section 43 may be carried out by the CMP method.

[0079] The grinding step of the first cross-section 43 may be performed until the element-forming wafer 41 reaches a desired thickness. In other words, the grinding step of the first cross-section 43 may include a thinning step of the element-forming wafer 41.

[0080] After the grinding step of the first cut surface 43, the second main surface electrode 45 is formed on the first cut surface 43 of the element formation wafer 41 (step S12 in Figure 2B). Of course, the grinding step of the first cut surface 43 may be omitted. In other words, the second main surface electrode 45 may be directly formed on the first cut surface 43 immediately after the separation step of the semiconductor wafer source 1.

[0081] Subsequently, the element-forming wafer 41 is cut along the dicing line 12 (see also Figures 1A and 1B) (step S13 in Figure 2B). This results in multiple semiconductor devices being cut out from the element-forming wafer 41.

[0082] The cutting process of the element-forming wafer 41 may be performed while it is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting process of the element-forming wafer 41. The cutting process of the element-forming wafer 41 may also be performed after the second support member 31 has been removed.

[0083] After the separation process of the semiconductor wafer source 1, it is determined whether the unformed wafer 42 can be reused as a new semiconductor wafer source (step S7 in Figure 2A).

[0084] The determination of whether the unformed wafer 42 can be reused may be performed based on the thickness Ta of the formed wafer 41 and the thickness Tb of the unformed wafer 42. If the thickness Tb of the unformed wafer 42 is less than or equal to the thickness Ta of the formed wafer 41 (Tb ≤ Ta), it may be determined that it cannot be reused. The condition for non-reuse is Tb <Taであってもよい。

[0085] The determination of whether the unformed-device wafer 42 can be reused may be performed based on the thickness Tch1 of the semiconductor device to be obtained from the unformed-device wafer 42. When the thickness Tch1 of the semiconductor device to be obtained is greater than or equal to the thickness Tb of the unformed-device wafer 42 (Tch1≧Tb), it may be determined that reuse is not possible. The non-reusable condition may also be Tch1>Tb.

[0086] The non-reusable conditions for the unformed-device wafer 42 may include cases where the unformed-device wafer 42 has a sufficient thickness Tb (for example, Tch1<Tb), while non-reusable circumstances occur.

[0087] When the unformed-device wafer 42 cannot be reused (step S7 in FIG. 2A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 ends.

[0088] When the unformed-device wafer 42 cannot be reused, a process of removing the unformed-device wafer 42 from the first support member 21 may be performed. The non-reusable unformed-device wafer 42 may be removed by a polishing process. The polishing process may be performed by the CMP method. After the removal process, a process of reusing the first support member 21 as a support member for supporting another semiconductor wafer source may be performed.

[0089] Referring to FIG. 3H, when the unformed-device wafer 42 can be reused as a new semiconductor wafer source (step S7 in FIG. 2A: YES), a new semiconductor element 52 is formed on the unformed-device wafer 42 (step S8 in FIG. 2A).

[0090] Hereinafter, the unformed-device wafer 42 is referred to as the "new semiconductor wafer source 51". The second cut surface 44 of the new semiconductor wafer source 51 corresponds to the first main surface 2 of the semiconductor wafer source 1. The new semiconductor element 52 may be formed on the second cut surface 44 of the new semiconductor wafer source 51 while the new semiconductor wafer source 51 is supported by the first support member 21.

[0091] The new semiconductor element 52 may be of the same type as the semiconductor element 11 described above, or of a different type. Figure 3H shows an example where the new semiconductor element 52 is of the same type as the semiconductor element 11. The new semiconductor element 52 is fabricated in each of the multiple element formation regions 10 set on the second cross-section 44 of the new semiconductor wafer source 51.

[0092] The process for forming the new semiconductor element 52 may include a step of polishing the second cut surface 44 of the new semiconductor wafer source 51. The process for forming the new semiconductor element 52 may also include a step of forming an epitaxial layer 29 on the second cut surface 44 of the new semiconductor wafer source 51.

[0093] The process for forming the new semiconductor element 52 may include a step of selectively introducing n-type impurities and / or p-type impurities into the epitaxial layer 29, depending on the properties of the new semiconductor element 52. The process for forming the new semiconductor element 52 may also include a step of forming a first main surface electrode 30 on the epitaxial layer 29.

[0094] In the polishing process, the second cross-section 44 of the new semiconductor wafer source 51 may be polished until the arithmetic mean roughness Ra is 1 nm or less. The polishing process may be carried out by the CMP method.

[0095] In the process of forming the epitaxial layer 29, SiC is epitaxially grown from the second cut surface 44 of the new semiconductor wafer source 51. After the polishing process, the epitaxial layer 29 can be properly formed on the second cut surface 44 of the new semiconductor wafer source 51. This allows a new semiconductor element 52 to be properly fabricated on the second cut surface 44 of the new semiconductor wafer source 51.

[0096] In the process of forming the first main surface electrode 30, the first main surface electrode 30, which is electrically connected to the element formation region 10, is formed in each of the multiple element formation regions 10.

[0097] Next, referring to Figure 3I, the second support member 31 is attached to the new semiconductor wafer source 51 (step S4 in Figure 2A). The second support member 31 supports the semiconductor wafer source 1 from the second cut surface 44 side of the new semiconductor wafer source 51. The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0098] Next, referring to Figure 3J, laser light is irradiated from the laser light irradiation device 33 toward the new semiconductor wafer source 51 (step S5 in Figure 2A). The laser light is irradiated toward the new semiconductor wafer source 51 while the new semiconductor wafer source 51 is supported by the second support member 31. The laser light is irradiated toward the new semiconductor wafer source 51 from the second main surface 3 side of the new semiconductor wafer source 51 via the first support member 21.

[0099] The focal point of the laser beam is set midway along the thickness direction of the new semiconductor wafer source 51. The distance W2 from the second cross-section 44 of the new semiconductor wafer source 51 to the focal point of the laser beam is set according to the thickness Tch1 of the semiconductor device to be acquired. The distance W2 may be between 50 μm and 100 μm.

[0100] The irradiation position of the laser beam onto the new semiconductor wafer source 51 is moved along a horizontal direction parallel to the second cross-section 44 of the new semiconductor wafer source 51. As a result, a second altered layer 55 is formed in the middle of the thickness direction of the new semiconductor wafer source 51, in which the crystalline state has been altered to properties different from other regions.

[0101] The second altered layer 55 is formed horizontally along the middle of the thickness direction of the new semiconductor wafer source 51. The second altered layer 55 has substantially the same configuration as the first altered layer 34 described above. A detailed explanation of the second altered layer 55 is omitted.

[0102] Next, referring to Figure 3K, the new semiconductor wafer source 51 is cut from a portion of its thickness along a horizontal direction parallel to the second cutting surface 44 (step S6 in Figure 2A).

[0103] More specifically, the new semiconductor wafer source 51 is cleaved horizontally, starting from the second altered layer 55. The cleavage of the new semiconductor wafer source 51 is performed while the new semiconductor wafer source 51 is supported (clamped) by the first support member 21 and the second support member 31.

[0104] As a result, the new semiconductor wafer source 51 is separated into a second element-forming wafer 61 (an element-formed wafer) on which a new semiconductor element 52 has been formed, and a second element-unformed wafer 62 on which no new semiconductor element 52 has been formed.

[0105] The second element-forming wafer 61 includes a second cross-section 44 on one side and a third cross-section 63 on the other side. The second element-forming wafer 61 has a thickness Tc. The second element-unforming wafer 62 includes a fourth cross-section 64 on one side and a second main surface 3 on the other side. The second element-unforming wafer 62 has a thickness Td.

[0106] After the separation process of the new semiconductor wafer source 51, the third cross-section 63 of the second device formation wafer 61 is ground (step S11 in Figure 2B). The grinding process of the third cross-section 63 may be carried out by the CMP method.

[0107] The grinding step of the third cross-section 63 may be performed until the second element-forming wafer 61 reaches a desired thickness. In other words, the grinding step of the third cross-section 63 may include a thinning step of the second element-forming wafer 61.

[0108] After the grinding step of the third cut surface 63, the second main surface electrode 45 is formed on the third cut surface 63 of the second element formation wafer 61 (step S12 in Figure 2B). Of course, the grinding step of the third cut surface 63 may be omitted. In other words, the second main surface electrode 45 may be directly formed on the third cut surface 63 immediately after the separation step of the new semiconductor wafer source 51.

[0109] Thereafter, the second element formation wafer 61 is cut along the dicing line 12 (also refer to FIGS. 1A and 1B) (step S13 in FIG. 2B). Thereby, a plurality of semiconductor devices are cut out from the second element formation wafer 61.

[0110] The cutting process of the second element formation wafer 61 may be performed while being supported by the second support member 31. In this case, after the cutting process of the second element formation wafer 61, the second support member 31 is removed. The cutting process of the second element formation wafer 61 may be performed after the second support member 31 is removed.

[0111] After the separation process of the new semiconductor wafer source 51, it is determined whether the second element-unformed wafer 62 can be reused as a new semiconductor wafer source (step S7 in FIG. 2A).

[0112] The determination of whether the second element-unformed wafer 62 can be reused may be performed based on the thickness Tc of the second element formation wafer 61 and the thickness Td of the second element-unformed wafer 62. When the thickness Td of the second element-unformed wafer 62 is less than or equal to the thickness Tc of the second element formation wafer 61 (Td ≦ Tc), it may be determined that it cannot be reused. The non-reusable condition may also be Td < Tc.

[0113] The determination of whether the second element-unformed wafer 62 can be reused may be performed based on the thickness Tch2 of the semiconductor device to be obtained from the second element-unformed wafer 62. When the thickness Tch2 of the semiconductor device to be obtained is greater than or equal to the thickness Td of the second element-unformed wafer 62 (Tch2 ≧ Td), it may be determined that it cannot be reused. The non-reusable condition may also be Tch2 > Td.

[0114] The non-reusable conditions of the second element-unformed wafer 62 may include a case where the second element-unformed wafer 62 has a sufficient thickness Td (for example, Tch2 < Td), while a non-reusable situation occurs.

[0115] If the second unformed wafer 62 cannot be reused as a new semiconductor wafer source (step S7:NO in Figure 2A), the manufacturing method of a semiconductor device using one semiconductor wafer source 1 is completed.

[0116] If the second unformed wafer 62 is unusable, a step may be taken to remove the second unformed wafer 62 from the first support member 21. The unusable second unformed wafer 62 may be removed by a polishing step. The polishing step may be performed by the CMP method. After the removal step, a step may be taken to reuse the first support member 21 as a support member for another semiconductor wafer source.

[0117] If the second unformed wafer 62 can be reused as a new semiconductor wafer source (step S7 in Figure 2A: YES), step S8 is performed. In this configuration, steps S4 to S7 are repeated until the unformed wafer can no longer be reused as a new semiconductor wafer source.

[0118] In this configuration, after the semiconductor element 11 formation process (step S3 in Figure 2A), the semiconductor wafer source 1 separation process (steps S5 and S6 in Figure 2A) is performed. The semiconductor wafer source 1 separation process is performed on the wafer attachment structure 101 to which the semiconductor wafer source 1 is attached to the first support member 21.

[0119] The semiconductor wafer source 1 is separated into an element-formed wafer 41 and an element-unformed wafer 42 by cleavage. In this case, the element-unformed wafer 42 is attached to the first support member 21. Therefore, multiple semiconductor devices can be cut from the element-formed wafer 41, while the element-unformed wafer 42 supported by the first support member 21 can be reused as a new semiconductor wafer source 51.

[0120] This suppresses manufacturing delays while simultaneously preventing excessive consumption of the semiconductor wafer source 1. Therefore, a wafer attachment structure 101 that can efficiently consume the semiconductor wafer source 1 can be provided.

[0121] In this configuration, a new semiconductor element 52 is fabricated onto the reused semiconductor wafer source 51 (step S8 in Figure 2A). In this configuration, a wafer source reuse repetition process (steps S5 to S7 in Figure 2A) is performed, in which the separation process of the semiconductor wafer source 1 and the reuse process of the semiconductor wafer source 1 are alternately repeated. This makes it possible to increase the number of semiconductor devices that can be obtained from a single semiconductor wafer source 1.

[0122] Furthermore, in this configuration, a cleavage process of the semiconductor wafer source 1 is performed using a laser irradiation method during the separation process of the semiconductor wafer source 1 (steps S5 and S6 in Figure 2A). This eliminates the need to adjust the thickness of the semiconductor device by grinding the semiconductor wafer source 1. Therefore, the increase in costs caused by grinding can be suppressed.

[0123] In particular, the laser irradiation method can be applied to a semiconductor wafer source 1 made of relatively hard SiC single crystal. Furthermore, the SiC single crystal semiconductor wafer source 1 can be appropriately separated into a device-formed wafer 41 and an unformed wafer 42.

[0124] Furthermore, the laser irradiation method has the advantage of suppressing the increase in costs caused by grinding, even if the initial unformed wafer 42 is unusable (step S7:NO in Figure 2A). The laser irradiation method is particularly beneficial for semiconductor wafer sources 1 made of relatively hard SiC single crystals.

[0125] Furthermore, in this configuration, during the separation process of the semiconductor wafer source 1 (steps S5 and S6 in Figure 2A), laser light is irradiated from the second main surface 3 side of the semiconductor wafer source 1 to a portion of the semiconductor wafer source 1 in the thickness direction.

[0126] No semiconductor elements 11 are formed on the second main surface 3 of the semiconductor wafer source 1. Therefore, laser light can be irradiated into the semiconductor wafer source 1 from the second main surface 3 side of the semiconductor wafer source 1, where there are fewer obstacles. As a result, the first altered layer 34 and the second altered layer 55 can be properly formed on the semiconductor wafer source 1, and the semiconductor wafer source 1 can be properly separated (cleaved).

[0127] If the second wafer edge 6 of the semiconductor wafer source 1 has a chamfered portion, a gap is formed in the region between the second wafer edge 6 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21. Errors in the focusing portion (focal point) of the laser beam include those caused by this gap.

[0128] Therefore, in this configuration, a second wafer edge 6 without a chamfered portion is formed in the semiconductor wafer source 1. This makes it possible to suppress the formation of a gap in the region between the second wafer edge 6 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21.

[0129] Therefore, errors in the focusing point of the laser beam can be suppressed, allowing the first altered layer 34 to be properly formed inside the semiconductor wafer source 1. As a result, the semiconductor wafer source 1 can be properly separated (cleaved) into the element-formed wafer 41 and the element-unformed wafer 42.

[0130] Furthermore, because errors in the laser beam's focusing point can be suppressed, the second altered layer 55 can be properly formed inside the new semiconductor wafer source 51. As a result, the new semiconductor wafer source 51 can be properly separated (cleaved) into a second element-formed wafer 61 and a second element-unformed wafer 62.

[0131] If the first support member 21 is made of a single-crystal semiconductor wafer with no impurities or a low impurity concentration, the absorption (attenuation) of laser light can be suppressed. Therefore, by devising the material of the first support member 21, the quality of the first modified layer 34 formed on the semiconductor wafer source 1 and the quality of the second modified layer 55 formed on the new semiconductor wafer source 51 can be improved.

[0132] Furthermore, in this configuration, the melting point of the first support member 21 is equal to or greater than the melting point of the semiconductor wafer source 1. This makes it possible to suppress melting and deformation of the first support member 21 during the manufacturing process.

[0133] Furthermore, in this configuration, the ratio of the thermal expansion coefficient of the support member to the thermal expansion coefficient of the semiconductor wafer source 1 is between 0.5 and 1.5. This reduces the stress difference between the thermal stress generated on the semiconductor wafer source 1 (new semiconductor wafer source 51) side and the thermal stress generated on the first support member 21 side during the manufacturing process. Therefore, warping of the semiconductor wafer source 1 (new semiconductor wafer source 51) can be suppressed.

[0134] If the first support member 21 is made of the same material (SiC) as the semiconductor wafer source 1, the melting point and thermal expansion coefficient will be approximately the same, thus reliably suppressing warping of the semiconductor wafer source 1 (new semiconductor wafer source 51). Furthermore, melting and deformation of the first support member 21 can also be reliably suppressed.

[0135] Figure 4 is a process diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. In the following description, the steps corresponding to those described in the first embodiment will not be explained.

[0136] In this embodiment, steps S21 to S22 are performed instead of steps S1 to S3 (see Figure 2A) according to the first embodiment. More specifically, first, a semiconductor wafer source 1 is prepared in which semiconductor elements 11 are formed in a plurality of element formation regions 10 (step S21 in Figure 4).

[0137] Next, the semiconductor wafer source 1 on which the semiconductor element 11 is formed is attached to the first support member 21 (step S22 in Figure 4). This forms the wafer attachment structure 101. After that, steps S4 to S8 are carried out.

[0138] In this embodiment, prior to the step of attaching the semiconductor wafer source 1 to the first support member 21 (step S22 in Figure 4), the semiconductor element 11 is formed on the semiconductor wafer source 1 (step S21 in Figure 4). This manufacturing method can also achieve the same effects as those described in the first embodiment.

[0139] Figure 5 is a process diagram illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. In the following description, the steps corresponding to those described in the first embodiment will not be explained.

[0140] In this embodiment, step S31 is performed instead of steps S1 to S3 (see Figure 2A) according to the first embodiment. More specifically, first, the wafer attachment structure 101 is prepared (step S31). The preparation step for the wafer attachment structure 101 may include the step of obtaining a wafer attachment structure 101 that is available on the market.

[0141] The wafer-bonded structure 101 may be manufactured by following the same process as steps S1 to S3 in the first embodiment (see also Figure 2A). Then, steps S4 to S8 are carried out. This manufacturing method can also produce the same effects as those described in the first embodiment.

[0142] Figure 6A is a process diagram illustrating a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Figure 6B is a process diagram illustrating a process performed on the element-formed wafer 41 (new semiconductor wafer source 51) obtained from the process shown in Figure 6A.

[0143] Figures 7A to 7G are schematic cross-sectional views illustrating the manufacturing method shown in Figures 6A and 6B. In the following description, the steps corresponding to those described in the first embodiment will not be explained.

[0144] In this embodiment, step S41 is performed instead of steps S1 to S3 (see Figure 2A) according to the first embodiment. Also, in this embodiment, step S42 is performed after step S5 and before step S6 according to the first embodiment. Also, in this embodiment, step S43 is performed after step S8.

[0145] More specifically, referring to Figure 7A, a semiconductor wafer source 1 is prepared in which a semiconductor element 11 is formed on the first main surface 2 (step S41 in Figure 6A). In this configuration, the second main surface 3 of the semiconductor wafer source 1 is exposed to the outside. In other words, the second main surface electrode 45 is not formed on the second main surface 3 of the semiconductor wafer source 1.

[0146] Next, referring to Figure 7B, the second support member 31 is attached to the first main surface 2 side of the semiconductor wafer source 1 (step S4 in Figure 6A). The second support member 31 may also be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0147] Next, referring to Figure 7C, laser light is irradiated from the laser light irradiation device 33 toward the semiconductor wafer source 1 (step S5 in Figure 6A). The laser light is irradiated toward the second main surface 3 of the semiconductor wafer source 1 while the semiconductor wafer source 1 is supported by the second support member 31.

[0148] In this configuration, the laser beam is directly irradiated from the second main surface 3 side of the semiconductor wafer source 1 to a point midway along the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the laser beam focusing point is set according to the thickness of the semiconductor device to be acquired. The distance W1 may be between 50 μm and 100 μm.

[0149] The irradiation position of the laser beam onto the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first altered layer 34 is formed in the middle of the thickness direction of the semiconductor wafer source 1, in which the crystalline state has been altered to properties different from other regions. +If the SiC semiconductor substrate is of a certain type, the first modified layer 34 may be formed in the middle of the SiC semiconductor substrate.

[0150] If the semiconductor wafer source 1 has a chamfered edge, an error occurs in the focusing point of the laser beam, which may cause the first altered layer 34 to not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0151] This suppresses errors in the laser beam's focusing point. As a result, the first altered layer 34 can be formed inside the semiconductor wafer source 1 parallel to the first main surface 2 across the entire thickness of the semiconductor wafer source 1. Therefore, the semiconductor wafer source 1 can be appropriately separated (cleaved) into an element-formed wafer 41 and an element-unformed wafer 42.

[0152] Next, referring to Figure 7D, the semiconductor wafer source 1 having the first altered layer 34 is attached to the first support member 21 (step S42 in Figure 6A). The semiconductor wafer source 1 is attached to the first support member 21 in a position where the second main surface 3 faces the first support main surface 22 of the first support member 21. This forms the wafer attachment structure 101. The method of attaching the semiconductor wafer source 1 to the first support member 21 is the same as described in the first embodiment, so the explanation is omitted.

[0153] Next, referring to Figure 7E, the semiconductor wafer source 1 is cut along a horizontal direction parallel to the first main surface 2, starting from a point midway along its thickness (step S6 in Figure 6A). More specifically, the semiconductor wafer source 1 is cleaved along a horizontal direction starting from the first altered layer 34.

[0154] The cleavage of the semiconductor wafer source 1 is performed while the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 without semiconductor elements 11.

[0155] In the cutting process of the semiconductor wafer source 1 (step S6 in Figure 6A), the semiconductor wafer source 1 should be separated into an element-formed wafer 41 having semiconductor elements 11 and an unformed wafer 42 without semiconductor elements 11. Not only in the case of cleavage as in this embodiment, but for example, the formation position and formation conditions of the first altered layer 34 may be adjusted so that the semiconductor wafer source 1 spontaneously separates into the element-formed wafer 41 and the unformed wafer 42.

[0156] Referring to Figure 7F, after the separation process of the semiconductor wafer source 1, the first cross-section 43 of the element formation wafer 41 is ground (step S44 in Figure 6B). The grinding process of the first cross-section 43 may be carried out by the CMP method.

[0157] The grinding step of the first cross-section 43 may be performed until the element-forming wafer 41 reaches a desired thickness. In other words, the grinding step of the first cross-section 43 may include a thinning step of the element-forming wafer 41.

[0158] Next, referring to Figure 7G, the second main surface electrode 45 is formed on the first cross-section 43 of the element formation wafer 41 (step S45 in Figure 6B). Of course, the grinding step of the first cross-section 43 may be omitted. In other words, the second main surface electrode 45 may be directly formed on the first cross-section 43 immediately after the separation step of the semiconductor wafer source 1.

[0159] After the grinding process of the element formation wafer 41 (step S44 in Figure 6B), and prior to the formation process of the second main surface electrode 45 (step S45 in Figure 6B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element formation wafer 41. The annealing treatment may be performed by laser irradiation. In this case, the ohmic properties of the second main surface electrode 45 with respect to the first cut surface 43 of the element formation wafer 41 can be increased.

[0160] Subsequently, the element-forming wafer 41 is cut along the dicing line 12 (see also Figures 1A and 1B) (step S46 in Figure 6B). This results in multiple semiconductor devices being cut out from the element-forming wafer 41.

[0161] The cutting process of the element-forming wafer 41 may be performed while it is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting process of the element-forming wafer 41. The cutting process of the element-forming wafer 41 may also be performed after the second support member 31 has been removed.

[0162] After the separation process of the semiconductor wafer source 1, it is determined whether the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 6A). The method for determining whether the unformed wafer 42 can be reused is the same as described in the first embodiment, so the explanation is omitted.

[0163] If the unformed wafer 42 is unusable (step S7:NO in Figure 6A), the manufacturing method of the semiconductor device using one semiconductor wafer source 1 is completed.

[0164] If the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 6A: YES), a new semiconductor element 52 is formed on the unformed wafer 42 (step S8 in Figure 6A).

[0165] Next, the first support member 21 is removed from the new semiconductor wafer source 51 (step S43 in Figure 6A). This exposes the second main surface 3 of the new semiconductor wafer source 51 to the outside. If a bonding layer 28 is attached to the second main surface 3 of the new semiconductor wafer source 51, the bonding layer 28 is removed from the conductive wafer source 51.

[0166] The first support member 21 may be removed by a polishing process. The polishing process may be carried out by the CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be used as a support member for another semiconductor wafer source. Then, step S4 is carried out.

[0167] Then, as in the first embodiment, steps S4 to S7 are repeated until the unformed wafer can no longer be reused as a new semiconductor wafer source. This manufacturing method can also produce the same effects as those described in the first embodiment.

[0168] In this embodiment, an example was described in which the removal of the first support member 21 (step S43 in Figure 6A) is performed after the formation of a new semiconductor element 52 (step S8 in Figure 6A). However, the removal of the first support member 21 (step S43 in Figure 6A) may be performed after determining whether the unformed wafer 42 can be reused (step S7 in Figure 6A) and prior to the formation of a new semiconductor element 52 (step S8 in Figure 6A).

[0169] Figure 8A is a process diagram illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. Figure 8B is a process diagram illustrating a process performed on an element-formed wafer 41 (new semiconductor wafer source 51) obtained from the process shown in Figure 8A.

[0170] Figures 9A to 9M are schematic cross-sectional views illustrating the manufacturing method shown in Figures 8A and 8B. In the following description, the steps corresponding to those described in the first embodiment will not be explained.

[0171] In this embodiment, step S51 is performed instead of steps S1 to S3 (see Figure 2A) according to the first embodiment. Also, in this embodiment, step S52 is performed after step S5 according to the first embodiment and before step S6. Furthermore, in this embodiment, steps S53 to S56, or steps S53, S57, and S58 are performed after step S7 according to the first embodiment.

[0172] More specifically, referring to Figure 9A, a semiconductor wafer source 1 is prepared on which a semiconductor element 11 is formed on the first main surface 2 (step S51 in Figure 8A).

[0173] Next, referring to Figure 9B, the second support member 31 is attached to the first main surface 2 side of the semiconductor wafer source 1 (step S4 in Figure 8A). The second support member 31 may also be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0174] Next, referring to Figure 9C, laser light is irradiated from the laser light irradiation device 33 toward the semiconductor wafer source 1 (step S5 in Figure 8A). The laser light is irradiated toward the second main surface 3 of the semiconductor wafer source 1 while the semiconductor wafer source 1 is supported by the second support member 31.

[0175] In this configuration, the laser beam is directly irradiated from the second main surface 3 side of the semiconductor wafer source 1 to a point midway along the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the laser beam focusing point is set according to the thickness of the semiconductor device to be acquired. The distance W1 may be between 50 μm and 100 μm.

[0176] The irradiation position of the laser beam onto the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first altered layer 34 is formed in the middle of the thickness direction of the semiconductor wafer source 1, in which the crystalline state has been altered to properties different from other regions. + If the SiC semiconductor substrate is of a certain type, the first modified layer 34 may be formed in the middle of the SiC semiconductor substrate.

[0177] If the semiconductor wafer source 1 has a chamfered edge, an error occurs in the focusing point of the laser beam, which may cause the first altered layer 34 to not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0178] This suppresses errors in the laser beam's focusing point. As a result, the first altered layer 34 can be formed inside the semiconductor wafer source 1 parallel to the first main surface 2 across the entire thickness of the semiconductor wafer source 1. Therefore, the semiconductor wafer source 1 can be appropriately separated (cleaved) into an element-formed wafer 41 and an element-unformed wafer 42.

[0179] Next, referring to Figure 9D, the semiconductor wafer source 1 having the first altered layer 34 is attached to the first support member 21 (step S52 in Figure 8A). The semiconductor wafer source 1 is attached to the first support member 21 in a position where the second main surface 3 faces the first support main surface 22 of the first support member 21. This forms the wafer attachment structure 101. The method of attaching the semiconductor wafer source 1 to the first support member 21 is the same as described in the first embodiment, so the explanation is omitted.

[0180] Next, referring to Figure 9E, the semiconductor wafer source 1 is cut along a horizontal direction parallel to the first main surface 2, starting from a point midway along its thickness (step S6 in Figure 8A). More specifically, the semiconductor wafer source 1 is cleaved along a horizontal direction starting from the first altered layer 34.

[0181] The cleavage of the semiconductor wafer source 1 is performed while the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 without semiconductor elements 11.

[0182] In the cutting process of the semiconductor wafer source 1 (step S6 in Figure 6A), the semiconductor wafer source 1 should be separated into an element-formed wafer 41 having semiconductor elements 11 and an unformed wafer 42 without semiconductor elements 11. Not only in the case of cleavage as in this embodiment, but for example, the formation position and formation conditions of the first altered layer 34 may be adjusted so that the semiconductor wafer source 1 spontaneously separates into the element-formed wafer 41 and the unformed wafer 42.

[0183] Referring to Figure 9F, after the separation process of the semiconductor wafer source 1, the first cross-section 43 of the element formation wafer 41 is ground (step S59 in Figure 8B). The grinding process of the first cross-section 43 may be carried out by the CMP method.

[0184] The grinding step of the first cross-section 43 may be performed until the element-forming wafer 41 reaches a desired thickness. In other words, the grinding step of the first cross-section 43 may include a thinning step of the element-forming wafer 41.

[0185] Next, referring to Figure 9G, the second main surface electrode 45 is formed on the first cross-section 43 of the element formation wafer 41 (step S60 in Figure 8B). Of course, the grinding step of the first cross-section 43 may be omitted. In other words, the second main surface electrode 45 may be directly formed on the first cross-section 43 immediately after the separation step of the semiconductor wafer source 1.

[0186] After the grinding process of the element formation wafer 41 (step S44 in Figure 6B), and prior to the formation process of the second main surface electrode 45 (step S45 in Figure 6B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element formation wafer 41. The annealing treatment may be performed by laser irradiation. In this case, the ohmic properties of the second main surface electrode 45 with respect to the first cut surface 43 of the element formation wafer 41 can be increased.

[0187] Subsequently, the element-forming wafer 41 is cut along the dicing line 12 (see also Figures 1A and 1B) (step S61 in Figure 8B). This results in multiple semiconductor devices being cut out from the element-forming wafer 41.

[0188] The cutting process of the element-forming wafer 41 may be performed while it is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting process of the element-forming wafer 41. The cutting process of the element-forming wafer 41 may also be performed after the second support member 31 has been removed.

[0189] After the separation process of the semiconductor wafer source 1, it is determined whether the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 8A). If the unformed wafer 42 cannot be reused (step S7: NO in Figure 8A), the manufacturing method of a semiconductor device using one semiconductor wafer source 1 is completed. The method for determining whether the unformed wafer 42 can be reused is the same as described in the first embodiment, so the explanation is omitted.

[0190] If the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 8A: YES), it is determined whether the unformed wafer 42 cannot be further divided and whether it will be the last semiconductor wafer source (step S53 in Figure 8A). The determination of whether the unformed wafer 42 can be further divided may be made based on the thickness of the semiconductor device to be obtained.

[0191] The unformed wafer 42 may be determined to be the last semiconductor wafer source if it is indivisible and has a thickness that can be adjusted to the thickness of the semiconductor device by short-time grinding. Alternatively, the unformed wafer 42 may be determined to be the last semiconductor wafer source if it is indivisible and has a thickness that is approximately equal to the thickness of the semiconductor device to be obtained.

[0192] Referring to Figure 9H, if the unformed wafer 42 is indivisible and becomes the last semiconductor wafer source (step S53 in Figure 8A: YES), the unformed wafer 42 is reused as the last semiconductor wafer source 81.

[0193] Then, the first support member 21 is removed from the last semiconductor wafer source 81 (step S54 in Figure 8A). As a result, the second main surface 3 of the last semiconductor wafer source 81 is exposed to the outside.

[0194] The first support member 21 may be removed by a polishing process. The polishing process may be carried out by the CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be used as a support member for another semiconductor wafer source.

[0195] Next, referring to Figure 9I, if the bonding layer 28 is attached to the second main surface 3 of the last semiconductor wafer source 81, the bonding layer 28 is removed from the last semiconductor wafer source 81.

[0196] Next, referring to Figure 9J, a new semiconductor element 52 is formed on the second cross-section 44 of the last semiconductor wafer source 81 (step S55 in Figure 8A). The new semiconductor element 52 may be of the same type as the aforementioned semiconductor element 11 or a different type.

[0197] Figure 9J shows an example where the new semiconductor element 52 is of the same type as the semiconductor element 11. The new semiconductor element 52 is fabricated in each of the multiple element formation regions 10 set on the second cross-section 44 of the last semiconductor wafer source 81. The process for forming the new semiconductor element 52 is the same as described in the first embodiment, so the explanation is omitted. Then, the second main surface electrode 45 is formed on the second main surface 3 of the last semiconductor wafer source 81.

[0198] Prior to the formation of the second main surface electrode 45, an annealing treatment may be performed on the second main surface 3 (grinding surface) of the last semiconductor wafer source 81. The annealing treatment may be performed by laser irradiation. In this case, the ohmic properties of the second main surface electrode 45 with respect to the second main surface 3 of the last semiconductor wafer source 81 can be increased.

[0199] Subsequently, the last semiconductor wafer source 81 is cut along the dicing line 12 (see also Figures 1A and 1B) (step S13 in Figure 2B). This results in multiple semiconductor devices being cut from the last semiconductor wafer source 81.

[0200] On the other hand, referring to Figure 9K, if the unformed wafer 42 can be divided again and does not become the last semiconductor wafer source (step S53:NO in Figure 8A), the unformed wafer 42 is reused as a new semiconductor wafer source 51.

[0201] Then, the first support member 21 is removed from the new semiconductor wafer source 51 (step S57 in Figure 8A). As a result, the second main surface 3 of the new semiconductor wafer source 51 is exposed to the outside.

[0202] The first support member 21 may be removed by a polishing process. The polishing process may be carried out by the CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be used as a support member for another semiconductor wafer source.

[0203] Next, referring to Figure 9L, if the bonding layer 28 is attached to the second main surface 3 of the new semiconductor wafer source 51, the bonding layer 28 is removed from the new semiconductor wafer source 51.

[0204] Next, referring to Figure 9M, a new semiconductor element 52 is formed on the second cross-section 44 of the new semiconductor wafer source 51 (step S58 in Figure 8A). The new semiconductor element 52 may be of the same type as the aforementioned semiconductor element 11 or a different type.

[0205] Figure 9M shows an example where the new semiconductor element 52 is of the same type as the semiconductor element 11. The new semiconductor element 52 is fabricated in each of the multiple element formation regions 10 set on the second cross-section 44 of the new semiconductor wafer source 51. The formation process for the new semiconductor element 52 is the same as described in the first embodiment, so the explanation is omitted.

[0206] In this configuration, steps S4 to S7 are repeated until the unformed wafer can no longer be reused as a new semiconductor wafer source. In this configuration, steps S4 to S53 are repeated until the unformed wafer is the last semiconductor wafer source.

[0207] This manufacturing method can also produce the same effects as those described in the first embodiment. In particular, in this embodiment, the unformed wafer 42 can be reused as the final semiconductor wafer source 81 (steps S53 to S56). This allows the initial semiconductor wafer source 1 to be consumed without waste.

[0208] In this process, an example was described in which the process of forming a new semiconductor element 52 on the last semiconductor wafer source 81 (step S55 in Figure 8A) is performed after the process of removing the first support member 21 (step S54 in Figure 8A). However, the process of forming a new semiconductor element 52 (step S55 in Figure 8A) may be performed prior to the process of removing the first support member 21 (step S54 in Figure 8A).

[0209] In this process, an example was described in which the process of forming a new semiconductor element 52 on a new semiconductor wafer source 51 (step S58 in Figure 8A) is performed after the process of removing the first support member 21 (step S57 in Figure 8A). However, the process of forming a new semiconductor element 52 (step S58 in Figure 8A) may be performed prior to the process of removing the first support member 21 (step S57 in Figure 8A).

[0210] Figure 10 is a cross-sectional view showing a semiconductor device 111 according to one embodiment of the present invention.

[0211] Referring to Figure 10, the semiconductor device 111 includes a Schottky barrier diode as an example of a semiconductor element 11. The semiconductor device 111 includes a chip-shaped SiC semiconductor layer 112. The SiC semiconductor layer 112 has a first main surface 113 on one side, a second main surface 114 on the other side, and a side surface 115 connecting the first main surface 113 and the second main surface 114.

[0212] In this configuration, the SiC semiconductor layer 112 is n + The structure has a laminated form including an n-type SiC semiconductor substrate 116 and an n-type SiC epitaxial layer 117. The n-type impurity concentration in the SiC epitaxial layer 117 is less than the n-type impurity concentration in the SiC semiconductor substrate 116.

[0213] The SiC semiconductor substrate 116 forms the second main surface 114 of the SiC semiconductor layer 112. The SiC epitaxial layer 117 forms the first main surface 113 of the SiC semiconductor layer 112. The SiC semiconductor substrate 116 and the SiC epitaxial layer 117 form the side surface 115 of the SiC semiconductor layer 112.

[0214] An n-type diode region 118 is formed on the surface of the first main surface 113 of the SiC semiconductor layer 112. In this configuration, the diode region 118 is formed in the central part of the first main surface 113 of the SiC semiconductor layer 112 in a plan view (hereinafter simply referred to as "plan view") taken from the direction normal to the first main surface 113 of the SiC semiconductor layer 112. In this configuration, the diode region 118 is formed using a part of the SiC epitaxial layer 117.

[0215] The surface portion of the first main surface 113 of the SiC semiconductor layer 112 contains p + A type of guard region 119 is formed. The guard region 119 is formed in a band shape that extends along the diode region 118 in a plan view. More specifically, the guard region 119 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) that surrounds the diode region 118 in a plan view. Thus, the guard region 119 is formed as a guard ring region.

[0216] The p-type impurities in the guard region 119 do not need to be activated. In this case, the guard region 119 is formed as a non-semiconductor region. The p-type impurities in the guard region 119 may be activated. In this case, the guard region 119 is formed as a p-type semiconductor region.

[0217] An insulating layer 120 is formed on the first main surface 113 of the SiC semiconductor layer 112. An opening 121 is formed in the insulating layer 120 that exposes the diode region 118. In this configuration, in addition to the diode region 118, the inner periphery of the guard region 119 is also exposed through the opening 121.

[0218] A first main surface electrode 30 is formed on the insulating layer 120. The first main surface electrode 30 extends from above the insulating layer 120 into the opening 121. The first main surface electrode 30 is electrically connected to the diode region 118 within the opening 121.

[0219] The first main surface electrode 30 forms a Schottky junction with the diode region 118. This forms a Schottky barrier diode with the first main surface electrode 30 as the anode and the diode region 118 as the cathode.

[0220] A second main surface electrode 45 is formed on the second main surface 114 of the SiC semiconductor layer 112. The second main surface electrode 45 forms ohmic contact with the second main surface 114 of the SiC semiconductor layer 112.

[0221] Figure 11A is a process diagram illustrating a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. Figure 11B is a process diagram illustrating a process performed on the element-forming wafer 41 obtained from the process shown in Figure 11A.

[0222] Figures 12A to 12I are schematic cross-sectional views illustrating the manufacturing method shown in Figures 11A and 11B, applied to the manufacturing method of the semiconductor device 111 shown in Figure 10.

[0223] Hereinafter, the description of the steps corresponding to the steps described in the first embodiment will be omitted. In FIGS. 12A to 12I, for convenience of explanation, only the region where one semiconductor device 111 is formed is shown, and the regions of other semiconductor devices and the end regions of the semiconductor wafer source 1 are omitted.

[0224] In this embodiment, instead of steps S1 to S5 (see FIG. 2A) according to the first embodiment, steps S71 to S74 are performed. Also, in this embodiment, after step S7 according to the first embodiment, step S75 is performed.

[0225] More specifically, first, referring to FIG. 12A, a semiconductor wafer source 1 made of an n- + type single-crystal SiC is prepared. Next, a part of the semiconductor element 11 is formed on the first main surface 2 of the semiconductor wafer source 1 (step S71 in FIG. 11A).

[0226] The step of forming a part of the semiconductor element 11 includes, in this embodiment, the step of forming an n-type SiC epitaxial layer 117 on the first main surface 2 of the semiconductor wafer source 1. Also, the step of forming a part of the semiconductor element 11 includes the step of forming an n-type diode region 118 and a p- + type guard region 119 in the surface layer portion of the SiC epitaxial layer 117.

[0227] In the step of forming the SiC epitaxial layer 117, SiC is epitaxially grown from the first main surface 2 of the semiconductor wafer source 1. The diode region 118 is formed using a part of the SiC epitaxial layer 117.

[0228] Next, referring to FIG. 12B, the semiconductor wafer source 1 on which a part of the semiconductor element 11 is formed is adhered to the first support member 21 (step S72 in FIG. 11A). The semiconductor wafer source 1 is adhered to the first support member 21 with the second main surface 3 facing the first support main surface 22 of the first support member 21. Thereby, the wafer adhesion structure 101 is formed. The method of adhering the semiconductor wafer source 1 to the first support member 21 is the same as that described in the first embodiment, so the description thereof will be omitted.

[0229] Next, referring to Figure 12C, laser light is irradiated from the laser light irradiation device 33 toward the semiconductor wafer source 1 (step S73 in Figure 11A). In this configuration, the laser light is irradiated from the first main surface 2 side of the semiconductor wafer source 1 toward a portion of the semiconductor wafer source 1 in the thickness direction.

[0230] In this process, no electrode layer is formed on the surface of the SiC epitaxial layer 117 on the first main surface 2 side of the semiconductor wafer source 1. Furthermore, no insulating layer is formed on the surface of the SiC epitaxial layer 117 on the first main surface 2 side of the semiconductor wafer source 1. Therefore, laser light can be irradiated into the semiconductor wafer source 1 from the first main surface 2 side of the semiconductor wafer source 1, where there are fewer obstacles.

[0231] The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the laser beam focusing section is set according to the thickness of the semiconductor device to be acquired. The distance W1 may be between 50 μm and 100 μm.

[0232] The irradiation position of the laser beam onto the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first altered layer 34 is formed in the middle of the thickness direction of the semiconductor wafer source 1, in which the crystalline state has been altered to properties different from other regions. The first altered layer 34 is n + It may be formed in the middle of the semiconductor wafer source 1 of the type.

[0233] If the semiconductor wafer source 1 has a chamfered edge, an error occurs in the focusing point of the laser beam, which may cause the first altered layer 34 to not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0234] This suppresses errors in the laser beam's focusing point. As a result, the first altered layer 34 can be formed inside the semiconductor wafer source 1 parallel to the first main surface 2 across the entire thickness of the semiconductor wafer source 1. Therefore, the semiconductor wafer source 1 can be appropriately separated (cleaved) into an element-formed wafer 41 and an element-unformed wafer 42.

[0235] Next, referring to Figure 12D, the second support member 31 is attached to the first main surface 2 of the semiconductor wafer source 1 (step S74 in Figure 11A). The second support member 31 may also be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0236] Next, referring to Figure 12E, the semiconductor wafer source 1 is cut along a horizontal direction parallel to the first main surface 2, starting from a point midway along its thickness (step S6 in Figure 11A). More specifically, the semiconductor wafer source 1 is cleaved along a horizontal direction starting from the first altered layer 34.

[0237] The cleavage of the semiconductor wafer source 1 is performed while the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having part of the semiconductor element 11, and an unformed wafer 42 that does not have the semiconductor element 11.

[0238] In the cutting process of the semiconductor wafer source 1 (step S6 in Figure 11A), the semiconductor wafer source 1 should be separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 without semiconductor elements 11. Not only in the case of cleavage as in this embodiment, but for example, the formation position and formation conditions of the first altered layer 34 may be adjusted so that the semiconductor wafer source 1 spontaneously separates into the element-formed wafer 41 and the element-unformed wafer 42.

[0239] Referring to Figure 12F, after the separation process of the semiconductor wafer source 1, the first cross-section 43 of the element formation wafer 41 is ground (step S76 in Figure 11B). The grinding process of the first cross-section 43 may be carried out by the CMP method.

[0240] The grinding step of the first cross-section 43 may be performed until the element-forming wafer 41 reaches a desired thickness. In other words, the grinding step of the first cross-section 43 may include a thinning step of the element-forming wafer 41.

[0241] Next, referring to Figure 12G, the second main surface electrode 45 is formed on the first cross-section 43 of the element formation wafer 41 (step S77 in Figure 11B). Of course, the grinding step of the first cross-section 43 may be omitted. In other words, the second main surface electrode 45 may be directly formed on the first cross-section 43 immediately after the separation step of the semiconductor wafer source 1.

[0242] After the grinding process of the element-forming wafer 41 (step S76 in Figure 11B), and prior to the formation process of the second main surface electrode 45 (step S77 in Figure 11B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element-forming wafer 41. The annealing treatment may be performed by laser irradiation. In this case, the ohmic properties of the second main surface electrode 45 with respect to the first cut surface 43 of the element-forming wafer 41 can be improved.

[0243] Next, referring to Figure 12H, the second support member 31 is removed from the first main surface 2 of the semiconductor wafer source 1 (step S78 in Figure 11B). The removal of the second support member 31 may be performed prior to the grinding of the first cut surface 43 or the formation of the second main surface electrode 45.

[0244] Next, referring to Figure 12I, the remaining portion of the semiconductor element 11 is formed on the first main surface 2 of the semiconductor wafer source 1 (step S79 in Figure 11B). In this embodiment, the insulating layer 120 and the first main surface electrode 30 are formed on the first main surface 2 of the semiconductor wafer source 1 as the remaining portion of the semiconductor element 11.

[0245] Subsequently, the element-forming wafer 41 is cut along the dicing line 12 (see also Figures 1A and 1B) (step S80 in Figure 11B). This results in multiple semiconductor devices 111 being cut out from the element-forming wafer 41.

[0246] After the separation process of the semiconductor wafer source 1, it is determined whether the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 11A). The method for determining whether the unformed wafer 42 can be reused is the same as described in the first embodiment, so the explanation is omitted.

[0247] If the unformed wafer 42 is unusable (step S7:NO in Figure 11A), the manufacturing method of the semiconductor device using one semiconductor wafer source 1 is completed.

[0248] If the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in Figure 11A: YES), then, similar to step S71, a portion of the new semiconductor element 52 is formed on the unformed wafer 42 (new semiconductor wafer source 51) (step S75 in Figure 11A).

[0249] The partial formation process of the new semiconductor element 52 (step S75 in Figure 11A) may be carried out with the new semiconductor wafer source 51 attached to the support member 21. Of course, the first support member 21 may be removed prior to the partial formation process of the new semiconductor element 52 (step S75 in Figure 11A). In this case, the support member 21 may be reattached to the new semiconductor wafer source 51 after the partial formation process of the new semiconductor element 52 (step S75 in Figure 11A).

[0250] Subsequently, step S73 is performed. In this configuration, steps S73 to S7 are repeated until the unformed wafer can no longer be reused as a new semiconductor wafer source. This manufacturing method can also achieve the same effects as those described in the first embodiment.

[0251] In this embodiment, an example in which a Schottky barrier diode is formed as an example of the semiconductor element 11 has been described. However, the semiconductor element 11 may include a functional element different from the Schottky barrier diode. As described in the first embodiment, the semiconductor element 11 may include at least one of a semiconductor rectifying element, a semiconductor switching element, or a semiconductor passive element.

[0252] Although the embodiments of the present invention have been described, the present invention can also be implemented in other forms.

[0253] In each of the above-described embodiments, the wafer bonding structure 101 shown in FIG. 13 may be employed. FIG. 13 is a cross-sectional view showing a first modification of the wafer bonding structure 101. Hereinafter, the description of the configuration corresponding to the configuration described in the first embodiment will be omitted.

[0254] Referring to FIG. 13, in the wafer bonding structure 101 according to this modification, the first wafer edge portion 5 of the semiconductor wafer source 1 has a chamfered portion. The first wafer edge portion 5 may have a C-chamfered C-chamfered portion. The first wafer edge portion 5 may have an R-chamfered R-chamfered portion.

[0255] On the other hand, the second wafer edge portion 6 of the semiconductor wafer source 1 does not have a chamfered portion. Thereby, in a state where the semiconductor wafer source 1 is supported by the first support member 21, it is possible to suppress the formation of a gap in the region between the second wafer edge portion 6 of the semiconductor wafer source 1 and the first support main surface 22 of the first support member 21.

[0256] As a result, it is possible to suppress the occurrence of an error in the condensing portion (focus) of the laser light irradiated inside the semiconductor wafer source 1. As described above, the wafer bonding structure 101 according to this modification can also achieve the same effects as those described in the first embodiment.

[0257] In each of the embodiments described above, the wafer attachment structure 101 shown in Figure 14 may be used. Figure 14 is a cross-sectional view showing a second modified example of the wafer attachment structure 101. In the following, the configurations corresponding to those described in the first embodiment will not be described.

[0258] Referring to Figure 14, in the wafer attachment structure 101 according to this modified example, a first orientation notch 71 (first marker) indicating the crystal orientation, etc., is formed on the semiconductor wafer source 1 instead of the first orientation flat 7.

[0259] The first orientation notch 71 includes a notch formed on the periphery of the semiconductor wafer source 1. The first orientation notch 71 includes a recess at the periphery of the semiconductor wafer source 1 that is recessed toward the center of the semiconductor wafer source 1.

[0260] Furthermore, in the wafer attachment structure 101 according to this modified example, a second orientation notch 72 (second marker) indicating the crystal orientation, etc., is formed on the first support member 21 instead of the second orientation flat 27.

[0261] The second orientation notch 72 includes a notch formed on the periphery of the first support member 21. The second orientation notch 72 includes a recess on the periphery of the first support member 21 that is recessed toward the central part of the first support member 21.

[0262] The second orientation notch 72 of the first support member 21 may indicate the same crystal orientation as the first orientation notch 71 of the semiconductor wafer source 1. This allows the semiconductor wafer source 1 to be attached to the first support member 21 while knowing its crystal orientation.

[0263] The second orientation notch 72 of the first support member 21 may be positionally aligned with the first orientation notch 71 of the semiconductor wafer source 1. In other words, the second orientation notch 72 may be in a position close to the first orientation notch 71 and facing the first orientation notch 71.

[0264] As a result, the crystal orientation of the semiconductor wafer source 1 and the crystal orientation of the first support member 21 coincide, making it easy to determine the crystal orientation of the semiconductor wafer source 1. This improves the convenience of handling the semiconductor wafer source 1.

[0265] As described above, the wafer attachment structure 101 according to this modified example can also achieve the same effects as those described in the first embodiment.

[0266] Of course, the semiconductor wafer source 1 may have a first orientation flat 7 while the first support member 21 has a second orientation notch 72. Alternatively, the semiconductor wafer source 1 may have a first orientation notch 71 while the first support member 21 has a second orientation flat 27.

[0267] In each of the embodiments described above, a semiconductor wafer source 1 made of Si (silicon) single crystal may be used instead of a semiconductor wafer source 1 made of SiC single crystal. In this case, the thickness T1 of the semiconductor wafer source 1 may be 100 μm or more and 1000 μm or less. The thickness T1 of the semiconductor wafer source 1 may be 500 μm or more and 800 μm or less.

[0268] When a semiconductor wafer source 1 made of Si single crystal is used, it is preferable that the first support member 21 includes a semiconductor wafer made of Si single crystal. This makes the physical properties of the first support member 21 approximately equal to the physical properties of the semiconductor wafer source 1.

[0269] The thickness T2 of the first support member 21 may be 100 μm or more and 1000 μm or less. Specifically, the thickness T2 of the first support member 21 is 500 μm or more and 800 μm or less. The thickness T2 of the first support member 21 may be equal to the thickness T1 of the semiconductor wafer source 1.

[0270] Furthermore, the description of the configuration of the first support member 21 according to the first embodiment described above also applies when the first support member 21 is made of a semiconductor wafer made of Si single crystal.

[0271] The hardness of Si is lower than that of SiC. Therefore, the difficulty of processing a semiconductor wafer source 1 made of Si single crystal is lower than the difficulty of processing a semiconductor wafer source 1 made of SiC single crystal. Thus, the same effects as those described in the first embodiment can be achieved with a semiconductor wafer source 1 made of Si single crystal.

[0272] Of course, in each of the embodiments described above, the first support member 21 may include a substrate (wafer) made of a material other than a semiconductor wafer. For example, the first support member 21 may include an insulating substrate having light transmittance. The insulating substrate may include a glass substrate or a resin substrate.

[0273] In the embodiments described above, the separation process of the semiconductor wafer source 1 using the laser light irradiation method (steps S5 and S6 in Figure 2A) was explained. However, the cutting method used in the separation process is not limited to the laser light irradiation method, as long as it can efficiently consume the semiconductor wafer source 1.

[0274] The separation step for the semiconductor wafer source 1 may include, in place of or in addition to, the laser irradiation method, at least one of the following: wire saw processing, dicing blade processing, or etching processing. Of these, the separation step for the semiconductor wafer source 1 preferably includes the laser irradiation method.

[0275] In each of the embodiments described above, after the element-unformed wafer 42 is removed from the first support member 21, a new semiconductor element 52 may be formed on the element-unformed wafer 42.

[0276] In this case, the wafer 42 without an element on which a new semiconductor element 52 is formed may be rejoined to the first support member 21 in order to perform steps S4 to S8. The wafer 42 without an element on which a new semiconductor element 52 is formed may be rejoined to a support member different from the first support member 21 in order to perform steps S4 to S8.

[0277] In each of the above-described embodiments, after the second wafer 62 without an element is removed from the first support member 21, a new semiconductor element may be formed on the second wafer 62 without an element.

[0278] In this case, the second wafer 62 without an element on which a new semiconductor element is formed may be rejoined to the first support member 21 in order to perform steps S4 to S8. The second wafer 62 without an element on which a new semiconductor element is formed may be rejoined to a support member different from the first support member 21 in order to perform steps S4 to S8.

[0279] In each of the above-described embodiments, the wafer 42 without an element may be used for purposes other than the formation of the new semiconductor element 52. The wafer 42 without an element may be reused as a support member for supporting another semiconductor wafer source. The other semiconductor wafer source may be a semiconductor wafer source having a smaller diameter and a thinner thickness than the wafer 42 without an element.

[0280] In each of the above-described embodiments, an example of manufacturing a vertical semiconductor device including the first main surface electrode 30 and the second main surface electrode 45 has been shown. However, a horizontal semiconductor device including only the first main surface electrode 30 may be manufactured. In this case, the formation process of the second main surface electrode 45 is excluded.

[0281] In each of the above-described embodiments, the formation process of the epitaxial layer 29 may be excluded. That is, a semiconductor device without the epitaxial layer 29 may be manufactured.

[0282] This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments can be combined with each other in any manner and in any form. In other words, any combination of the features shown in the first to sixth embodiments in any manner and in any form is included in the examples of the present invention.

[0283] This application corresponds to Japanese Patent Application No. 2017-119704, filed with the Japan Patent Office on 19 June 2017, and the full disclosure of this application is incorporated herein by reference.

[0284] Although embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited only by the appended claims. [Explanation of Symbols]

[0285] 1. Semiconductor wafer source 2. First main surface of semiconductor wafer source 3. Second main surface of the semiconductor wafer source 4. Sidewall of semiconductor wafer source 5. First wafer edge of semiconductor wafer source 6. Second wafer edge of semiconductor wafer source 10 Element formation region 11 Semiconductor devices 21 First support member 22 First support main surface of the first support member 23 Second main support surface of the first support member 24 Support side wall of the first support member 25 First support edge of the first support member 26 Second support edge of the first support member 34. First altered layer 41. Element Formation Wafer 42 Unformed wafers 51 New semiconductor wafer sources 52 New semiconductor devices 55 Second altered layer 61 Second element formation wafer 62 Second unformed wafer

Claims

1. n has a first impurity concentration and has a first main surface on one side and a second main surface on the other side. ＋ The process of preparing a type SiC semiconductor wafer source, A step of forming an n-type SiC epitaxial layer having a second impurity concentration lower than a first impurity concentration on the first main surface, A step of forming a semiconductor element on the surface side of the n-type SiC epitaxial layer opposite to the second main surface, The process of forming the semiconductor element is followed by the step of attaching a first main surface support member made of SiC to the surface side of the n-type SiC epitaxial layer, The aforementioned n ＋ A step of forming a modified layer extending along a horizontal direction parallel to the first main surface at a thickness position in the middle portion of a type SiC semiconductor wafer source, Along the modified layer, the n ＋ A method for manufacturing a semiconductor device, comprising the steps of separating a type SiC semiconductor wafer source into an element-forming wafer having semiconductor elements supported by the first main surface side support member and an element-unforming wafer.

2. The step of forming the modified layer is the n ＋ A laser beam is irradiated onto a type SiC semiconductor wafer source, and the n ＋ A method for manufacturing a semiconductor device according to claim 1, comprising a step of modifying the properties of a type SiC semiconductor wafer source.

3. The process of forming the modified layer is The optical aggregation portion of the laser light is the n ＋ A process of setting the thickness position in the middle portion of the type SiC semiconductor wafer source, Along the horizontal direction parallel to the first main surface, the n ＋ A method for manufacturing a semiconductor device according to claim 2, comprising the step of moving the irradiation position of the laser light on a type SiC semiconductor wafer source.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the laser light is irradiated from the second main surface side.

5. The aforementioned n ＋ A step of attaching a second main surface support member to the second main surface side of a type SiC semiconductor wafer source, In a state supported by the first main surface side support member and the second main surface side support member, the n ＋ step of separating the type SiC semiconductor wafer source, A method for manufacturing a semiconductor device according to any one of claims 1 to 4, further comprising the step of supporting the element-unformed wafer with the second main surface side support member.

6. n has a first impurity concentration and has a first main surface on one side and a second main surface on the other side. ＋ The process of preparing a type SiC semiconductor wafer source, A step of forming an n-type SiC epitaxial layer having a second impurity concentration lower than a first impurity concentration on the first main surface, A step of forming a semiconductor element on the surface side of the n-type SiC epitaxial layer opposite to the second main surface, The process of forming the semiconductor element is followed by the step of attaching a first main surface support member made of SiC to the surface side of the n-type SiC epitaxial layer, The aforementioned n ＋ A step of forming a modified layer extending along a horizontal direction parallel to the first main surface at a thickness position in the middle portion of a type SiC semiconductor wafer source, Along the modified layer, the n ＋ A step of separating a type SiC semiconductor wafer source into an element-forming wafer having semiconductor elements supported by the first main surface side support member and an element-unforming wafer, The aforementioned n ＋ A method for manufacturing a semiconductor device, comprising the step of separating a type SiC semiconductor wafer source and then grinding the separation surface of the element-forming wafer while it is supported by the first main surface side support member.

7. The step of forming the modified layer is the n ＋ A laser beam is irradiated onto a type SiC semiconductor wafer source, and the n ＋ A method for manufacturing a semiconductor device according to claim 6, comprising a step of modifying the properties of a type SiC semiconductor wafer source.

8. The process of forming the modified layer is The optical aggregation portion of the laser light is the n ＋ A process of setting the thickness position in the middle portion of the type SiC semiconductor wafer source, Along the horizontal direction parallel to the first main surface, the n ＋ A method for manufacturing a semiconductor device according to claim 7, comprising the step of moving the irradiation position of the laser light on a type SiC semiconductor wafer source.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the laser light is irradiated from the second main surface side.

10. The aforementioned n ＋ A step of attaching a second main surface support member to the second main surface side of a type SiC semiconductor wafer source, The n ＋ A process for separating the type SiC semiconductor wafer source, A method for manufacturing a semiconductor device according to any one of claims 6 to 9, further comprising the step of supporting the element-unformed wafer with the second main surface side support member.

11. n has a first impurity concentration and has a first main surface on one side and a second main surface on the other side. ＋ The process of preparing a type SiC semiconductor wafer source, A step of forming an n-type SiC epitaxial layer having a second impurity concentration lower than a first impurity concentration on the first main surface, A step of forming a semiconductor element on the surface side of the n-type SiC epitaxial layer opposite to the second main surface, The process of forming the semiconductor element is followed by the step of attaching a first main surface support member made of SiC to the surface side of the n-type SiC epitaxial layer, The aforementioned n ＋ A step of forming a modified layer extending along a horizontal direction parallel to the first main surface at a thickness position in the middle portion of a type SiC semiconductor wafer source, Along the modified layer, the n ＋ The process includes separating a type SiC semiconductor wafer source into an element-forming wafer having semiconductor elements supported by the first main surface side support member and an element-unforming wafer, The aforementioned n ＋ After separating the type SiC semiconductor wafer source, the element-less wafer is used to create a new n ＋ The process further includes a step of reusing the wafer as a SiC semiconductor source, and the reusing step is: The aforementioned n ＋ A step of attaching a second main surface support member to the second main surface side of a type SiC semiconductor wafer source, The n ＋ A process for separating the type SiC semiconductor wafer source, A method for manufacturing a semiconductor device, comprising the step of reusing the element-unformed wafer while it is supported by the second main surface side support member.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the step of reusing the wafer without formed elements is performed when the thickness of the wafer without formed elements is equal to or greater than the thickness of the wafer with formed elements.

13. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of attaching a new first main surface support member to the new n-type SiC epitaxial layer side.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of removing the second main surface support member from the element-unformed wafer before the step of attaching the new first main surface support member.

15. A method for manufacturing a semiconductor device according to any one of claims 11 to 14, comprising the step of grinding the separation surface of the wafer before the element is formed, before the step of forming the new n-type SiC epitaxial layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the separation surface of the wafer before the element is formed is ground until the arithmetic mean roughness Ra is 1 nm or less.

17. The method for manufacturing a semiconductor device according to claim 1 or 6, wherein the step of forming the semiconductor device includes the step of forming a surface electrode on the n-type SiC epitaxial layer.

18. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of performing an annealing treatment on the separation surface of the element-forming wafer before the step of forming the back electrode.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the annealing process includes a step of irradiating the separation surface of the element-forming wafer with laser light.

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