Nitride semiconductor transistor

Abstract

To provide a nitride semiconductor transistor that can improve current density. [Solution] The nitride semiconductor transistor comprises a first channel layer having a first upper surface with nitrogen polarity, a ferroelectric nitride semiconductor layer located above the first upper surface and having a second upper surface with metallic polarity, a second channel layer located above the second upper surface and having a third upper surface with metallic polarity, and a first barrier layer located above the third upper surface and having a fourth upper surface with metallic polarity.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor transistors. [Background technology]

[0002] Conventionally, high electron mobility transistors (HEMTs) with multiple channels have been proposed. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-183311 [Overview of the project] [Problems that the invention aims to solve]

[0004] In recent years, there has been a growing demand for further improvements in current density.

[0005] This disclosure aims to provide a nitride semiconductor transistor capable of improving current density. [Means for solving the problem]

[0006] The nitride semiconductor transistor of this disclosure comprises a first channel layer having a first upper surface having nitrogen polarity, a ferroelectric nitride semiconductor layer located on the first upper surface and having a second upper surface having metallic polarity, a second channel layer located on the second upper surface and having a third upper surface having metallic polarity, and a first barrier layer located on the third upper surface and having a fourth upper surface having metallic polarity. [Effects of the Invention]

[0007] According to this disclosure, current density can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a nitride semiconductor transistor according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a band structure of a nitride semiconductor transistor according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 5) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) showing a method of manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a nitride semiconductor transistor according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing an example of a band structure of a nitride semiconductor transistor according to the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A nitride semiconductor transistor according to one aspect of the present disclosure comprises: a first channel layer having a first upper surface having nitrogen polarity; a ferroelectric nitride semiconductor layer located on the first upper surface and having a second upper surface having metallic polarity; a second channel layer located on the second upper surface and having a third upper surface having metallic polarity; and a first barrier layer located on the third upper surface and having a fourth upper surface having metallic polarity.

[0011] The first upper surface of the first channel layer has nitrogen polarity, the second of the ferroelectric nitride semiconductor layer has metallic polarity, the third upper surface of the second channel layer has metallic polarity, and the fourth upper surface of the first barrier layer has metallic polarity. Therefore, the first channel layer and the second channel layer can each contain a two-dimensional electron gas. Consequently, the current density can be improved.

[0012] [2] In [1], the ferroelectric nitride semiconductor layer may include aluminum and at least one selected from the group consisting of scandium and yttrium. In this case, it is easy to obtain a large residual polarization in the ferroelectric nitride semiconductor layer.

[0013] [3] In [1] or [2], the first channel layer has a first lower surface opposite to the first upper surface, the second channel layer has a second lower surface opposite to the third upper surface, the first channel layer contains a first two-dimensional electron gas at a position closer to the first upper surface than the first lower surface, and the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface. In this case, the first two-dimensional electron gas is mainly generated by the spontaneous polarization of the ferroelectric nitride semiconductor layer, and the second two-dimensional electron gas is mainly generated by the spontaneous polarization of the first barrier layer.

[0014] [4] In [1] or [2], a second barrier layer having a fifth upper surface with nitrogen polarity is provided, and the first channel layer may be located on the second barrier layer. In this case, the second barrier layer generates a two-dimensional electron gas in the first channel layer.

[0015] [5] In [4], the first channel layer has a first lower surface opposite to the first upper surface, the second channel layer has a second lower surface opposite to the third upper surface, the first channel layer contains a first two-dimensional electron gas at a position closer to the first lower surface than the first upper surface, and the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface. In this case, the first two-dimensional electron gas is mainly generated by the spontaneous polarization of the second barrier layer, and the second two-dimensional electron gas is mainly generated by the spontaneous polarization of the first barrier layer.

[0016] [6] In any of [1] to [5], the ferroelectric nitride semiconductor layer and the second channel layer may be lattice matched. In this case, compressive strain on the second channel layer due to lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer is not generated, and the decrease in electron mobility due to compressive strain can be avoided.

[0017] [7] In any of [1] to [6], the ferroelectric nitride semiconductor layer includes a first nitride having a first lattice constant, and the second channel layer includes a second nitride having a second lattice constant, and the ratio of the first lattice constant to the second lattice constant may be 99% or more. In this case, compressive strain on the second channel layer due to lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer is less likely to occur, and a decrease in electron mobility due to compressive strain is less likely to occur.

[0018] [8] In any of [1] to [7], the ferroelectric nitride semiconductor layer is an aluminum scandium nitride layer, and in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms may be 40% or less. In this case, the aluminum scandium nitride layer is likely to have a wurtzite-type crystal structure.

[0019] [9] In [8], the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms in the aluminum scandium nitride layer may be 10% or more and 40% or less. In this case, compressive strain in the second channel layer due to lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer is less likely to occur, and a decrease in electron mobility due to compressive strain can be easily avoided.

[0020]

[10] In any of [1] to [7], the ferroelectric nitride semiconductor layer is an aluminum yttrium nitride layer, and in the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms may be 80% or less. In this case, the aluminum yttrium nitride layer is likely to have a wurtzite-type crystal structure.

[0021]

[11] In

[10] , the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms in the aluminum yttrium nitride layer may be 10% or more and 80% or less.

[0022] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In this disclosure, "plan view" means viewing the object from above. In this disclosure, the direction in which the nitride semiconductor layer is located relative to the substrate is defined as "up".

[0023] (First Embodiment) The first embodiment relates to a nitride semiconductor transistor. The nitride semiconductor transistor is, for example, a gallium nitride-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to the first embodiment.

[0024] As shown in Figure 1, the nitride semiconductor transistor 1 according to the first embodiment includes a substrate 10, a nitride semiconductor layer 120, an insulating film 30, a regrowth layer 41S, a regrowth layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0025] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is the carbon (C) polar surface.

[0026] The nitride semiconductor layer 120 includes a buffer layer 21, a channel layer 23, a ferroelectric nitride semiconductor layer 24, a channel layer 25, and a barrier layer 26. The nitride semiconductor layer 120 may have a nucleation layer between the substrate 10 and the buffer layer 21.

[0027] The buffer layer 21 is located on the substrate 10. The buffer layer 21 has a top surface 21A with nitrogen polarity. The buffer layer 21 is, for example, a gallium nitride (GaN) layer. The thickness of the buffer layer 21 is, for example, 100 nm to 2000 nm.

[0028] The channel layer 23 is located on the upper surface 21A of the buffer layer 21. The channel layer 23 has an upper surface 23A with nitrogen polarity and a lower surface 23B opposite to the upper surface 23A. The channel layer 23 has polarization directed from the lower surface 23B toward the upper surface 23A. The channel layer 23 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 23 is, for example, 5 nm to 40 nm. The conductivity type of the channel layer 23 is, for example, n-type or undoped (i-type). The channel layer 23 is an example of a first channel layer. The upper surface 23A is an example of a first upper surface, and the lower surface 23B is an example of a first lower surface. The buffer layer 21 and the channel layer 23 do not need to be distinguished.

[0029] The ferroelectric nitride semiconductor layer 24 is on the upper surface 23A of the channel layer 23. The ferroelectric nitride semiconductor layer 24 has an upper surface 24A and a lower surface 24B opposite to the upper surface 24A. The upper surface 24A has a metal polarity, and the lower surface 24B has a nitrogen polarity. The ferroelectric nitride semiconductor layer 24 has a polarization directed from the upper surface 24A toward the lower surface 24B. The ferroelectric nitride semiconductor layer 24 is, for example, a scandium aluminum nitride (ScAlN) layer. The thickness of the ferroelectric nitride semiconductor layer 24 is, for example, 5 nm or more and 40 nm or less. The composition of the ferroelectric nitride semiconductor layer 24 is, for example, Sc X Al 1-X N(0 < X ≦ 0.4). That is, in the ScAlN layer, the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms (Sc composition ratio) is more than 0% and 40% or less. The upper surface 24A is an example of the second upper surface.

[0030] The channel layer 25 is on the upper surface 24A of the ferroelectric nitride semiconductor layer 24. The channel layer 25 has an upper surface 25A having a metal polarity and a lower surface 25B opposite to the upper surface 25A. The channel layer 25 has a polarization directed from the upper surface 25A toward the lower surface 25B. The channel layer 25 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 25 is, for example, 5 nm or more and 40 nm or less. The conductivity type of the channel layer 25 is, for example, n-type or undoped (i-type). The channel layer 25 is an example of the second channel layer. The upper surface 25A is an example of the third upper surface, and the lower surface 25B is an example of the second lower surface.

[0031] The barrier layer 26 is on the upper surface 25A of the channel layer 25. The barrier layer 26 has an upper surface 26A having a metal polarity. The barrier layer 26 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 26 is smaller than the electron affinity of the channel layer 25. The bandgap of the barrier layer 26 is larger than the bandgap of the channel layer 25. The thickness of the barrier layer 26 is, for example, 5 nm or more and 40 nm or less. The composition of the barrier layer 26 is, for example, Al Y Ga 1-YN(0.15≦Y≦0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is between 15% and 55%. The conductivity type of the barrier layer 26 is, for example, n-type or undoped (i-type). Barrier layer 26 is an example of the first barrier layer. Top surface 26A is an example of the fourth top surface.

[0032] A source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 120. The recesses 40S and 40D penetrate the barrier layer 26, the channel layer 25, and the ferroelectric nitride semiconductor layer 24. The bottoms of the recesses 40S and 40D are closer to the bottom surface of the nitride semiconductor layer 120 than the top surface 23A of the channel layer 23. In other words, the recesses 40S and 40D are formed deeper than the top surface 23A of the channel layer 23. The recesses 40S and 40D may further penetrate the channel layer 23. The bottoms of the recesses 40S and 40D may be in the channel layer 23 or in the buffer layer 21.

[0033] The insulating film 30 is located on the upper surface 26A of the barrier layer 26. The insulating film 30 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 30 is, for example, 5 nm to 100 nm. An opening 30S for the source, an opening 30D for the drain, and an opening 30G for the gate are formed in the insulating film 30. The opening 30S is connected to a recess 40S, and the opening 30D is connected to a recess 40D. In a plan view, the opening 30G is located between the openings 30S and 30D. The opening 30G reaches the barrier layer 26.

[0034] The regrowth layer 41S is located within the recess 40S on top of the buffer layer 21 or the channel layer 23. The regrowth layer 41D is located within the recess 40D on top of the buffer layer 21 or the channel layer 23. The regrowth layers 41S and 41D are, for example, n-type GaN layers. The regrowth layers 41S and 41D contain germanium (Ge) or silicon (Si) as n-type impurities.

[0035] The source electrode 42S is on the regrowth layer 41S, and the drain electrode 42D is on the regrowth layer 41D. The source electrode 42S contacts the regrowth layer 41S, and the drain electrode 42D contacts the regrowth layer 41D. The source electrode 42S makes an ohmic contact with the regrowth layer 41S, and the drain electrode 42D makes an ohmic contact with the regrowth layer 41D.

[0036] In plan view, the gate electrode 43 is between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is on the insulating film 30 and contacts the barrier layer 26 through the opening 30G.

[0037] Here, an example of the band structure of the nitride semiconductor transistor 1 will be described. FIG. 2 is a diagram showing an example of the band structure of the nitride semiconductor transistor 1 according to the first embodiment. In FIG. 2, the Fermi level E F and the lower end E C of the conduction band are shown. In FIG. 2, the horizontal axis represents the depth based on the upper surface 26A of the barrier layer 26, and the vertical axis represents the energy based on the Fermi level E F . In the example shown in FIG. 2, the buffer layer 21 and the channel layer 23 are GaN layers with a total thickness of 20 nm or more, the ferroelectric nitride semiconductor layer 24 is a Sc 0.2 Al 0.8 N layer with a thickness of 5 nm, the channel layer 25 is a GaN layer with a thickness of 15 nm, and the barrier layer 26 is an Al 0.3 Ga 0.7 N layer with a thickness of 10 nm.

[0038] In nitride semiconductor transistor 1, the upper surface 23A of the channel layer 23 has nitrogen polarity, the upper surface 24A of the ferroelectric nitride semiconductor layer 24 has metallic polarity, and the lower surface 24B of the channel layer 24 has nitrogen polarity. Therefore, as shown in Figures 1 and 2, a two-dimensional electron gas (2DEG) 121 is generated near the upper surface 23A of the channel layer 23. That is, the channel layer 23 contains the two-dimensional electron gas 121 at a position closer to the upper surface 23A than to the lower surface 23B. Also, the upper surface 25A of the channel layer 25 has metallic polarity, and the upper surface 26A of the barrier layer 26 has metallic polarity. Therefore, as shown in Figures 1 and 2, a two-dimensional electron gas 122 is generated near the upper surface 25A of the channel layer 25. That is, the channel layer 25 contains the two-dimensional electron gas 122 at a position closer to the upper surface 25A than to the lower surface 25B. The two-dimensional electron gas 121 is mainly generated by the spontaneous polarization of the ferroelectric nitride semiconductor layer 24, and the two-dimensional electron gas 122 is generated by the spontaneous polarization of the barrier layer 26. The two-dimensional electron gas 121 is an example of the first two-dimensional electron gas, and the two-dimensional electron gas 122 is an example of the second two-dimensional electron gas.

[0039] Furthermore, the polarity of the nitride semiconductor layer can be determined, for example, using an annular bright-field scanning transmission electron microscope (ABF-STEM).

[0040] Next, a method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment will be described. Figures 3 to 8 are cross-sectional views showing the method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment.

[0041] First, as shown in Figure 3, a buffer layer 21, a channel layer 23, and a ferroelectric nitride semiconductor layer 24 are sequentially formed on the substrate 10, for example, by metal-organic chemical vapor deposition (MOCVD). After forming the buffer layer 21 and the channel layer 23 by MOCVD, the ferroelectric nitride semiconductor layer 24 may be formed by, for example, sputtering or electron beam epitaxy (MBE). At this point, the upper surface 21A of the buffer layer 21, the upper surface 23A of the channel layer 23, and the upper surface 24A of the ferroelectric nitride semiconductor layer 24 possess nitrogen polarity.

[0042] Next, as shown in Figure 4, the polarization direction of the ferroelectric nitride semiconductor layer 24 is reversed by applying an electric field E greater than or equal to the coelectric field of the ferroelectric nitride semiconductor layer 24. As a result, the arrangement of atoms in the ferroelectric nitride semiconductor layer 24 changes, and the upper surface 24A of the ferroelectric nitride semiconductor layer 24 acquires metallic polarity, while the lower surface 24B acquires nitrogen polarity. In addition, a two-dimensional electron gas 121 is generated near the upper surface 23A of the channel layer 23. The electric field E can be applied, for example, by irradiation with a corona charge or by applying a voltage between two electrodes (not shown). When reversing the polarization direction, the ferroelectric nitride semiconductor layer 24 may be heated to a temperature of about 500°C or less. Note that there may be a region in the ferroelectric nitride semiconductor layer 24 where the polarization has not been reversed.

[0043] Next, as shown in Figure 5, a channel layer 25 and a barrier layer 26 are sequentially formed on the ferroelectric nitride semiconductor layer 24, for example, by the MOCVD method. Then, an insulating film 30 is formed on the barrier layer 26.

[0044] Next, as shown in Figure 6, a source opening 30S and a drain opening 30D are formed in the insulating film 30, and a source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 120. The openings 30S and 30D, and the recesses 40S and 40D can be formed, for example, by reactive ion etching (RIE) or ion milling using a mask (not shown).

[0045] Next, as shown in Figure 7, a regrowth layer 41S is formed on the buffer layer 21 or channel layer 23 within the recess 40S, and a regrowth layer 41D is formed on the buffer layer 21 or channel layer 23 within the recess 40D. The regrowth layers 41S and 41D can be formed by physical vapor deposition (PVD) methods such as vapor deposition, sputtering, or MBE, or by MOCVD.

[0046] Next, as shown in Figure 8, a source electrode 42S is formed on the regrowth layer 41S, and a drain electrode 42D is formed on the regrowth layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) that constitutes the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) with an opening formed in the region where the metal layer is to be formed is used for film deposition, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0047] Next, an opening 30G for the gate is formed in the insulating film 30 (see Figure 1). The opening 30G can be formed, for example, by RIE using a mask (not shown). Next, a gate electrode 43 that contacts the barrier layer 26 through the opening 30G is formed on the insulating film 30 (see Figure 1). When forming the gate electrode 43, a metal layer is deposited using, for example, a growth mask (not shown) with an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0048] In this way, nitride semiconductor transistor 1 can be manufactured.

[0049] Furthermore, the method and timing for reversing the polarization of the ferroelectric nitride semiconductor layer 24 are not particularly limited.

[0050] (Second Embodiment) The second embodiment differs from the first embodiment mainly in the configuration of the nitride semiconductor layer. Figure 9 is a cross-sectional view showing a nitride semiconductor transistor according to the second embodiment.

[0051] As shown in Figure 9, the nitride semiconductor transistor 2 according to the second embodiment has a nitride semiconductor layer 220 instead of the nitride semiconductor layer 120.

[0052] The nitride semiconductor layer 220 includes a buffer layer 21, a barrier layer 22, a channel layer 23, a ferroelectric nitride semiconductor layer 24, a channel layer 25, and a barrier layer 26. The nitride semiconductor layer 220 may have a nucleation layer between the substrate 10 and the buffer layer 21.

[0053] The barrier layer 22 is located on the upper surface 21A of the buffer layer 21. The barrier layer 22 has an upper surface 22A with nitrogen polarity. The channel layer 23 is located on the upper surface 22A of the barrier layer 22. The barrier layer 22 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 22 is smaller than that of the channel layer 23. The band gap of the barrier layer 22 is larger than that of the channel layer 23. The thickness of the barrier layer 22 is, for example, 5 nm to 40 nm. The composition of the barrier layer 22 is, for example, Al Z Ga 1-Z N(0.15≦Z≦0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is between 15% and 55%. The conductivity type of the barrier layer 22 is, for example, n-type or undoped (i-type). The barrier layer 22 is an example of a second barrier layer. The top surface 22A is an example of a fifth top surface.

[0054] Recesses 40S and 40D penetrate the barrier layer 26, the channel layer 25, the ferroelectric nitride semiconductor layer 24, and the channel layer 23. Recesses 40S and 40D may further penetrate the barrier layer 22. The bottoms of recesses 40S and 40D may be on the barrier layer 22 or on the buffer layer 21. The regrowth layer 41S is located within recess 40S on either the barrier layer 22 or the buffer layer 21. The regrowth layer 41D is located within recess 40D on either the barrier layer 22 or the buffer layer 21.

[0055] The other components of nitride semiconductor transistor 2 are the same as those of nitride semiconductor transistor 1.

[0056] Here, an example of the band structure of nitride semiconductor transistor 2 will be described. Figure 10 shows an example of the band structure of nitride semiconductor transistor 2 according to the second embodiment. Figure 10 shows the Fermi level E F and the lower end E of the conduction band C This is shown in Figure 10. In Figure 10, the horizontal axis represents the depth relative to the upper surface 26A of the barrier layer 26, and the vertical axis represents the Fermi level E F This shows the energy relative to [a certain value]. In the example shown in Figure 10, the buffer layer 21 is a GaN layer with a thickness of 10 nm or more, and the barrier layer 22 is an Al layer with a thickness of 30 nm. 0.3 Ga 0.7 The N layer and channel layer 23 are GaN layers with a thickness of 10 nm, and the ferroelectric nitride semiconductor layer 24 is made of Sc with a thickness of 5 nm. 0.2 Al 0.8 The N layer and channel layer 25 are GaN layers with a thickness of 15 nm, and the barrier layer 26 is Al with a thickness of 10 nm. 0.3 Ga 0.7 It is assumed to be an N-layer structure.

[0057] In the nitride semiconductor transistor 2, the upper surface 22A of the barrier layer 22 has nitrogen polarity, and the upper surface 23A of the channel layer 23 also has nitrogen polarity. Therefore, as shown in Figures 9 and 10, a two-dimensional electron gas 221 is generated near the lower surface 23B of the channel layer 23. That is, the channel layer 23 contains the two-dimensional electron gas 221 at a position closer to the lower surface 23B than to the upper surface 23A. Also, the upper surface 25A of the channel layer 25 has metallic polarity, and the upper surface 26A of the barrier layer 26 also has metallic polarity. Therefore, as shown in Figures 9 and 10, a two-dimensional electron gas 222 is generated near the upper surface 25A of the channel layer 25. That is, the channel layer 25 contains the two-dimensional electron gas 222 at a position closer to the upper surface 25A than to the lower surface 25B. The two-dimensional electron gas 221 is mainly generated by the spontaneous polarization of the barrier layer 22, and the two-dimensional electron gas 222 is generated by the spontaneous polarization of the barrier layer 26. Two-dimensional electron gas 221 is an example of a first two-dimensional electron gas, and two-dimensional electron gas 222 is an example of a second two-dimensional electron gas.

[0058] The composition of the ferroelectric nitride semiconductor layer 24 is not limited. When the ferroelectric nitride semiconductor layer 24 and the channel layer 25 are lattice-matched, compressive strain on the channel layer 25 due to lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is avoided, and the decrease in electron mobility in the two-dimensional electron gas 122 or 222 due to compressive strain can be avoided.

[0059] The ferroelectric nitride semiconductor layer 24 may contain yttrium (Y) instead of scandium (Sc), or it may contain both scandium and yttrium. That is, the ferroelectric nitride semiconductor layer 24 may contain aluminum and at least one selected from the group consisting of scandium and yttrium. In this case, it is easy to obtain a large residual polarization in the ferroelectric nitride semiconductor layer 24. The ferroelectric nitride semiconductor layer 24 may further contain gallium (Ga) or indium (In). When the ferroelectric nitride semiconductor layer 24 contains gallium, the coercive field of the ferroelectric nitride semiconductor layer 24 can be lowered. The lattice constants in the a-axis direction of various nitrides are shown in Table 1.

[0060] [Table 1]

[0061] Sc contained in the ferroelectric nitride semiconductor layer 24 X Al 1-X N is an example of a first nitride, Sc X Al 1-X The lattice constant of N is an example of the first lattice constant. The GaN contained in the channel layer 25 is an example of the second nitride, and the lattice constant of GaN is an example of the second lattice constant. If the ratio of the first lattice constant to the second lattice constant is 99% or more, compressive strain on the channel layer 25 due to lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, and it is easier to avoid a decrease in electron mobility in the two-dimensional electron gas 122 or 222 due to compressive strain.

[0062] Furthermore, even if the lattice constants differ between the channel layer 23 and the ferroelectric nitride semiconductor layer 24, if the thickness of the ferroelectric nitride semiconductor layer 24 is less than or equal to the critical thickness, the interatomic distance in the ferroelectric nitride semiconductor layer 24 will be approximately the same as the interatomic distance in the channel layer 23. Therefore, if both the channel layer 23 and the channel layer 25 are GaN layers, the interatomic distance in the channel layer 25 will be approximately the same as the interatomic distance in the ferroelectric nitride semiconductor layer 24, and almost no stress due to lattice strain will act on the channel layer 25.

[0063] When the ferroelectric nitride semiconductor layer 24 is an aluminum scandium nitride layer, if the ratio of Sc atoms to the total number of Al and Sc atoms in the aluminum scandium nitride layer (Sc composition ratio) is 40% or less, the aluminum scandium nitride layer is likely to have a wurtzite-type crystal structure. If the ratio of Sc atoms is between 10% and 40%, compressive strain on the channel layer 25 due to lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, and a decrease in electron mobility in the two-dimensional electron gas 122 or 222 due to compressive strain is less likely to occur.

[0064] When the ferroelectric nitride semiconductor layer 24 is an aluminum yttrium nitride layer, if the ratio of the number of Y atoms to the total number of Al atoms in the aluminum yttrium nitride layer (Y composition ratio) is 80% or less, the aluminum yttrium nitride layer is likely to have a wurtzite-type crystal structure. If the ratio of Y atoms is between 10% and 80%, compressive strain on the channel layer 25 due to lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, and a decrease in electron mobility in the two-dimensional electron gas 122 or 222 due to compressive strain is less likely to occur.

[0065] The Sc and Y composition ratios can be measured, for example, by transmission electron microscope energy dispersive X-ray spectroscopy (TEM-EDX), secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy.

[0066] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0067] 1, 2 Nitride semiconductor transistors 10 circuit boards 21 Buffer Layer 21A, 22A, 23A, 24A, 25A, 26A Top 22 Barrier layer 23 channel layers 23B, 24B, 25B bottom surface 24 Ferroelectric nitride semiconductor layer 25 channel layer 26 Barrier layer 30 insulating film 30D, 30G, 30S aperture 40D, 40S recess 41D, 41S regrowth layer 42D drain electrode 42S Source Electrode 43 gate 120, 220 Nitride semiconductor layer 121, 122, 221, 222 Two-dimensional electron gas E electric field

Claims

1. A first channel layer having a first upper surface with nitrogen polarity, A ferroelectric nitride semiconductor layer having a second upper surface with metallic polarity, located above the first upper surface, A second channel layer having a third upper surface having metallic polarity, located above the second upper surface, A first barrier layer having a fourth upper surface with metallic polarity, located above the third upper surface, A nitride semiconductor transistor having the following characteristics.

2. The ferroelectric nitride semiconductor layer is Aluminum and At least one species selected from the group consisting of scandium and yttrium, A nitride semiconductor transistor according to claim 1, comprising:

3. The first channel layer has a first lower surface opposite to the first upper surface, The second channel layer has a second lower surface opposite to the third upper surface, The first channel layer contains a first two-dimensional electron gas at a position closer to the first upper surface than to the first lower surface. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface.

4. It has a second barrier layer having a fifth upper surface with nitrogen polarity, The nitride semiconductor transistor according to claim 1 or claim 2, wherein the first channel layer is located on the second barrier layer.

5. The first channel layer has a first lower surface opposite to the first upper surface, The second channel layer has a second lower surface opposite to the third upper surface, The first channel layer contains a first two-dimensional electron gas at a position closer to the first lower surface than to the first upper surface. The nitride semiconductor transistor according to claim 4, wherein the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface.

6. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ferroelectric nitride semiconductor layer and the second channel layer are lattice-matched.

7. The ferroelectric nitride semiconductor layer includes a first nitride having a first lattice constant, The second channel layer comprises a second nitride having a second lattice constant, The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ratio of the first lattice constant to the second lattice constant is 99% or more.

8. The ferroelectric nitride semiconductor layer is an aluminum scandium nitride layer. The nitride semiconductor transistor according to claim 1 or claim 2, wherein in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms is 40% or less.

9. The nitride semiconductor transistor according to claim 8, wherein in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms is 10% or more and 40% or less.

10. The ferroelectric nitride semiconductor layer is an aluminum yttrium nitride layer. The nitride semiconductor transistor according to claim 1 or claim 2, wherein in the aluminum nitride yttrium layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms is 80% or less.

11. The nitride semiconductor transistor according to claim 10, wherein in the aluminum nitride yttrium layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms is 10% or more and 80% or less.

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