Thin-film transistor, method for manufacturing the same, thin-film transistor substrate containing the same, and display device containing the same

Abstract

To provide thin-film transistors with improved reliability and mobility. [Solution] One embodiment of the present disclosure provides a thin-film transistor comprising a source conductive material layer and a drain conductive material layer spaced apart from each other, an active layer disposed between the source conductive material layer and the drain conductive material layer, and a gate electrode superimposed on the active layer, wherein the direction from the drain conductive material layer to the source conductive material layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, the active layer is arranged vertically in a direction not parallel to the first and second directions, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor, a method for manufacturing the same, a thin film transistor substrate including the same, and a display device including the same.

Background Art

[0002] Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is widely used as a switching element or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] Thin film transistors can be classified into amorphous silicon thin film transistors using amorphous silicon as an active layer, polycrystalline silicon thin film transistors using polycrystalline silicon as an active layer, and oxide semiconductor thin film transistors using an oxide semiconductor as an active layer, based on the material constituting the active layer.

[0004] In recent years, as the pixel density of high-resolution or mobile display devices has increased and many pixels are arranged in a narrow space, the area of thin film transistors has been decreasing. Conventionally, when reducing the area of a thin film transistor, the cost of the process increased due to the limitations of the patterning process and the etching process, and it could be vulnerable to large-area integration. In recent years, research has been continuously conducted to reduce the area of thin film transistors while solving such problems.

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of an embodiment of the present disclosure is to provide a thin film transistor having a short channel including an active layer standing at a certain angle.

[0006] Another embodiment of the present disclosure aims to provide a thin-film transistor with improved reliability and mobility, comprising source conductive material layers and drain conductive material layers having different work functions.

[0007] Another embodiment of the present disclosure aims to provide a thin-film transistor in which multiple active layers having different mobilities in the horizontal direction of the substrate are arranged to improve high junction stress (HJS).

[0008] Another embodiment of this disclosure aims to provide a thin-film transistor with reduced area.

[0009] Another embodiment of this disclosure aims to provide a thin-film transistor substrate including such a thin-film transistor.

[0010] Another embodiment of this disclosure aims to provide a display device including such a thin-film transistor. [Means for solving the problem]

[0011] One embodiment of the present disclosure for achieving the aforementioned technical challenges provides a thin-film transistor comprising a source conductive layer and a drain conductive layer spaced apart from each other, an active layer disposed between the source conductive layer and the drain conductive layer, and a gate electrode superimposed on the active layer, wherein the direction from the drain conductive layer to the source conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, the active layer is arranged vertically in a direction not parallel to the first and second directions, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

[0012] The active layer has a first surface that contacts the source conductive material layer and a second surface that contacts the drain conductive material layer, wherein the first surface and the second surface may be parallel to each other, but not parallel to the first and second directions.

[0013] The entire region of the active layer may overlap with the gate electrode.

[0014] The upper surface of the active layer, the upper surface of the source conductive material layer, and the upper surface of the drain conductive material layer can form a single plane.

[0015] The system further includes a buffer layer, the active layer being positioned on the buffer layer, and the lower surface of the active layer, the lower surface of the source conductive material layer, and the lower surface of the drain conductive material layer being in contact with the buffer layer to form a single plane.

[0016] The source conductive layer and the drain conductive layer are made of different materials, and the work function of the source conductive layer may be smaller than the work function of the gate electrode, while the work function of the drain conductive layer may be larger than the work function of the gate electrode.

[0017] The active layer includes a first active layer in contact with the source conductive material layer and a second active layer in contact with the drain conductive material layer, wherein the second active layer does not contact the source conductive material layer, and any straight line parallel to the upper surface of the active layer can pass through both the first active layer and the second active layer.

[0018] The mobility of the second active layer may be greater than the mobility of the first active layer.

[0019] The gate insulating film between the active layer and the gate electrode is further included, wherein the upper surface of the first active layer and the upper surface of the second active layer may be in contact with the gate insulating film.

[0020] The active layer further includes a third active layer between the first active layer and the second active layer. The third active layer does not contact the source conductive material layer, and any straight line parallel to the upper surface of the active layer can pass through all of the first active layer, the second active layer, and the third active layer.

[0021] The mobility of the third active layer may be greater than the mobility of the first active layer and less than the mobility of the second active layer.

[0022] It further includes a gate insulating film between the active layer and the gate electrode, and the upper surfaces of the first active layer, the second active layer, and the third active layer may contact the gate insulating film.

[0023] A groove portion is provided on the upper surface of the active layer, and the thickness of the active layer may be thinner than the thickness of the source conductive material layer and the thickness of the drain conductive material layer.

[0024] A protrusion is provided on the upper surface of the active layer, and the thickness of the active layer may be thicker than the thickness of the source conductive material layer and the thickness of the drain conductive material layer.

[0025] The upper surface of the active layer has a first length, the lower surface of the active layer has a second length, the first length is shorter than the second length, and the first length and the second length can be measured along a direction parallel to the first direction.

[0026] On a plane, at least a part of the source conductive material layer and at least a part of the drain conductive material layer may overlap the gate electrode.

[0027] Another embodiment of the present disclosure includes a base substrate, a first thin film transistor, and a second thin film transistor disposed on the base substrate. The first thin film transistor includes a first source conductive material layer and a first drain conductive material layer spaced apart from each other, a first sub-active layer disposed between the first source conductive material layer and the first drain conductive material layer, and a first gate electrode overlapping the first sub-active layer. The second thin film transistor includes a second source conductive material layer and a second drain conductive material layer spaced apart from each other, a second sub-active layer disposed between the second source conductive material layer and the second drain conductive material layer, and a second gate electrode overlapping the second sub-active layer. When the direction from the first drain conductive material layer to the first source conductive material layer is defined as the first direction and the direction perpendicular to the first direction is defined as the second direction, the first sub-active layer and the second sub-active layer are arranged upright in a direction that is not parallel to the first direction and the second direction. The maximum length of the first sub-active layer in the second direction is longer than the minimum length of the first sub-active layer in the first direction, and the maximum length of the second sub-active layer in the second direction is longer than the minimum length of the second sub-active layer in the first direction. A thin film transistor substrate is provided.

[0028] The first source conductive material layer and the second source conductive material layer are integrally formed, and the first thin film transistor and the second thin film transistor can be connected in parallel.

[0029] The first sub-active layer has a third side surface that contacts the first source conductive material layer, the second sub-active layer has a fourth side surface that contacts the second source conductive material layer, and the third side surface and the fourth side surface may not be parallel to the first direction and the second direction, respectively.

[0030] The upper surfaces of the first drain conductive material layer, the first sub-active layer, the first source conductive material layer, the second source conductive material layer, the second sub-active layer, and the second drain conductive material layer can form a single plane.

[0031] Another embodiment of the present disclosure provides a method for manufacturing a thin-film transistor, comprising the steps of: forming a buffer layer on a base substrate; forming a first metallic material layer on the buffer layer; forming an active material layer on the first metallic material layer; forming a second metallic material layer on the active material layer; performing a chemical mechanical polishing step to flatten the upper surfaces of the first metallic material layer, the active material layer, and the second metallic material layer to form a source conductive material layer and a drain conductive material layer separated from each other, and an active layer disposed between the source conductive material layer and the drain conductive material layer; forming a gate insulating film on the source conductive material layer, the drain conductive material layer, and the active layer; and forming a gate electrode on the gate insulating film, wherein when the direction from the drain conductive material layer to the source conductive material layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, the active layer is arranged vertically in a direction not parallel to the first and second directions, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

[0032] The first metal layer and the second metal layer are made of different materials, and the work function of the second metal layer may be greater than the work function of the first metal layer.

[0033] Another embodiment of the present disclosure may provide a display device including a thin-film transistor. [Effects of the Invention]

[0034] A thin-film transistor according to one embodiment of the present disclosure may include an active layer positioned at a certain angle and have a short channel.

[0035] A thin-film transistor according to another embodiment of the present disclosure can improve reliability and mobility by including a source conductive layer and a drain conductive layer having different work functions.

[0036] Another thin-film transistor according to another embodiment of the present disclosure has multiple active layers arranged horizontally on the substrate, each having different mobilities, which can improve high junction stress (HJS). [Brief explanation of the drawing]

[0037] [Figure 1] This is a plan view of a thin-film transistor according to one embodiment of the present disclosure. [Figure 2] This is a cross-sectional view of a thin-film transistor according to one embodiment of the present disclosure. [Figure 3] This is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure. [Figure 4] This is a cross-sectional view of a thin-film transistor according to yet another embodiment of the present disclosure. [Figure 5] This is a cross-sectional view of a thin-film transistor according to yet another embodiment of the present disclosure. [Figure 6] This is a cross-sectional view of a thin-film transistor according to yet another embodiment of the present disclosure. [Figure 7] This is a cross-sectional view of a thin-film transistor substrate according to yet another embodiment of the present disclosure. [Figure 8] Figure 7 is a circuit diagram of the thin-film transistor substrate shown. [Figure 9A] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the present disclosure. [Figure 9B] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9C] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9D] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9E] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9F]This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9G] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 9H] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the disclosure of the present invention. [Figure 10] This is a schematic diagram of a display device according to yet another embodiment of the present disclosure. [Modes for carrying out the invention]

[0038] The advantages and features of this disclosure, and the methods for achieving them, will become clearer by referring to an example described below in detail with accompanying figures. However, this disclosure is not limited to the example disclosed below, but can be embodied in a variety of different forms, and the example provided is merely to complete the disclosure and to fully inform those ordinary skill in the art to which this disclosure pertains. The present invention is defined solely by the claims.

[0039] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the diagrams illustrating examples of this disclosure are illustrative and not limited to those shown in the diagrams of this disclosure. Throughout the specification, the same components may refer to the same reference numerals. In explaining examples of this disclosure, if it is determined that a specific explanation of related prior art would unnecessarily obscure the essence of the application, such detailed explanation will be omitted.

[0040] Wherever "includes," "contains," etc., are used in this disclosure, other parts may be added unless "only" is used. This includes cases where a singular component includes multiple components unless otherwise explicitly stated.

[0041] In interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0042] For example, when the positional relationship between two parts is described using phrases such as "on top," "above," "below," or "next to," one or more other parts may be located between the two parts unless expressions such as "immediately" or "directly" are used.

[0043] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the diagram. Spatially relative terms should be understood as terms that include different directions in use or operation, in addition to the directions shown in the diagram. For example, if the elements shown in the diagram are flipped over, the element described as "below" or "down" of another element may be placed "above" of the other element. Thus, the exemplary term "below" may include both downward and upward directions. Similarly, the exemplary term "upper" or "upper" may include both upward and downward directions.

[0044] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it may include cases that are not continuous unless "immediately" or "directly" is used.

[0045] While terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this disclosure.

[0046] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of item 1, item 2, and item 3" could mean not just each of item 1, item 2, or item 3 individually, but all possible combinations of items that can be presented from two or more of items 1, item 2, and item 3.

[0047] The features of some of the examples in this disclosure can be combined or combined with each other, either partially or as a whole, allowing for a variety of technically interconnected and driven interactions, and each embodiment can be carried out independently of each other or in association with each other.

[0048] When adding reference numerals to the components of each figure illustrating the embodiments of this disclosure, the same components may, as far as possible, have the same reference numeral, even if they are shown in different figures.

[0049] In the embodiments of this disclosure, the source electrode and the drain electrode are distinguished only for the sake of explanation, and the source electrode and the drain electrode can be interchangeable. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Furthermore, the source electrode in one embodiment can become the drain electrode in another embodiment, and the drain electrode in one embodiment can become the source electrode in another embodiment.

[0050] In some embodiments of this disclosure, for convenience of explanation, the source region and source electrode may be distinguished, and the drain region and drain electrode may be distinguished, but the embodiments of this disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0051] Figure 1 is a plan view of a thin-film transistor 100 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view of a thin-film transistor 100 according to one embodiment of the present disclosure. Figure 3 is a cross-sectional view of a thin-film transistor 200 according to one embodiment of the present disclosure. Figure 4 is a cross-sectional view of a thin-film transistor 300 according to one embodiment of the present disclosure. Figure 5 is a cross-sectional view of a thin-film transistor 400 according to one embodiment of the present disclosure. Figure 6 is a cross-sectional view of a thin-film transistor 500 according to one embodiment of the present disclosure. Figures 2 to 6 may correspond to cross-sectional views taken along line I-I' in Figure 1.

[0052] A thin-film transistor 100 according to one embodiment of the present disclosure includes a source conductive material layer 135, a drain conductive material layer 136, an active layer 130, and a gate electrode 150, all of which are spaced apart from each other.

[0053] According to one embodiment of the present disclosure, the source conductive material layer 135, drain conductive material layer 136, active layer 130, and gate electrode 150 of the thin-film transistor 100 may be arranged on a base substrate 110.

[0054] The components of the thin-film transistor 100 are described in detail below.

[0055] Glass or plastic can be used as the base substrate 110. As the plastic, a transparent plastic with flexible properties, such as polyimide, can be used.

[0056] A light-shielding layer (not shown) may be placed on the base substrate 110. The light-shielding layer (not shown) protects the active layer 130 by blocking light incident from the base substrate 110. The light-shielding layer (not shown) may be omitted if other structures serve to block light.

[0057] According to one embodiment of the present disclosure, a buffer layer 120 can be placed on a base substrate 110.

[0058] The buffer layer 120 is insulating and protects the active layer 130. The buffer layer 120 may contain at least one of the insulating silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0059] Figure 2 shows the buffer layer 120 as a single layer, but the embodiment of this disclosure is not limited to this and can consist of multiple layers. Furthermore, another layer can be placed between the base substrate 110 and the buffer layer 120, and yet another layer can be placed between the buffer layer 120 and the active layer 130.

[0060] According to one embodiment of the present disclosure, the active layer 130 is placed on the buffer layer 120.

[0061] According to one embodiment of the present disclosure, the active layer 130 may be composed of one of the following: an oxide semiconductor material, low-temperature polycrystalline silicon (LTPS), and amorphous silicon (A-Si).

[0062] According to one embodiment of the present disclosure, a source conductive material layer 135 and a drain conductive material layer 136 can be arranged on the buffer layer 120, spaced apart from each other.

[0063] Figure 2 shows the source conductive material layer 135 and the drain conductive material layer 136 arranged apart from each other with the active layer 130 in between.

[0064] According to one embodiment of the present disclosure, the direction from the drain conductive material layer 136 to the source conductive material layer 135 can be defined as the first direction (X), and the direction perpendicular to the first direction (X) can be defined as the second direction (Y).

[0065] For example, the first direction (X) can correspond to the horizontal direction of the base substrate 110, and the second direction (Y) can correspond to a direction parallel to the straight line connecting the base substrate 110 and the gate electrode 150 at the shortest distance.

[0066] According to one embodiment of the present disclosure, the active layer 130 may be positioned vertically in a direction not parallel to the first direction (X) and the second direction (Y). Specifically, the active layer 130 may be positioned vertically in a direction not parallel to the first direction (X) and not parallel to the second direction (Y).

[0067] For example, the maximum length of the active layer 130 in the second direction (Y) may be longer than the minimum length of the active layer 130 in the first direction (X). For example, the height of the active layer 130 may be greater than the length of the active layer 130. Here, the height of the active layer 130 is measured in the second direction (Y), and the length of the active layer 130 is measured in the first direction (X).

[0068] According to one embodiment of this disclosure, the active layer 130 can be arranged vertically at a certain angle to have a short channel. As a result, the area of ​​the thin-film transistor can be reduced, and the process cost of the thin-film transistor can be reduced.

[0069] According to one embodiment of the present disclosure, the active layer 130 may have a first surface (SS1) that contacts the source conductive material layer 135 and a second surface (SS2) that contacts the drain conductive material layer 136.

[0070] For example, Figure 2 shows a configuration where the first side surface (SS1) and the second side surface (SS2) are parallel. The first side surface (SS1) refers to a surface in the active layer 130 that is in contact with the source conductive material layer 135 but is not parallel to the first direction (X). The second side surface (SS2) refers to a surface in the active layer 130 that is in contact with the drain conductive material layer 136 but is not parallel to the first direction (X). For example, the first side surface (SS1) and the second side surface (SS2) may not be parallel to the second direction (X) and the second direction (Y).

[0071] According to one embodiment of the present disclosure, the active layer 130 may overlap with the gate electrode 150. According to one embodiment of the present disclosure, at least a portion of the source conductive material layer 135 and at least a portion of the drain conductive material layer 136 may overlap with the gate electrode 150 on a planar surface. Other portions of the source conductive material layer 135 and other portions of the drain conductive material layer 136 may not overlap with the gate electrode 150.

[0072] For example, Figures 1 and 2 show how the entire area of ​​the active layer 130 overlaps with the gate electrode 150. Figure 1 shows how the entire area of ​​the active layer 130 overlaps with the gate electrode 150 on a plane.

[0073] According to one embodiment of the present disclosure, the active layer 130 may have steps.

[0074] Referring to Figure 2, the step in the active layer 130 may be a region formed by patterning the active layer 130. The step in the active layer 130 may overlap with the gate electrode 150.

[0075] According to one embodiment of the present disclosure, the active layer 130 may have an upper surface (TS1), a first side surface (SS1), a second side surface (SS2), and a lower surface (BS1).

[0076] According to one embodiment of the present disclosure, the source conductive material layer 135 may have an upper surface (TS2) and a lower surface (BS2).

[0077] According to one embodiment of the present disclosure, the drain conductive material layer 136 may have an upper surface (TS3) and a lower surface (BS3).

[0078] Referring to Figure 2, the upper surface of the active layer 130 (TS1), the upper surface of the source conductive material layer 135 (TS2), and the upper surface of the drain conductive material layer 136 (TS3) can form a single plane.

[0079] For example, the plane formed by the upper surface (TS1) of the active layer 130, the upper surface (TS2) of the source conductive material layer 135, and the upper surface (TS3) of the drain conductive material layer 136 may be parallel to the first direction (X) and may be parallel to the upper surface of the base substrate 110. For example, the upper surface (TS1) of the active layer 130, the upper surface (TS2) of the source conductive material layer 135, and the upper surface (TS3) of the drain conductive material layer 136 may be in contact with the gate insulating film 140 to form a single plane.

[0080] Referring to Figure 2, the lower surface of the active layer 130 (BS1), the lower surface of the source conductive material layer 135 (BS2), and the lower surface of the drain conductive material layer 136 (BS3) can form a single plane.

[0081] For example, the plane formed by the lower surface (BS1) of the active layer 130, the lower surface (BS2) of the source conductive material layer 135, and the lower surface (BS3) of the drain conductive material layer 136 may be parallel to the first direction (X) and may be parallel to the upper surface of the base substrate 110. For example, the lower surface (BS1) of the active layer 130, the lower surface (BS2) of the source conductive material layer 135, and the lower surface (BS3) of the drain conductive material layer 136 may be in contact with the buffer layer 120 to form a single plane.

[0082] Specifically, the plane formed by the upper surface of the active layer 130 (TS1), the upper surface of the source conductive material layer 135 (TS2), and the upper surface of the drain conductive material layer 136 (TS3) may be parallel to the plane formed by the lower surface of the active layer 130 (BS1), the lower surface of the source conductive material layer 135 (BS2), and the lower surface of the drain conductive material layer 136 (BS3).

[0083] However, the embodiment of this disclosure is not limited thereto, and due to etching differences caused by differences in the materials of the active layer 130, source conductive material layer 135, and drain conductive material layer 136, the active layer 130 may be over-etched or the etching may be insufficient (see Figures 5 and 6).

[0084] According to one embodiment of the present disclosure, the source conductive layer 135 and the drain conductive layer 136 may each contain at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, the embodiment of the present disclosure is not limited thereto.

[0085] Specifically, the source conductive layer 135 and the drain conductive layer 136 can be made of different materials. For example, the work function of the source conductive layer 135 may be smaller than that of the gate electrode 150, and the work function of the drain conductive layer 136 may be larger than that of the gate electrode 150.

[0086] For example, if the work function of the gate electrode 150 is 4.7 eV, the work function of the source conductive material layer 135 may be less than 4.7 eV, and the work function of the drain conductive material layer 136 may be greater than 4.7 eV. In other words, the work functions of the source conductive material layer 135 and the drain conductive material layer 136 can vary depending on the work function of the gate electrode 150. According to one embodiment of this disclosure, the ranges of the work function values ​​of the source conductive material layer 135 and the drain conductive material layer 136 do not overlap.

[0087] For example, if the gate electrode 150 is made of copper (Cu), the source conductive material layer 135 may contain at least one of aluminum (Al), titanium (Ti), nickel (Ni), and chromium (Cr), and the drain conductive material layer 136 may contain at least one of gold (Au) and platinum (Pt).

[0088] When the work function of the source conductive layer 135 is smaller than the work function of the gate electrode 150, carrier injection into the active layer 130 becomes easier, which can improve the current characteristics of the thin-film transistor.

[0089] Furthermore, if the work function of the drain conductive material layer 136 is greater than the work function of the gate electrode 150, carrier mobility from the active layer 130 to the drain conductive material layer 136 is improved, which can improve the current characteristics of the thin-film transistor in the ON state and potentially improve the reliability of the thin-film transistor.

[0090] Generally, in the case of thin-film transistors, conductivity may be required for electrical contact between the active layer and other components. However, process errors can occur during the conductivity process for the active layer.

[0091] This disclosure may eliminate the need for a separate conductor formation process by directly contacting the active layer 130 with the source conductive material layer 135 and the drain conductive material layer 136, thereby preventing process errors caused by the conductor formation process.

[0092] According to one embodiment of the present disclosure, a gate insulating film 140 is placed on the active layer 130. Specifically, the gate insulating film 140 is placed between the active layer 130 and the gate electrode 150.

[0093] According to one embodiment of the present disclosure, the gate insulating film 140 can cover the entire upper surface of the active layer 130. Figure 2 shows how the gate insulating film 140 covers the entire upper surface of multiple active layers 130.

[0094] The gate insulating film 140 may contain at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-film structure or a multilayer structure. The gate insulating film 140 protects the active layer 130.

[0095] According to one embodiment of the present disclosure, a gate electrode 150 can be placed on a gate insulating film 140.

[0096] According to one embodiment of the present disclosure, the gate electrode 150 may be superimposed on the active layer 130. For example, referring to Figure 2, the gate electrode 150 may be superimposed on the entire area of ​​the active layer 130.

[0097] The gate electrode 150 may contain at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys; silver-based metals such as silver (Ag) or silver alloys; copper-based metals such as copper (Cu) or copper alloys; molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). The gate electrode 150 may have a multilayer structure comprising at least two conductive films with different physical properties.

[0098] An interlayer insulating film 160 is placed on the gate electrode 150. The interlayer insulating film 160 is an insulating layer made of an insulating material. Specifically, the interlayer insulating film 160 may be made of organic material, or inorganic material, or it may be made of a laminate of an organic layer and an inorganic layer.

[0099] A source electrode 171 and a drain electrode 172 are placed on the interlayer insulating film 160. The source electrode 171 and the drain electrode 172 are spaced apart from each other and are connected to the source conductive material layer 135 and the drain conductive material layer 136, respectively. The source electrode 171 and the drain electrode 172 are connected to the source conductive material layer 135 and the drain conductive material layer 136, respectively, through contact holes formed in the interlayer insulating film 160.

[0100] The source electrode 171 and the drain electrode 172 may each contain at least one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrode 171 and the drain electrode 172 may each consist of a single layer of metal or a metal alloy, or they may consist of two or more layers.

[0101] According to one embodiment of the present disclosure, the active layer 130 may be composed of multiple layers. For example, the active layer 130 may include a first active layer 131 and a second active layer 132.

[0102] Referring to Figure 3, the first active layer 131 may be in contact with the source conductive material layer 135, and the second active layer 132 may be in contact with the drain conductive material layer 136. For example, the second active layer 132 may not be in contact with the source conductive material layer 135.

[0103] Referring to Figure 3, any straight line parallel to the top surface (TS1) of the active layer 130 in a portion of the thickness of the active layer 130 can pass through both the first active layer 131 and the second active layer 132. For example, any straight line parallel to the top surface of the base substrate 110 can pass through both the first active layer 131 and the second active layer 132.

[0104] When a gate voltage is applied to the gate electrode 150, current can flow through the path of the active layer 130 that is closer to the gate electrode 150. According to one embodiment of the present disclosure, the gate electrode 150 is located on top of the active layer 130. Therefore, when a gate voltage is applied to the gate electrode 150, current can flow through the upper region of the active layer 130, passing through both the upper regions of the first active layer 131 and the second active layer 132.

[0105] According to one embodiment of the present disclosure, the upper surface of the first active layer 131 and the upper surface of the second active layer 132 can both be in contact with the gate insulating film 140. The upper surface (TS1) of the active layer 130 may be composed of the upper surface of the first active layer 131 and the upper surface of the second active layer 132.

[0106] According to one embodiment of the present disclosure, the mobility of the second active layer 132 may be greater than the mobility of the first active layer 131. For example, the mobility of the second active layer 132 in contact with the drain conductive material layer 136 may be greater than the mobility of the first active layer 131 in contact with the source conductive material layer 135.

[0107] Generally, high junction stress (HJS) refers to the stress that occurs during carrier transfer between two distinct media within a transistor, such as between the source conductive layer 135 and the active layer 130, or between the active layer 130 and the drain conductive layer 136.

[0108] For example, when high junction stress (HJS) is applied to a thin-film transistor, a decrease in mobility may occur over time, which can degrade the current characteristics of the thin-film transistor.

[0109] When the mobility of the second active layer 132 is greater than that of the first active layer 131, carrier movement in the second active layer 132 increases, which can relieve high junction stress (HJS) in the thin-film transistor. This can improve the current characteristics of the thin-film transistor.

[0110] For example, the mobility of the first active layer 131 is 1 cm 2 / Vs~10cm 2 The range is / Vs, and the mobility of the second active layer 132 is 10cm 2 / Vs exceeds 100cm 2 / Vs may be less than or equal to this. However, the embodiments of this disclosure are not limited thereto.

[0111] According to one embodiment of the present disclosure, the active layer 130 may further include a third active layer 133 between the first active layer 131 and the second active layer 132.

[0112] Referring to Figure 4, the second active layer 132 and the third active layer 133 may not be in contact with the source conductive layer 135. For example, the first active layer 131 may be positioned between the source conductive layer 135 and the third active layer 133, and the second active layer 132 may be positioned between the third active layer 133 and the drain conductive layer 136.

[0113] Referring to Figure 4, any straight line parallel to the top surface (TS1) of the active layer 130 in a portion of the thickness of the active layer 130 can pass through all of the first active layer 131, the second active layer 132, and the third active layer 133. For example, any straight line parallel to the top surface of the base substrate 110 can pass through all of the first active layer 131, the second active layer 132, and the third active layer 133.

[0114] When a gate voltage is applied to the gate electrode 150, current can flow through the path of the active layer 130 that is closer to the gate electrode 150. According to one embodiment of the present disclosure, the gate electrode 150 is located on top of the active layer 130. Therefore, when a gate voltage is applied to the gate electrode 150, current can flow through the upper region of the active layer 130, and the current can flow through all of the upper regions of the first active layer 131, the second active layer 132, and the third active layer 133.

[0115] According to one embodiment of the present disclosure, the upper surfaces of the first active layer 131, the second active layer 132, and the third active layer 133 can all be in contact with the gate insulating film 140. The upper surface (TS1) of the active layer 130 can consist of the upper surface of the first active layer 131, the upper surface of the second active layer 132, and the upper surface of the third active layer 133.

[0116] The mobility of the third active layer 133 may be greater than that of the first active layer 131 and less than that of the second active layer 132. For example, the mobility may decrease in the order of the first active layer 131, the second active layer 132, and the third active layer 133.

[0117] According to one embodiment of the present disclosure, the upper surface (TS1) of the active layer 130 may be provided with a groove (H1). When etching the source conductive material layer 135, the active layer 130, and the drain conductive material layer 136, the active layer 130 may be over-etched due to the differences in material properties of the source conductive material layer 135, the active layer 130, and the drain conductive material layer 136. Therefore, the upper surface (TS1) of the active layer 130 may be provided with a groove (H1).

[0118] Referring to Figure 5, the shortest distance between the upper surface of the buffer layer 120 and the upper surface of the active layer 130 (TS1) may be shorter than the shortest distance between the upper surface of the buffer layer 120 and the upper surface of the source conductive material layer 135 (TS2) or the upper surface of the drain conductive material layer 136 (TS3).

[0119] For example, if the groove (H1) is provided in the active layer 130, the thickness of the active layer 130 may be thinner than the thickness of the source conductive material layer 135 and the drain conductive material layer 136. Here, the thickness can be measured along the second direction (Y).

[0120] Referring to Figure 5, the groove (H1) provided on the upper surface (TS1) of the active layer 130 can be filled with the gate insulating film 140.

[0121] According to one embodiment of the present disclosure, the upper surface (TS1) of the active layer 130 may be provided with a protrusion (H2). When etching the source conductive material layer 135, the active layer 130, and the drain conductive material layer 136, the active layer 130 may not be sufficiently etched due to differences in the material properties of the source conductive material layer 135, the active layer 130, and the drain conductive material layer 136. Therefore, the upper surface (TS1) of the active layer 130 may be provided with a protrusion (H2).

[0122] Referring to Figure 6, the shortest distance from the top surface of the buffer layer 120 to the top surface of the active layer 130 (TS1) may be longer than the shortest distance from the top surface of the buffer layer 120 to the top surface of the source conductive material layer 135 (TS2) or the top surface of the drain conductive material layer 136 (TS3).

[0123] For example, if the protrusion (H2) is provided in the active layer 130, the thickness of the active layer 130 may be greater than the thickness of the source conductive material layer 135 and the drain conductive material layer 136. Here, the thickness can be measured along the second direction (Y).

[0124] According to one embodiment of the present disclosure, the upper surface (TS1) of the active layer 130 may have a first length (L1), and the lower surface (BS1) of the active layer 130 may have a second length (L2). Referring to Figure 2, the second length (L2) may be longer than the first length (L1). In other words, the first length (L1) may be shorter than the second length (L2). For example, the first length (L1) may be in the range of 10 to 50 nm. Referring to Figure 3, the first length (L1) of the upper surface (TS1) and the second length (L2) of the lower surface (BS1) of the active layer 130 may be narrower than the width of the gate electrode.

[0125] According to one embodiment of the present disclosure, the first length (L1) of the upper surface (TS1) and the second length (L2) of the lower surface (BS1) are measured along a direction parallel to the first direction (X).

[0126] Figure 7 is a cross-sectional view of a thin-film transistor substrate 600 according to yet another embodiment of the present disclosure. Figure 8 is a circuit diagram of the thin-film transistor substrate 600 shown in Figure 7.

[0127] A thin-film transistor substrate 600 according to one embodiment of the present disclosure may include a base substrate 110, a first thin-film transistor (T1) and a second thin-film transistor (T2) disposed on the base substrate 110.

[0128] The first thin-film transistor (T1) includes a first source conductive material layer 135a, a first drain conductive material layer 136a, a first subactive layer 130a disposed between the first source conductive material layer 135a and the first drain conductive material layer 136a, and a gate electrode 151.

[0129] The second thin-film transistor (T2) includes a second source conductive material layer 135b, a second drain conductive material layer 136b, a second subactive layer 130b positioned between the second source conductive material layer 135b and the second drain conductive material layer 136b, and a gate electrode 152, all spaced apart from each other.

[0130] The explanation of the first source conductive material layer 135a and the second source conductive material layer 135b is omitted as it overlaps with the explanation of the source conductive material layer 135 in Figure 2.

[0131] The explanation of the first drain conductive material layer 136a and the second drain conductive material layer 136b is omitted because it overlaps with the explanation of the drain conductive material layer 136 in Figure 2.

[0132] The explanation for the first sub-active layer 130a and the second sub-active layer 130b is omitted because it overlaps with the explanation for the active layer 130 in Figure 2.

[0133] The explanation for the first gate electrode 151 and the second gate electrode 152 is omitted because it overlaps with the explanation for the gate electrode 150 in Figure 2.

[0134] Furthermore, the explanations for the base substrate 110, buffer layer 120, gate insulating film 140, and interlayer insulating film 160 shown in Figure 7 are omitted because they overlap with the explanation for Figure 2.

[0135] According to one embodiment of the present disclosure, the first subactive layer 130a and the second subactive layer 130b are arranged vertically in directions that are not parallel to the first direction (X) and the second direction (Y).

[0136] According to one embodiment of the present disclosure, the maximum length of the first subactive layer 130a and the second subactive layer 130b in the second direction (Y) may be longer than the minimum length of the first subactive layer 130a and the second subactive layer 130b in the first direction (X).

[0137] According to one embodiment of the present disclosure, the first source conductive material layer 135a and the second source conductive material layer 135b may be formed as a single unit. For example, referring to Figures 7 and 8, the first thin-film transistor (T1) and the second thin-film transistor (T2) may be configured in parallel. For example, the first source conductive material layer 135a of the first thin-film transistor (T1) and the second source conductive material layer 135b of the second thin-film transistor (T2) are connected in common to the source electrode 171a. For example, the first drain electrode 172a of the first thin-film transistor (T1) and the second drain electrode 172b of the second thin-film transistor (T2) are connected to the first drain conductive material layer 136a and the second drain conductive material layer 136b, respectively.

[0138] According to one embodiment of the present disclosure, the first source conductive material layer 135a is disposed between the first drain conductive material layer 136a and the second source conductive material layer 135b, and the second source conductive material layer 136a may be disposed between the second drain conductive material layer 136b and the first source conductive material layer 135a.

[0139] According to one embodiment of the present disclosure, the first subactive layer 130a may have a third surface (SS3) that contacts the first source conductive material layer 135a, and the second subactive layer 130b may have a fourth surface (SS4) that contacts the second source conductive material layer 135b.

[0140] For example, referring to Figure 7, the third side surface (SS3) and the fourth side surface (SS4) may not be parallel to each other but may have equal taper angles. For example, the third side surface (SS3) and the fourth side surface (SS4) may be arranged symmetrically with respect to the integral first source conductive material layer 135a and the second source conductive material layer 135b. For example, the third side surface (SS3) and the fourth side surface (SS4) may not be parallel to the first direction (X) and the second direction (Y), respectively.

[0141] According to one embodiment of the present disclosure, the upper surface of the first drain conductive material layer 136a (TS4), the upper surface of the first subactive layer 130a (TS5), the upper surface of the first source conductive material layer 135a (TS6), the upper surface of the second source conductive material layer 135b (TS7), the upper surface of the second subactive layer 130b (TS8), and the upper surface of the second drain conductive material layer 136b (TS9) can form a single plane.

[0142] According to one embodiment of the present disclosure, the lower surface (BS4) of the first drain conductive material layer 136a, the lower surface (BS5) of the first subactive layer 130a, the lower surface (BS6) of the first source conductive material layer 135a, the lower surface (BS7) of the second source conductive material layer 135b, the lower surface (BS8) of the second subactive layer 130b, and the lower surface (BS9) of the second drain conductive material layer 136b may form a single plane.

[0143] Figures 9A to 9H are manufacturing process diagrams for a thin-film transistor 100 according to yet another embodiment of the present disclosure. The details of the configuration already described above are omitted.

[0144] Referring to Figure 9A, a buffer layer 120 can be formed on the base substrate 110. The buffer layer 120 can be arranged over the entire base substrate 110.

[0145] Referring to Figure 9B, a first metallic material layer 135m can be formed on the buffer layer 120. The first metallic material layer 135m is formed on the buffer layer 120 by patterning. The first metallic material layer 135m may contain at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, embodiments of the present disclosure are not limited thereto.

[0146] Referring to Figure 9C, an active material layer 130m can be formed on the first metallic material layer 135m. The active material layer 130m may consist of one of the following: oxide semiconductor material, low-temperature polycrystalline silicon (LTPS), and amorphous silicon (A-Si).

[0147] The active material layer 130m is formed by patterning on the first metallic material layer 135m.

[0148] Referring to Figure 9D, a second metallic material layer 136m can be formed on the active material layer 130m. The second metallic material layer 136m may contain at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, embodiments of the present disclosure are not limited thereto.

[0149] According to one embodiment of the present disclosure, the first metallic layer 135m and the second metallic layer 136m may be composed of different materials. For example, the work function of the first metallic layer 135m may be smaller than the work function of the gate electrode 150, and the work function of the second metallic layer 136m may be larger than the work function of the gate electrode 150. For example, if the gate electrode 150 is made of copper (Cu), the first metallic layer 135m may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), and chromium (Cr), and the second metallic layer 136m may include at least one of gold (Au) and platinum (Pt).

[0150] Referring to Figure 9E, a chemical mechanical polishing (CMP) process can be performed to flatten the upper surfaces of the first metal material layer 135m, the active material layer 130m, and the second metal material layer 136m. The chemical mechanical polishing (CMP) process can form the source conductive material layer 135 and the drain conductive material layer 136, which are separated from each other, and the active layer 130 which is placed between the source conductive material layer 135 and the drain conductive material layer 136.

[0151] For example, the active material layer 130m and the second metal material layer 136m can be partially etched so that their upper surfaces become flat. The first metal material layer 135m can also be partially etched.

[0152] Referring to Figure 9F, a gate insulating film 140 can be formed on the source conductive material layer 135, the drain conductive material layer 136, and the active layer 130. The explanation of the gate insulating film 140 is omitted as it would be redundant with the previous explanation.

[0153] Referring to Figure 9G, a gate electrode 150 can be formed on the gate insulating film 140. The explanation of the gate electrode 150 is omitted as it would be redundant with the previous explanation. Figure 9G shows the gate electrode 150 positioned only on the right side of the figure.

[0154] Referring to Figure 9H, an interlayer insulating film 160, a source electrode 171, and a drain electrode 172 can be formed on the gate electrode 150. The explanation of the interlayer insulating film 160, the source electrode 171, and the drain electrode 172 is omitted as it would be redundant with the previous explanation.

[0155] Figure 10 is a schematic diagram of a display device 1000 according to yet another embodiment of the present disclosure.

[0156] A display device 1000 according to yet another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340, as shown in Figure 10.

[0157] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged in the intersection region of the gate lines (GL) and data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), data lines (DL), and pixels (P) may be arranged on the base substrate 110.

[0158] The control unit 340 controls the gate driver 320 and the data driver 330.

[0159] The control unit 340 outputs a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330, using signals supplied from an external system (not shown). The control unit 340 also samples the input video data received from the external system, rearranges it, and supplies the rearranged digital video data (RGB) to the data driver 330.

[0160] The gate control signal (GCS) includes the gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). The gate control signal (GCS) may also include control signals for controlling the shift register.

[0161] Data control signals (DCS) include source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), polarity control signal (POL), etc.

[0162] The data driver 330 supplies data voltage to the data lines (DL) of the display panel 310. Specifically, the data driver 330 converts the video data (RGB) input from the control unit 340 into analog data voltage and supplies the data voltage to the data lines (DL).

[0163] According to one embodiment of this disclosure, the gate driver 320 can be mounted on the display panel 310. This structure, in which the gate driver 320 is directly mounted on the display panel 310, is called a Gate In Panel (GIP) structure. Specifically, in a Gate In Panel (GIP) structure, the gate driver 320 can be placed on a base substrate 110.

[0164] A display device 1000 according to one embodiment of the present disclosure may include the thin-film transistors 100, 200, 300, 400, and 500 described above. According to one embodiment of the present disclosure, a gate driver 320 may include the thin-film transistors 100, 200, 300, 400, and 500 described above.

[0165] The gate driver 320 may include a shift register 350.

[0166] The shift register 350 sequentially supplies gate pulses to the gate line (GL) for one frame using a start signal and gate clock transmitted from the control unit 340. Here, one frame refers to the period during which one image is output via the display panel 310. The gate pulses have a turn-on voltage that can turn on the switching elements (thin-film transistors) placed in the pixels (P).

[0167] Furthermore, the shift register 350 supplies a gate-off signal to the gate line (GL) during the remaining period in a frame when no gate pulse is supplied, which can turn off the switching element. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the scan signal (SS or Scan).

[0168] The shift register 350 may include the thin-film transistors 100, 200, 300, 400, and 500 described above.

[0169] The present disclosure described above is not limited to the embodiments and accompanying figures described above, and it will be apparent to those ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the present disclosure. Accordingly, the scope of the present invention is indicated by the claims described below, and all modified or altered forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included within the scope of the present invention. [Explanation of Symbols]

[0170] 110: Base board 120: Buffer layer 130: Active layer 131, 132, 133: Active Layers 1, 2, and 3 130a, 130b: 1st and 2nd sub-active layers 135, 136: Source conductive material layer, drain conductive material layer 135a, 135b: First and second source conductive material layers 136a, 136b: First and second drain conductive material layers 140: Gate Insulator 150: Gate Shutdown 151, 152: 1st and 2nd gates 160: Interlayer insulating film 171, 172: Source electrode, drain electrode SS1, SS2, SS3, SS4: 1st, 2nd, 3rd, and 4th sides TS1, TS2, TS3, TS4, TS5, TS6, TS7, TS8, TS9: Upper surfaces of the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, and 9th BS1, BS2, BS3, BS4, BS5, BS6, BS7, BS8, BS9: Lower part of channels 1, 2, 3, 4, 5, 6, 7, 8, and 9 H1, H2: Groove, protrusion

Claims

1. A source conductive material layer and a drain conductive material layer separated from each other, The system includes an active layer disposed between the source conductive material layer and the drain conductive material layer, and a gate electrode superimposed on the active layer, When the direction from the drain conductive material layer to the source conductive material layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The active layer is arranged vertically in a direction not parallel to the first direction and the second direction, A thin-film transistor in which the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

2. The active layer has a first surface that contacts the source conductive material layer and a second surface that contacts the drain conductive material layer. The thin-film transistor according to claim 1, wherein the first and second sides are parallel to each other, but not parallel to the first and second directions.

3. The thin-film transistor according to claim 1, wherein the entire region of the active layer is superimposed on the gate electrode.

4. The thin-film transistor according to claim 1, wherein the upper surface of the active layer, the upper surface of the source conductive material layer, and the upper surface of the drain conductive material layer form a single plane.

5. The active layer further includes a buffer layer, and the active layer is arranged on the buffer layer. The thin-film transistor according to claim 1, wherein the lower surface of the active layer, the lower surface of the source conductive material layer, and the lower surface of the drain conductive material layer are in contact with the buffer layer to form a single plane.

6. The source conductive material layer and the drain conductive material layer are made of different materials. The work function of the source conductive material layer is smaller than the work function of the gate electrode. The thin-film transistor according to claim 1, wherein the work function of the drain conductive material layer is greater than the work function of the gate electrode.

7. The aforementioned active layer is A first active layer in contact with the source conductive material layer, It includes a second active layer that contacts the drain conductive material layer, The second active layer does not come into contact with the source conductive material layer. The thin-film transistor according to claim 1, wherein any straight line parallel to the upper surface of the active layer passes through both the first active layer and the second active layer.

8. The thin-film transistor according to claim 7, wherein the mobility of the second active layer is greater than the mobility of the first active layer.

9. The gate insulating film between the active layer and the gate electrode further comprises The thin-film transistor according to claim 7, wherein the upper surface of the first active layer and the upper surface of the second active layer are in contact with the gate insulating film.

10. The active layer further includes a third active layer between the first active layer and the second active layer, The third active layer does not come into contact with the source conductive material layer. The thin-film transistor according to claim 7, wherein any straight line parallel to the upper surface of the active layer passes through all of the first active layer, the second active layer, and the third active layer.

11. The thin-film transistor according to claim 10, wherein the mobility of the third active layer is greater than the mobility of the first active layer and less than the mobility of the second active layer.

12. The gate insulating film between the active layer and the gate electrode further comprises The thin-film transistor according to claim 10, wherein the upper surface of the first active layer, the upper surface of the second active layer, and the upper surface of the third active layer are in contact with the gate insulating film.

13. A groove is provided on the upper surface of the active layer. The thin-film transistor according to claim 1, wherein the thickness of the active layer is thinner than the thickness of the source conductive material layer and the thickness of the drain conductive material layer.

14. A protrusion is provided on the upper surface of the active layer, The thin-film transistor according to claim 1, wherein the thickness of the active layer is greater than the thickness of the source conductive material layer and the thickness of the drain conductive material layer.

15. The upper surface of the active layer has a first length, The lower surface of the active layer has a second length, The first length is shorter than the second length. The thin-film transistor according to claim 1, wherein the first length and the second length are measured along a direction parallel to the first direction.

16. The thin-film transistor according to claim 1, wherein at least a portion of the source conductive material layer and at least a portion of the drain conductive material layer are superimposed on the gate electrode on a plane.

17. Base board and The base substrate includes a first thin-film transistor and a second thin-film transistor, The first thin-film transistor is A first source conductive material layer and a first drain conductive material layer are spaced apart from each other, A first subactive layer disposed between the first source conductive material layer and the first drain conductive material layer, The first subactive layer includes a first gate electrode superimposed on the first subactive layer, The second thin-film transistor is A second source conductive material layer and a second drain conductive material layer are spaced apart from each other, A second subactive layer is disposed between the second source conductive material layer and the second drain conductive material layer, The second subactive layer includes a second gate electrode superimposed on the second subactive layer, When the direction from the first drain conductive material layer to the first source conductive material layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The first subactive layer and the second subactive layer are arranged vertically in directions not parallel to the first and second directions, The maximum length of the first subactive layer in the second direction is longer than the minimum length of the first subactive layer in the first direction. A thin-film transistor substrate in which the maximum length of the second subactive layer in the second direction is longer than the minimum length of the second subactive layer in the first direction.

18. The first source conductive material layer and the second source conductive material layer are integrally formed, The thin-film transistor substrate according to claim 17, wherein the first thin-film transistor and the second thin-film transistor are connected in parallel.

19. The first subactive layer has a third surface that contacts the first source conductive material layer, and the second subactive layer has a fourth surface that contacts the second source conductive material layer. The thin-film transistor substrate according to claim 17, wherein the third and fourth sides are not parallel to the first and second directions, respectively.

20. The thin-film transistor substrate according to claim 17, wherein the upper surface of the first drain conductive material layer, the upper surface of the first subactive layer, the upper surface of the first source conductive material layer, the upper surface of the second source conductive material layer, the upper surface of the second subactive layer, and the upper surface of the second drain conductive material layer form a single plane.

21. A process of forming a buffer layer on a base substrate, The steps include forming a first metallic material layer on the buffer layer, A step of forming an active material layer on the first metal material layer, The process of forming a second metallic material layer on the active material layer, A step of performing a chemical mechanical polishing process to flatten the upper surfaces of the first metal material layer, the active material layer, and the second metal material layer to form a source conductive material layer and a drain conductive material layer separated from each other, and an active layer disposed between the source conductive material layer and the drain conductive material layer, A step of forming a gate insulating film on the source conductive material layer and the drain conductive material layer and the active layer, The step includes forming a gate electrode on the gate insulating film, When the direction from the drain conductive material layer to the source conductive material layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The active layer is arranged vertically in a direction not parallel to the first and second directions, A method for manufacturing a thin-film transistor, wherein the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

22. The first metal material layer and the second metal material layer are made of different materials. The method for manufacturing a thin-film transistor according to claim 21, wherein the work function of the second metal material layer is greater than the work function of the first metal material layer.

23. A display device comprising a thin-film transistor according to any one of claims 1 to 16.

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