Method and system for mitigating multi-type stochastic quantum errors

Abstract

A computer implementation method is provided for mitigating errors in quantum circuits that involve the generation of at least one quantum logic operation of a quantum processor. [Solution] The method comprises computing a set of coefficients associated with a set of basis operations and obtaining a quasi-probability decomposition of a target version of the quantum logic operation on the set of basis operations. The set of basis operations includes ideal unitary basis operations and ideal non-unitary basis operations. The decomposition is computed to reach a decomposition target based on a target of use for the ideal non-unitary basis operations, and at least one of a decomposition accuracy target, a decomposition sampling overhead target, and a target of use for the ideal unitary basis operations. The quasi-probability decomposition is implemented in the quantum processor to estimate the result of a target quantum circuit in which the target version of the quantum logic operation replaces the at least one occurrence of the quantum logic operation.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 524,046, “Methods and Systems for Multi-Type Probabilistic Quantum Error Mitigation,” filed on 29 June 2023, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to the field of quantum computing, and more specifically, to the field of quantum error mitigation. [Background technology]

[0003] Quantum computers are expected to dramatically expand the range of computational problems that can be solved efficiently, and have a wide range of applications across various industrial and academic fields. However, the development of quantum computers that can realize this potential depends heavily on reducing errors, which are the difference between the actual implementation of quantum logic operations and the ideal implementation.

[0004] Certain types of errors, namely coherent errors (including stochastic coherent errors and associated subcorrelation-time coherent interactions with the environment), can be significantly reduced through quantum error suppression (QES). A key feature of QES is that it does not require significant overhead in terms of the number of qubits, circuit depth, or circuit iterations required to obtain a result up to a given statistical error (total number of "shots"). A prototypical example of QES is "dynamic decoupling," where a non-idle quantum circuit implements better quantum memory than an idle circuit. Another important example is given by "Pauli-Twiling," where a single noisy circuit is replaced by an average across noisy circuits obtained by randomly adding specific Pauli layers. Several distinct circuits must be used, but the total number of shots required is similar to that of the original circuit. In both examples of QES, all the circuits mentioned are ideally equal, i.e., identical in the absence of errors, and the effect of QES is to average out the rotated coherent errors, and therefore reduce them. Furthermore, QES may be performed by precisely characterizing coherent errors and adding small unitary gates to invert these errors.

[0005] Other types of errors, namely dissipative errors (particularly those exceeding the associated correlation time, stochastic coherent errors, and those resulting from coherent interactions with the environment), cannot be eliminated using QES, i.e., without significant resource overhead. A long-term strategy to address such errors is quantum error correction (QEC), in which quantum information is encoded into a redundant number of qubits so that errors can be measured and corrected during computation. However, known QEC schemes require the error rate to be below a very low threshold in the first place, and involve further polynomial excess overhead in terms of the number of qubits and circuit depth. Furthermore, QEC requires reliable and efficient adaptive "syndrome" measurements, including intermediate circuit measurements, non-trivial real-time classical logic for decoding the measurement results, and the ability to apply correction gates conditioned on this logic.

[0006] Recently, a family of methods to complement QEC has been developed for existing quantum processing units (QPUs) that do not yet meet the requirements of QEC. These are known as quantum error reduction (QEM) methods and require overhead in the total number of shots, but little to no overhead in the number of qubits and circuit depth. The shot overhead of QEM is known to be exponential in IF × V "total nonfiction" in noisy circuits to be reduced, where the circuit volume V is the total number of noisy gates and IF is the nonfiction per gate. Thus, while QEM is exponential in circuit volume, the shot overhead is moderate for circuits where V is up to several times 1 / IF, and this increases as the hardware improves and the nonfiction decreases. Currently, state-of-the-art QPUs have a 2-qubit gate nonfiction IF ~ 10 -3 -10 -2(and single qubit gate fidelity of lower digits). Therefore, QEM currently enables noise-free results for circuits with hundreds to thousands of two-qubit gates, approaching a volume far beyond the reach of classical simulations, which is a requirement for the advantages of quantum algorithms. QEM not only makes it possible to reduce errors on current and near-future hardware, but can also be combined with QEC to smooth the otherwise sharp transition from noisy QPUs to error-corrected QPUs as the hardware evolves.

[0007] A notable method for QEM is known as "probabilistic error cancellation" (PEC) or "quasiprobability method" (QP method). As far as the applicant knows, this is the only known QEM method that is theoretically guaranteed to produce an estimator that is unbiased with respect to the result of an ideal quantum circuit (assuming the errors are exactly known). The QP method is based on the following expression.

[0008] [Number] The ideal quantum logic operation G0 is expressed as a linear combination B = {B p} ∋ G of noisy quantum logic operations, including the noisy version G of G0, and has coefficients {c p}. Under standard assumptions, namely, assuming that both G0 and all basis elements B i are Hermitian-preserving and trace-preserving, the coefficients c p are real numbers, and Σ p c p = 1 is normalized, thus defining a quasiprobability (QP) distribution. Equation 1 is sometimes called the QP representation of the ideal operation G0 in the basis B. Note that the term "QP decomposition" is interchangeable with the term "QP representation".

[0009] Equation 1 is for the available noisy operations B pThis represents an ideal operation G0 that is unavailable as a quasi-expected value for , and the result of an ideal quantum circuit including G0 is the operation B sampled according to QP expression 1. p This can be implemented on a given QPU by substituting G with a suitable average across the results of a noise quantum circuit obtained by randomly substituting G. Assuming an error in operation B, the coefficient c i A linear equation can be set for B. Knowledge of errors in B can be obtained through detailed quantum characterization protocols such as gate-set tomography or cycle benchmarking.

[0010] The fundamental challenge in applying the QP method is constructing a basis B consisting of operations that have sufficient expressive power to mitigate all critical errors, are natively available on the QPU, and preferably have short duration and high fidelity. p An additional useful feature when it acts on a subset of qubits in an ideal circuit (e.g., single or two-qubit operations) is operation B p The fact is that they can be applied to each other and simultaneously with other gates in the circuit.

[0011] QP bases have been proposed that have sufficient expressive power to allow the reduction of any quantum operation on n qubits, and that include only layers of noisy operations G and single-qubit operations, and have been used in 2-qubit experiments. However, a practical difficulty associated with the proposed bases is that they include non-unitary operations. In particular, the proposed bases are,

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[0013] In accordance with the difficulties described above, large-scale QEM experiments utilizing the QP method do not employ non-unitary operations. Instead, these experiments rely on two-qubit Clifford gates, such as the unconditional gate CX, and employ the following mitigation strategy: All quantum circuits can be compiled on alternating layers of CX gates and single-qubit gates. Ignoring errors in single-qubit gates for errors in CX gates, which is usually a reasonable approximation, this method focuses on the CX layer. These can be Pauli-twiled, resulting in a simple Pauli error channel before (or equivalently after) the ideal gate, which is the basis.

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[0015] For the non-Clifford 2-qubit gate layer, it remains unclear how the QP method can be applied without the drawbacks of non-unitary operations. While non-Clifford 2-qubit gates can be constructed using single-qubit gates and 2-qubit Clifford gates, using natively implemented non-Clifford 2-qubit gates typically leads to a significant reduction in non-fidelity IF, which in turn leads to a potential reduction in QEM shot overhead. Indeed, the aforementioned IF reduction is why many quantum hardware manufacturers support native non-Clifford 2-qubit gates. Nevertheless, existing QP methods either require the use of non-unitary operations to mitigate non-Clifford gates or are based on highly suboptimal composite implementations that rely on Clifford gates. [Overview of the project]

[0016] As described above, state-of-the-art QP methods generally require computationally expensive methods in terms of execution time, availability, and / or noise. This disclosure provides a method that rectifies these drawbacks. The need for non-unitary computation is reduced and eliminated in some embodiments. The need for suboptimal compilation of multi-qubit gates is also reduced and eliminated in some embodiments.

[0017] This disclosure introduces “multitype” QP bases. These can be defined with respect to a restricted set S of “mitigation operations” that are desired to be used to construct QP base elements and enable optimal mitigation given this restriction. Furthermore, in numerical simulations, it is demonstrated that multitype QP bases enable efficient error mitigation in quantum circuits compiled using two-qubit non-Clifford gates without relying on non-unitary operations or on significantly noisy compilation onto two-qubit Clifford gates. In addition, a scalable algorithm for constructing multitype QP decompositions is provided, namely the coefficient c in Equation 1. pA classical algorithm is introduced, and a multitype QP basis B based on n qubits is given, whose execution time is a polynomial of n.

[0018] A multitype basis B may be defined by a user-specified set S of "mitigated operations" corresponding to a set of "simple" quantum operations available on the associated QPU, and a noisy operation G (having a target version G0). Given set S, the multitype basis B is a base element B which is a subcircuit constructed from elements of G and S. p ∈B, where each "type" corresponds to a specific subcircuit structure. In other words, different types of a multitype basis B may be defined by a specific way in which composite operations are formed from G and S. The definition of a type may depend, among other things, on the specific mitigation operations used, how the mitigation operations are combined with gate G, the number of mitigation operations used, and the order in which the mitigation operations are used. Consider a multitype basis as an example.

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[0023] The elements of S act on the same number of qubits as G. The set S may, at least ideally, be closed under multiplication (forming semigroups), and further, under inversion (forming groups). As a simple but already useful example, S may be a set of layers of single-qubit unitary gates, in particular S may be a group of Pauli layers P. Another useful example is G=G α is an element of a parameterized gate family (where parameter α may be, for example, a rotation angle), and S is an additional element G from the family. α’ Includes.

[0024] The operation G can be a single gate, a layer of gates acting in parallel, or a subcircuit containing several such layers, i.e., G = L k ...L1 may also be used. In the latter case, base element B i The set of layers L={L1,...,L k This enables a more general multi-type base that corresponds to subcircuits constructed from a set S of} and reduced operations. Each type corresponds to a subcircuit structure of the following form:

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[0026] Given a noisy circuit to be mitigated, there is freedom in decomposing it into subcircuits G into which the QP decomposition is constructed. Taking larger subcircuits (acting on a larger subset of qubits or a larger subset of layers) allows for the mitigation of errors that cannot be mitigated by smaller subcircuits. Firstly, larger subcircuits allow for more types of basis elements, thus extending to a potentially larger space of mitigable errors. Secondly, if the decomposition into subcircuits is fixed, it may become more difficult to mitigate errors involving different subcircuits, i.e., crosstalk or temporal correlation between subcircuits separated by space or time, respectively. On the other hand, multi-type QP decompositions for larger subcircuits are more difficult to construct computationally, and either the depth or width of the subcircuits (but not both) must be restricted to allow for efficient computation. In particular, constructing a QP decomposition for an entire circuit is more computationally difficult than simulating an ideal circuit, and is therefore difficult to handle for useful quantum circuits.

[0027] It is possible to have different sets S1, S2, ... for different instances of S, in this case,

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[0030] The target operation G0 may have several noisy implementations, given by the set G, in which case G and {G} in Equation 1 may be substituted with the set G.

[0031] According to a first aspect of the subject matter of this disclosure, a computer implementation method for mitigating errors in quantum circuits is provided. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor represented by G. The method is {c p This involves calculating the set of coefficients represented by {c}. p} is B={B p It is associated with a set of basis operations (sometimes called subcircuits) represented by}. The calculation of the set of coefficients is performed on the set of basis operations B using quasi-probability decomposition.

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[0033] According to embodiments of this disclosure, the implementation of quasi-probability decomposition is the set of coefficients {cp The set of base operations {B} is based on}. p This includes sampling the quantum circuit. The sampling is done to obtain at least one corresponding set of sampled operations. Sampling is performed for each of at least one occurrences of the quantum operation G in the quantum circuit. The implementation of quasi-probability decomposition further includes the step of executing the sampled set of quantum circuits on a quantum processor. The set of sampled quantum circuits is determined by substituting at least one occurrence in the quantum circuit G with one of the sampled operations from the corresponding set of sampled operations. Executing the set of sampled quantum circuits is to obtain the sampled quantum circuit results. The implementation of quasi-probability decomposition further includes the step of estimating the results of the target quantum circuit based on the sampled quantum circuit results.

[0034] In addition to the features described above, a computer implementation method for mitigating errors in quantum circuits according to this aspect of the subject matter of the present disclosure may optionally include one or more of the following features (i) to (xli) in any technically possible combination or permutation. i. Set of basis operations {B p} contains at least two base operation types. ii. Set of basis operations {B p} is a combination of multiple base operation types GS i ,S j G,S k GS l ,S m Includes at least two base operation types selected from S i ,...,S m This is an element of the set S of reduction operations. iii. The substitution of at least one generation of G in a quantum circuit is performed by substituting each generation of G with a sample from the corresponding set of basis operations. iv. Sampling is weighted

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[0039] According to a second aspect of the subject matter of this disclosure, a computer implementation method for mitigating errors in quantum circuits is provided. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor represented by G. The method is {c p This involves calculating the set of coefficients represented by {c}. p} is {B p It is associated with a set of basis operations (sometimes called subcircuits) indicated by}. The step of calculating the set of coefficients is associated with the set of basis operations {B p Quasi-probability decomposition on}

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[0041] According to one embodiment of the present disclosure, the target of using an ideal nonunitary basis operation is minimized by computing a quasi-probability decomposition, and the set of basis operations {B p} forms a multitype basis. A multitype basis is constructed from quantum logic operations G and an ideal unitary element S of a set of reduced operations. Furthermore, the target of use of ideal non-unitary basis operations is minimized by computing a set of complementary coefficients. The set of complementary coefficients is

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[0046] In addition to the above features, a computer-implemented method for reducing errors in a quantum circuit according to this aspect of the subject matter of the present disclosure may optionally include one or more of the following features (i)-(iv) in any technically possible combination or permutation. i. A set of complementary basis operations i.

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[0058] According to a third aspect of the subject matter of the present disclosure, a computer-implemented method for reducing errors in a quantum circuit is provided. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor represented by G. The method includes calculating a set of coefficients represented by {c p}. The set of coefficients {c p} is associated with a set of basis operations (sometimes called subcircuits) represented by {B p}. The step of calculating the set of coefficients is performed to obtain an exact probability decomposition p} on the set of basis operations {B

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[0062] According to a fourth aspect of the subject matter of the present disclosure, a computer - implemented method for reducing errors in a quantum circuit is provided. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor denoted by G. The method includes calculating a set of coefficients denoted by {c p}. The set of coefficients {c p} is associated with a set of base operations (which may be called a sub - circuit) denoted by {B p}. The step of calculating the set of coefficients is performed to obtain a probabilistic decomposition on the set of base operations {B p}. The probabilistic decomposition is of a target version of the quantum logic operation G denoted by G0. The quantum logic operation G is a sub - operation

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[0076] The methods according to the second, third, and fourth embodiments can be generalized. Instead of a distinction between (ideal) unitary and non-unitary operations, operations may be distinguished as "easy" and "difficult," and "easy" operations are preferred over "difficult" operations. That is, for example, it is preferable to minimize the probability of sampling a "hard" operation. The distinction between "easy" and "difficult" operations may be based, for example, on duration, fidelity, availability as a native operation, or the parallelism of the operations.

[0077] A fifth aspect of the subject matter of this disclosure provides a computer implementation method for mitigating errors in quantum circuits. The quantum circuit includes the generation of at least one quantum logic operation G of a quantum processor. The method includes implementing a quasi-probability decomposition. The quasi-probability decomposition is implemented using a basis operation that includes the quantum logic operation G and a basis operation selected from a multitype basis B.

[0078] According to one embodiment, the multi-type base B is type GS i ,Sj G,S k GS l ,S m Includes at least two types from S i ,...,S m These are elements of the set of reduced operations S. Instead of these types, or in combination with these types, the set of base operations {B p} includes a subcircuit that includes two or more occurrences G of quantum logic operations, or two or more reduction operations selected from a set S of reduction operations.

[0079] According to one embodiment, the quantum logic operation G is a sub-operation

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[0082] In any given method, the quantum operation G is not necessarily an ideal unitary operation; for example, the quantum operation G may be a state-prepared measurement (SPAM) operation.

[0083] In general, any method in any form can be used to mitigate errors in linear combinations of outputs from multiple circuits, or more generally, in functions that may require the computation of multiple circuits. Different circuits may be decomposed (preferably according to different embodiments), the decomposition may be implemented on a quantum processor, and the measurement results may then be processed to estimate the value of the function.

[0084] According to a sixth aspect of the subject matter of this disclosure, a non-temporary computer-readable storage medium for storing computer instructions is provided, which is used to cause a computer to execute the methods according to the first to fifth aspects of the subject matter of this disclosure.

[0085] According to the seventh aspect of the subject matter of this disclosure, a computer program product is provided, which, when executed by a computer, implements the methods according to the first to fifth aspects of the subject matter of this disclosure.

[0086] According to an eighth aspect of the subject matter of this disclosure, a computer system for mitigating errors in quantum circuits is provided. The computer system includes a classical processor that executes computer executable components stored in memory, and a quantum processor. The quantum processor includes at least one qubit and a measuring device. The quantum processor is configured to receive commands from the classical processor. The computer system is configured to implement the methods according to the first to fourth aspects of the subject matter of this disclosure.

[0087] According to one embodiment, a computer system is configured to read a non-temporary computer-readable storage medium disclosed in a sixth embodiment of the subject matter of this disclosure, and / or to execute a computer program product disclosed in a seventh embodiment of the subject matter of this disclosure.

[0088] According to a ninth aspect of the subject matter of this disclosure, a computer system comprising a quantum processor and a classical processor is provided. The classical processor is configured to execute computer executable components stored in memory, and the computer executable components include disassembled components and implementation components. The disassembled components are a set of basis operations {B p Quasi-probability decomposition of G0, the target version of quantum logic operations on}

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[0090] In this disclosure, the following terms and their derivatives may be understood in accordance with the following definitions: The term “unbiased estimator” may refer to a random variable X, meaning that X approximates or estimates a quantity x such that X reproduces the expected x, E[X]=x.

[0091] The term "ideal" can mean "free from implementation errors or noise." Therefore, the term "ideal unitary" can refer to a quantum operation or gate that can be represented by a unitary matrix in the absence of noise. Similarly, the term "ideal non-unitary" can refer to a quantum operation or gate that cannot be represented by a unitary matrix, even in the absence of noise.

[0092] When referring to qubits on which quantum logic operations can be applied (acted upon), these qubits may include qubits that are affected (or expected to be affected) by the operation but are not configured (intended) to be affected by the operation. Such unintended actions can result from implementation errors, particularly crosstalk errors.

[0093] The term "Pauligate" refers to the Pauli Group P nThis can refer to any gate represented by the matrix contained in, where n is the number of qubits on which the gate acts. A Pauli group is defined as a subgroup of unitary groups that include the tensor product of Pauli matrices with possible multiplication by integer powers of the imaginary unit. In the formula,

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[0095] The term "Clifford Gate" is used by the Clifford Group C. n This can refer to any gate represented by a matrix contained within, where n is the number of qubits on which the gate acts. Clifford Group C n is a group of unitary matrices that, when acted upon via a similarity transformation, map Pauli groups to themselves. In the formula,

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[0097] The term "hypergraph" can refer to a generalization of a graph in which edges can connect any number of vertices.

[0098] The notation P·Q represents a superoperator where P and Q are operators and act through left and right multiplication.

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[0100] The notation SS' can represent a set of products SS' where S and S' are (super)operators, such as S∈S, S'∈S', etc. Similarly, the notation SG can represent a set of products SG where G is a (super)operator, such as S∈S, etc. This notation is applicable to combinations of three or more operators / sets, such as SS'S''. [Brief explanation of the drawing]

[0101] Embodiments are described herein, only as non-limiting examples, with reference to the accompanying drawings, in order to better understand the subject matter disclosed herein and to illustrate how it may actually be carried out. [Figure 1] A flowchart illustrating a method for mitigating errors according to embodiments of this disclosure is shown. [Figure 2A] The characteristics of the set of quantum gates according to the embodiments of this disclosure are schematically shown. [Figure 2B] The characteristics of the set of quantum gates according to the embodiments of this disclosure are schematically shown. [Figure 3A] The characteristics of quantum logic operations and basis operations according to embodiments of this disclosure are shown. [Figure 3B] The characteristics of quantum logic operations and basis operations according to embodiments of this disclosure are shown. [Figure 3C] The characteristics of quantum logic operations and basis operations according to embodiments of this disclosure are shown. [Figure 3D] The characteristics of quantum logic operations and basis operations according to embodiments of this disclosure are shown. [Figure 3E] The characteristics of quantum logic operations and basis operations according to embodiments of this disclosure are shown. [Figure 4] Further features of the methods for mitigating errors in the embodiments of this disclosure are outlined below. [Figure 5] This flowchart shows some steps of the method according to the embodiments of this disclosure. [Figure 6]This flowchart shows a modified example of a method for mitigating errors in the embodiments disclosed herein. [Figure 7] This flowchart shows some steps of a method for reducing errors according to embodiments of the present disclosure. [Figure 8A] A graph is shown demonstrating the performance of the error reduction method according to the embodiments of this disclosure compared to error reduction methods known in the art. [Figure 8B] A graph is shown demonstrating the performance of the error reduction method according to the embodiments of this disclosure compared to error reduction methods known in the art. [Figure 9] A graph demonstrating the performance of the error reduction method according to embodiments of this disclosure is shown. [Figure 10] A computer implementing the method according to the embodiments of this disclosure is schematically illustrated. [Figure 11] A schematic diagram of a system implementing the method according to the embodiments of this disclosure is provided. [Modes for carrying out the invention]

[0102] This specification describes several examples of systems and methods useful for mitigating errors in quantum circuits.

[0103] The following detailed description includes numerous specific details to ensure a complete understanding of the subject matter. However, it will be understood by those skilled in the art that some examples of the subject matter can be carried out without these specific details. In other examples, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the subject matter of this disclosure.

[0104] As used herein, phrases such as “for example,” “etc.,” and “as an example,” and variations thereof, describe non-limiting embodiments of the subject matter of this disclosure.

[0105] In this specification, references to “one example,” “several examples,” “another example,” “other examples,” “one instance,” “several examples,” “another example,” “another example,” “one case,” “several cases,” “another case,” “other cases,” or variations thereof, mean that a particular feature, structure, or characteristic described is included in at least one example of the subject matter, but the appearance of the same term does not necessarily refer to the same example.

[0106] For clarity, certain features, structures, and / or properties disclosed herein, described in the context of separate examples, may be provided in combination in a single example. Conversely, various features, structures, and / or properties disclosed herein, described in the context of a single example for brevity, may be provided separately or in any appropriate partial combination.

[0107] Unless otherwise specified, as will be apparent from the following descriptions, any use of terms such as “calculate,” “determine,” “execute,” “implement,” “use,” and “perform” throughout this specification may refer to actions and / or processes of any combination of software, hardware, and / or firmware. For example, these terms may, in some cases, refer to actions and / or processes of a programmable machine that manipulate and / or convert data, which is represented as a physical quantity such as an electronic quantity in the registers and / or memory of the programmable machine, into other data, which is similarly represented as a physical quantity in the memory, registers, and / or other such information storage, transmission, and / or display elements of the programmable machine.

[0108] mathematical form Quantum operation G0 (G has a noisy version) and B in Equation 1 p It can be described as a superoperator that maps density operators (which describe quantum states) to density operators. In particular, such a superoperator is Hermitian-conserved, and therefore 4 n ×4 nThese matrices can also be represented by a real sequence of n, where n is the number of qubits. These matrices can be explicitly described, for example, in terms of Pauli bases.

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[0112] For noisy gates G, all errors to be mitigated are considered in contrast to, for example, the number of qubits on which G0 nontrivially acts. For example, suppose G0 is a two-qubit gate acting on qubits q1 and q2, and suffers from a crosstalk error coupling q2 to qubit q3. In this case, the noisy gate G acts on n=3 qubits, and a three-qubit QP decomposition may be required to mitigate the latter crosstalk error. Similarly, assume that

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[0114] Sampling overhead and QP resolution accuracy Given an "ideal" quantum circuit including the desired but unavailable ideal operation G0 and the QP decomposition in Equation 1, error mitigation allows G0 to be used as an available, noisy operation B. p Substitute with, probability w p =|c p Randomly sample with | / W and apply the "QP norm" W=||c||1=Σ to the corresponding circuit result. p |c p | and sign s p =sgn(c p This can be done by multiplying by ). Averaging over N such permutations gives an unbiased estimator for the "ideal" circuit result, but the limit obtained by running a single noisy circuit N times (shots) is

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[0117] coefficient c p The positive and negative parts,

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[0121] The last equation is the QP norm W, and therefore the sampling overhead is negative W. - Related to the QP norm W or W 2 These terms are often used interchangeably in literature to refer to closely related quantities.

[0122] Equation 1 shows the W (entanglement) non-fidelity IF between a noisy G and an ideal G0. e (G) = IF e It can be shown that (G,G0)∈[0,1] implies overhead nonfiction.

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[0124] "Entanglement misfiring" is,

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[0127] The QP norm W is multiplicative, and therefore this method is V of G0. G When applied to an ideal circuit with instances, the overall QP norm is

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[0132] An accurate implementation of the ideal gate G0 is a very strict requirement and is an approximate QP representation.

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[0135] Equation 3.2 is also applicable when intentionally partially removing noise or adding noise, as it may be relevant when using QP decomposition with various QEM methods such as zero-noise extrapolation, Clifford or free fermion data regression, error detection, symmetric-based post-selection, or multiple voting. When adding noise, IF e (G QP )>IF e If (G), the overhead non-fidelity limit is less than the trivial limit W≧1, meaning that noise addition, as opposed to noise removal, can be performed without sampling overhead. Thus, the methods disclosed herein are directly applicable to any target quantum logic operation and any target quantum circuit (whether noise reduction, noise amplification, noise shaping, etc.) and not only to the desired ideal quantum logic operation. In other words, the methods disclosed herein are applicable to any desired quantum logic operation and any desired quantum circuit. For convenience and brevity, this disclosure refers to an example where the ideal quantum logic operation is the target quantum logic operation, implying a generalization to any target quantum logic operation.

[0136] The main challenges in error mitigation using the QP method are constructing a QP basis and a corresponding representation that minimizes both inaccuracy and sampling overhead as much as possible, and, when minimizing both is impossible, prioritizes them according to a given specification. Generally speaking, good accuracy requires that the basis B extends to a sufficiently large subspace within the space of the superoperators required. To identify the required subspace, a noisy gate is used, which is the ideal gate multiplied by a pre-error, i.e.,

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[0143] The condition number of basis B (viewed as a matrix where the columns are vectorized basis elements) determines the efficiency of B' over the space of mitigable errors and controls the sampling overhead according to the QP norm W. Generally speaking, a larger condition number means a larger W. As an example of basis B' in the multitype case, Equation 2 can be rephrased as follows:

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[0146] An example of a basis for this subspace is given as follows:

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[0151] The applicants have found that the QP method can be improved in accordance with the subject matter of this disclosure. In some embodiments disclosed in more detail herein, the improved QP method may be referred to as a “multi-type QP” method. In some embodiments, as described in more detail herein, the improved QP method can reduce the use of (ideal) non-unitary and multi-qubit operations. In some embodiments, the improved QP method can replace the use of non-unitary and multi-qubit operations with a QP basis that includes subcircuits having multiple types of subcircuit structures.

[0152] Figure 1 shows a flowchart illustrating steps of a broad embodiment of a computer implementation method 100 for mitigating errors in quantum circuits according to embodiments of the present disclosure. The quantum circuit may include at least one occurrence of a quantum logic operation G of a quantum processor. The quantum logic operation G may be noisy, i.e., may deviate from the intended ideal operation G0. This deviation is a coherent error (e.g.,

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[0156] Note that the base operation type can follow the expression given in Equation 5. That is, the base operation type may include the following:

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[0158] The use of multiple basis operation types can, advantageously, allow for the avoidance of using resource-intensive operations in decomposition. For example, the use of (ideal) non-unitary operations such as reset operations or intermediate circuit measurements can be advantageously avoided or reduced. The absence of such resource-intensive operations can be compensated for by multiple basis operation types, providing operations that extend linearly across equivalent or similar subspaces within the space of quantum operations. Furthermore, the suboptimal compilation of multi-qubit non-Clifford gates to multi-qubit Clifford gates and single-qubit gates can be avoided.

[0159] Union of quantum operations

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[0161] The decomposition 120 may be calculated to reach the decomposition target 130. The decomposition target may be based on a decomposition accuracy target, a decomposition sampling overhead target, or both targets. In other words, the decomposition accuracy target may include the condition that the decomposition accuracy can remain below (cannot exceed) a predefined accuracy threshold ε. Alternatively, or in conjunction with, the decomposition sampling overhead target may include the condition that the decomposition sampling overhead can remain below (cannot exceed) a predetermined sampling overhead threshold η. In some embodiments, the decomposition sampling overhead target may include the condition that the quasi-probability norm can be below a predetermined sampling overhead threshold η, i.e., W ≤ η.

[0162] Method 100 may include a step 140 for implementing quasi-probability decomposition on a quantum processor. Step 140 for implementing quasi-probability decomposition may be for estimating the result of an ideal quantum circuit in which an ideal version G0 of a quantum logic operation G replaces at least one occurrence of the quantum logic operation G. Specifically, step 140 for implementing quasi-probability decomposition may preferably be for estimating the result of a quantum circuit in which G0 replaces G for each occurrence of G in the quantum circuit. Step 140 for implementing quasi-probability decomposition is for a set of basis operations {B p This may include performing quantum logic operations on the quantum processor included in (121).

[0163] In some embodiments, step 140 of implementing quasi-probability decomposition involves a set of basis operations {B p This may include randomly sampling operations from}(121). The set of basis operations {B p The step of sampling}(121) may involve computing a set (i.e., a list) of operations, which may be selected from a set of basis operations. This set (list) of operations may include several occurrences of the same basis operation. Sampling is done by sampling a set of coefficients {c p} may be based on a probability distribution defined by probabilities or weights. In some embodiments, sampling may be based on a probability distribution defined by probabilities or weights.

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[0165] In some embodiments, method 100 may include calculating the statistical error of the estimated ideal calculation result.

[0166] In some embodiments, method 100 may include a step of characterizing errors (not shown). The error characterization step may include obtaining error characterization in the quantum logic operation G in order to find an error model of the quantum logic operation G. In other words, the quantum logic operation G can be characterized in order to find out how it deviates from the ideal version G0. The characterization step is based on the basis operation {B p To find the error model of} (at least one of them), we use the basis operation {B p This may include obtaining a characterization of an error in at least one of the base operations {B}. p The characterization of at least one of the}(quantum logic operations G, base operations {B}) may involve obtaining an error characterization in at least one mitigation operation within the set S. p Characterization of errors in the} or mitigation operation S may be necessary when these error models are not known with sufficient detail or precision, for example, when the quantum processor has not yet been (sufficiently) characterized, or when it is suspected that the noise in the processor has changed for the latest characterization, for example, due to naturally occurring fluctuations or drift, or technical changes such as recalibration. The characterization step may utilize characterization protocols such as randomized benchmarking, cycle benchmarking, process tomography, state tomography, measurement tomography, or gate set tomography. In some embodiments, characterization may include training coefficients of the QP decomposition, i.e., a noise model may be found using an iterative process of refining candidate models. The iterative process may use techniques such as machine learning tools, and a known result noise-sensitive circuit may be used. A known result noise-sensitive circuit may be called a training circuit or characterization circuit.

[0167] Method 100 is the corresponding ideal version

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[0175] Figure 2A shows further characteristics of the set of mitigation operations S210 in some embodiments of the present disclosure. In some embodiments, the set of mitigation operations S210 may exclude intermediate circuit measurements 215. In some embodiments, the set of mitigation operations S210 may exclude adaptive operations 217. Adaptive operations 217 are quantum gates controlled by classical logic applied to the results of intermediate circuit measurements. For example, a reset operation is a classically controlled X π It may also be implemented by gates, and after the intermediate circuit measurement of that qubit in computation, the result of the measurement is

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[0177] Figure 2B shows further characteristics of the reduction calculation S and sets S1,...,S5 in some embodiments of the present disclosure. In some embodiments, at least one of sets S1,...,S5 is about 10 nOr it may include more than 240 elements (different operations). Here, we assume that n is the number of qubits on which G acts. This includes the qubits on which G acts nontrivially, and additional qubits on which G is known or assumed to act unintentionally due to noise (i.e., crosstalk). Preferably, about 10 n Or, elements beyond that may be linearly independent. Preferably, each set S1, ..., S5 is about 10 n Or it may have elements beyond that. As described above, in some embodiments, ideal non-unitary operations and multi-qubit operations may be excluded from sets S1,...,S5. Thus, when G is applied to a single qubit, the operations included in each of sets S1,...,S5 may extend to a vector space of up to 10 dimensions instead of the entire 16-dimensional space of single-qubit quantum operations. For two or more qubits, the dimension is 16 n Instead, up to 10 n This can be done. In some embodiments, at least one of the sets S1,...,S5 may have linearly dependent elements, i.e., it may extend to a vector space with dimensions smaller than the number of elements 245. Note that the linear dependency is defined with respect to the superoperator, as described above. Having the linearly dependent sets S1,...,S5 allows the same reduced operation

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[0181] Figures 3A-3E show, in some embodiments of this disclosure, a set of quantum logic operations G and a set of basis operations {B}. p} shows further features that can be assumed. Referring to Figure 3A, in some embodiments, the quantum logic operation G305 may also be a layer of gates that act on a set of non-overlapping qubits (i.e., quantum gates that can be compiled to act in parallel), for example, a 2-qubit gate

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[0186] Referring to Figure 3B, in some embodiments, the ideal version of the quantum logic operation G0310 is a non-Clifford gate 315, i.e., the unitary operator representing the gate cannot be included in Clifford group 316. As shown above, Clifford group C nA Pauli group is a group of unitary matrices that map a Pauli group to itself when acting through a similarity transformation. A Pauli group P on n qubits is the tensor product of four single-qubit Pauli matrices (including identity). n The "Paulist Ring" P s This is a group of matrices generated by a set of elements. The elements of a Pauli group are Pauli rings up to a phase of ±i or ±1.

[0187] Referring to Figure 3C, in some embodiments, the set of basis operations {B p} is a subcircuit B constructed from any number of generation and any number of reduction operations S selected from a set of quantum logic operations G. p This may include, that is, types or subcircuit structures having two or more occurrences of quantum logic operations G or two or more reduced operations, which are not of the type described above (i.e., not of the type shown in Figure 1). For example, basis operation 352 may consist of two consecutive applications of quantum logic operations G preceded by an operation from set S. Basis operation 354 consists of two consecutive applications of an operation from set S, followed by an application of quantum logic operations G from set S, and in yet another example, basis operation (not shown) may consist of two consecutive applications of reduced operations included in set S. In some embodiments, subcircuit B pSubcircuits can be limited in size by requiring that certain metrics of the subcircuit, such as the depth or volume of the subcircuit, be below a predetermined threshold. Subcircuit depth can be defined as the number of layers within the subcircuit, and subcircuit volume can be defined as the total number of gates within the subcircuit. For example, assuming that each operation in the figure corresponds to a single layer, subcircuit 352 has a depth of 3 and subcircuit 354 has a depth of 4. Certain characteristics of the layers or gates may be incorporated into these metrics; for example, only multi-qubit gates or layers of multi-qubit gates may be counted. For example, if the reduced operations in S are layers of single-qubit gates that are ignored in the definition of depth, and G contains one multi-qubit operation, then subcircuit 354 has a depth of 2 and subcircuit 352 has a depth of 1.

[0188] Referring to Figure 3D, in some embodiments, the quantum logic operation G360 is a subcircuit given by a sequence of suboperations, i.e.,

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[0196] It should be noted that in some embodiments, the quantum logic operation G360 may consist of a single sub-operation (e.g., an operation natively available for the QPU). If the quantum logic operation G360 includes any two sub-operations ξ1, ξ2 that can be operated in parallel, then the combined operation

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[0199] Twiling and restricted Pauli Twiling Assuming that both the mitigation operations in operations G and S are (ideally) unitary, the multitype basis constructed from G and S is the error generator L b This does not allow for efficient mitigation of non-unitary or trace-non-preserving errors contained within (see Equation 5). More generally, the selected basis B may not be able to (efficiently) extend to the space of all n-qubit superoperators, resulting in certain types of errors that cannot be (efficiently) mitigated. In this scenario, it is useful to limit the noise channels to be mitigated, which is generally done by "twiling" the noisy gates. In some embodiments, the quantum logic operation G320 may be twiling. Mathematically speaking, twiling can be thought of as "averaging across group actions," which will be further detailed below.

[0200] Superoperator representation of subgroup G⊆U(n)

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[0207] When twiling with the Pauli group, that is, G=P n In this case, the Twiling operation tw is performed in both the Pauli and Choi bases for the superoperator. p (A) is a Pauli channel, i.e., a diagonal superoperator. The Pauli base is

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[0228] Here, the generator Q∈P s n-qubit Pauli rotation gate G0=R Q Considering (α), the operator e iαQ / 2 This is the corresponding superoperator. For α that is not a multiple of π / 2, the ideal gate G0 is non-Clifford,

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[0240] Therefore, gate R ZZ (α) Twilight commutator P ZZWhen twilting, it creates an X-shaped forward error.

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[0243] Generalizing the above example, consider any (ideal unitary) 2-qubit gate G that is generally non-Clifford. In the absence of noise, the gate can be described with respect to its "KAK decomposition".

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[0252] General P Q The twilled super operator takes the form of a 4x4 block diagonal.

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[0256] In particular, the above example of twilling a noisy gate G can, of course, be incorporated into the QP method and is essentially "free" in terms of sampling overhead. More generally, this applies to any twilling of G, which can be broadly defined as replacing a single noisy operation G with a probability distribution (see expected value).

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[0262] As explained above, the implementation form of Twiling is shown in Figure 3E. It is an ideal unitary, and the set of gates {g} forms group (subgroup of unitary group) 330. j} may be combined with quantum logic operations G320 to form a set of intermediate operations 325. In some embodiments, a set of gates {g j} can be interchangeable with quantum logic operation G320 and 335. Intermediate operation 325 is set {g j A quantum logic operation G320 may be preceded by a gate from} and succeeded by the inverse (Hermitian conjugate) of the gate preceding the quantum logic operation G320. In other words, a set of intermediate operations 325 can be represented by a set of similar transformations of quantum logic operations G320, and the transformation matrices can form subgroups of unitary groups. Probability a j This is the Twiling operation G tw Each intermediate operation 340 that defines may be assigned to each base operation Bp In this case, the quantum logic operation G320 is the corresponding QP coefficient {c p a j}Base operation {B p,j The probability a of forming a modified set of} j Intermediate operations having

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[0264] From a different perspective, the set of 325 intermediate operations is the set of base operations {B p As can be seen in {B}, it can be combined (by recompilation) with a set of "raw" base operations. From this perspective, Twiling can be combined with a set of base operations {B}. p This can be seen as part of the method of constructing}.

[0265] Calculation of multi-type QP decomposition Figure 4 shows the selected multitype basis {B p Decomposition coefficient for} {c pThe characteristics of the calculation of} are shown. When tracking the decomposition target 410, the calculation may include the constraint that the sum of the coefficients may be equal to 1, thereby allowing the decomposition to be trace-preserved 420. The calculation may include calculating a quasi-probability norm 430. Calculating the quasi-probability norm 430 may be for calculating the decomposition sampling overhead. The step of calculating the decomposition sampling overhead may be for satisfying the decomposition sampling overhead target. The calculation may include optimizing the trade-off between precision and the quasi-probability norm 440, i.e., minimizing a cost function that may depend on the quasi-probability norm and precision. In some embodiments, the step of optimizing the trade-off may include optimizing the decomposition precision by solving a least-squares problem. In some embodiments, the step of optimizing the trade-off may include minimizing the sampling overhead by solving a linear program. The calculation may include calculating a distance measure 450 between the decomposition and an ideal version of the quantum logic operation G0. Exemplary distance measures that can be used to define the precision of resolution include non-fidelity 460, Frobenius distance 470, Diamond distance 480, or l p This includes, but is not limited to, operator norm 490.

[0266] Figure 5 shows the decomposition coefficient {c} in some embodiments. p A flowchart detailing algorithm 500, which can be used to calculate}, is shown. The input to the algorithm 505 is the pre-error generator.

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[0270] Below, we will discuss the fixed multitype basis {B p Noisy operations

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[0275] The least squares problem described above is that the vector space of the superoperator on n qubits is 16 n Because it is dimensional, it can only be solved directly for a small number of qubits. poly(n) complexity, extended L b To obtain the following least squares problem, which has L, several selected orders may be used. b Assuming locality, the resulting superoperator becomes an element of a poly(n)-dimensional subspace.

[0276] For example, development to the first stage may be considered.

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[0290] To show the complexity poly(n) of the least-squares problem in Equation 11, the error generator L b may be assumed to be r-local, that is, it may be assumed to be the sum of k < r quantum-bit terms, and each term acts on the tensor product with the identity on a subset of n - k quantum bits. The set of quantum bits on which the k-qubit superoperator A acts non-trivially may be called the support of A and may be denoted by supp(A). The set of r-local superoperators is poly(n)-dimensional

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[0295] r-localL b The assumption holds, and the expansion is a linear equation (Equation 11), and the basis

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[0304] Algorithm 500 may include a step 530 for generating data for the least squares problem. The Choi basis (obtained in step 520 for constructing the set of basis vectors) is orthonormal in the Hilbert-Schmidt inner product. Thus, equation 11 can be rewritten as follows:

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[0310] If r-local is not assumed, or

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[0314] Algorithm 500 may include a step of calculating the singular value decomposition (SVD) of matrix M535. Algorithm 500 may also include a step 540 of solving the least squares problem equation 12.

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[0318] The matrix M may have a non-trivial kernel ker(M), i.e., it is one or more singular values ​​that are equal to 0 or numerically less than the threshold ε. If M may have a non-trivial kernel,

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[0326] Algorithm 500 is the l² optimal solution (found in the step of calculating least squares 540).

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[0330] The result of Decision 550 is,

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[0333] The results of test 550 are,

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[0337] Algorithm 500 may include a projection step 560,

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[0340] Algorithm 500 may include step 570 of solving a linear program. Minimizing sampling overhead.

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[0355] The above linear program transforms

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[0361] Solutions for linear programming

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[0364] In some embodiments, algorithm 500 may include sanity checks (not shown), i.e., checks that the results of intermediate and / or final calculations can be considered reasonably correct by verifying that certain general properties that must be theoretically preserved can actually be preserved. For example, sanity checks may be required due to numerical stability limits of subroutines that may be incorporated into algorithm 500. Sanity checks can also help verify that algorithm 500 is correctly implemented. Sanity checks may include verifying the following properties:

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[0366] In some embodiments, algorithm 500 may include a step 590 for calculating a performance metric. If the decomposition can be implemented on a quantum processor, the performance metric can estimate how much the performance of the decomposition calculated by algorithm 500 can improve over existing QP decompositions or over the performance of quantum logic operations G.

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[0372] In some embodiments, algorithm 500 can be repeated according to the result 595 of step 590, which calculates the performance metric. Repetition of algorithm 500 may be necessary if the performance metric is not satisfactory, for example, if the QP norm does not satisfy the resolved sampling overhead target, or if the distance measurement does not satisfy the resolved accuracy target. In some embodiments, algorithm 500 can be repeated if any of the sanity checks fail.

[0373] To further reduce classical computational resources, a divide-and-conquer modification of the above first-order algorithm can be used. b Since it is assumed that is r-local,

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[0381] The sum of the Frobenius distances achieved by the solutions to the r' qubit problem on the right side restricts the Frobenius distance of the solutions to the complete linear problem on the left side. Therefore, we solve r' using the algorithm above and obtain the resulting n-qubit QP decomposition.

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[0386] Here

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[0390] In some embodiments of this disclosure, for example, with respect to the parameterization of errors in G, the QP coefficient c p By obtaining a simple formula, it is possible to solve some of the optimization problems mentioned above analytically (i.e., symbolically rather than numerically). In such cases, the calculation of the QP decomposition using the algorithm described above can be reduced to substituting the error parameters into the simple formula.

[0391] 2-Step Multi-Type Damping Figure 6 shows a flowchart illustrating the steps of a broad embodiment of a modified computer implementation method 600 for mitigating errors in quantum circuits according to embodiments of the present disclosure. The quantum circuit may include at least one occurrence of a quantum logic operation G of a quantum processor. Quantum logic operations G are noisy and can be susceptible to implementation errors, i.e., coherent errors and dissipative errors. Method 600 involves a set of coefficients {c p The calculation step 610 may include the calculation of the set of coefficients {c p} is the set of base operations {B p It may also be associated with}, that is, the coefficient c p The corresponding basis operation B p This is possible. The calculation step 610 is the set of basis operations {B p This could include computing the quasi-probability decomposition 611 of the ideal version of the quantum logic operation G G0 on {B}. That is, the quantum logic operation G is a set of basis operations {B}. p The decomposition can be approximated by the weighted sum of operations obtained from}612.

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[0393] Method 600 may include a step 620 for implementing quasi-probability decomposition on a quantum processor. Step 620 for implementing quasi-probability decomposition may be for estimating the result of an ideal quantum circuit in which an ideal version G0 of a quantum logic operation G replaces at least one occurrence of the quantum logic operation G. In other words, step 620 for implementing quasi-probability decomposition may be for estimating the result of a quantum circuit in which G0 replaces G. Step 620 for implementing quasi-probability decomposition is for basis operation {B p This may include performing quantum logic operations included in the set of} on a quantum processor.

[0394] The decomposition target 614 may include a step 615 to optimize the decomposition, i.e., to minimize a cost function that may depend on sampling overhead, precision, the metric for using ideal non-unitary basis operations, and the metric for using ideal unitary basis operations. In some embodiments, the optimization step 615 may include minimizing the use of ideal non-unitary basis operations. For example, minimizing the number of ideal non-unitary basis operations included in the decomposition 611, or minimizing the relative weights of one or more basis operations included in the decomposition 611 that are ideal non-unitary. The relative weights of one or more basis operations included in the decomposition 611 may be defined as the sum of the absolute values ​​of the coefficients corresponding to these basis operations, divided by a quasi-probability norm.

[0395] The step of minimizing the use of ideal non-unitary basis operations can include computing a quasi-probability decomposition 612, and the set of basis operations {B p {GS} may include quantum logic operations G and basis operations selected from at least two basis operation types. The basis operation types may include the following types: {GS} i ,S j G,S k GS l ,S m In other words, the base operation types may include the following types: 1. GS i - A quantum operation, wherein the quantum logic operation G may be preceded by a quantum operation included in a set of quantum operations S1. 2.S j A G-quantum operation, wherein the quantum logic operation G may be succeeded by a quantum operation included in the set of quantum operations S2. 3.S k GS l - A quantum operation in which a quantum logic operation G may be preceded or succeeded by quantum operations included in sets of quantum operations S3 and S4, respectively. 4.S m- A quantum operation that is included in the set of quantum operations S5, and for which the quantum logic operation G does not necessarily exist.

[0396] Union of quantum operations

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[0398] The step to minimize the use of ideal non-unitary basis operations is residual error

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[0410] In some embodiments, step 620 of implementing quasi-probability decomposition involves a set of basis operations {B p Step 622 may include randomly sampling {B}, i.e., compiling a set of operations (i.e., a list) such that the operations are based on a set of base operations {B}. p} may be selected. This set (list) of operations may contain several occurrences of the same basis operation. Sampling 622 is the set of coefficients {c p} may be based on. In some embodiments, the sampling 622 is a probability distribution defined by probability or weights.

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[0421] Step 620 of implementing quasi-probability decomposition may further include step 626 of executing a sampled set of quantum circuits on a quantum processor. The sampled set of quantum circuits may be determined by 624 of substituting at least one occurrence of quantum logic operations G in the quantum circuits with one sampled operation from the corresponding set of sampled operations. The execution of the sampled quantum circuits 626 may be for obtaining the sampled quantum circuit results. Step 620 of implementing quasi-probability decomposition may further include step 628 of estimating the results of an ideal quantum circuit based on the sampled quantum circuit results. In some embodiments, substituting at least one occurrence of quantum logic operations G in the quantum circuit 624 may be performed by substituting each occurrence of quantum logic operations G with a sample from the corresponding set of basis operations.

[0422] In some embodiments, method 600 may include calculating the statistical error of the estimated ideal calculation result.

[0423] In some embodiments, method 600 may include a characterization step (not shown). The characterization step may include obtaining an error characterization in the quantum logic operation G in order to find an error model of the quantum logic operation G. In other words, the quantum logic operation G may be characterized to find out how it deviates from the ideal version G0. The characterization step may include (at least one) basis operation {B p To find the error model of}, we use the set of basis operations {B pThis may include obtaining an error characterization for at least one of the base operations. The characterization step may include obtaining an error characterization for at least one operation included in the set of mitigation operations S. Set of complementary base operations

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[0427] Method 600 is the corresponding ideal version {G0 [β] Multiple quantum logic operations having}

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[0439] In some embodiments, the set of base operations {B p} is sub-circuit B p It may also include: Sub-circuit B p This may include the generation of two or more quantum logic operations G, or it may include two or more mitigation operations selected from a set of mitigation operations S. In some embodiments, a set of complementary basis operations

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[0444] Further features that some embodiments of Method 600 may be assumed can be found above in the description relating to Figures 2A to 5. It should be noted that the set of basis operations {B p The possible features of} are a set of complementary basis operations, except that it excludes any (in all sense) ideal nonunitary operations.

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[0447] Method 600 can be generalized. Instead of distinguishing between unitary and non-unitary operations, operations may be distinguished as "easy" and "difficult." "Easy" operations are preferred over "hard" operations; that is, for example, it is preferable that the probability of sampling a "hard" operation is minimized. This generalization is well understood on the basis that on one QPU, some operations may have negligible noise (or are generally not resource-intensive), while the same operation on a different QPU may be very noisy (or even not natively available).

[0448] Figure 7 shows a flowchart illustrating a computer implementation method 700 for mitigating errors in a quantum circuit according to an embodiment of the present disclosure. The quantum circuit Cir705 may include at least one generation of a quantum logic operation G of a quantum processor, which may be noisy. The goal may be to mitigate errors in the quantum circuit 705 arising from G.

[0449] Method 700 may include a step 710 for characterizing an error. The step 710 for characterizing an error may include characterizing an error in a quantum logic operation G and a set of basis operations {B}. p This may include characterizing errors in}.

[0450] Method 700 may include a step 720 for calculating coefficients. Step 720 for calculating coefficients may receive the quantum circuit 705 and the error characterization obtained in step 710 for characterizing errors as inputs. Step 720 for calculating coefficients may include a set of coefficients {c p This may include calculating the set of coefficients {c}. p} is the set of base operations {B p It can be associated with the set of coefficients {c p} is a quasi-probability decomposition

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[0452] The set of coefficients obtained in step 720 for calculating the coefficients {cp} can be used to calculate the probability measure 730. The probability measure is weight

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[0454] Method 700 is a set of sampled quantum circuits {Cir Q The step 740 may include generating {Cir}. The probability measurement 730 is a sampled set of quantum circuits {Cir}. Q} can be used to generate 740. A sampled set of quantum circuits {Cir Q} can be determined by substituting at least one occurrence in the quantum circuit G with one of the sampled operations from the corresponding set of sampled operations. The generation of the set of sampled circuits may be done in a representative way, for example, by storing a list of lists of indices, where each index points to a sample and each list corresponds to a sampled circuit. For each sampled quantum circuit in the set of sampled quantum circuits, the corresponding sampled circuit code

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[0462] Method 700 is a circuit sampled on the quantum processor 750 {Cir Q The step may include performing the sampled circuit {Cir Q} execution 750 may be to obtain sampled quantum circuit results. Each sampled circuit Cir Q Regarding this, the qubit may be reset, and the sampled circuit Cir Q The following may be performed, and the state of the qubit may be measured, and the measurement result o Q It may be registered.

[0463] The first test, 760, is a sampled circuit Cir Q The number of iterations ("shots") required to execute the action is N. s It may be performed to determine whether or not it was reached. If the result of the first test 760 is negative, Cir QThis may be executed again (sampled circuit {Cir Q (This is shown as returning to step 750, which is performed). If the result of the first test 760 is positive, the second test 770 can be performed. The second test 770 can test whether all sampled circuits have been performed. If the result of the second test is negative, the next sampled circuit may be performed again (sampled circuit {Cir Q (This is shown as returning to step 750, which executes}.

[0464] If the result of the second test 770 is positive, the method is to obtain the results of the sampled quantum circuit o Q The process may proceed to step 780, which estimates the result o of an ideal quantum circuit based on the above. Step 780, which estimates the result o of an ideal quantum circuit, is the result o. Q This may include calculating the average of . Result o Q is the corresponding code

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[0467] The method may proceed to step 790, which calculates the statistical error in the estimate obtained in step 780, which estimates the result o of an ideal quantum circuit. Step 790, which estimates the statistical error, may include visually presenting the error, for example, as an error bar.

[0468] Numerical simulation To demonstrate the advantages of the methods of this disclosure over known art, the applicant simulated several methods for error mitigation on a classical computer. The methods according to embodiments of this disclosure and methods known in the art were simulated. In all methods, the gates to be mitigated are non-Clifford gates, and the mitigation operations to be allowed are ideal unitary.

[0469] Figures 8A-8B show graphs demonstrating the performance of the error-mitigating method according to the embodiments of the present disclosure compared with other error-mitigating methods known in the art.

[0470] The simulated noisy quantum logic operation is a 2-qubit ZZ rotation gate Gα=R with rotation angle α∈(0,π / 2). ZZ These were the (α) family. These are non-Clifford gates for α that are not multiples of π / 2. The gate for angle α=0, π / 2 is a Clifford gate and was therefore not simulated. As explained above, Clifford gates can be optimally reduced using "Clifford reduction", twiling in full Pauli group P, and ideally unitary single-type basis

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[0472] Non-Clifford R ZZ The (α) gate is interesting because it appears commonly in quantum algorithms and can be implemented as a native gate on various types of QPUs. ZZ The (α) gate has been natively implemented in tunable frequency-coupled transmon qubits and trap ion qubits. Up to single-qubit basis changes, R ZZ(α) gates are also cross-resonant gates R in fixed-frequency and coupled transmonk bits. ZX (α) corresponds to the trapped ion qubit

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[0474] In all simulated methods, the basis operation B in all basis B considered i Gate G should be reduced α , and ideally constructed from a set S of unitary mitigation operations. These mitigation operations consist of 16 two-qubit Pauli layers.

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[0476] The methods implemented according to the embodiments of this disclosure are as follows: a) Two non-trivial type G α S and SG α multitype base including

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[0485] In the simulated methods of this disclosure described above, the QP decomposition of a multitype basis was computed according to the first-order algorithm described above (in the section “Calculation of Multitype QP Decomposition”). To enable a simple comparison with methods known in the art, the same algorithm was applied to a single-type basis in methods (d) and (e) below.

[0486] The methods that were implemented are known in the relevant technical field as follows: d) A single non-trivial type

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[0491] The "combined reduction" reduction method can be summarized as follows: Non-Clifford family G α Known methods for reducing errors in composite G α This means compiling G α This is implemented as a subcircuit including a two-qubit Clifford gate and a single-qubit gate. Then, the aforementioned "Clifford mitigation" is applied to each of the two-qubit Clifford gates while ignoring generally negligible errors in the single-qubit gate. As an example, a combined implementation is as follows.

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[0497] G α The simulated noise model for this involves standard amplitude decay (T1) and pure defaging that occur on each qubit during gate operations.

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[0502] Generalizing to any single-qubit dissipation process that occurs during gate operations does not qualitatively alter the results presented below.

[0503] Noisy G α The gate is Group P ZZ It is twiling, i.e., a group of Pauli layers interchangeable with ZZ (see above for twiling). Composite implementation

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[0505] As described above, Figures 8A and 8B show graphs demonstrating the performance of an error-mitigating method implemented according to an embodiment of the present disclosure, compared to error-mitigating methods known in the art.

[0506] The difference between Figure 8A and Figure 8B is simply the marking of different datasets in the graph. In Figure 8A, different datasets are marked by different line types (e.g., solid / dashed, gray / black). In Figure 8B, different datasets are marked by different markers (e.g., square / triangle / circle, solid / hollow). For clarity, two types of dataset marking are shown. Due to this similarity, if both figures may be referenced, the abbreviated Figure 8 may refer to either figure.

[0507] Four panels are shown in Figure 8. In panels (a) and (c) (top left and bottom left), ε is ε = 5 × 10⁻⁶ -3 α is fixed at α = π / 4, and ε is in the range α ∈ (0, π / 2). In panels (b) and (d) (upper right and lower right), α is fixed at α = π / 4, and ε ∈ (10 -4 ,10 -1 It is within the range of ).

[0508] The markings for the datasets corresponding to the enumeration of simulated methods used above are as follows: a) Uneven black dashed lines / black circles. b) Black even-numbered dashed / downward-pointing solid triangles. c) Solid black line / upward-pointing black triangle. d) Gray, uneven dashed line / hollow circle. e) Gray even-numbered dashed lines / white outlined squares. f) An upward-pointing gray solid line / white outlined triangle.

[0509] It should be noted that methods according to embodiments of this disclosure are indicated by black / solid line symbols, while methods known in the art are indicated by gray / hollow line symbols.

[0510] Panel (a) in Figure 8 provides a legend for the dataset. The order of the legend from top to bottom corresponds to the enumeration of the simulated methods used above (for example, the top item corresponds to method (a), and the bottom item corresponds to method (f)). The legend further includes reduced calculations (G αExplicitly indicate (excluding).

[0511] As the first performance metric for QP decomposition, the QP norm W is used as a measure for sampling overhead. This is shown in panels (a) and (b). More specifically, the "blow-up rate" (W-1) / IF is considered. The "blow-up rate" is the QP-norm W of the volume V circuit relative to the "total non-fidelity" IF × V. V The exponential dependence of is quantified. As mentioned above, the blow-up rate has an optimal value of 2, which sets the lower limit of the y-axis for panels (a) and (b). Note that in both panels (a) and (b), the overlapping lines are slightly separated vertically for better visibility. Panel (b) is as expected, the blow-up rate is

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[0513] The second performance metric is the relative residual Frobenius distance.

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[0515] To demonstrate the advantages of multi-type mitigation, several single-type mitigation strategies are considered (methods (d) to (f)). The first single-type mitigation considered is composite mitigation (method (f) described above). This method can be easily applied non-linearly and therefore gives vanishing inaccuracies (this is why the corresponding datasets are not present in panels (c) and (d)). Furthermore, this method,

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[0520] As explained below, multi-type mitigation allows for complete primary mitigation of the noise model considered while achieving the optimal blow-up rate.

[0521] Next, we will describe in detail the execution of multi-type QP decomposition as shown in Figure 8. The simplest multi-type QP basis to consider is:

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[0523] Let α → π / 2 and B a The excess QP norm obtained for this is due to the angle α that appears in both types of basis elements. This results in a QP basis with a high condition number (when viewed as a matrix), which in effect inefficiently extends into the space of mitigable errors. Indeed, at α = π / 2, gate G α =G π / 2 is (ideally) a Clifford gate, which maps the Pauli group to itself via conjugation. As a result, G π / 2P=PG π / 2, and at α=π / 2, multitype basis B a This is effectively reduced to a single-type basis. The solution to this problem is to use an additional 2-qubit gate G as the reduction operation. α’ This includes the following. As an example, a basis using α'=π / 2-α

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[0525] Multitype base

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[0529] In summary, in contrast to single-type mitigation strategies known in the art, the multi-type mitigation according to the embodiments of the present disclosure enables optimal first-order mitigation of rotating gates with non-Clifford ZZ single-qubit dissipation occurring during gate operations, without relying on non-unitary mitigation operations.

[0530] The results presented so far are qualitatively gated.

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[0533] Figure 9 shows an embodiment of the present disclosure, G α A graph is shown demonstrating the implementation of a method to mitigate errors applied to multiple gates from the β,γ families. α 1000 gates from the β and γ families were simulated on a classical computer. Parameters

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[0537] The two panels are shown in Figure 9. In both panels, the x-axis labeled "Index" represents a specific combination of parameters, i.e.,

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[0539] Panel (a) shows that the QP decomposition has a blow-up rate very close to the optimal value of 2. The slight non-optimality is due to numerical inaccuracies inherent in the linear programming included in the calculation algorithm. Panel (b) shows that the multi-type decomposition also has better accuracy than the first-order one.

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[0541] The advantages of the method described herein are that it is a non-Clifford gate G α =R ZZ (α) This can be seen further by reconsidering the family, but error generator L b This is entirely general before the above. That is, the assumption of single-qubit dissipation in the gate is not assumed. To mitigate such a general noise model, larger twiling groups and a larger set of mitigation operations may be used compared to the simulation described above. To reduce the noise model as much as possible,

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[0547] Combinations γ1 and γ2 are commutator P ZZ It includes Pauli operators not included in P, and γ3 is P ZZ It includes the Pauli operator, which is included in R. Nevertheless, all combinations of the three parameters are R ZZThis corresponds to a super operator interchangeable with (α), and therefore can be considered to act before, during, or after an ideal gate.

[0548] All three combinations in Equation 14 correspond to two-qubit dissipation. γ3 can be generated by twiling coherent errors, but γ1 and γ2 cannot. Assuming that γ3 is solely due to twiling coherent errors, γ_3 is given (for the preceding order) by the following equation: γ3=h XX h YY -h XY h YX

[0549] The sum of γ1 + γ2 determines the nonunitary error in the ZZ direction.

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[0551] Furthermore, as demonstrated by the numerical simulations above, R α' ≠ α ZZ By adding (α') as a reduction operation, we obtain a QP norm that is close to optimal.

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[0553] Figure 10 and the following discussion are intended to provide a brief and general description of exemplary computing environments in which the disclosed technology may be implemented. While not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, executed by a personal computer (PC). Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Furthermore, the disclosed technology may be implemented in other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, and mainframe computers. The disclosed technology may also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0554] Referring to Figure 10, an exemplary system for implementing the disclosed technology includes a general-purpose (classical) computing device in the form of an exemplary conventional PC 1000, comprising one or more processing units 1010, a system memory 1020, and a system bus 1030 that connects various system components, including the system memory 1020, to one or more processing units 1010. The system bus 1030 may be one of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, and / or a local bus using any of various bus architectures. The exemplary system memory 1020 includes read-only memory (ROM) 1022 and random-access memory (RAM) 1027. A basic input / output system (BIOS) 1025, which contains basic routines useful for transferring information between elements within the PC 1000, is stored in the ROM 1022. As shown in Figure 10, the system memory 1020 may store computer-executable instructions for performing any of the disclosed techniques (e.g., sending instructions to a quantum computer to apply a characterization gate sequence and an adjacent gate sequence to a subset of qubits, measuring the results, collecting frequencies, and calculating model parameters) in their respective memory portions (generally indicated as executable software 1029 for performing any embodiment of the disclosed synthesis technique).

[0555] An exemplary PC1000 further includes one or more storage devices 1040, such as a hard disk drive for reading and writing to a hard disk, a magnetic disk drive for reading and writing to a removable magnetic disk, and / or an optical disk drive for reading and writing to a removable optical disk (such as a CD-ROM or other optical medium). Each of these storage devices can be connected to the system bus 1030 by a hard disk drive interface, a magnetic disk drive interface, and / or an optical drive interface. The drives and their associated computer-readable media provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data for the PC1000. In the exemplary operating environment, other types of computer-readable media that can store data accessible by the PC may also be used, such as magnetic cassettes, flash memory, digital video discs, CDs, DVDs, RAM, NVRAM, and ROM. As used herein, the terms storage, memory, and computer-readable media may not include or encompass the propagating carrier or signal itself.

[0556] The operating system, one or more application programs, other program modules, and several program modules including program data may be stored in the storage device 1040. The storage of quantum measurement results and instructions for obtaining such measurements (and / or instructions for carrying out any embodiment of the disclosed technology) may also be stored in the storage device 1040. The user may input commands and information to the PC 1000 via one or more input devices 1050, such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, gamepad, satellite receiver, scanner, etc. These and other input devices are often connected to one or more processing units 1010 via a serial port interface coupled to the system bus 1030, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 1080 or other type of display device is also connected to the system bus 1030 via an interface such as a video adapter. Other peripheral output devices 1060 may include speakers and a printer (not shown). In some cases, a user interface is displayed so that the user can input the circuit for synthesis and verify the success of the synthesis.

[0557] The PC1000 may operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1090. In some examples, this may include one or more network or communication connections 1070. The remote computer 1090 may be another PC, server, router, network PC, or peer device or other common network node, and typically includes many or all of the elements described above with respect to the PC1000, although Figure 10 illustrates only the memory storage device 1095. The personal computer 1000 and / or remote computer 1090 may be connected to a local area network (LAN) and a wide area network (WAN). Such networking environments are common in offices, enterprise-wide computer networks, intranets, and the internet.

[0558] When used in a LAN networking environment, the PC1000 is connected to the LAN via a network interface. When used in a WAN networking environment, the PC1000 typically includes a modem or other means for establishing communication over a WAN such as the Internet. In a networked environment, program modules or parts thereof described in relation to the personal computer 1000 may be stored in a remote memory storage device or other location on the LAN or WAN. The illustrated network connection is illustrative, and other means may be used to establish communication links between computers.

[0559] Referring to Figure 11, an exemplary system for implementing the disclosed technology includes a computing environment 1100, the environment including one or more quantum processing units 1110, each including one or more monitoring / measurement devices. The quantum processing units execute quantum circuits provided by classical processing units 1120. The quantum circuits are downloaded to the quantum processing units 1110 or used to program or configure the quantum processing units (e.g., via control lines (quantum buses), 1170). Procedures according to any of the disclosed embodiments (e.g., a high-level description of a set of quantum circuits applied to a qubit patch and neighboring qubits) may be stored in memory 1130.

[0560] Referring to Figure 11, a high-level description of quantum software can be translated into a quantum circuit (e.g., a sequence of quantum gates, or a layer of gates acting in parallel on different qubits). Such a high-level description may, in some cases, be stored on one or more external computers 1160 outside the computing environment 1100 using one or more memory and / or storage devices 1165, and then, if necessary, can be downloaded to the computing environment 1100 via one or more communication connections 1140. The quantum circuit (according to any of the disclosed embodiments) is coupled to a quantum processor 1110.

[0561] The quantum processing unit may be, but is not limited to, one or more of the following: (a) a superconducting quantum computer, (b) an ion-trap quantum computer, (c) a topological quantum computer using, for example, a Majorana zero-mode, (d) a photon quantum computer, or (e) a neutral-atom quantum computer. A set of gates (e.g., using any of the disclosed embodiments) may be transmitted to the quantum processing unit via control lines 1170 in the controller 1150 (or may be otherwise applied). In the illustrated example, the desired quantum computing process is carried out using one or more controllers 1150, each specifically adapted to control one of the corresponding quantum processors 1110. The classical processor 1120 can further interact with a measurement / monitoring device (e.g., a readout device) 1180 to help control and implement the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit when available).

[0562] While the principles of the disclosed technology have been described and illustrated with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in configuration and detail without departing from such principles. For example, elements of the illustrated embodiments shown in software can be implemented in hardware, and vice versa. Furthermore, technology from any example can be combined with technology described in any one or more of the other examples. It will be understood that procedures and functions, such as those described with reference to the illustrated examples, can be implemented in a single hardware or software module, or separate modules may be provided. The above configurations are provided for convenient illustration purposes, and other configurations can be used.

[0563] Therefore, applying the wording of the clauses, this disclosure provides methods and systems that comply with the following clauses, but are not limited to these. Clause 1: A computer implementation method for mitigating errors in a quantum circuit including the generation of at least one quantum logic operation G of a quantum processor, wherein the method is • Set of basis operations {B p Set of coefficients associated with {c p Calculate} and set the basis operation {B p On}, the quasi-probability decomposition of the target version G0 of the quantum logic operation G.

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Claims

1. A computer implementation method for mitigating errors in a quantum circuit including the generation of at least one quantum logic operation G of a quantum processor, wherein the method is • Base operation set {B ｐ Set of coefficients associated with {c} ｐ } is calculated, and the set of base operations {B ｐ } Above, the target version G of the quantum logic operation G ０ Quasi-probability decomposition [Math 1] Includes the step of obtaining, i) The set of the basis operations {B ｐ } includes ideal non-unitary basis operations and ideal unitary basis operations, ii) The decomposition is calculated to reach a decomposition target based on an ideal non-unitary basis operation usage target, and at least one of the decomposition accuracy target, decomposition sampling overhead target, and ideal unitary basis operation usage target. - Implementing the quasi-probability decomposition in the quantum processor to estimate the result of the target quantum circuit, and the target version G of the quantum logic operation G ０ A method for substituting the occurrence of at least one of the quantum logic operations G.

2. The method according to claim 1, wherein the target usage of an ideal nonunitary basis operation is minimized by the following, - Calculating the quasi-probability decomposition, wherein the set of basis operations {B ｐ The steps include:} forming a multitype base constructed from ideal unitary elements of the quantum logic operation G and reduction operation set S, - Set of complementary basis operations [Math 2] Set of interpolation coefficients associated with [Math 3] Calculate residual error [Math 4] A step of obtaining a quasi-probability decomposition for the set of complementary basis operations. [Math 5] This involves steps, including an ideal non-unitary operation, A method comprising the step of refining the estimation of the result of an ideal quantum circuit by implementing the quasi-probability decomposition for the residual error in the quantum processor.

3. The set of complementary basis operations [Math 6] However, the set of quantum logic operations G and complementary mitigation operations [Number 7] The method according to claim 2, wherein a multitype base is constructed from the elements of the following.

4. The set {B ｐ} of the base operations ｉ includes at least two base operation types GS ｊ , S ｋ GS ｌ , S ｍ selected from ｉ , . . , S ｍ The method according to claim 2, wherein is an element of the set S of the reduction calculation.

5. The set of complementary basis operations [Number 8] However, multiple base operation types GS ｉ , S ｊ G, S ｋ GS ｌ , S ｍ Includes at least two base operation types selected from, the S ｉ , . . , S ｍ This is a set of interpolation and mitigation operations. [Number 9] The method according to claim 2, which is an element of the method.

6. The set of the aforementioned base operations {B ｐ } is sub-circuit B ｐ It further comprises, or the set of complementary basis operations. [Number 10] Sub-circuit [Math 11] The subcircuit [Math 12] However, it includes the generation of two or more quantum logic operations G, or each includes a set of mitigation operations S and a set of complementary mitigation operations. [Number 13] The method according to claim 2, comprising two or more reduction operations selected from.

7. A system for reducing errors in quantum circuits, Quantum processors, Classical processors and, Equipped with memory, A system wherein the memory stores instructions that cause the system to perform the method according to any one of claims 1 to 6 when executed by the classical processor.

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