Display boards and display devices

Abstract

We provide display boards and display devices belonging to the field of display technology. [Solution] The display board is arranged on a base board and includes two adjacent pixels arranged along a first direction, and in each pixel, the pixel circuit includes a drive transistor, a first reset transistor, and a second reset transistor. The first reset transistor is arranged symmetrically with respect to the axis of symmetry of a first portion of a coupled first reset signal line, and the first portion of the first reset signal line extends along a second direction intersecting the first direction, thereby facilitating layout and signal routing, for example, allowing multiple signal lines coupled to each pixel to be centrally located and optimizing the pixel space.

Description

Technical Field

[0001] This disclosure is a divisional application of a Japanese patent application with application number Japanese Patent Application No. 2022-523694, which is the national phase application in Japan of an international application with application number PCT / CN2021 / 099017 filed on June 8, 2021, and all of its contents are incorporated herein by reference.

[0002] This disclosure relates to the field of display technologies, and particularly to display substrates and display devices.

Background Art

[0003] Organic light emitting diode (OLED) display substrates are widely used in the display field due to advantages such as self-emission, wide viewing angles, and high-speed response.

[0004] In related technologies, an OLED display substrate includes a base substrate and a plurality of pixels arranged on the base substrate. Each pixel includes a light emission control circuit, a light emission driving circuit, and a light emission element. Here, the light emission control circuit can provide a DC power signal to the light emission driving circuit in response to a light emission control signal provided from a light emission control line connected thereto. The light emission driving circuit can provide a light emission driving signal to the light emission element in response to a gate driving signal provided from a gate line connected thereto and the received DC power signal. And the light emission control circuits connected to different pixels are different.

[0005] Since the light emission control circuits connected to different pixels are different, it is necessary to provide more light emission control lines on the display substrate. These multiple light emission control lines occupy a large area of the base substrate, which is disadvantageous for achieving high resolution.

Summary of the Invention

Means for Solving the Problems

[0006] Embodiments of this disclosure provide a display substrate and a display device. The technical solution is as follows. According to one perspective, Base board and Displaced on the base substrate and arranged in an array, each including a light emission control circuit, a light emission driving circuit, and a light-emitting element, and at least two of them share the same light emission control circuit and a plurality of pixels, The base substrate includes a gate drive circuit, a plurality of light emission control lines, a plurality of gate lines, and a plurality of drive signal lines, Includes, The gate drive circuit is connected to the plurality of drive signal lines, the plurality of light emission control lines, and the plurality of gate lines, respectively, the plurality of light emission control lines are connected to the light emission control circuit included in each of the pixels, the plurality of gate lines are connected to the light emission drive circuit included in each of the pixels, and the gate drive circuit is used to output a light emission control signal to the plurality of light emission control lines and to output a gate drive signal to the plurality of gate lines in response to drive signals provided from the plurality of drive signal lines. Regarding display boards.

[0007] As one option, at least two of the pixels that share the same light-emitting control circuit are arranged in the same row.

[0008] As one option, at least two of the pixels that share the same light-emitting control circuit are adjacent to each other.

[0009] As one option, the same light-emitting control circuit is shared for each of the two pixels arranged in the same row.

[0010] As one option, two pixels sharing the same light emission control circuit are arranged symmetrically on both sides of the light emission control line connected to the light emission control circuit.

[0011] As one option, each of the aforementioned drive signal lines is arranged between two adjacent rows of pixels.

[0012] As one option, up to two drive signal lines are provided between two adjacent rows of pixels.

[0013] As one option, the gate drive circuit includes a plurality of cascaded shift register units, At least two cascaded shift register units are positioned between two adjacent rows of pixels.

[0014] As one option, at least two cascaded shift register units are arranged between two adjacent rows of target pixels. Of the two rows of target pixels, the light emission control circuit connected to one row of target pixels is different from the light emission control circuit connected to the other row of target pixels.

[0015] As one option, two cascaded shift register units are provided between two adjacent rows of target pixels. Here, one shift register unit is connected to the target pixels of one row, and the other shift register unit is connected to the target pixels of the other row. As one option, the two cascaded shift register units are arranged symmetrically between the two rows of target pixels.

[0016] As one option, the shift register unit includes an input subcircuit, a pull-down control subcircuit, a pull-down subcircuit, and an output subcircuit. The input subcircuit is connected to a first input terminal, a second input terminal, a first control signal terminal, a second control signal terminal, and a pull-up node, respectively. The input subcircuit is used to output a first control signal provided by the first control signal terminal to the pull-up node in response to a first input signal provided by the first input terminal, and to output a second control signal provided by the second control signal terminal to the pull-up node in response to a second input signal provided by the second input terminal. The pull-down control subcircuit is connected to the first clock signal terminal, the pull-up node, the pull-down power supply terminal, the pull-down node, and the output terminal, respectively. The pull-down control subcircuit is used to output the first clock signal to the pull-down node in response to the first clock signal provided from the first clock signal terminal, and to output the pull-down power supply signal provided from the pull-down power supply terminal to the pull-down node in response to the potential of the pull-up node and the output signal provided from the output terminal. The pull-down subcircuit is connected to the reset signal terminal, the pull-down node, the pull-down power supply terminal, the pull-up node, and the output terminal, respectively, and is used to output the pull-down power supply signal to the pull-up node and the output terminal in response to the potential of the pull-down node, and to output the pull-down power supply signal to the pull-up node in response to the reset signal provided from the reset signal terminal. The output subcircuit is connected to the pull-up node, the second clock signal terminal, and the output terminal, respectively, and the output subcircuit is used to output the second clock signal provided from the second clock signal terminal to the output terminal in response to the potential of the pull-up node.

[0017] As one option, the display board further includes a plurality of data lines arranged on the base board, The plurality of gate lines include a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines; the light emission control circuit includes a light emission control transistor; and the light emission drive circuit includes a data writing transistor, a reset transistor, a drive transistor, a compensation transistor, and a storage capacitor. The gate of the data writing transistor is connected to one of the first gate lines, the first pole is connected to the gate of the driving transistor, the second pole is connected to one of the data lines, the first pole of the driving transistor is connected to the first pole of the light emission control transistor, the second pole is connected to the light emitting element, the gate of the light emission control transistor is connected to one of the light emission control lines, the second pole is connected to the DC power supply terminal, the gate of the reset transistor is connected to one of the second gate lines, the first pole is connected to the first initial signal terminal, the second pole is connected to the second pole of the driving transistor, the gate of the compensation transistor is connected to one of the third gate lines, the first pole is connected to the second initial signal terminal, and the second pole is connected to the gate of the driving transistor.

[0018] According to another aspect, it includes a source driving circuit and the display substrate described in the above aspect, The source driving circuit is connected to a plurality of data lines on the display substrate, and the source driving circuit is used to provide data signals to each of the data lines. Relates to a display device.

[0019] To more clearly explain the technical solutions in the embodiments of the present disclosure, the drawings that need to be used in the following description of the embodiments will be briefly described below. The drawings in the following description are only some embodiments of the present disclosure. It is obvious that those skilled in the art can obtain other drawings based on these drawings without creative labor.

Brief Description of the Drawings

[0020] [Figure 1] It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure. [Figure 2] It is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure. [Figure 3] It is a schematic structural diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 4] It is a schematic diagram of the circuit structure of two adjacent pixels according to an embodiment of the present disclosure. [Figure 5] The layout diagram of the selectable structure of two adjacent pixels according to an embodiment of the present disclosure. [Figure 6] The schematic structural diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 7] The schematic structural diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 8] The schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. [Figure 9] The schematic structural diagram of another shift register unit according to an embodiment of the present disclosure. [Figure 10] The schematic structural diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 11] The operation timing chart of pixels according to an embodiment of the present disclosure. [Figure 12] The schematic structural diagram of a display device according to an embodiment of the present disclosure.

Modes for Carrying Out the Invention

[0021] In order to make the purpose, technical solution and advantages of the inventive concept of the embodiments of the present disclosure clearer, hereinafter, the inventive concept protected by the embodiments of the present disclosure will be described in detail with reference to the drawings and some embodiments.

[0022] The transistors used in all embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other devices having the same characteristics, and depending on their role in the circuit, the transistors used in embodiments of this disclosure are primarily switching transistors. The source and drain of the switching transistors used herein are symmetrical, and their source and drain are interchangeable. In embodiments of this disclosure, the source is referred to as the first pole and the drain as the second pole, or the drain as the first pole and the source as the second pole. In the form of the drawings, the middle terminal of the transistor is defined as the gate, the signal input terminal as the source, and the signal output terminal as the drain. Furthermore, the switching transistors used in embodiments of this disclosure may be either P-type switching transistors or N-type switching transistors, where a P-type switching transistor is on when the gate is low and off when the gate is high, and an N-type switching transistor is on when the gate is high and off when the gate is low.

[0023] Figure 1 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 1, the display substrate may include a base substrate 01 and a plurality of pixels 02 arranged in an array on the base substrate 01. Figure 2 is a schematic diagram of another display substrate according to an embodiment of the present disclosure. As can be seen from Figures 1 and 2, each pixel 02 includes a light emission control circuit 021, a light emission drive circuit 022, and a light-emitting element 023. At least two pixels 02 can share the same light emission control circuit 021, that is, at least two pixels 02 can be operated by the same light emission control circuit 021.

[0024] As can be seen by referring to Figure 2, the display board may further include a gate drive circuit 03 located on the base board 01, a plurality of light emission control lines (e.g., EM1 to EMn shown in Figure 2), a plurality of gate lines (e.g., G1 to Gm shown in Figure 2), and a plurality of drive signal lines (L1 to Li shown in Figure 2).

[0025] Here, the gate drive circuit 03 can be connected to a plurality of drive signal lines, a plurality of light emission control lines, and a plurality of gate lines, respectively. The plurality of light emission control lines can be connected to a light emission control circuit 021 included in each pixel 02, and the plurality of gate lines can be connected to a light emission drive circuit 022 included in each pixel 02. In response to drive signals provided from the plurality of drive signal lines, the gate drive circuit 03 can output a light emission control signal to the plurality of light emission control lines and a gate drive signal to the plurality of gate lines. That is, the gate drive circuit 03 can be operated by drive signals provided from the plurality of drive signal lines.

[0026] As one option, generally, multiple rows of pixels 02 may be connected to multiple gate lines in a one-to-one correspondence, and multiple rows of pixels 02 may be connected to multiple light emission control lines in a one-to-one correspondence. That is, in multiple pixels 02 arranged in the same row, the light emission control circuit 021 included in each pixel 02 may be connected to the same light emission control line, and the light emission drive circuit 022 included in each pixel 02 may be connected to the same gate line. Correspondingly, in the embodiments of this disclosure, the number of gate lines included in the display board and the number of rows of pixels are the same. Since at least two pixels 02 can share the same light emission control circuit 021, if the at least two pixels 02 are arranged in the same row, correspondingly, the number of light emission control circuits 021 that need to be installed can be reduced, and if the at least two pixels 02 are arranged in the same column, correspondingly, the number of light emission control circuits 021 that need to be installed and the number of light emission control lines that need to be installed can be reduced. In this way, the effect of optimizing the pixel space can be achieved without affecting the normal display of pixel 02, that is, the area occupied by pixel 02 on the base substrate 01 becomes smaller compared to related technologies. Furthermore, the area of ​​surplus space on the base substrate 01 can be increased, and this surplus space can be used to reliably install the gate drive circuit 03 and the drive signal lines necessary for connection to the gate drive circuit 03. As a result, a display substrate in which the gate drive circuit 03 is provided within the substrate (gate drive in array, GIA), i.e., a GIA display substrate, can be obtained.

[0027] As can be seen by referring to Figure 2, in each pixel 02, the light emission control circuit 021 may be connected to the light emission drive circuit 022, and the light emission drive circuit 022 may be connected to the light-emitting element 023. The light emission control circuit 021 can be used to output a DC power supply signal to the connected light emission drive circuit 022 in response to a light emission control signal provided from a connected light emission control line. The light emission drive circuit 022 can be used to drive the light-emitting element 023 to emit light by outputting a drive signal to the connected light-emitting element 023 in response to a gate drive signal provided from a connected gate line and the received DC power supply signal.

[0028] As described above, the embodiments of this disclosure provide a display board. In this display board, at least two pixels arranged on the base board can share a light emission control circuit for the same connected light emission control line. This reduces the number of light emission control circuits that need to be installed on the display board, and also reduces the number of light emission control lines that need to be installed on the display board, ultimately reducing the area that each pixel occupies on the base board. Furthermore, a gate drive circuit that provides signals to signal lines connected to pixels and a drive signal line connected to the gate drive circuit can be provided on the base board. The display board according to the embodiments of this disclosure has high resolution.

[0029] As one option, as can be seen with reference to Figure 2, in the embodiment of this disclosure, at least two pixels 02 that share the same light emission control circuit 021 may be arranged in the same row. In this way, according to the above embodiment, it is possible to reduce not only the number of light emission control circuits 021 that need to be installed on the base substrate 01, but also the number of light emission control lines that need to be installed on the base substrate 01, compared to related technologies.

[0030] For example, assuming that the display board contains m rows of pixels 02, if at least two pixels 02 arranged in the same column share the same light emission control circuit 021, then the number of light emission control lines provided on the base board 01 is less than the number of rows of pixels 02. That is, in Figure 2, n is less than m, where both m and n may be integers greater than 1.

[0031] As an option, at least two pixels 02 that share the same light emission control circuit 021 may not only be arranged in the same row, but may also be adjacent to each other. This would facilitate layout and signal routing.

[0032] For example, Figure 3 shows another display board, taking the case where two adjacent pixels 02 arranged in the same column share the same light emission control circuit 021. Figure 3 schematically shows that adjacent pixels 02 in the nth row and pixels 02 in the (n+1)th row share the same light emission control circuit 021, and adjacent pixels 02 in the (n+2)th row and pixels 02 in the (n+3)th row also share the same light emission control circuit 021. As can be seen by referring to Figure 3, when two pixels 02 that share the same light emission control circuit 021 are arranged in the same column, two adjacent pixels 02 can also share the same light emission control line (e.g., EMn and EM(n+1)).

[0033] As one option, referring to Figure 3, we take as an example two adjacent pixels 02 in the nth row and pixel 02 in the (n+1)th row, where the first column is located. Figure 4 shows a selectable circuit diagram for these two pixels 02, and Figure 5 shows a layout diagram of the selectable circuit for these two pixels 02. Referring to Figures 3 to 5, in the embodiments of this disclosure, two pixels 02 sharing the same light emission control circuit 021 can be arranged symmetrically on both sides of the light emission control line EMn connected to the shared light emission control circuit 021. That is, each transistor and connected signal line in one of the two pixels 02, and each transistor and connected signal line in the other pixel 02, can be symmetrically placed on both sides of the light emission control line EMn. This design not only makes layout and signal routing easier, but also allows for the centralized placement of signal lines and further optimizes the pixel space.

[0034] Referring further to Figures 4 and 5, in embodiments of the present disclosure, the display substrate may further include a plurality of data lines arranged on the base substrate 01 in order to reliably drive the light-emitting element 023 included in the pixel 02 to emit light. The plurality of gate lines may include a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines.

[0035] Here, the number of data lines may be the same as the number of pixel columns, and the number of first gate lines, second gate lines, and third gate lines may all be the same as the number of pixel rows. Figures 4 and 5 show only one data line D1, two first gate lines G1n and G1(n+1), two second gate lines G2n and G2(n+1), and two third gate lines G3n and G3(n+1).

[0036] Continuing to refer to Figures 4 and 5, in each pixel 02, the light emission control circuit 021 may include a light emission control transistor T1. The light emission drive circuit 022 may include a data writing transistor T2, a reset transistor T3, a drive transistor T4, a compensation transistor T5, and a storage capacitor C1.

[0037] The gate of the data writing transistor T2 can be connected to one first gate line, the first pole can be connected to the gate of the drive transistor T4, and the second pole can be connected to one data line D1. Here, the gate of the data writing transistor T2 at pixel 02 in row n is connected to the first gate line G1n, and the gate of the data writing transistor T2 at pixel 02 in row n+1 is connected to the first gate line G1(n+1).

[0038] The first pole of the drive transistor T4 can be connected to the first pole of the light-emitting control transistor T1, and the second pole can be connected to the light-emitting element 023, which can also be connected to the power supply terminal VSS.

[0039] The gate of the light emission control transistor T1 can be connected to a single light emission control line EMn, and the second pole of the light emission control transistor T1 can be connected to the DC power supply terminal VDD.

[0040] The gate of reset transistor T3 can be connected to one second gate line, the first pole can be connected to the first initial signal terminal Vin1, and the second pole can be connected to the second pole of drive transistor T4. Here, the gate of reset transistor T3 at pixel 02 in row n is connected to the second gate line G2n, and the gate of reset transistor T3 at pixel 02 in row n+1 is connected to the second gate line G2(n+1).

[0041] The gate of the compensating transistor T5 can be connected to one third gate line, the first pole can be connected to the second initial signal terminal Vin2, and the second pole can be connected to the gate of the driving transistor T4. Here, the gate of the compensating transistor T5 at pixel 02 in row n is connected to the third gate line G3n, and the gate of the compensating transistor T5 at pixel 02 in row n+1 is connected to the third gate line G3(n+1).

[0042] The above is a schematic representation of the selectable structure of pixel 02, which is a 5T1C (i.e., five transistors and one capacitor) structure. Of course, the embodiments of this disclosure do not limit the structure of pixel 02, and other structures such as a 7T1C structure may also be used.

[0043] The following embodiment illustrates a selectable structure for a display board, using as an example a case where two adjacent pixels 02 arranged in the same row share the same light-emitting control circuit 021.

[0044] As one option, in the embodiment of this disclosure, each drive signal line connected to the gate drive circuit 03 can be placed between two adjacent rows of pixels 02. For example, referring to Figure 6, another display board is shown in which two adjacent pixels 02 arranged in the same row share the same light emission control circuit 021, so that extra areas such as areas 5 and 6 shown in Figure 6 can be left between two adjacent rows of pixels 02. Correspondingly, the drive signal lines connected to the gate drive circuit 03 can be placed in areas 5 and 6.

[0045] As one option, since the area between two adjacent rows of pixels 02 is limited, a maximum of two drive signal lines can be placed between two adjacent rows of pixels 02 to ensure reliable placement of the drive signal lines.

[0046] In embodiments of the present disclosure, the gate drive circuit 03 may include a plurality of cascaded shift register units 031. At least two cascaded shift register units 031 can be positioned between two adjacent rows of pixels 02.

[0047] For example, referring further to Figure 6, since the same light emission control circuit 021 is shared for every two adjacent pixels 02 located in the same column, it is possible to leave extra regions between two adjacent rows of pixels 02, such as regions 1, 2, 3, and 4 shown in Figure 6. Correspondingly, at least two cascaded shift register units 031 can be installed in regions 1 to 4 between two adjacent rows of pixels 02.

[0048] Furthermore, to facilitate signal routing, as shown in Figure 6, at least two cascaded shift register units 031 can be placed between two adjacent rows of target pixels 02. Of these two rows of target pixels 02, the light emission control circuit connected to one row of target pixels 02 is different from the light emission control circuit connected to the other row of target pixels 02. That is, at least two cascaded shift register units 031 can be placed between two rows of pixels 02 that do not share a light emission control circuit 021.

[0049] As one option, Figure 7 is a schematic diagram of yet another display board according to an embodiment of the present disclosure. As shown in Figure 7, only two cascaded shift register units 031 may be provided between two adjacent rows of target pixels 02. Here, one shift register unit 031 may be connected to one row of target pixels 02, and the other shift register unit 031 may be connected to another row of target pixels 02 (not shown in Figure 7).

[0050] As an option, the two cascaded shift register units 031 may be arranged symmetrically between the two rows of target pixels. That is, each transistor in one shift register unit 031 may be arranged symmetrically with each transistor in the other shift register unit 031. In this way, some drive signal lines (e.g., power supply signals that supply DC signals) can be shared, further optimizing the GIA space, i.e., reducing the area of ​​the base board 01 required for the shift register units 031.

[0051] Figure 8 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure. As shown in Figure 10, the shift register unit 031 may include an input subcircuit 0311, a pull-down control subcircuit 0312, a pull-down subcircuit 031, and an output subcircuit 0314.

[0052] The input subcircuit 0311 can be connected to the first input terminal IN1, the second input terminal IN2, the first control signal terminal CN, the second control signal terminal CNB, and the pull-up node PU, respectively. The input subcircuit 0311 can be used to output the first control signal provided by the first control signal terminal CN to the pull-up node PU in response to the first input signal provided by the first input terminal IN1, and to output the second control signal provided by the second control signal terminal CNB to the pull-up node PU in response to the second input signal provided by the second input terminal IN2.

[0053] For example, the input subcircuit 0311 may output the first control signal provided from the first control signal terminal CN to the pull-up node PU when the potential of the first input signal provided from the first input terminal IN1 is a first potential, and may output the second control signal provided from the second control signal terminal CNB to the pull-up node PU when the potential of the second input signal provided from the second input terminal IN2 is a first potential.

[0054] As an option, the first input terminal IN1 may be connected to the output terminal of the upper shift register unit 031, and the second input terminal IN2 may be connected to the output terminal of the lower shift register unit 031. The potentials of the first control signal and the second control signal are complementary. That is, if the potential of the first control signal is the first potential, the potential of the second control signal is the second potential, and if the potential of the first control signal is the second potential, the potential of the second control signal is the first potential. Here, the first potential may be an active potential, and the second potential may be an active potential. If the transistor is an N-type transistor, the first potential may be higher than the second potential, and if the transistor is a P-type transistor, the first potential may be lower than the second potential.

[0055] Furthermore, since the first-stage shift register unit 031 does not have an upper-stage shift register unit 031, and the final-stage shift register unit 031 does not have a lower-stage shift register unit 031, in order to ensure the normal operation of the gate drive circuit 03, the first-stage shift register unit 031 and the final-stage shift register unit 031 may be connected to an initial signal terminal. This initial signal terminal may be used to provide an initial signal at a first potential to a first input terminal IN1 connected to the first-stage shift register unit 031, or to provide an initial signal at a first potential to a second input terminal IN2 connected to the final-stage shift register unit 031. As a result, the normal operation of the first-stage shift register unit 031 and the final-stage shift register unit 031 is ensured.

[0056] The pull-down control subcircuit 0312 can be connected to the first clock signal terminal CK, the pull-up node PU, the pull-down power supply terminal VGL, the pull-down node PD, and the output terminal OUT, respectively. The pull-down control subcircuit 0312 can be used to output the first clock signal to the pull-down node PD in response to the first clock signal provided from the first clock signal terminal CK, and to output the pull-down power supply signal provided from the pull-down power supply terminal VGL to the pull-down node PD in response to the potential of the pull-up node PU and the output signal provided from the output terminal OUT.

[0057] For example, the pull-down control subcircuit 0312 can charge the pull-down node PD by outputting the first clock signal provided from the first clock signal terminal CK to the pull-down node PD when the potential of the first clock signal is the first potential. The pull-down control subcircuit 0312 may also reduce noise for the pull-down node PD by outputting the pull-down power supply signal provided from the pull-down power supply terminal VGL to the pull-down node PD when the potential of the pull-up node PU is the first potential, and the potential of the pull-down power supply signal may be the second potential. Furthermore, the pull-down control subcircuit 0312 can reduce noise for the pull-down node PD by outputting the pull-down power supply signal to the pull-down node PD when the potential of the output signal provided from the output terminal OUT is the first potential.

[0058] The pull-down subcircuit 0313 can be connected to the reset signal terminal RST, the pull-down node PD, the pull-down power terminal VGL, the pull-up node PU, and the output terminal OUT, respectively. The pull-down subcircuit 0313 can be used to output a pull-down power signal to the pull-up node PU and the output terminal OUT in response to the potential of the pull-down node PD, and to output a pull-down power signal to the pull-up node PU in response to a reset signal provided from the reset signal terminal RST.

[0059] For example, the pull-down subcircuit 0313 can reduce noise to the pull-up node PU and output terminal OUT by outputting the pull-down power supply signal to the pull-up node PU and output terminal OUT when the potential of the pull-down node PD is the first potential. Furthermore, when the potential of the reset signal provided from the reset signal terminal RST is the first potential, it can reduce noise to the pull-up node PU by outputting the pull-down power supply signal to the pull-up node PU.

[0060] The output subcircuit 0314 can be connected to the pull-up node PU, the second clock signal terminal CKB, and the output terminal OUT, respectively. The output subcircuit 0314 can be used to output the second clock signal provided from the second clock signal terminal CKB to the output terminal OUT in response to the potential of the pull-up node PU.

[0061] For example, the output subcircuit 0314 may output a second clock signal provided from the second clock signal terminal CKB to the output terminal OUT when the potential of the pull-up node PU is at the first potential. This second clock signal may be provided to the gate line as a gate drive signal, or to the light emission control line as a light emission control signal.

[0062] Figure 9 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in Figure 9, the input subcircuit 0311 may include a first input transistor M1 and a second input transistor M2. The pull-down control subcircuit 0312 may include a first pull-down control transistor M3, a second pull-down control transistor M4, and a third pull-down control transistor M5. The pull-down subcircuit 0313 may include a first pull-down transistor M6, a second pull-down transistor M7, a third pull-down transistor M8, and a pull-down capacitor C2. The output subcircuit 0314 may include an output transistor M9 and an output capacitor C3.

[0063] Here, the gate of the first input transistor M1 may be connected to the first input terminal IN1, the first pole may be connected to the first control signal terminal CN, and the second pole may be connected to the pull-up node PU. Correspondingly, when the potential of the first input signal provided from the first input terminal IN1 is a first potential, the first input transistor M1 can charge the pull-up node PU by outputting the first control signal provided from the first control signal terminal CN to the pull-up node PU.

[0064] The gate of the second input transistor M2 may be connected to the second input terminal IN2, the first pole may be connected to the second control signal terminal CNB, and the second pole may be connected to the pull-up node PU. Correspondingly, when the potential of the second input signal provided from the second input terminal IN2 is the first potential, the second input transistor M2 can reset the pull-up node PU by outputting the second control signal provided from the second control signal terminal CNB to the pull-up node PU.

[0065] The gate and first pole of the first pull-down control transistor M3 may both be connected to the first clock signal terminal CK, and the second pole may be connected to the pull-down node PD. Correspondingly, the first pull-down control transistor M3 can charge the pull-down node PD by outputting the first clock signal to the pull-down node PD when the potential of the first clock signal provided from the first clock signal terminal CK is the first potential.

[0066] The gate of the second pull-down control transistor M4 may be connected to the pull-up node PU, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-down node PD. Correspondingly, when the potential of the pull-up node PU is the first potential, the second pull-down control transistor M4 can reduce noise for the pull-down node PD by outputting the pull-down power supply signal to the pull-down node PD.

[0067] The gate of the third pull-down control transistor M5 may be connected to the output terminal OUT, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-down node PD. Correspondingly, when the potential of the output signal provided from the output terminal OUT is the first potential, the third pull-down control transistor M5 can reduce noise to the pull-down node PD by outputting the pull-down power supply signal to the pull-down node PD.

[0068] The gate of the first pull-down transistor M6 may be connected to the reset signal terminal RST, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-up node PU. Correspondingly, when the potential of the reset signal provided from the reset signal terminal RST is the first potential, the first pull-down transistor M6 can reduce noise for the pull-up node PU by outputting the pull-down power supply signal provided from the pull-down power supply terminal VGL to the pull-up node PU.

[0069] The gates of the second pull-down transistor M7 and the third pull-down transistor M8 may both be connected to the pull-down node PD, the first pole of the second pull-down transistor M7 and the first pole of the third pull-down transistor M8 may both be connected to the pull-down power supply terminal VGL, the second pole of the second pull-down transistor M7 may be connected to the pull-up node PU, and the second pole of the third pull-down transistor M8 may be connected to the output terminal OUT. Correspondingly, when the potential of the pull-down node PD is at the first potential, the second pull-down transistor M7 can reduce noise to the pull-up node PU by outputting the pull-down power supply signal to the pull-up node PU. When the potential of the pull-down node PD is at the first potential, the third pull-down transistor M8 can reduce noise to the output terminal OUT by outputting the pull-down power supply signal to the output terminal OUT.

[0070] One end of the pull-down capacitor C2 may be connected to the pull-down node PD, and the other end may be connected to the pull-down power supply terminal VGL. The pull-down capacitor C2 can be used to maintain the potential of the pull-down node PD.

[0071] One end of the output capacitor C3 may be connected to the pull-up node PU, and the other end may be connected to the output terminal OUT. The output capacitor C3 can be used to maintain the potential of the pull-up node PU.

[0072] The gate of output transistor M9 may be connected to a pull-up node PU, the first pole may be connected to the second clock signal terminal CKB, and the second pole may be connected to the output terminal OUT.

[0073] Correspondingly, with respect to the gate drive circuit 03 to which the shift register unit 031 shown in Figures 7 and 8 belongs, the drive signal lines connected to the gate drive circuit 03 include a signal line connected to the first control signal terminal CN, a signal line connected to the second control signal terminal CNB, a signal line connected to the reset signal terminal RST, a signal line connected to the first clock signal terminal CK, a signal line connected to the second clock signal terminal CKB, a signal line connected to the pull-down power supply terminal VGL, and a signal line connected to the initial signal terminal. Referring to the embodiment in Figure 8, the initial signal terminal is connected to the first input terminal IN1 connected to the first stage shift register unit 031 and the second input terminal IN2 connected to the final stage shift register unit 031, respectively. In this way, when two shift register units 031 are arranged symmetrically between two rows of target pixels 02, the two shift register units 031 can share a signal line connected to a single pull-down power supply terminal VGL.

[0074] Referring further to Figure 10, using the shift register unit 031 shown in Figure 8 as an example, the circuit structure of the shift register unit 031 placed between two adjacent rows of pixels 02 and the selectable placement positions of the drive signal lines (e.g., signal lines STV connected to the initial signal terminal) are shown. As can be seen by referring to Figures 6 to 9, during layout, relatively large transistors in the shift register unit 031 can be placed in the relatively large area regions 1 and 2, and relatively small transistors in the shift register unit 031 can be placed in the relatively small area regions 3 and 4. Furthermore, referring further to Figure 10, two transistors can be connected in series to form one transistor (e.g., two transistors M7 shown in Figure 10), or two capacitors can be connected in series to form one capacitor (e.g., two capacitors C2 and two capacitors C3 shown in Figure 10), thereby ensuring that all transistors in the shift register unit 031 can be placed within the limited space of the base board 01.

[0075] When the area of ​​the base substrate 01 is determined, compared to related technologies that do not share the light emission control circuit 021, the embodiments of this disclosure are configured such that at least two pixels 02 share the same light emission control circuit 021, thereby increasing the area of ​​the region on the base substrate 01 other than the region where the pixels 02 are located. This provides effective technical support for arranging the gate drive circuit 03 on the base substrate 01, i.e., provides technical support for high-resolution (per pixel inch, PPI) GIA display substrates.

[0076] Assuming that all transistors in pixel 02 are N-type transistors, the operating principle of the pixel according to the embodiment of this disclosure will be explained with reference to two adjacent pixels 02 that share the same light emission control circuit 021 shown in Figure 4, and Figure 11 is an operating timing chart of the pixel according to the embodiment of this disclosure.

[0077] Referring to Figure 11, in stage t1, at the nth row pixel 02, the second gate line G2n connected to the reset transistor T3 provides a gate drive signal at the first potential, turning on the reset transistor T3. The third gate line G3n connected to the compensation transistor T5 also provides a gate drive signal at the first potential, turning on the compensation transistor T5. Correspondingly, the first initial signal terminal Vin1 outputs the first initial signal at the second potential via the reset transistor T3 to the second pole of the drive transistor T4 at the nth row pixel 02, thereby achieving a reset of the second pole of the drive transistor T4. The second initial signal terminal Vin2 outputs the second initial signal via the compensation transistor T5 to the gate of the drive transistor T4 at the nth row pixel 02, and the second initial signal may be compensation data Vref1. Stage t1 is also called the reset stage when driving the nth row pixel 02.

[0078] In stage t2, at pixel 02 of row n, the third gate line G3n connected to the compensation transistor T5 continues to provide a gate drive signal at the first potential. The compensation transistor T5 remains on. The second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the drive transistor T4 at pixel 02 of row n via the compensation transistor T5. Coupling by the storage capacitor C1 allows the gate potential of the drive transistor T4 to change according to the potential of the second pole of the drive transistor T4 until it becomes Vref1-Vth1, where Vth1 is the threshold voltage of the drive transistor T4. Stage t2 may also be called the compensation stage when driving pixel 02 of row n.

[0079] In stage t3, at pixel 02 of the nth row, the first gate line G1n connected to the data writing transistor T2 begins to provide a gate drive signal at a first potential, and the data writing transistor T2 turns on. The data line D1 outputs the data signal to the gate of the driving transistor T4 via the data writing transistor T2. Stage t3 may also be called the data writing stage when driving pixel 02 of the nth row.

[0080] In stage t4, at pixel 02 of the (n+1) row, the second gate line G2(n+1) connected to the reset transistor T3 provides a gate drive signal at the first potential, and the reset transistor T3 turns on. The third gate line G3(n+1) connected to the compensation transistor T5 also provides a gate drive signal at the first potential, and the compensation transistor T5 turns on. Correspondingly, the first initial signal terminal Vin1 outputs the first initial signal at the second potential to the second pole of the drive transistor T4 at pixel 02 of the (n+1) row via the reset transistor T3, thereby achieving a reset of the second pole of the drive transistor T4. The second initial signal terminal Vin2 can output the second initial signal to the gate of the drive transistor T4 at pixel 02 of the (n+1) row via the compensation transistor T5, and the second initial signal may be the compensation data Vref2 when driving the pixel of that row. Stage t4 may also be called the reset stage when driving pixel 02 of the (n+1) row.

[0081] In stage t5, at pixel 02 of row (n+1), the third gate line G3(n+1) connected to the compensation transistor T5 continues to provide a gate drive signal at the first potential. The compensation transistor T5 remains on. The second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the drive transistor T4 at pixel 02 of row (n+1) via the compensation transistor T5. Due to the coupling of the storage capacitor C1 at pixel 02 of that row, the gate potential of the drive transistor T4 at pixel 02 of that row can change according to the potential of its second pole until Vref2-Vth2, where Vth2 is the threshold voltage of the drive transistor T4. Stage t5 may also be called the compensation stage when driving pixel 02 of row (n+1).

[0082] In step t6, at pixel 02 of the (n+1) row, the first gate line G1(n+1) connected to the data writing transistor T2 begins to provide a gate drive signal at a first potential, and the data writing transistor T2 turns on. The data line D1 can output a data signal to the gate of the drive transistor T4 at pixel 02 of that row via the data writing transistor T2. Step t6 may also be called the data writing step when driving pixel 02 of the (n+1) row.

[0083] Referring to Figure 10, in steps t1, t2, t4, and t5, the light emission control line EMn connected to the light emission control transistor T1 shared by the nth row pixel 02 and the (n+1)th row pixel 02 provides a light emission control signal that is always at the first potential. The DC power supply terminal VDD can output the DC power supply signal via the light emission control transistor T1 to the first pole of the drive transistor T4 included in each row of the two rows of pixels 02. After step t3, in the nth row pixel 02, the drive transistor T4 can drive the nth row light-emitting element 023 to emit light by outputting a drive signal to the connected light-emitting element 023 based on the DC power supply signal and the data signal. After step t6, in the (n+1)th row pixel 02, the drive transistor T4 can drive the (n+1)th row light-emitting element 023 to emit light by outputting a drive signal to the connected light-emitting element 023 based on the DC power supply signal and the data signal.

[0084] As described above, the embodiments of this disclosure provide a display board. In this display board, at least two pixels arranged on the base board can share a light emission control circuit for the same connected light emission control line. This reduces the number of light emission control circuits that need to be installed on the display board, and also reduces the number of light emission control lines that need to be installed on the display board, ultimately reducing the area that each pixel occupies on the base board. Furthermore, a gate drive circuit that provides signals to signal lines connected to pixels and a drive signal connected to the gate drive circuit can be provided on the base board. The display board according to the embodiments of this disclosure has high resolution.

[0085] Figure 12 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 12, the display device may include a source drive circuit 100 and a display board 000 shown in any of Figures 1 to 3, 6, 7, and 10.

[0086] Here, the source drive circuit 100 can be connected to a plurality of data lines D1 through Dm on the display board 000, and the source drive circuit 100 can be used to provide data signals to each data line.

[0087] Figure 12 shows a gate drive circuit 03, multiple first gate lines G11 to G1m, multiple second gate lines G21 to G2m, multiple third gate lines G3 to G3m, and multiple light emission control lines EM1 to EMn included in the display board 000. The gate drive circuit 03 can be connected to the multiple first gate lines G11 to G1m, multiple second gate lines G21 to G2m, multiple third gate lines G3 to G3m, and multiple light emission control lines EM1 to EMn. The gate drive circuit 03 can provide gate drive signals to the multiple first gate lines G11 to G1m, multiple second gate lines G21 to G2m, and multiple third gate lines G3 to G3m, and can also provide light emission control drive signals to the multiple light emission control lines EM1 to EMn.

[0088] As one option, in the embodiments of this disclosure, in order to reliably provide drive signals to a plurality of first gate lines G11 to G1m, a plurality of second gate lines G21 to G2m, a plurality of third gate lines G3 to G3m, and a plurality of light emission control lines EM1 to EMn, the gate drive circuit 03 may actually include four gate drive circuits: a gate drive circuit for providing a gate drive signal to the first gate lines, a gate drive circuit for providing a gate drive signal to the second gate lines, a gate drive circuit for providing a gate drive signal to the third gate lines, and a gate drive circuit for providing a light emission control drive signal to the light emission control lines. Referring to Figure 7, each gate drive circuit may consist of at least two cascaded shift register units 031, and each shift register unit 031 may be connected to a corresponding signal line (e.g., a first gate line).

[0089] As one option, the display device may be any product or component with display capabilities, such as an OLED display device, e-paper, mobile phone, tablet computer, television, display, laptop computer, or digital photo frame.

[0090] It should be understood that "multiple" as used herein means two or more. The foregoing are merely optional embodiments of the Disclosure and do not limit the Disclosure, and any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the Disclosure shall be included within the scope of the Disclosure. [Explanation of Symbols]

[0091] 000 Display board 01 Base board 02 pixels 021 Light emission control circuit 022 Light-emitting drive circuit 023 Light-emitting element 03 Gate drive circuit 031 Shift Register Unit 0311 Input Sub-circuit 0312 Pull-down control sub-circuit 0313 Pull-down sub-circuit 0314 Output Sub-circuit 100 Source Drive Circuit

Claims

1. Base board and The base substrate is arranged in an array, each of which includes a light emission control circuit, a light emission driving circuit, and a light-emitting element, and at least two of them share the same light emission control circuit and a plurality of pixels, The base substrate includes a gate drive circuit, a plurality of light emission control lines, a plurality of gate lines, and a plurality of drive signal lines, Includes, The gate drive circuit is connected to the plurality of drive signal lines, the plurality of light emission control lines, and the plurality of gate lines, respectively, the plurality of light emission control lines are connected to the light emission control circuit included in each of the pixels, the plurality of gate lines are connected to the light emission drive circuit included in each of the pixels, the gate drive circuit is used to output a light emission control signal to the plurality of light emission control lines and a gate drive signal to the plurality of gate lines in response to drive signals provided from the plurality of drive signal lines, and the gate drive circuit includes a plurality of cascaded shift register units. Display board.

2. At least two cascaded shift register units are positioned between two adjacent rows of pixels, The display board according to claim 1.

3. At least two cascaded shift register units are positioned between two adjacent rows of target pixels. Of the two rows of target pixels, the light emission control circuit connected to one row of target pixels is different from the light emission control circuit connected to the target pixels of the other row. The display board according to claim 2.

4. Two cascaded shift register units are provided between two adjacent rows of target pixels. Here, one shift register unit is connected to the target pixels of one row, and the other shift register unit is connected to the target pixels of the other row. The display board according to claim 3.

5. The display board according to claim 4, wherein the two cascaded shift register units are arranged symmetrically between the two rows of target pixels.

6. The shift register unit includes an input subcircuit, a pull-down control subcircuit, a pull-down subcircuit, and an output subcircuit. The input subcircuit is connected to a first input terminal, a second input terminal, a first control signal terminal, a second control signal terminal, and a pull-up node, respectively. The input subcircuit is used to output a first control signal provided by the first control signal terminal to the pull-up node in response to a first input signal provided by the first input terminal, and to output a second control signal provided by the second control signal terminal to the pull-up node in response to a second input signal provided by the second input terminal. The pull-down control subcircuit is connected to the first clock signal terminal, the pull-up node, the pull-down power supply terminal, the pull-down node, and the output terminal, respectively. The pull-down control subcircuit is used to output the first clock signal to the pull-down node in response to the first clock signal provided from the first clock signal terminal, and to output the pull-down power supply signal provided from the pull-down power supply terminal to the pull-down node in response to the potential of the pull-up node and the output signal provided from the output terminal. The pull-down subcircuit is connected to the reset signal terminal, the pull-down node, the pull-down power supply terminal, the pull-up node, and the output terminal, respectively, and is used to output the pull-down power supply signal to the pull-up node and the output terminal in response to the potential of the pull-down node, and to output the pull-down power supply signal to the pull-up node in response to the reset signal provided from the reset signal terminal. The output subcircuit is connected to the pull-up node, the second clock signal terminal, and the output terminal, respectively, and the output subcircuit is used to output the second clock signal provided from the second clock signal terminal to the output terminal in response to the potential of the pull-up node. The display board according to claim 2.

7. The display board further includes a plurality of data lines arranged on the base board, The plurality of gate lines include a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines; the light emission control circuit includes a light emission control transistor; and the light emission drive circuit includes a data writing transistor, a reset transistor, a drive transistor, a compensation transistor, and a storage capacitor. The gate of the data writing transistor is connected to one of the first gate lines, the first pole is connected to the gate of the drive transistor, and the second pole is connected to one of the data lines, the first pole of the drive transistor is connected to the first pole of the light emission control transistor, and the second pole is connected to the light emission element, the gate of the light emission control transistor is connected to one of the light emission control lines, and the second pole is connected to the DC power supply terminal, the gate of the reset transistor is connected to one of the second gate lines, the first pole is connected to the first initial signal terminal, and the second pole is connected to the second pole of the drive transistor, the gate of the compensation transistor is connected to one of the third gate lines, the first pole is connected to the second initial signal terminal, and the second pole is connected to the gate of the drive transistor. A display board according to any one of claims 1 to 6.

8. Each of the aforementioned drive signal lines is arranged between two adjacent rows of pixels, and a maximum of two of the aforementioned drive signal lines are provided between two adjacent rows of pixels. Two cascaded shift register units are provided between two adjacent rows of target pixels, and the two cascaded shift register units are arranged symmetrically between the two rows of target pixels, where one shift register unit is connected to the target pixels of one row, and the other shift register unit is connected to the target pixels of the other row, and the light emission control circuit connected to the target pixels of one row of the two rows differs from the light emission control circuit connected to the target pixels of the other row. The display board further includes a plurality of data lines arranged on the base board, the plurality of gate lines including a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines, the light emission control circuit includes a light emission control transistor, and the light emission drive circuit includes a data writing transistor, a reset transistor, a drive transistor, a compensation transistor, and a storage capacitor. The gate of the data writing transistor is connected to one of the first gate lines, the first pole is connected to the gate of the drive transistor, and the second pole is connected to one of the data lines, the first pole of the drive transistor is connected to the first pole of the light emission control transistor, and the second pole is connected to the light emission element, the gate of the light emission control transistor is connected to one of the light emission control lines, and the second pole is connected to the DC power supply terminal, the gate of the reset transistor is connected to one of the second gate lines, the first pole is connected to the first initial signal terminal, and the second pole is connected to the second pole of the drive transistor, the gate of the compensation transistor is connected to one of the third gate lines, the first pole is connected to the second initial signal terminal, and the second pole is connected to the gate of the drive transistor. The display board according to claim 6.

9. Each of the drive signal lines is arranged between two adjacent rows of pixels, as described in any one of claims 1 to 6.

10. The display board according to claim 9, wherein up to two drive signal lines are provided between two adjacent rows of pixels.

11. The circuit includes a source drive circuit and a display board according to any one of claims 1 to 10, The source drive circuit is connected to a plurality of data lines on the display board, and the source drive circuit is used to provide data signals to each of the data lines. Display device.

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