Electronic device having transistors stacked vertically on a substrate

Abstract

To provide electronic devices that increase performance, reliability, and IC device density. [Solution] In an integrated circuit (IC), the gate structure 151 includes a first surface facing a second surface. A first semiconductor layer 144 is arranged between the first surface of the gate structure and the lower dielectric structure 126. A second semiconductor layer 146 is located on the second surface of the gate structure. In an electronic device including first and second gate electrodes 136 within a dielectric layer 150 on a substrate, the first and second gate electrodes overlap one or more conductive wiring structures. A gate dielectric layer 148 overlaps the first and second gate electrodes. The first semiconductor layer is arranged on a gate dielectric layer above the first gate electrode, and the second semiconductor layer is arranged on a gate dielectric layer above the second gate electrode. A first source / drain structure pair 132, 134 is arranged on the first semiconductor layer, and a second source / drain structure pair 140, 142 is arranged on the second semiconductor layer.

Description

[Background technology]

[0001] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As ICs evolve, the size of semiconductor devices (e.g., transistor area) is scaled down, for example, by reducing the minimum feature size and / or the lateral spacing between adjacent semiconductor devices. This has led to an increase in device density (e.g., the number of semiconductor devices integrated into a given area). However, as lateral spacing between adjacent semiconductor devices continues to shrink, it is becoming increasingly difficult to increase device density without negatively impacting semiconductor device performance. Therefore, advancements in the IC manufacturing industry that increase device density without negatively impacting semiconductor device performance are desired. [Overview of the project] [Problems that the invention aims to solve]

[0002] In back-end-of-line (BEOL) structures, forming n-channel and p-channel transistors adjacent to each other laterally can present challenges. For example, forming a p-type semiconductor layer may involve performing deposition and / or doping processes at relatively high temperatures (e.g., temperatures above 400°C), which can damage underlying conductive wiring structures, underlying front-end-of-line (FEOL) devices / structures, and / or other devices arranged within the BEOL structure (e.g., capacitors, memory devices). This can result in reduced IC yield and / or reliability. Furthermore, in efforts to reduce the lateral footprint of electronic devices and increase device density, the lateral distance between p-type and n-type semiconductor layers is relatively small. However, one or more elements within the p-type semiconductor layer may easily diffuse or migrate into the n-type semiconductor layer due to the relatively small lateral distance and / or interaction with the dielectric material between the n-type and p-type semiconductor layers. This can reduce the performance of n-channel transistors and / or p-channel transistors (e.g., reduced carrier mobility, changes in threshold voltage, etc.), potentially degrading the overall performance of the electronic device. [Means for solving the problem]

[0003] In efforts to increase device density on a substrate, transistors in an electronic device may be arranged within back-of-line (BEOL) structures on the substrate. For example, an electronic device may include a first gate electrode and a second gate electrode within a dielectric layer on the substrate, with the first and second gate electrodes overlapping one or more conductive wiring structures. The gate dielectric layer overlaps the first and second gate electrodes. An n-type semiconductor layer is arranged on the gate dielectric layer on the first gate electrode, and a p-type semiconductor layer is arranged on the gate dielectric layer on the second gate electrode. A first source / drain structure pair is arranged on the n-type semiconductor layer, and a second source / drain structure pair is arranged on the p-type semiconductor layer. The first gate electrode, the n-type semiconductor layer, the first segment of the gate dielectric layer, and the first source / drain structure pair define an n-channel transistor. The second gate electrode, the p-type semiconductor layer, the second segment of the gate dielectric layer, and the second source / drain structure pair define a p-channel transistor. The n-channel transistor is directly adjacent to the p-channel transistor in the lateral direction. [Effects of the Invention]

[0004] Because the n-channel transistor is stacked vertically on top of the p-channel transistor, the lateral footprint of the electronic device is reduced, thereby increasing the device density of the IC. Furthermore, the first semiconductor layer of the p-channel transistor is offset vertically from the n-channel transistor by a relatively large distance. As a result, the diffusion of one or more elements from the first semiconductor layer to the second semiconductor layer is prevented or mitigated. In addition, the dielectric materials of the first and second dielectric layers may be different from each other and are selected to optimize the performance of the p-channel and n-channel transistors. Therefore, an electronic device including an n-channel transistor stacked vertically on top of a p-channel transistor increases the performance and reliability of the electronic device, as well as the device density of the IC. [Brief explanation of the drawing]

[0005] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0006] [Figure 1] Cross-sectional views of some embodiments of an integrated chip (IC) having an electronic device including transistors stacked perpendicular to each other on a semiconductor substrate are shown. [Figure 2] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3A] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3B] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3C] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3D] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3E] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3F] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3G] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 3H] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 4A] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 4B] Cross-sectional views of some other embodiments of the IC of FIG. 1 are shown. [Figure 5A] Cross-sectional views of some embodiments of an IC having an electronic device including transistors stacked in a perpendicular direction to each other in a first region of a semiconductor substrate and horizontally adjacent to a second region of the semiconductor substrate are shown. [Figure 5B]Another cross-sectional view of several embodiments of an IC having an electronic device including transistors stacked perpendicularly to each other in a first region of a semiconductor substrate and adjacent laterally to each other in a second region of the semiconductor substrate. [Figure 5C] The layout diagrams of several embodiments of the IC in Figure 5A are shown, cut along the line A-A' in Figure 5A. [Figure 5D] Another layout diagram of several embodiments of the IC in Figure 5A, cut along the line A-A' in Figure 5A, is shown. [Figure 6] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 7] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 8] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 9] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 10] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 11] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 12] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 13]The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 14] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 15] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 16] The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 17] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 18] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 19] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 20] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 21] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 22] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 23] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 24] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 25] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 26] The following are cross-sectional views of various cross-sectional views of several embodiments of a second method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 27] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 28] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 29] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 30] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 31] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 32] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 33] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 34] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 35] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 36] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 37] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 38] The images show cross-sectional views in various cross-sectional views of several embodiments of a third method for forming an IC having an electronic device including transistors stacked perpendicular to each other. [Figure 39] Flowcharts of several embodiments of a method for forming an IC having an electronic device including transistors stacked perpendicularly to each other are shown. [Modes for carrying out the invention]

[0007] The present invention provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features, resulting in the first and second features not being in direct contact. Furthermore, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not, in itself, define the relationships between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein for explanatory convenience to describe the relationship between one element or feature and another, as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or otherwise oriented), and the spatial relative descriptors used herein may be interpreted accordingly.

[0009] An integrated chip (IC) may include electronic devices. These electronic devices may be, for example, inverters, latches, logic gates, static random-access memory (SRAM), dynamic random-access memory (DRAM), or other suitable devices. The electronic device may include multiple semiconductor devices. These multiple semiconductor devices may consist of one or more n-channel transistors and one or more p-channel transistors, or include these, and are electrically coupled in a predefined manner to form the electronic device. Typically, the transistors of the electronic device are located within a front-end-of-line (FEOL) structure on / in the substrate and formed in a FEOL process.

[0010] As an effort to increase device density on a substrate, transistors in an electronic device may be arranged within back-of-line (BEOL) structures on the substrate. For example, an electronic device may include a first gate electrode and a second gate electrode within a dielectric layer on the substrate, with the first and second gate electrodes overlapping one or more conductive wiring structures. The gate dielectric layer overlaps the first and second gate electrodes. An n-type semiconductor layer is arranged on the gate dielectric layer above the first gate electrode, and a p-type semiconductor layer is arranged on the gate dielectric layer above the second gate electrode. A first source / drain structure pair is arranged on the n-type semiconductor layer, and a second source / drain structure pair is arranged on the p-type semiconductor layer. The first gate electrode, the n-type semiconductor layer, the first segment of the gate dielectric layer, and the first source / drain structure pair define an n-channel transistor. The second gate electrode, the p-type semiconductor layer, the second segment of the gate dielectric layer, and the second source / drain structure pair define a p-channel transistor. The n-channel transistor is directly adjacent to the p-channel transistor in the lateral direction.

[0011] In BEOL structures, forming n-channel and p-channel transistors laterally adjacent to each other can present challenges. For example, forming a p-type semiconductor layer may involve performing deposition and / or doping processes at relatively high temperatures (e.g., temperatures above 400°C), which can damage the underlying conductive wiring structure, the underlying FEOL device / structure, and / or other devices arranged within the BEOL structure (e.g., capacitors, memory devices). This can result in reduced IC yield and / or reliability. Furthermore, in efforts to reduce the lateral footprint of electronic devices and increase device density, the lateral distance between p-type and n-type semiconductor layers is relatively small. However, one or more elements within the p-type semiconductor layer may easily diffuse or migrate into the n-type semiconductor layer due to the relatively small lateral distance and / or interaction with the dielectric material between the n-type and p-type semiconductor layers. This can reduce the performance of the n-channel and / or p-channel transistors (e.g., reduced carrier mobility, changes in threshold voltage, etc.), thereby degrading the overall performance of the electronic device.

[0012] Various embodiments of the present invention relate to an integrated chip (IC) having an electronic device (e.g., an inverter) having transistors stacked perpendicularly to each other on a substrate to increase device density and the overall performance of the electronic device. The transistors of the electronic device include n-channel transistors and p-channel transistors on one or more conductive wiring structures on the substrate. The p-channel transistor includes a first source / drain structure pair on one or more conductive wiring structures, a first semiconductor layer on the first source / drain structure pair, and a first gate dielectric layer on the first semiconductor layer. The gate electrode overlaps the first gate dielectric layer. Furthermore, the n-channel transistor includes a second gate dielectric layer on the gate electrode, a second semiconductor layer on the second gate dielectric layer, and a second source / drain structure pair on the second semiconductor layer. The gate electrode is shared by the p-channel transistor and the n-channel transistor.

[0013] Because the n-channel transistor is stacked vertically on top of the p-channel transistor, the lateral footprint of the electronic device is reduced, thereby increasing the device density of the IC. Furthermore, the first semiconductor layer of the p-channel transistor is vertically offset from the n-channel transistor by a relatively large distance. As a result, the diffusion of one or more elements from the first semiconductor layer to the second semiconductor layer is prevented or mitigated. In addition, the dielectric materials of the first and second dielectric layers may be different from each other and are selected to optimize the performance of the p-channel and n-channel transistors. Therefore, an electronic device including an n-channel transistor stacked vertically on top of a p-channel transistor increases the performance and reliability of the electronic device, as well as the device density of the IC.

[0014] Figure 1 shows cross-sectional views 100 of several embodiments of an integrated chip (IC) having an electronic device 130 including transistors 131a and 131b stacked perpendicularly to each other.

[0015] The IC includes a front-end-of-line (FEOL) structure 104 disposed within and / or on a semiconductor substrate 102, and a back-end-of-line (BEOL) structure 106 on top of the FEOL structure 104. The semiconductor substrate 102 may be, or may include, a bulk substrate (e.g., bulk silicon), single-crystal silicon, silicon germanium (SiGe), silicon-on-insulator (SOI), etc. The FEOL structure 104 includes one or more lower semiconductor devices 108 on the semiconductor substrate 102, an interlayer dielectric (ILD) layer 124 on the semiconductor substrate 102, and one or more conductive contacts 118 within the ILD layer 124.

[0016] In some embodiments, one or more lower semiconductor devices 108 are configured as transistors such as metal oxide semiconductor field-effect transistors (MOSFETs), finFETs, and gate-all-around FETs (GAAFETs). In various embodiments, one or more lower semiconductor devices 108 each include a source / drain region pair 110 in a semiconductor substrate 102, a lower gate electrode 114 positioned laterally on the semiconductor substrate 102 and between the source / drain region pair 110, a lower gate dielectric 112 between the lower gate electrode 114 and the semiconductor substrate 102, and a sidewall spacer 116 positioned on the sidewalls of the lower gate electrode 114 and the lower gate dielectric 112. The source / drain region may refer to the source or drain individually or collectively, depending on the context. The semiconductor substrate 102 may have a first doping type (e.g., p-type). In some embodiments, the source / drain region pair 110 is a doped region of the semiconductor substrate 102 having a second doping type (e.g., n-type) opposite to the first doping type. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. One or more conductive contacts 118 overlap on the semiconductor substrate 102 and are electrically coupled to one or more underlying semiconductor devices 108.

[0017] The BEOL structure 106 is superimposed on the semiconductor substrate 102 and further includes a lower dielectric structure 126, a plurality of dielectric layers 128a to d, a plurality of conductive wires 120, and a plurality of conductive vias 122. The plurality of conductive wires 120 and the plurality of conductive vias 122 are configured to electrically couple the electronic device 130 to other semiconductor devices (e.g., one or more lower semiconductor devices 108 and / or devices on another IC). The plurality of dielectric layers 128a to d include a first dielectric layer 128a on the lower dielectric structure 126, a second dielectric layer 128b on the first dielectric layer 128a, a third dielectric layer 128c on the second dielectric layer 128b, and a fourth dielectric layer 128d on the third dielectric layer 128c.

[0018] The electronic device 130 is located within the BEOL structure 106 and directly overlaps at least some individual lower semiconductor devices within one or more lower semiconductor devices 108. The electronic device 130 includes a plurality of transistors 131a-b stacked perpendicularly to each other. The electronic device 130 may be, for example, an inverter, or may include an inverter. In further embodiments, the electronic device 130 may be, for example, a logic gate, a latch, an SRAM cell, other suitable devices, or a combination thereof, or may include these. In some embodiments, the plurality of transistors 131a-b include a p-channel transistor 131a and an n-channel transistor 131b overlapping the p-channel transistor 131a. The p-channel transistor 131a and the n-channel transistor 131b may be referred to as semiconductor devices. In various embodiments, the p-channel transistor 131a and the n-channel transistor 131b are configured as oxide semiconductor (OS) transistors, thin-film transistors (TFTs), etc., respectively.

[0019] The p-channel transistor 131a includes a first source / drain structure pair 132, 134 located within a second dielectric layer 128b, a first semiconductor layer 144 on the first source / drain structure pair 132, 134, and a first gate dielectric layer 148 on the first semiconductor layer 144. Depending on the context, the source / drain structure may refer to the source or the drain individually or collectively. The gate electrode 136 is located within a third dielectric layer 128c and overlaps the first gate dielectric layer 148. The n-channel transistor 131b includes a second gate dielectric layer 150 on the gate electrode 136, a second semiconductor layer 146 on the second gate dielectric layer 150, and a second source / drain structure pair 140, 142 located within a fourth dielectric layer 128d and on the second semiconductor layer 146. Furthermore, the conductive source / drain via 138 extends from the first source / drain structure 132 in the first source / drain structure pair 132, 134 to the first source / drain structure 140 in the second source / drain structure pair 140, 142. The gate electrode 136 is shared by the p-channel transistor 131a and the n-channel transistor 131b. In some embodiments, the first semiconductor layer 144 contains a first conductivity type (e.g., p-type), and the second semiconductor layer 146 contains a second conductivity type (e.g., n-type) opposite to the first conductivity type. In various embodiments of the present invention, the n-channel transistor 131b overlaps the p-channel transistor 131a, but in some embodiments, the vertical stacking may be inverted so that the p-channel transistor 131a overlaps the n-channel transistor 131b (e.g., as shown and / or described in Figure 3H).

[0020] The electronic device 130 includes a gate structure 151 comprising a gate electrode 136, a first gate dielectric layer 148, and a second gate dielectric layer. The gate structure 151 has a first surface facing the semiconductor substrate 102 and a second surface facing the second source / drain structure pair 140, 142. The first semiconductor layer 144 extends along the first surface of the gate structure 151, and the second semiconductor layer 146 extends along the second surface of the gate structure 151. In various embodiments, during the operation of the electronic device 130, a first selective conductive channel may be formed in the first semiconductor layer 144 of the p-channel transistor 131a between the first source / drain structure pair 132, 134. Furthermore, a second selective conductive channel may be formed in the second semiconductor layer 146 of the n-channel transistor 131b between the second source / drain structure pair 140, 142.

[0021] Because the n-channel transistor 131b is stacked vertically on top of the p-channel transistor 131a, the lateral footprint of the electronic device 130 is reduced, thereby increasing the device density of the IC. Furthermore, by vertically stacking the p-channel transistor 131a and the n-channel transistor 131b, it becomes easier for the first semiconductor layer 144 to be offset from the second semiconductor layer 146 by a relatively large distance compared to an embodiment (not shown) in which the baseline p-channel and n-channel transistors are directly adjacent to each other laterally on the same plane and spaced apart. As a result, the diffusion of one or more elements from the first semiconductor layer 144 to the second semiconductor layer 146 is mitigated or prevented, thereby improving the performance of the p-channel transistor 131a and the n-channel transistor 131b. Therefore, the electronic device 130 in which the p-channel transistor 131a is stacked vertically with the n-channel transistor 131b improves the overall performance and device density of the IC.

[0022] The first semiconductor layer 144 comprises a first metal oxide compound having a first conductivity type (e.g., p-type). In some embodiments, the first semiconductor layer 144 is Cu X Ni Y Sn ZNO compound (where X is within the range of 0 to 1, Y is within the range of 0 to 1, and Z is within the range of 0 to 1), Cu X Ni Y Sn Z O compound (where X is within the range of 0 to 1, Y is within the range of 0 to 1, and Z is within the range of 0 to 1), or other suitable materials. In various embodiments, Cu is copper, Ni is nickel, Sn is tin, O is oxygen, and N is tellurium (Te), antimony (Sb), magnesium (Mg), boron (B), aluminum (Al), gallium (Ga), or iron (Fe). In some embodiments, the first semiconductor layer 144 is Cu X Ni Y Sn Z a single layer containing NO compound or a multi-layer stack. In various embodiments, the layers within the multi-layer stack are Cu X Ni Y Sn Z containing different forms of NO compound (e.g., each layer is Cu X Ni Y Sn Z different elements within the NO compound and / or Cu X Ni Y Sn Z containing different concentrations of elements within the NO compound). For example, the first semiconductor layer 144 may be a stack of a NiO layer and a CuO layer, a stack of a metal-doped SnO layer and a SnO layer, a stack of a Cu-rich CuNiO layer and a Cu-poor NiO layer, a stack of other suitable layers, or the like, or may include these. The first metal oxide of the first semiconductor layer 144 may be a binary compound, a ternary compound, a quaternary compound, a quinary compound, or the like. In still other embodiments, the first semiconductor layer 144 includes 1 to 10 metal oxide layers. In still other embodiments, the thickness of the first semiconductor layer 144 is within the range of about 3 to 10 nanometers (nm) or other suitable values. In various embodiments, the mobility of charge carriers within the first semiconductor layer 144 is 6 square centimeters per volt-second (cm 2 / Vs) or more.

[0023] In various embodiments, the first semiconductor layer 144 is in direct contact with the top surface of the first source / drain structure pair 132, 134. In further embodiments, the first semiconductor layer 144 is in direct contact with the opposing side walls of the conductive source / drain via 138 and the bottom surface of the first gate dielectric layer 148. The first gate dielectric layer 148 may be, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicate oxide, hafnium titanium oxide, other suitable dielectric materials, or any combination thereof, or may include these. In various embodiments, the first gate dielectric layer 148 has a dielectric constant greater than 9. In yet other embodiments, the first gate dielectric layer 148 may be, for example, a ferroelectric material (e.g., lead zirconate titaniumate, barium titaniumate), an antiferroelectric material (e.g., lead zirconate, lead hafnate), or similar materials, or may include these. In some embodiments, the first gate dielectric layer 148 containing a ferroelectric material facilitates the configuration of the p-channel transistor 131a as a capacitorless ferroelectric transistor. The thickness of the first gate dielectric layer 148 is, for example, in the range of 1 to 20 nm or other suitable values. In various embodiments, the thickness of the first gate dielectric layer 148 is greater than the thickness of the first semiconductor layer 144.

[0024] The second semiconductor layer 146 comprises a second metal oxide compound having a second conductivity type (e.g., n-type). In various embodiments, the first metal oxide compound of the first semiconductor layer 144 is different from the second metal oxide compound of the second semiconductor layer 146. In some embodiments, the second semiconductor layer 146 is In X Ga Y Zn Z MO compound (where X is in the range of 0 to 1, Y is in the range of 0 to 1, Z is in the range of 0 to 1), In X Ga Y Zn Z The material comprises an O compound (where X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), or other suitable material. In various embodiments, In is Indium, Ga is Gallium, Zn is Zinc, O is Oxygen, and M is Titanium (Ti), Aluminum (Al), Silver (Ag), Tungsten (W), Cerium (Ce), Tin (Sn), Vanadium (V), or Scandium (Sc). In some embodiments, the second semiconductor layer 146 is In X Ga Y Zn Z It includes a single layer containing the MO compound or a multilayer stack. In various embodiments, the layers within the multilayer stack are In X Ga Y Zn Z Contains different forms of MO compounds (for example, each layer is In X Ga Y Zn Z Different elements and / or In within the MO compound X Ga Y Zn Z(This includes different concentrations of elements within the MO compound). For example, the second semiconductor layer 146 may be a stack of a GaZnO layer and an InZnO layer, a stack of an In1Ga3Zn2O layer (e.g., Ga-rich) and an InGaZnO layer (e.g., Ga-poor), a stack of an InGaZnO layer and a Sn-doped InGaZnO layer, a stack of other suitable layers, or similar configurations, or may include these. The second metal oxide of the second semiconductor layer 146 may be a binary compound, a ternary compound, a quaternary compound, a pentary compound, or similar configurations. In further embodiments, the second semiconductor layer 146 includes 1 to 10 layers of metal oxide. In yet another embodiment, the thickness of the second semiconductor layer 146 is in the range of about 3 to 10 nm or other suitable value. In various embodiments, the mobility of charge carriers in the second semiconductor layer 146 is 6 cm². 2 / Vs or greater. In further embodiments, the first and second semiconductor layers 144, 146 each have an amorphous phase (e.g., lacking long-range order found at least partially in amorphous and / or crystalline phases), a short-range ordered phase (e.g., having structure or regularity in the arrangement of atoms or molecules over interatomic or molecular intervals), or similar. In such embodiments, the first and second semiconductor layers 144, 146 having an amorphous phase or a short-range ordered phase reduce damage to the first and second semiconductor layers 144, 146 during the thermal annealing process, while simultaneously reducing device leakage and / or performance degradation within the transistors 131a, 131b.

[0025] In some embodiments, the second semiconductor layer 146 is in direct contact with the bottom surface of the second source / drain structure pair 140, 142. In further embodiments, the second semiconductor layer 146 is in direct contact with the opposing side walls of the conductive source / drain via 138 and the top surface of the second gate dielectric layer 150. The second gate dielectric layer 150 may be, for example, Al2O3, HfO2, ZrO2, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicate oxide, hafnium titanium oxide, other suitable dielectric materials, or any combination thereof, or may include these. In various embodiments, the second gate dielectric layer 150 has a dielectric constant greater than 9. In yet another embodiment, the second gate dielectric layer 150 may be, for example, a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnate, etc.), or similar, or may include these. In some embodiments, a second gate dielectric layer 150 containing a ferroelectric material facilitates the configuration of the n-channel transistor 131b as a capacitorless ferroelectric transistor. The thickness of the second gate dielectric layer 150 is, for example, in the range of 1 to 20 nm or other suitable values. In various embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the second semiconductor layer 146. In yet another embodiment, the first gate dielectric layer 148 contains a first material, and the second gate dielectric layer 150 contains a second material different from the first material.

[0026] The ILD layer 124, the lower dielectric structure 126, and the plurality of dielectric layers 128a to d may, for example, be an oxide (e.g., silicon dioxide), a low-dielectric constant (low-k) dielectric material, an undoped silicate glass, an undoped silicon dioxide, another suitable dielectric, or any combination thereof, or may include these. As used herein, a low-dielectric constant dielectric material is a dielectric material having a dielectric constant of less than 3.9. In various embodiments, the first source / drain structure pairs 132, 134, the conductive source / drain via 138, the gate electrode 136, and the second source / drain structure pairs 140, 142 may, for example, be tantalum nitride, tantalum, titanium, titanium nitride, tungsten, molybdenum, ruthenium, copper, another conductive material, or any combination thereof, or may include these. In some embodiments, the heights of the first source / drain structure pairs 132, 134, the gate electrode 136, and the second source / drain structure pairs 140, 142 are each within a range of approximately 5 to 50 nm or other suitable values. In various embodiments, the height of the gate electrode 136 is greater than the first sum of the thicknesses of the first semiconductor layer 144 and the first gate dielectric layer 148, and greater than the second sum of the thicknesses of the second semiconductor layer 146 and the second gate dielectric layer 150. In further embodiments, the width of the gate electrode 136 is greater than the width of the individual source / drain structures in the first source / drain structure pairs 132, 134 or the second source / drain structure pairs 140, 142.

[0027] In various embodiments, the distance between the first semiconductor layer 144 and the second semiconductor layer 146 is relatively large (for example, greater than the height of the gate electrode 136). As a result, the diffusion of one or more elements from the first semiconductor layer 144 to the second semiconductor layer 146 is mitigated, thereby improving the performance of transistors 131a and 131b.

[0028] Figure 2 shows cross-sectional views 200 of several other embodiments of the IC shown in Figure 1.

[0029] In some embodiments, the conductive source / drain via 138 includes a lower via segment 138a and an upper via segment 138b that overlaps the lower via segment 138a. The upper via segment 138b is in direct contact with the lower via segment 138a. The lower via segment 138a extends through the third dielectric layer 128c, the first gate dielectric layer 148, and the first semiconductor layer 144. In various embodiments, the top surface of the lower via segment 138a is coplanar with the top surface of the third dielectric layer 128c and the top surface of the gate electrode 136. The upper via segment 138b extends through the second gate dielectric layer 150 and the second semiconductor layer 146. In some embodiments, the top surface of the upper via segment 138b is coplanar with the top surface of the second semiconductor layer 146. The conductive source / drain via 138 directly electrically couples the first source / drain structure 132 in the first source / drain structure pair 132, 134 to the first source / drain structure 140 in the second source / drain structure pair 140, 142.

[0030] In some embodiments, the electronic device 130 is configured as an inverter. The gate electrode 136 is electrically coupled to an input voltage node configured to receive an input voltage Vin. In various embodiments, the gate electrode 136 is electrically coupled to a conductive via (not shown) located laterally offset from the electronic device 130. The first source / drain structure 132 in the first source / drain structure pair 132, 134 and the first source / drain structure 140 in the second source / drain structure pair 140, 142 are electrically coupled to an output voltage node. The second source / drain structure 134 in the first source / drain structure pair 132, 134 is electrically coupled to a first power supply voltage node (e.g., Vdd) which may be coupled to a power supply voltage of about 1.8 volts (V), 3.3 V, 5 V, in the range of about 1.8 to 15 V, or other suitable value. In the second source / drain structure pair 140, 142, the second source / drain structure 142 is electrically coupled to a reference voltage node (e.g., Vss) which may be ground (e.g., 0V) or another suitable value. In some embodiments, the individual source / drain regions in the source / drain region pair 110 of the semiconductor device in one or more lower semiconductor devices 108 are directly electrically coupled to the gate electrode 136.

[0031] Figure 3A shows a cross-sectional view 300a of several other embodiments of the IC of Figure 1.

[0032] In some embodiments, the outer wall of the first semiconductor layer 144 is spaced between the first source / drain structure pair 132, 134. The first outer wall of the first semiconductor layer 144 overlaps directly above the first source / drain structure 132 in the first source / drain structure pair 132, 134, and the second outer wall of the first semiconductor layer 144 overlaps directly above the second source / drain structure 134 in the first source / drain structure pair 132, 134. Furthermore, the first semiconductor layer 144 may be laterally offset from the conductive source / drain via 138 at a non-zero distance. In such embodiments, this can reduce damage to the first semiconductor layer 144 when forming the conductive source / drain via 138 (for example, by reducing damage from the etching process used to form the opening for the conductive source / drain via 138). In various embodiments, the first gate dielectric layer 148 is in direct contact with the outer wall of the first semiconductor layer 144 and the top surface of the first semiconductor layer 144. The bottom surface of the first gate dielectric layer 148 can be aligned with the bottom surface of the first semiconductor layer 144. In some embodiments, the outer wall of the first semiconductor layer 144 is spaced apart between the first source / drain structure pair 132, 134 to improve the insulation between the p-channel transistor 131a and other transistors (not shown) located within the BEOL structure 106 at the same level as the p-channel transistor 131a.

[0033] In some embodiments, the outer wall of the second semiconductor layer 146 is spaced between the second source / drain structure pair 140, 142. The first outer wall of the second semiconductor layer 146 is located directly beneath the first source / drain structure 140 in the second source / drain structure pair 140, 142, and the second outer wall of the second semiconductor layer 146 is located directly beneath the second source / drain structure 142 in the second source / drain structure pair 140, 142. The second semiconductor layer 146 may be laterally offset from the conductive source / drain via 138 at a non-zero distance. In such embodiments, this can reduce damage to the second semiconductor layer 146 when forming the conductive source / drain via 138 (for example, by reducing damage from the etching process used to form the opening for the conductive source / drain via 138). In various embodiments, the fourth dielectric layer 128d is in direct contact with the outer wall and top surface of the second semiconductor layer 146. The bottom surface of the fourth dielectric layer 128d may be aligned with the bottom surface of the second semiconductor layer 146. In some embodiments, the outer wall of the second semiconductor layer 146 is spaced between the second source / drain structure pairs 140, 142 to improve the insulation between the n-channel transistor 131b and other transistors (not shown) located in the same layer as the n-channel transistor 131b within the BEOL structure 106.

[0034] The bottom surface of the first gate dielectric layer 148 is in direct contact with a portion of the top surface of the first source / drain structure 132 in the first source / drain structure pair 132, 134, and a portion of the top surface of the second source / drain structure 134 in the first source / drain structure pair 132, 134. The fourth dielectric layer 128d is in direct contact with a portion of the bottom surface of the first source / drain structure 140 in the second source / drain structure pair 140, 142, and a portion of the bottom surface of the second source / drain structure 142 in the second source / drain structure pair 140, 142. In various embodiments, the thickness of the first gate dielectric layer 148 is greater than the thickness of the second gate dielectric layer 150. In further embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the first semiconductor layer 144 and the second semiconductor layer 146. In yet another embodiment, the centers of the first and second semiconductor layers 144, 146 are aligned with the center of the gate electrode 136.

[0035] Figure 3B shows cross-sectional views 300b of several other embodiments of the IC of Figure 1.

[0036] In some embodiments, the first outer wall of the first semiconductor layer 144 is aligned with the outer edge and / or outer wall of the first source / drain structure 132 in the first source / drain structure pair 132, 134. The second outer wall of the first semiconductor layer 144 is aligned with the outer edge and / or outer wall of the second source / drain structure 134 in the first source / drain structure pair 132, 134. Furthermore, the first outer wall of the second semiconductor layer 146 is aligned with the outer edge and / or outer wall of the first source / drain structure 140 in the second source / drain structure pair 140, 142. The second outer wall of the second semiconductor layer 146 is aligned with the outer edge and / or outer wall of the second source / drain structure 142 in the second source / drain structure pair 140, 142.

[0037] Figure 3C shows a cross-sectional view 300c of several other embodiments of the IC of Figure 3A, in which the intermediate dielectric layer 302 is arranged around the outer wall of the first semiconductor layer 144.

[0038] In some embodiments, the intermediate dielectric layer 302 is positioned between the first gate dielectric layer 148 and the first source / drain structure pair 132, 134. The intermediate dielectric layer 302 is in direct contact with the outer wall of the first semiconductor layer 144. The intermediate dielectric layer 302 may be, for example, silicon dioxide, a low dielectric constant dielectric material, silicon nitride, silicon carbide, any other suitable dielectric material, or any combination thereof, or may include these.

[0039] Figure 3D shows a cross-sectional view 300d of several other embodiments of the IC of Figure 1.

[0040] In some embodiments, the conductive source / drain via 138 includes a curved first sidewall segment pair, which contacts the curved sidewall of the first semiconductor layer 144. Furthermore, the conductive source / drain via 138 includes a curved second sidewall segment pair, which contacts the curved sidewall of the second semiconductor layer 146.

[0041] Figure 3E shows cross-sectional views 300e of several other embodiments of the IC of Figure 1.

[0042] In various embodiments, the first semiconductor layer 144 includes a first metal oxide layer 144a and a second metal oxide layer 144b containing a material different from that of the first metal oxide layer 144a. In some embodiments, the first metal oxide layer 144a contains CuO and the second metal oxide layer 144b contains NiO. The first metal oxide layer 144a contains SnO and the second metal oxide layer 144b contains metal-doped SnO. The first metal oxide layer 144a contains Cu-rich CuNiO and the second metal oxide layer 144b contains Cu-poor NiO. Or equivalents.

[0043] In further embodiments, the second semiconductor layer 146 includes a first metal oxide layer 146a and a second metal oxide layer 146b containing a different material from the first metal oxide layer 146a. In some embodiments, the first metal oxide layer 146a contains GaZnO and the second metal oxide layer 146b contains InZnO. The first metal oxide layer 146a contains In1Ga3Zn2O and the second metal oxide layer 146b contains InGaZnO. The first metal oxide layer 146a contains InGaZnO and the second metal oxide layer 146b contains Sn-doped InGaZnO. Or equivalent. Figure 3E shows first and second semiconductor layers 144, 146 having two different layers, but this is a non-limiting example and it is understood that the first and second semiconductor layers 144, 146 may contain any number of layers.

[0044] Figure 3F shows cross-sectional views 300f of several other embodiments of the IC of Figure 1.

[0045] In some embodiments, the outer wall of the first semiconductor layer 144 is spaced between the first source / drain structure pairs 132, 134, and the second source / drain structure pairs 140, 142 are spaced between the outer walls of the second semiconductor layer 146. The outer wall of the second semiconductor layer 146 is aligned with the outer wall of the second gate dielectric layer 150. In various embodiments, the first semiconductor layer 144 may be configured as shown and / or described in Figure 3A. In some embodiments, during the manufacturing of the IC in Figure 3F, the first semiconductor layer 144 is deposited and then patterned so that the outer wall of the first semiconductor layer 144 is defined between the first source / drain structure pairs 132, 134.

[0046] Figure 3G shows cross-sectional views of several other embodiments of the IC in Figure 1.

[0047] In some embodiments, the first source / drain structure pairs 132, 134 are spaced apart between the outer walls of the first semiconductor layer 144, and the outer wall of the second semiconductor layer 146 is spaced apart between the second source / drain structure pairs 140, 142. The outer wall of the first semiconductor layer 144 is aligned with the outer wall of the first gate dielectric layer 148. In various embodiments, the second semiconductor layer 146 may be configured as shown and / or described in Figure 3A. In some embodiments, during the manufacturing of the IC in Figure 3F, the second semiconductor layer 146 is deposited and then patterned so that the outer wall of the second semiconductor layer 146 is defined between the second source / drain structure pairs 140, 142.

[0048] Figure 3H shows cross-sectional views 300h of several other embodiments of the IC of Figure 1.

[0049] In some embodiments, the p-channel transistor 131a overlaps the n-channel transistor 131b. In such embodiments, the second semiconductor layer 146 overlaps the second source / drain structure pair 140, 142, and the second gate dielectric layer 150 is positioned between the top surface of the second semiconductor layer 146 and the bottom surface of the gate electrode 136. Furthermore, the first gate dielectric layer 148 is positioned between the top surface of the gate electrode 136 and the bottom surface of the first semiconductor layer 144, and the first source / drain structure pair 132, 134 overlaps the first semiconductor layer 144.

[0050] Figure 4A shows a cross-sectional view 400a of several other embodiments of the IC of Figure 1.

[0051] In some embodiments, a plurality of conductive wires and vias 120, 122, first source / drain structure pairs 132, 134, gate electrode 136, conductive source / drain via 138, and second source / drain structure pairs 140, 142 each include a conductive structure 404 and a conductive liner 402. The conductive liner 402 is positioned along the opposing side walls and the bottom surface of the conductive structure 404. The conductive structure 404 may be, for example, copper, aluminum, tungsten, ruthenium, other conductive materials, or any combination thereof, or may include these. The conductive liner 402 may be, for example, titanium, titanium nitride, tantalum, tantalum nitride, other suitable conductive materials, or any combination thereof, or may include these. The conductive liner 402 may be configured as a diffusion barrier layer and / or adhesive layer.

[0052] Figure 4B shows a cross-sectional view 400b of several other embodiments of the IC of Figure 4A.

[0053] In some embodiments, the first source / drain structure pairs 132 and 134 each share a conductive structure 404 and a conductive liner 402 corresponding to the underlying conductive via 122. In further embodiments, the first source / drain structure 140 in the second source / drain structure pairs 140 and 142 shares a conductive structure 404 and a conductive liner 402 corresponding to the conductive source / drain via 138.

[0054] Figure 5A shows a cross-sectional view 500a of several embodiments of an IC having an electronic device including transistors stacked perpendicularly to each other in a first region of a semiconductor substrate that is laterally adjacent to a second region of the semiconductor substrate.

[0055] The semiconductor substrate 102 includes a first region 502 that is laterally adjacent to the second region 504. In some embodiments, electronic devices 130 are arranged in the first region 502. The electronic devices 130 include a p-channel transistor 131a and an n-channel transistor 131b that overlaps the p-channel transistor 131a. The second region 504 may include one or more lower semiconductor devices 108 on the semiconductor substrate 102, a second plurality of conductive wires 502a-d, and a second plurality of conductive vias 504a-c.

[0056] The second plurality of conductive wires 502a-d and the second plurality of conductive vias 504a-c are arranged in different layers. For example, the first conductive wire 502a is arranged in the first wiring layer, the second conductive wire 502b is arranged in the second wiring layer, the third conductive wire 502c is arranged in the third wiring layer, and the fourth conductive wire 502d is arranged in the fourth wiring layer. In some embodiments, the first source / drain structure pairs 132, 134, gate electrode 136, and the second source / drain structure pairs 140, 142 may be configured as conductive wires aligned with the corresponding conductive wires in the second plurality of conductive wires 502a-d. In various embodiments, the first source / drain structure pairs 132, 134 are aligned with and / or arranged in the second wiring layer. For example, the bottom surface of the second conductive wire 502b is aligned with the bottom surface of the first source / drain structure pairs 132, 134. In further embodiments, the gate electrode 136 is aligned with and / or arranged in the third wiring layer, and the second source / drain structure pair 140, 142 is aligned with and / or arranged in the fourth wiring layer.

[0057] Figure 5B shows cross-sectional views 500b of several embodiments of the IC shown in Figure 5A.

[0058] In some embodiments, the BEOL device 506 is arranged in a second region 504 adjacent to the electronic device 130. In some embodiments, the BEOL device 506 is configured as a capacitor, a memory device, or other electronic device. The BEOL device 506 may include, for example, a dielectric layer 510 arranged between the bottom electrode 508 and the top electrode 512. In various embodiments, the dielectric layer 510 is configured as a data storage layer, a capacitor dielectric, or something similar.

[0059] Figure 5C shows a layout diagram of several embodiments of the IC in Figure 5A taken along line A-A'.

[0060] In some embodiments, the IC includes a plurality of electronic devices 130a-f arranged in a BEOL structure (106 in Figure 5A). In various embodiments, the plurality of electronic devices 130a-f are configured as shown and / or described in Figures 1, 2, 3A-3E, 4A-4B, or 5A-5B, respectively. The plurality of electronic devices 130a-f include a first row of electronic devices 130a-c and a second row of electronic devices 130d-f. The first row of electronic devices 130a-c share a first gate electrode 136a that extends over the length of the first row of electronic devices 130a-c. The second row of electronic devices 130d-f share a second gate electrode 136b. The first and second gate electrodes 136b are each represented as dashed boxes in layout diagram 500c. In various embodiments, the first gate electrode 136a and the second gate electrode 136b are electrically coupled to conductive vias (not shown) at a position laterally offset from the plurality of electronic devices 130a-f. In some embodiments, the respective second source / drain structure pairs 140, 132 of the electronic devices 130a-f extend in the same direction as the first and second gate electrodes 136a-b, respectively. In further embodiments, the first source / drain structure pair of each electronic device 130a-f (e.g., 132, 134 in Figure 5A) is located directly below the second source / drain structure pairs 140, 142.

[0061] Figure 5D shows layout diagram 500d of several other embodiments of the IC in Figure 5C. Layout diagram 500d is taken along line A-A' in Figure 5A.

[0062] In some embodiments, rows of multiple electronic devices 130a-f share a corresponding second semiconductor layer 146 and first semiconductor layer (e.g., the first semiconductor layer 144 in Figure 5A) extending in a first direction. In various embodiments, the first gate electrode 136a and the second gate electrode 136b extend in a second direction perpendicular to the first direction.

[0063] Figures 6 to 16 show cross-sectional views 600 to 1600 of several embodiments of a first method for forming an integrated chip (IC) having electronic devices including transistors stacked perpendicularly to each other according to this disclosure. Although the cross-sectional views 600 to 1600 shown in Figures 6 to 16 are described with reference to the first method, it is understood that the structures shown in Figures 6 to 16 are not limited to the first method but may exist separately and independently from the first method. Furthermore, although Figures 6 to 16 are described as a series of steps, these steps are not limited in that the order of the steps can be changed in other embodiments, and it is understood that the disclosed method is applicable to other structures as well. In other embodiments, some of the illustrated and / or described steps may be omitted in whole or in part.

[0064] As shown in the cross-sectional view 600 of Figure 6, a semiconductor substrate 102 is provided, and a FEOL structure 104 and a lower BEOL structure 602 are formed on the semiconductor substrate 102. The semiconductor substrate 102 may be, for example, a bulk substrate (e.g., bulk silicon), single-crystal silicon, SiGe, SOI, etc., or may include these. The FEOL structure 104 includes a semiconductor device 108 on the semiconductor substrate 102, an ILD layer 124 on the semiconductor substrate 102, and one or more conductive contacts 118 within the ILD layer 124. The lower BEOL structure 602 may be referred to as a lower wiring structure.

[0065] In various embodiments, the semiconductor device 108 includes a source / drain region pair 110, a lower gate electrode 114, a lower gate dielectric 112, and a sidewall spacer 116. In some embodiments, the process for forming the semiconductor device 108 includes depositing a gate dielectric material on a semiconductor substrate 102 (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.), depositing a gate electrode material on the gate dielectric material (e.g., by CVD, PVD, ALD, etc.), etching the gate dielectric material and the gate electrode material to form the lower gate electrode 114 and the lower gate dielectric 112, depositing a sidewall spacer material on the lower gate electrode 114 and the lower gate dielectric 112, etching the sidewall spacer material to form the sidewall spacer 116, and performing a selective ion implantation process to form the source / drain region pair 110 in the semiconductor substrate 102 on the side opposite the lower gate electrode 114. The ILD layer 124 is formed on the semiconductor substrate 102 by, for example, a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. Furthermore, one or more conductive contacts 118 may be formed by etching the ILD layer 124 to form openings within the ILD layer 124, depositing a conductive material (for example by CVD, PVD, ALD, etc.) within the openings, and performing a planarization process (for example, a chemical mechanical polishing (CMP) process) on the conductive material.

[0066] Furthermore, the lower BEOL structure 602 includes a lower dielectric structure 126, a plurality of conductive wires 120, a first dielectric layer 128a, and a plurality of conductive vias 122. The lower dielectric structure 126 and the first dielectric layer 128a may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. The plurality of conductive wires 120 and the plurality of conductive vias 122 may be formed, for example, by a single damascene process, a dual damascene process, or other suitable process.

[0067] As shown in the cross-sectional view 700 of Figure 7, a second dielectric layer 128b is formed on the first dielectric layer 128a, and a plurality of openings 702 are formed within the second dielectric layer 128b. The second dielectric layer 128b may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. In some embodiments, the process for forming the plurality of openings 702 includes forming a masking layer (not shown) on the second dielectric layer 128b, etching the second dielectric layer 128b, and performing a removal process to remove the masking layer.

[0068] As shown in the cross-sectional view 800 of Figure 8, the first source / drain structure pair 132, 134 is formed within the second dielectric layer 128b. In some embodiments, the process of forming the first source / drain structure pair 132, 134 includes depositing one or more conductive materials within a plurality of openings (702 in Figure 7) (e.g., by CVD, PVD, ALD, etc.) and performing a planarization process (e.g., a CMP process) on one or more conductive materials. In various embodiments, depositing one or more conductive materials includes depositing a conductive liner layer (e.g., titanium nitride, tantalum nitride, etc.) that lines the openings (702 in Figure 7) and depositing a conductive core (e.g., copper, aluminum, tungsten, other conductive materials, or any combination thereof) on top of the conductive liner layer.

[0069] As shown in the cross-sectional view 900 of Figure 9, a first semiconductor layer 144 is formed on a first source / drain structure pair 132, 134, and a first gate dielectric layer 148 is formed on the first semiconductor layer 144. In some embodiments, the first semiconductor layer 144 is formed by one or more deposition processes, which may include one or more of the following: a PVD process, a CVD process, an ALD process, or other suitable growth or deposition processes. Furthermore, one or more deposition processes are performed at a first deposition temperature, for example, about 400°C or less. By forming the first semiconductor layer 144 at the first deposition temperature, damage to the structures in the lower BEOL structure 602 and / or FEOL structure 104 can be mitigated or reduced. The first semiconductor layer 144 includes a first conductivity type (e.g., p-type). In various embodiments, the first semiconductor layer 144 is formed to a thickness in the range of about 3 to 10 nm or other suitable value. Furthermore, the first semiconductor layer 144 may be made of, for example, Cu X Ni Y Sn Z NO compounds (where X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), Cu X Ni Y Sn Z O compound (where X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), or other suitable material, or may contain these. In various embodiments, Cu is copper, Ni is nickel, Sn is tin, O is oxygen, and N is tellurium (Te), antimony (Sb), magnesium (Mg), boron (B), aluminum (Al), gallium (Ga), or iron (Fe). In some embodiments, the first semiconductor layer 144 is Cu X Ni Y Sn Z It includes a single layer containing an NO compound, or a multilayer stack.

[0070] In some embodiments, the first gate dielectric layer 148 is formed on the first semiconductor layer 144 by, for example, a PVD process, a CVD process, an ALD process, or other suitable growth or deposition process. The first gate dielectric layer 148 may be, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicate oxide, hafnium titanium oxide, other suitable dielectric materials, or any combination thereof, or may include these. In various embodiments, the first gate dielectric layer 148 has a dielectric constant greater than 9. In further embodiments, the first gate dielectric layer 148 may be, for example, a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnate, etc.), or similar, or may include these. In a further embodiment, the thickness of the first gate dielectric layer 148 is greater than the thickness of the first semiconductor layer 144.

[0071] In various embodiments, a patterning process may be performed on the first semiconductor layer 144 before forming the first gate dielectric layer 148 on the first semiconductor layer 144. In such embodiments, the first gate dielectric layer 148 extends along the outer wall of the first semiconductor layer 144 and contacts the outer wall of the first semiconductor layer 144 (for example, as shown and / or described in Figure 3A). In some embodiments, the patterning process includes forming a masking layer (not shown) on the first semiconductor layer 144, etching the first semiconductor layer 144 according to the masking layer, and removing the masking layer.

[0072] As shown in the cross-sectional view 1000 of Figure 10, a third dielectric layer 128c is formed on the first gate dielectric layer 148, and an opening 1002 is formed within the third dielectric layer 128c. The third dielectric layer 128c may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. In some embodiments, the process of forming the opening 1002 includes forming a masking layer (not shown) on the third dielectric layer 128c, etching the third dielectric layer 128c, and performing a removal process to remove the masking layer.

[0073] As shown in the cross-sectional view 1100 of Figure 11, the gate electrode 136 is formed within the third dielectric layer 128c, thereby forming the p-channel transistor 131a on the lower BEOL structure 602. In some embodiments, the process of forming the gate electrode 136 includes depositing one or more conductive materials within the opening (1002 in Figure 10) (e.g., by CVD, PVD, ALD, etc.) and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing one or more conductive materials includes depositing a conductive liner layer (e.g., titanium nitride, tantalum nitride, etc.) to line the opening (1002 in Figure 10) and depositing a conductive core (e.g., copper, aluminum, tungsten, other conductive materials, or any combination thereof) on the conductive liner layer. In some embodiments, the process of forming the p-channel transistor 131a includes the processing steps shown and / or described in Figures 7 to 11.

[0074] As shown in the cross-sectional view 1200 of Figure 12, a second gate dielectric layer 150 is formed on the gate electrode 136, and a second semiconductor layer 146 is formed on the second gate dielectric layer 150. In some embodiments, the second gate dielectric layer 150 is formed on the gate electrode 136 by, for example, a PVD process, a CVD process, an ALD process, or other suitable growth or deposition process. In some embodiments, the second semiconductor layer 146 is formed by one or more deposition processes, which may include one or more of the PVD process, a CVD process, an ALD process, or other suitable growth or deposition processes. Furthermore, one or more deposition processes are performed at a second deposition temperature, for example, about 400°C or less. By forming the second semiconductor layer 146 at the second deposition temperature, damage to the lower BEOL structure 602, the FEOL structure 104, and / or structures within the p-channel transistor 131a can be mitigated or reduced. The second semiconductor layer 146 includes a second conductivity type (e.g., n-type). In various embodiments, the second semiconductor layer 146 is formed to a thickness in the range of approximately 3 to 10 nm or other suitable values. Furthermore, the second semiconductor layer 146 is, for example, In X Ga Y Zn Z MO compound (where X is in the range of 0 to 1, Y is in the range of 0 to 1, Z is in the range of 0 to 1), In X Ga Y Zn Z O compound (where X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), or other suitable material may be or may contain. In various embodiments, In is indium, Ga is gallium, Zn is zinc, O is oxygen, and M is titanium (Ti), aluminum (Al), silver (Ag), tungsten (W), cerium (Ce), tin (Sn), vanadium (V), or scandium (Sc). In some embodiments, the first semiconductor layer 144 is In X Ga Y Zn Z It includes a single layer containing an MO compound, or a multilayer stack.

[0075] In some embodiments, the second gate dielectric layer 150 may be, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicate oxide, hafnium titanium oxide, other suitable dielectric materials, or any combination thereof. In various embodiments, the second gate dielectric layer 150 has a dielectric constant greater than 9. In further embodiments, the second gate dielectric layer 150 may be, for example, a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnate, etc.), or similar. In further embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the second semiconductor layer 146.

[0076] In various embodiments, a patterning process may be performed on the second semiconductor layer 146. In such embodiments, the outer wall of the second semiconductor layer 146 is spaced apart from the outer wall of the second gate dielectric layer 150 (for example, as shown and / or described in Figure 3A). In some embodiments, the patterning process includes forming a masking layer (not shown) on the second semiconductor layer 146, etching the second semiconductor layer 146 according to the masking layer, and removing the masking layer.

[0077] As shown in the cross-sectional view 1300 of Figure 13, a fourth dielectric layer 128d is formed on the second semiconductor layer 146, and a masking structure 1302 is formed on the fourth dielectric layer 128d. In some embodiments, the masking structure 1302 includes a first hard mask 1304 on the fourth dielectric layer 128d, a first photoresist 1308 on the first hard mask 1304, a patterned hard mask 1306 on the first photoresist 1308, and a second photoresist 1310 on the patterned hard mask 1306. The second photoresist 1310 includes sidewalls defining an opening 1312 above the individual source / drain structure 132 in the first source / drain structure pair 132, 134. The fourth dielectric layer 128d may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process.

[0078] In some embodiments, the first hard mask 1304 and the patterned hard mask 1306 may be, for example, titanium, titanium nitride, tungsten, other metals, other suitable materials, or any combination thereof, or may include these. In various embodiments, the process for forming the masking structure 1302 includes depositing the first hard mask 1304 on the fourth dielectric layer 128d (e.g., by CVD, PVD, etc.), depositing the first photoresist 1308 on the first hard mask 1304 (e.g., by spin coating or other suitable process), depositing the second hard mask on the first photoresist 1308 (e.g., by CVD, PVD, etc.), patterning the second hard mask to form or define the patterned hard mask 1306, depositing the second photoresist 1310 on the patterned hard mask 1306 (e.g., by spin coating or other suitable process), and forming openings 1312 within the second photoresist 1310 (e.g., by a photolithography process or other suitable process).

[0079] As shown in the cross-sectional view 1400 of Figure 14, a first etching process is performed on the first semiconductor layer 144, the first gate dielectric layer 148, the third dielectric layer 128c, the second gate dielectric layer 150, the second semiconductor layer 146, and the fourth dielectric layer 128d according to the masking structure 1302, thereby forming via openings 1402. The via openings 1402 expose the upper surfaces of the individual source / drain structures 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes dry etching processes (e.g., reactive ion etching (RIE) processes, deep reactive ion etching (DRIE) processes, plasma etching processes, etc.), wet etching processes, other suitable etching processes, or any combination thereof. In various embodiments, the first semiconductor layer 144 and the second semiconductor layer 146 may be etched faster than the first and second gate dielectric layers 148, 150 and / or the third and fourth dielectric layers 128c, 128d during the first etching process (e.g., with relatively high etching selectivity). In such embodiments, the inner walls of the first and second semiconductor layers 144, 146 defining at least a portion of the via opening 1402 may be recessed (e.g., as shown and / or described in Figure 3D). In various embodiments, the first etching process reduces the thickness of the second photoresist 1310.

[0080] As shown in the cross-sectional view 1500 of Figure 15, a second etching process is performed on the fourth dielectric layer 128d according to the masking structure (1302 in Figure 14), thereby forming the first opening 1502 and the second opening 1504. The second etching process may include, for example, a dry etching process (e.g., RIE process, DRIE process, plasma etching process, etc.), a wet etching process, another suitable etching process, or any combination thereof. Furthermore, after the second etching process, a removal process is performed to remove the masking structure (1302 in Figure 14) from above the fourth dielectric layer 128d. The first opening 1502 includes a portion of the via opening (1402 in Figure 14) below the fourth dielectric layer 128d.

[0081] As shown in the cross-sectional view 1600 of Figure 16, conductive source / drain vias 138 and second source / drain structure pairs 140, 142 are formed within the first and second openings (1502, 1504 in Figure 15), thereby forming an n-channel transistor 131b on top of a p-channel transistor 131a, and defining or forming an electronic device 130 on top of the BEOL structure 104. In the conductive source / drain vias 138 and second source / drain structure pairs 140, 142, the first source / drain structure 140 is formed within the first opening (1502 in Figure 15), and in the second source / drain structure pairs 140, 142, the second source / drain structure 142 is formed within the second opening (1504 in Figure 15). In various embodiments, the lower BEOL structure (602 in Figure 15) and the electronic device 130 are part of the BEOL structure 106. In some embodiments, the process for forming the conductive source / drain via 138 and the second source / drain structure pairs 140, 142 includes depositing one or more conductive materials within the first and second openings (1502, 1504 in Figure 15) (e.g., by CVD, PVD, ALD, etc.) and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing one or more conductive materials includes depositing a conductive liner layer (e.g., titanium nitride, tantalum nitride, etc.) to line the first and second openings (1502, 1504 in Figure 15) and depositing a conductive core (e.g., copper, aluminum, tungsten, other conductive materials, or any combination thereof) on the conductive liner layer. In various embodiments, the process for forming the n-channel transistor 131b includes the processing steps shown and / or described in Figures 10 to 16.

[0082] In various embodiments, forming the n-channel transistor 131b after the p-channel transistor 131a reduces the number of thermal annealing processes to which the n-channel transistor 131b is subjected. As a result, the diffusion of one or more elements from the second semiconductor layer 146 to the adjacent dielectric material is mitigated. This improves the reliability and performance of the n-channel transistor 131b.

[0083] In some embodiments, additional layers of conductive vias and wires (not shown) may be formed on the electronic device 130. These additional layers of conductive vias and wires are part of the BEOL structure 106. Furthermore, conductive vias and / or wires may be formed within the BEOL structure 106 in layers that are simultaneous with and aligned with the first source / drain structure pairs 132, 134, the gate electrode 136, the conductive source / drain via 138, and the second source / drain structure pairs 140, 142. For example, conductive wires (not shown) in the first layer may be formed within the BEOL structure 106 in a region laterally offset from the first source / drain structure pairs 132, 134, where the bottom surface of the conductive wires in the first layer is aligned with the bottom surface of the source / drain structure in the first source / drain structure pairs 132, 134.

[0084] Figures 17 to 26 show cross-sectional views 1700 to 2600 of several embodiments of a second method according to the present invention for forming an integrated chip (IC) having an electronic device including transistors stacked perpendicularly to each other. While the cross-sectional views 1700 to 2600 shown in Figures 17 to 26 are described with reference to the second method, it should be understood that the structures shown in Figures 17 to 26 are not limited to the second method and may exist independently of it. Furthermore, while Figures 17 to 26 are described as a series of steps, these steps are not limited in that the order of the steps can be changed in other embodiments, and it should be understood that the disclosed method is applicable to other structures. In other embodiments, some of the illustrated and / or described steps may be omitted in whole or in part.

[0085] As shown in the cross-sectional view 1700 of Figure 17, a semiconductor substrate 102 is provided, and a FEOL structure 104, a lower BEOL structure 602, and a p-channel transistor 131a are formed on the semiconductor substrate 102. In various embodiments, the structure of Figure 17 is formed as shown and / or described in Figures 6 to 11.

[0086] As shown in the cross-sectional view 1800 of Figure 18, the first masking structure 1806 is formed on the gate electrode 136 and the third dielectric layer 128c. In some embodiments, the first masking structure 1806 includes a hard mask 1802 on the third dielectric layer 128c and a photoresist 1804 on the hard mask 1802. The hard mask 1802 may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. The photoresist 1804 may be formed, for example, by spin coating or other suitable process. The hard mask 1802 may be, for example, titanium, titanium nitride, tungsten, other metals, other suitable materials, or any combination thereof, or may include them.

[0087] As shown in the cross-sectional view 1900 of Figure 19, an opening 1902 is formed within the photoresist 1804. In some embodiments, the process of forming the opening 1902 includes exposing the photoresist 1804 to a pattern on a photomask (for example, by passing ultraviolet (UV) light) and immersing the photoresist 1804 in a developer.

[0088] As shown in the cross-sectional view 2000 of Figure 20, a first etching process is performed on the third dielectric layer 128c, the first gate dielectric layer 148, and the first semiconductor layer 144 to form an opening 2002 on the individual source / drain structure 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes exposing the third dielectric layer 128c, the first gate dielectric layer 148, and the first semiconductor layer 144 to one or more etchants with a first masking structure (1806 in Figure 19) in place. The first etching process is, for example, a RIE process, a DRIE process, a plasma etching process, a wet etching process, another suitable etching process, or any combination thereof. After the first etching process, a removal process is performed to remove the first masking structure (1806 in Figure 19).

[0089] As shown in the cross-sectional view 2100 of Figure 21, the lower via segment 138a is formed within the opening (2002 in Figure 20). In some embodiments, the process of forming the lower via segment 138a includes depositing one or more conductive materials within the opening (2002 in Figure 20) (e.g., by CVD, PVD, ALD, etc.) and performing a planarization process (e.g., a CMP process) on the one or more conductive materials.

[0090] As shown in the cross-sectional view 2200 of Figure 22, the second gate dielectric layer 150 is formed on the gate electrode 136 and the lower via segment 138a, and the second semiconductor layer 146 is formed on the second gate dielectric layer 150. In various embodiments, the second gate dielectric layer 150 and the second semiconductor layer 146 are formed as shown and / or described in Figure 12.

[0091] As shown in the cross-sectional view 2300 of Figure 23, a fourth dielectric layer 128d is formed on the second semiconductor layer 146, and a second masking structure 2302 is formed on the fourth dielectric layer 128d. In some embodiments, the second masking structure 2302 includes a first hard mask 2304 on the fourth dielectric layer 128d, a first photoresist 2308 on the first hard mask 2304, a patterned hard mask 2306 on the first photoresist 2308, and a second photoresist 2310 on the patterned hard mask 2306. The second photoresist 2310 includes sidewalls defining an opening on the lower via segment 138a. The fourth dielectric layer 128d may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. In some embodiments, the second masking structure 2302 may be formed by a process described with respect to forming the masking structure 1302 of Figure 13. In some embodiments, the first hard mask 2304 and the patterned hard mask 2306 may be, for example, titanium, titanium nitride, tungsten, other metals, other suitable materials, or any combination thereof, or may include these.

[0092] As shown in the cross-sectional view 2400 of Figure 24, a second etching process is performed on the fourth dielectric layer 128d, the second semiconductor layer 146, and the second gate dielectric layer 150 according to the second masking structure 2302, thereby forming an opening 2402. The opening 2402 exposes the upper surface of the lower via segment 138a. The second etching process may include, for example, a dry etching process (e.g., RIE process, DRIE process, plasma etching process, etc.), a wet etching process, another suitable etching process, or any combination thereof.

[0093] As shown in the cross-sectional view 2500 of Figure 25, a third etching process is performed on the fourth dielectric layer 128d according to the second masking structure (2302 in Figure 24), thereby forming the first opening 2502 and the second opening 2504. The third etching process may include, for example, a dry etching process (e.g., RIE process, DRIE process, plasma etching process, etc.), a wet etching process, another suitable etching process, or any combination thereof. Furthermore, after the third etching process, a removal process is performed to remove the second masking structure (2302 in Figure 24) from above the fourth dielectric layer 128d. The first opening 2502 includes a portion of the opening below the fourth dielectric layer 128d (2402 in Figure 24).

[0094] As shown in the cross-sectional view 2600 of Figure 26, the upper via segment 138b and the second source / drain structure pairs 140, 142 are formed within the first and second openings (2502, 2504 in Figure 25), thereby forming an n-channel transistor 131b on top of a p-channel transistor 131a and defining or forming an electronic device 130 on top of the FEOL structure 104. In the upper via segment 138b and the second source / drain structure pairs 140, 142, the first source / drain structure 140 is formed within the first opening (2502 in Figure 25), and in the second source / drain structure pairs 140, 142, the second source / drain structure 142 is formed within the second opening (2504 in Figure 25). In various embodiments, the lower BEOL structure (106 in Figure 25) and the electronic device 130 are part of the BEOL structure 106. In some embodiments, the process for forming the upper via segment 138b and the second source / drain structure pairs 140, 142 includes depositing one or more conductive materials within the first and second openings (2502, 2504 in Figure 25) (e.g., by CVD, PVD, ALD, etc.) and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing one or more conductive materials includes depositing a conductive liner layer (e.g., titanium nitride, tantalum nitride, etc.) to line the first and second openings (2502, 2504 in Figure 25) and depositing a conductive core (e.g., copper, aluminum, tungsten, other conductive materials, or any combination thereof) on the conductive liner layer. In various embodiments, the process for forming the n-channel transistor 131b includes the processing steps shown and / or described in Figures 18 to 26. The lower via segment 138a and the upper via segment 138b define the conductive source / drain via 138.

[0095] Figures 27–38 show cross-sectional views 2700–3800 of several embodiments of a third method for forming an integrated chip (IC) having electronic devices including transistors stacked perpendicularly to each other, according to the present disclosure. Although the cross-sectional views 2700–3800 shown in Figures 27–38 are described with reference to the third method, it is understood that the structures shown in Figures 27–38 are not limited to the third method, but rather may exist separately and independently from the third method. Furthermore, although Figures 27–38 are described as a series of steps, these steps are not limited in that the order of the steps can be changed in other embodiments, and it is understood that the disclosed method is applicable to other structures as well. In other embodiments, some of the steps shown and / or described may be omitted in whole or in part.

[0096] As shown in the cross-sectional view 2700 of Figure 27, a semiconductor substrate 102 is provided, and a FEOL structure 104, a lower BEOL structure 602, a second dielectric layer 128b, and a first source / drain structure pair 132, 134 are formed on the semiconductor substrate 102. In some embodiments, the structure of Figure 27 is formed as shown and / or described in Figures 6 to 8.

[0097] As shown in the cross-sectional view 2800 of Figure 28, the first semiconductor layer 144 is formed on the first source / drain structure pair 132, 134. The first semiconductor layer 144 may be formed by one or more deposition processes, which may include, for example, one or more of the following: a PVD process, a CVD process, an ALD process, or other suitable growth or deposition processes. Furthermore, one or more deposition processes are performed at a first deposition temperature, for example, about 400°C or less.

[0098] As shown in the cross-sectional view 2900 of Figure 29, a patterning process is performed on the first semiconductor layer 144. The patterning process may include, for example, forming a masking layer (not shown) on the first semiconductor layer 144, etching the first semiconductor layer 144 according to the masking layer, and removing the masking layer.

[0099] As shown in the cross-sectional view 3000 of Figure 30, the first gate dielectric layer 148 is formed on the first semiconductor layer 144 and the first source / drain structure pair 132, 134. The first gate dielectric layer 148 may be formed, for example, by a PVD process, a CVD process, an ALD process, or other suitable growth or deposition process. In various embodiments, the first gate dielectric layer 148 is in direct contact with the opposing outer sidewalls of the first semiconductor layer 144 and has a bottom surface aligned with the bottom surface of the first semiconductor layer 144.

[0100] Furthermore, as shown in cross-sectional figure 3000, a third dielectric layer 128c is formed on the first gate dielectric layer 148, and an opening 3002 is formed within the third dielectric layer 128c. The third dielectric layer 128c may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. In some embodiments, the process for forming the opening 3002 includes forming a masking layer (not shown) on the third dielectric layer 128c, etching the third dielectric layer 128c according to the masking layer, and performing a removal process to remove the masking layer.

[0101] As shown in the cross-sectional view 3100 of Figure 31, the gate electrode 136 is formed within the third dielectric layer 128c, thereby forming the p-channel transistor 131a on the lower BEOL structure 602. The gate electrode 136 may be formed as shown and / or described in Figure 11.

[0102] As shown in the cross-sectional view 3200 of Figure 32, a second gate dielectric layer 150 is formed on the gate electrode 136, and a second semiconductor layer 146 is formed on the second gate dielectric layer 150. The second gate dielectric layer 150 and the second semiconductor layer 146 may be formed as shown and / or described in Figure 12.

[0103] As shown in the cross-sectional view 3300 of Figure 33, a patterning process is performed on the second semiconductor layer 146. The patterning process may include, for example, forming a masking layer (not shown) on the second semiconductor layer 146, etching the second semiconductor layer 146 according to the masking layer, and removing the masking layer.

[0104] As shown in the cross-sectional view 3400 of Figure 34, the fourth dielectric layer 128d is formed on the second semiconductor layer 146. The fourth dielectric layer 128d may be formed, for example, by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. In various embodiments, the fourth dielectric layer 128d is in direct contact with the opposing outer wall of the second semiconductor layer 146, and the bottom surface of the fourth dielectric layer 128d is aligned with the bottom surface of the second semiconductor layer 146.

[0105] As shown in the cross-sectional view 3500 of Figure 35, the masking structure 3502 is formed on the fourth dielectric layer 128d. In some embodiments, the masking structure 3502 includes a first hard mask 3504 on the fourth dielectric layer 128d, a first photoresist 3508 on the first hard mask 3504, a patterned hard mask 3506 on the first photoresist 3508, and a second photoresist 3510 on the patterned hard mask 3506. The second photoresist 3510 includes sidewalls defining an opening 3512 above the individual source / drain structure 132 in the first source / drain structure pair 132, 134. In some embodiments, the masking structure 3502 may be formed by the process described with respect to forming the masking structure 1302 of Figure 13. In some embodiments, the first hard mask 3504 and the patterned hard mask 3506 may be, for example, titanium, titanium nitride, tungsten, other metals, other suitable materials, or any combination thereof, or may include them.

[0106] As shown in the cross-sectional view 3600 of Figure 36, a first etching process is performed on the first gate dielectric layer 148, the third dielectric layer 128c, the second gate dielectric layer 150, and the fourth dielectric layer 128d according to the masking structure 3502, thereby forming via openings 3602. The via openings 3602 expose the upper surfaces of the individual source / drain structures 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes a dry etching process (e.g., RIE process, DRIE process, plasma etching process, etc.), a wet etching process, another suitable etching process, or any combination thereof.

[0107] As shown in the cross-sectional view 3700 of Figure 37, a second etching process is performed on the fourth dielectric layer 128d according to the masking structure (3502 in Figure 36), thereby forming the first opening 3702 and the second opening 3704. The second etching process may include, for example, a dry etching process (e.g., RIE process, DRIE process, plasma etching process, etc.), a wet etching process, another suitable etching process, or any combination thereof. Furthermore, after the second etching process, a removal process is performed to remove the masking structure (3502 in Figure 36) from the fourth dielectric layer 128d. The first opening 3702 includes a portion of the via opening (3602 in Figure 36) below the fourth dielectric layer 128d.

[0108] As shown in the cross-sectional view 3800 of Figure 38, conductive source / drain vias 138 and second source / drain structure pairs 140, 142 are formed within the first and second openings (3702, 3704 in Figure 37), thereby forming an n-channel transistor 131b on top of a p-channel transistor 131a and defining or forming an electronic device 130 on top of the FEOL structure 104. The conductive source / drain vias 138 and second source / drain structure pairs 140, 142 may be formed as shown and / or described in Figure 16.

[0109] Figure 39 shows a flowchart of several embodiments of Method 3900 for forming an integrated chip (IC) having an electronic device including transistors stacked perpendicularly to each other according to the present disclosure. Although Method 3900 is shown and / or described as a series of steps or events, it is understood that the Method is not limited to the shown order or steps. Thus, in some embodiments, the steps may be performed in a different order and / or simultaneously than those shown. Furthermore, in some embodiments, the shown steps or events may be subdivided into multiple steps or events, which may be performed at separate times or simultaneously with other steps or sub-steps. In some embodiments, some of the shown steps or events may be omitted, and other unshown steps or events may be included.

[0110] In step 3902, a FEOL structure is formed on a semiconductor substrate, and a lower BEOL structure is formed on the FEOL structure. The FEOL structure includes one or more lower semiconductor devices on the semiconductor substrate. Figure 6 shows cross-sectional views 600 corresponding to various embodiments of step 3902.

[0111] In step 3904, a first source / drain structure pair is formed within the first dielectric layer on top of the lower BEOL structure. Figures 7 and 8 show cross-sectional views 700 and 800 corresponding to various embodiments of step 3904.

[0112] In step 3906, a first semiconductor layer is formed on a first source / drain structure pair, and the first semiconductor layer includes a first conductivity type. Figure 9 shows a cross-sectional view 900 corresponding to various embodiments of step 3906. Figures 28 and 29 show cross-sectional views 2800 and 2900 corresponding to several other embodiments of step 3906.

[0113] In step 3908, a first gate dielectric layer is formed on the first semiconductor layer. Figure 9 shows cross-sectional views 900 corresponding to various embodiments of step 3908. Figure 30 shows cross-sectional views 3000 corresponding to some other embodiments of step 3908.

[0114] In step 3910, a gate electrode is formed within a second dielectric layer on a first gate dielectric layer, thereby defining a p-channel transistor on the lower BEOL structure. Figures 10 and 11 show cross-sectional views 1000 and 1100 corresponding to several embodiments of step 3910. Figures 30 and 31 show cross-sectional views 3000 and 3100 corresponding to several other embodiments of step 3910.

[0115] In step 3912, a second gate dielectric layer is formed on the gate electrode and the second dielectric layer. Figure 12 shows cross-sectional views 1200 corresponding to various embodiments of step 3912. Figure 22 shows cross-sectional views 2200 corresponding to some other embodiments of step 3912. Figure 32 shows cross-sectional views 3200 corresponding to further embodiments of step 3912.

[0116] In step 3914, a second semiconductor layer is formed on the second gate dielectric layer, and the second semiconductor layer contains a second conductivity type opposite to the first conductivity type. Figure 12 shows cross-sectional views 1200 corresponding to various embodiments of step 3914. Figure 22 shows cross-sectional views 2200 corresponding to several other embodiments of step 3914. Figures 32 and 33 show cross-sectional views 3200 and 3300 corresponding to several other embodiments of step 3914.

[0117] In step 3916, conductive source / drain vias are formed on the first source / drain structure in the first source / drain structure pair. Figures 13 to 16 show cross-sectional views 1300 to 1600 corresponding to various embodiments of step 3916. Figures 18 to 21 and 23 to 26 show cross-sectional views 1800 to 2100 and 2300 to 2600 corresponding to some other embodiments of step 3916. Figures 35 to 38 show cross-sectional views 3500 to 3800 corresponding to further embodiments of step 3916.

[0118] In step 3918, a second source / drain structure pair is formed within a third dielectric layer on a second semiconductor layer, thereby forming an n-channel transistor and electronic device within a BEOL structure on top of a FEOL structure. The first source / drain structure in the second source / drain structure pair overlaps a conductive source / drain via. Figures 15 and 16 show cross-sectional views 1500 and 1600 corresponding to various embodiments of step 3918. Figures 25 and 26 show cross-sectional views 2500 and 2600 corresponding to several other embodiments of step 3918. Figures 37 and 38 show cross-sectional views 3700 and 3800 corresponding to further embodiments of step 3918.

[0119] Accordingly, in some embodiments, the present invention relates to an IC including an electronic device disposed within a BEOL structure on a semiconductor substrate, wherein the electronic device includes an n-channel transistor superimposed on a p-channel transistor.

[0120] In some embodiments, the present invention provides an integrated chip (IC) comprising: a lower dielectric structure overlapping a semiconductor substrate; a gate structure on the lower dielectric structure, wherein the gate structure includes a first surface facing a second surface; a first semiconductor layer arranged between the first surface of the gate structure and the lower dielectric structure; and a second semiconductor layer on the second surface of the gate structure. In embodiments, the IC further includes a plurality of conductive wires and a plurality of conductive vias disposed within the lower dielectric structure and below the first and second semiconductor layers. In embodiments, the gate structure includes a gate electrode, a first gate dielectric layer, and a second gate dielectric layer, wherein the first gate dielectric layer is arranged between the gate electrode and the first semiconductor layer, and the second gate dielectric layer is arranged between the gate electrode and the second semiconductor layer. In an embodiment, the IC further includes a first source / drain structure pair arranged on the first semiconductor layer and spaced apart on the opposing sides of the gate electrodes, and a second source / drain structure pair arranged on the second semiconductor layer and spaced apart on the opposing sides of the gate electrodes. In an embodiment, the IC further includes conductive vias extending perpendicularly from the first source / drain structure in the first source / drain structure pair to the first source / drain structure in the second source / drain structure pair. In an embodiment, the conductive vias are in direct contact with the opposing sidewalls of the first semiconductor layer and the opposing sidewalls of the second semiconductor layer. In an embodiment, the outer wall of the first semiconductor layer is spaced apart between the first source / drain structure pairs, and the outer wall of the second semiconductor layer is spaced apart between the second source / drain structure pairs. In an embodiment, the first semiconductor layer comprises a first material, the second semiconductor layer comprises a second material, and the semiconductor substrate comprises a third material, wherein the first material, the second material, and the third material are different from each other.

[0121] In some embodiments, the present invention provides an integrated chip (IC) comprising: a lower wiring structure on a semiconductor substrate; a first semiconductor device on the lower wiring structure, wherein the first semiconductor device comprises a first source / drain structure pair on the lower wiring structure, a first semiconductor layer on the first source / drain structure pair, and a first gate dielectric layer on the first semiconductor layer; a gate electrode on the first gate dielectric layer; and a second semiconductor device on the first semiconductor device, wherein the second semiconductor device comprises a second gate dielectric layer on the gate electrode, a second semiconductor layer on the second gate dielectric layer, and a second source / drain structure pair on the second semiconductor layer. In embodiments, the IC further comprises a first dielectric layer disposed between the first gate dielectric layer and the second gate dielectric layer, wherein the first dielectric layer encloses the gate electrode from the side. In embodiments, the first semiconductor device is configured as a p-channel transistor, and the second semiconductor device is configured as an n-channel transistor. In an embodiment, the outer wall of the first semiconductor layer is spaced apart between the first source / drain structure pair, and the outer wall of the second semiconductor layer is spaced apart between the second source / drain structure pair. In an embodiment, the first gate dielectric layer is in direct contact with the opposing side walls of the first semiconductor layer. In an embodiment, the first semiconductor layer comprises a first metal oxide, and the second semiconductor layer comprises a second metal oxide different from the first metal oxide. In an embodiment, the IC further comprises transistors arranged on the semiconductor substrate, the transistors comprising source / drain region pairs arranged within the semiconductor substrate, and a lower gate electrode on the semiconductor substrate between the source / drain region pairs, wherein the individual source / drain regions in the source / drain region pairs are electrically coupled to the first source / drain structure in the first source / drain structure pair via the lower wiring structure.

[0122] In some embodiments, the present invention provides a method for forming an integrated circuit (IC), the method comprising: forming a lower wiring structure on a semiconductor substrate; forming a first source / drain structure pair on the lower wiring structure; depositing a first semiconductor layer on the first source / drain structure pair; depositing a first gate dielectric layer on the first semiconductor layer; forming a gate electrode on the first gate dielectric layer; forming a second gate dielectric layer on the gate electrode; forming a second semiconductor layer on the second gate dielectric layer; and forming a second source / drain structure pair on the second semiconductor layer. In embodiments, the method further comprises forming conductive vias between the first source / drain structure in the first source / drain structure pair and the second source / drain structure in the second source / drain structure pair. In embodiments, the conductive vias and the second source / drain structure are formed simultaneously. In one embodiment, forming the gate electrode includes depositing a dielectric layer on the first gate dielectric layer, etching the dielectric layer to form an opening within the dielectric layer, depositing one or more conductive materials within the opening, and performing a planarization process on the one or more conductive materials. In another embodiment, depositing the one or more conductive materials includes depositing a liner layer within the opening and depositing a conductive core on the liner layer.

[0123] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or achieve the same advantages as those described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0124] The present invention relates to an integrated chip (IC) which may include electronic devices. The electronic devices may be, for example, inverters, latches, logic gates, static random access memory (SRAM), dynamic random access memory (DRAM), or other suitable devices. The electronic device includes a plurality of semiconductor devices. The plurality of semiconductor devices may include, or may include, one or more n-channel transistors and one or more p-channel transistors electrically coupled in a predefined manner to form the electronic device. Typically, the transistors of the electronic device are located within a front-end-of-line (FEOL) structure on / in the substrate and formed during a FEOL process. [Explanation of Symbols]

[0125] 100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 200, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 300b, 300c, 300d, 300e, 300f, 300g, 300h, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 400b, 500b, 600, 700, 800, 900: Cross-sectional view 102: Semiconductor substrate 104:FEOL structure 106, 602: BEOL structure 108: Semiconductor devices 110: Source / Drain Area 112: Lower gate dielectric 114: Lower gate electrode 116: Side wall spacer 120: First stabilized capacitor electrode 122, 504a~c: Beer 120, 502a~d: Conductive wires 124:ILD layer 126: Lower dielectric structure 128a~d: Dielectric layer 130: Electronic devices 130a~c, 130a~f, 130d~f: Electronic devices 131a~b: Transistors 132, 134, 140, 142: Source / Drain Structure 136, 136a~b: TE gate 138a, 138b: Segments 144, 146: Semiconductor layer 144a, 146a: first metal oxide layer 144b, 146b: Second metal oxide layer 148, 150: Gate dielectric layer 151: Gate structure 300a, 400a, 500a: Cross-sectional view 302: Intermediate dielectric layer 402: Conductive Liner 404: Conductive structure 500c, 500d: Layout diagram 502:Second area 502a: First conductive wire 502b: Second conductive wire 502c: Third conductive wire 502d: Fourth conductive wire 504:Second area 506: BEOL devices 508:Bottom electrode 510: Dielectric layer 512:Top electrode 702, 1002, 1312, 1402, 1902, 2002, 2402, 3002, 3512, 3602: Openings 1302, 3502: Masking structure 1304, 2304, 3504: First hard mask 1306, 2306, 3506: Patterned hard masks 1308, 2308, 3508: First photoresist 1310, 2310, 3510: Second photoresist 1502, 1504, 2502, 2504, 3702, 3704: Opening 1700~2600, 2700~3800, 600~1600: Cross-sectional view 1802: Hard Mask 1804: Photoresist 1806: First masking structure 2302: Second masking structure 3900: Method

Claims

1. A lower dielectric structure superimposed on a semiconductor substrate, A gate structure on the lower dielectric structure, The gate structure includes a first surface facing a second surface, A first semiconductor layer arranged between the first surface of the gate structure and the lower dielectric structure, A second semiconductor layer on the second surface of the gate structure, An integrated chip equipped with these features.

2. A plurality of conductive wires and a plurality of conductive vias are disposed within the lower dielectric structure and located below the first semiconductor layer and the second semiconductor layer. The integrated chip according to claim 1, further comprising:

3. The gate structure includes a gate electrode, a first gate dielectric layer, and a second gate dielectric layer. The first gate dielectric layer is arranged between the gate electrode and the first semiconductor layer. The second gate dielectric layer is arranged between the gate electrode and the second semiconductor layer. The integrated chip according to claim 1.

4. A first source / drain structure pair arranged on the first semiconductor layer and spaced apart on the opposite side of the gate electrode, A second source / drain structure pair arranged on the second semiconductor layer and spaced apart on the opposing side of the gate electrode, The integrated chip according to claim 3, comprising:

5. Conductive vias extending vertically from the first source / drain structure in the first source / drain structure pair to the first source / drain structure in the second source / drain structure pair The integrated chip according to claim 4, further comprising:

6. The conductive vias are in direct contact with the opposing side walls of the first semiconductor layer and the opposing side walls of the second semiconductor layer. The integrated chip according to claim 5.

7. The outer wall of the first semiconductor layer is positioned with a gap between the first source / drain structure pair, The outer wall of the second semiconductor layer is positioned with a gap between the second source / drain structure pair. The integrated chip according to claim 4.

8. The first semiconductor layer comprises a first material, the second semiconductor layer comprises a second material, and the semiconductor substrate comprises a third material. The first material, the second material, and the third material are different from each other. The integrated chip according to claim 1.

9. The underlying wiring structure on the semiconductor substrate, A first semiconductor device on the lower wiring structure, The first semiconductor device includes a first source / drain structure pair on the lower wiring structure, a first semiconductor layer on the first source / drain structure pair, and a first gate dielectric layer on the first semiconductor layer. The gate electrode on the first gate dielectric layer, A second semiconductor device on the first semiconductor device, The second semiconductor device includes a second gate dielectric layer on the gate electrode, a second semiconductor layer on the second gate dielectric layer, and a second source / drain structure pair on the second semiconductor layer, An integrated chip equipped with these features.

10. The first dielectric layer is further disposed between the first gate dielectric layer and the second gate dielectric layer, The first dielectric layer encloses the gate electrode from the side. The integrated chip according to claim 9.

11. The first semiconductor device is configured as a p-channel transistor, The second semiconductor device is configured as an n-channel transistor. The integrated chip according to claim 9.

12. The outer wall of the first semiconductor layer is positioned with a gap between the first source / drain structure pair, The outer wall of the second semiconductor layer is positioned with a gap between the second source / drain structure pair. The integrated chip according to claim 9.

13. The first gate dielectric layer is in direct contact with the opposing sidewall of the first semiconductor layer. The integrated chip according to claim 12.

14. The first semiconductor layer comprises a first metal oxide, The second semiconductor layer contains a second metal oxide different from the first metal oxide. The integrated chip according to claim 9.

15. The semiconductor substrate further comprises transistors arranged on the semiconductor substrate, The aforementioned transistor is A source / drain region pair arranged within the semiconductor substrate, Includes a lower gate electrode on the semiconductor substrate between the source / drain region pair, Each individual source / drain region in the source / drain region pair is electrically coupled to the first source / drain structure in the first source / drain structure pair via the lower wiring structure. The integrated chip according to claim 9.

16. A method for forming an integrated chip, Forming a sub-wiring structure on a semiconductor substrate, Forming a first source / drain structure pair on the lower wiring structure, The first semiconductor layer is deposited on the first source / drain structure pair, The first gate dielectric layer is deposited on the first semiconductor layer, Forming a gate electrode on the first gate dielectric layer, Forming a second gate dielectric layer on the gate electrode, Forming a second semiconductor layer on the second gate dielectric layer, Forming a second source / drain structure pair on the second semiconductor layer, Methods that include...

17. A conductive via is formed between the first source / drain structure in the first source / drain structure pair and the second source / drain structure in the second source / drain structure pair. The method according to claim 16, further comprising:

18. The conductive via and the second source / drain structure are formed simultaneously. The method according to claim 17.

19. Forming the aforementioned terminal Depositing a dielectric layer on the aforementioned first gate dielectric layer, Etching the dielectric layer to form an opening within the dielectric layer, Depositing one or more conductive materials within the opening, Performing a planarization process on one or more conductive materials, The method according to claim 17, including the method described in claim 17.

20. Depositing one or more conductive materials is Depositing a liner layer within the aforementioned opening, Depositing a conductive core on the liner layer, The method according to claim 19, including the method described in claim 19.

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