Shared multiport memory from a single port

Abstract

This invention provides a multiport memory system that performs multiple read and write operations in parallel, using single-port memory, which is a memory element that can perform read-only or write-only operations at any given time. [Solution] A multiport memory system can perform multiple reads and writes (e.g., 1R / 1W, 1R / 3W, 2R / 2W, 3R / 1W, etc.) in parallel, even if the memory in the system can only perform one read or one write at any given time. [Effect] Area and power consumption can be reduced.

Description

Technical Field

[0003] , , , , , s

[0001] Examples of the present disclosure generally relate to a multi-port memory system (e.g., a system capable of performing multiple reads and writes in parallel) that uses a single-port memory (e.g., a memory element that can only perform a read or a write at any given time).

Background Art

[0002] Many applications require a memory (e.g., a multi-port memory system) that can perform reads and writes in parallel. These systems typically include dual-port memory (i.e., a memory that can perform at least one read and one write in parallel) to implement large delay buffers and dynamic coefficient storage devices. In an application specific integrated circuit (ASIC), the dual-port memory consumes more area and power per bit than a single-port memory (i.e., a memory that can only perform a single read or a single write at any given time). Also, multiple independent small memories are inefficient in terms of area compared to a single large memory. Therefore, replacing a multi-port memory (e.g., a two-port memory that can perform reads and writes in parallel) with a single-port memory has significant advantages in terms of area and power. By doing so, the area of the memory macro can be reduced by 40%.

Summary of the Invention

[0003] One embodiment describes a multiport memory system comprising: a single-port memory capable of performing only one read or one write operation at a time, wherein the address space of the single-port memory is less than or equal to half the address space of the multiport memory system; a divider configured to divide a received read address and a write address; a first register coupled to the write data port of the single-port memory and configured to store a write data word received while the single-port memory is performing a read operation; and a second register coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during a read operation. Furthermore, from the perspective of an external entity, the multiport memory system performs at least one of the following: (i) performing at least one read and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel using the single-port memory.

[0004] Another embodiment described herein is a method comprising: writing a first plurality of data words to a single-port memory using a write data port during a first cycle; reading a second plurality of data words from a first memory address of the single-port memory using a read data port during a second cycle; storing the first data word of the second plurality of data words in a first register coupled to the read data port during a second cycle; outputting the second data word of the second plurality of data words as read data during a second cycle; storing the first received word in a second register coupled to the write data port of the single-port memory during a second cycle; writing the first received word and the second received word to a second memory address of the single-port memory using a write data port during a third cycle; and during a third cycle The method includes outputting the second data word from among a second set of multiple data words as read data.

[0005] Another embodiment described herein is a multiport memory system comprising: a single-port memory capable of performing only one read or one write at a time, wherein the depth of the multiport memory system is greater than the depth of the single-port memory and the width of the multiport memory system is less than the width of the single-port memory; a first register coupled to the write data port of the single-port memory and configured to store a write data word received when the single-port memory is performing a read operation; and a second register coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during a read operation. Furthermore, the access pattern corresponding to the multiport system is sequential such that the memory addresses used to perform read and write operations increment according to a fixed amount.

[0006] To ensure a detailed understanding of the above features, a more specific explanation, concisely summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram illustrating a multiport memory system implemented using single-port memory, as an example. [Figure 2] This is a timing diagram illustrating an example of performing parallel read and write operations using a single-port memory. [Figure 3] This is a diagram illustrating a multiport memory system implemented using single-port memory, as an example. [Figure 4]This is a diagram illustrating a 1W3R memory system implemented using a single-port memory, as an example. [Figure 5] This is a diagram illustrating a configurable multiport memory system implemented using single-port memory, as an example. [Figure 6A] This example demonstrates how to perform peak cancellation and crest factor reduction using a multiport memory system. [Figure 6B] This example demonstrates how to perform peak cancellation and crest factor reduction using a multiport memory system. [Modes for carrying out the invention]

[0008] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of features. They are not characterized as an exhaustive description of the specification or as a limitation on the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not illustrated or explicitly described in that way.

[0009] Embodiments of this specification include one or more single-port memories (e.g., 1W or 1R memory). This document describes a multiport memory system that includes memory (referred to as "R") which can perform only one read or one write operation at any given time. In other words, a multiport memory system can perform multiple reads and writes (e.g., 1R / 1W, 1R / 3W, 2R / 2W, 3R / 1W, etc.) in parallel, even if the memory in the system can only perform one read or one write operation at any given time. A multiport system does not include any dual-port memory and relies solely on single-port memory. The advantages of doing so include reduced area and power consumption.

[0010] In one embodiment, the single-port memory includes a reduced depth (e.g., half the memory space) but stores multiple words (e.g., twice the width) at each address as a multi-port memory. Therefore, when a write operation is performed, the multi-port memory stores two data words at the same address in the single-port memory. Furthermore, when a read operation is performed, the system retrieves two (or more) words from the same address. However, the system also includes a register for storing (or buffering) one of the retrieved words so that only one of the retrieved words is output in the current cycle, and the other retrieved word is output in a subsequent cycle. In parallel, the multi-port memory system can receive and buffer the first word to be written to the single-port memory. In the next cycle, the system can perform another write operation to write the buffered word and the currently received word to the single-port memory. As a result, in each clock cycle, the multi-port system can perform one word read and one word write in parallel. This can be used with any application where the access pattern of a given port is sequential or consistent (for example, memory addresses increment by 1 rather than changing randomly).

[0011] Figure 1 shows a multiport memory system 100 implemented using a single-port memory 150, as an example. From the perspective of external circuitry (e.g., external entities), the multiport memory system 100 is a dual-port memory, for example, a memory capable of performing read and write operations in parallel. However, the memory system 100 includes a single-port memory 150 (i.e., a 1R or 1W memory) that can perform only one read or one write operation during any given clock cycle. In one embodiment, the memory system 100 is implemented in an IC (e.g., a processor, ASIC, field-programmable gate array, graphics processing unit, etc.).

[0012] As shown, the memory system 100 receives a write address 105, a read address 110, and write data 160 from an external circuit (e.g., a memory controller or processor). The memory system 100 uses a count 125 to switch between writing to or reading from the single-port memory 150. The count 125 can switch values ​​every clock cycle (e.g., high and low periods), during the first clock cycle the count 125 causes the memory system 100 to write data to the single-port memory 150, and during the next clock cycle the count causes the memory system 100 to read data from the single-port memory 150.

[0013] To perform the write operation, count 125 controls the multiplexer (mux) 120 so that "1" is supplied to the single-port memory 150, and instructs the memory 150 to write the data received at its write data port (i.e., WDATA). As shown, the write data at the WDATA input port has two words (2W), not just a single data word. For example, a dual-port memory can receive a single data word and write that word to the corresponding memory address. Yes, it is possible. However, the single-port memory 150 writes two words to each memory address instead. Therefore, the single-port memory 150 uses half the depth (e.g., half the memory addresses) as a dual-port memory, but has twice the width to store two words at each address.

[0014] The external circuitry, unaware that the multiport memory system 100 uses the single-port memory 150 instead of the dual-port memory, provides one word to be written each clock cycle. Meanwhile, the count 125 allows the memory system 100 to perform writes every other cycle. Thus, the memory system 100 includes a register 135 for storing or buffering the data word received during the cycle in which the single-port memory 150 is performing a read. Then, in the next cycle, the single-port memory 150 performs a write to store both the currently received word and the buffered word stored in register 135. The count 125 also controls the mux 115 to ensure that when a write is performed, the write address 105 is entered into the single-port memory 150, but when a read is performed, the read address 110 is entered. Furthermore, these addresses 105 and 110 are divided by 2 using the divider 130 (for example, by performing a bit shift operation), since the single-port memory 150 has half the memory space of the address space of the multi-port system 100 and stores two words in each memory location.

[0015] When performing a read, count 125 controls mux 120 to provide "0" to single-port memory 150 and instructs mux 120 to output the data stored at the memory location of read address 110 (divided by 2) using the read data port (RDATA). In response, single-port memory 150 outputs both words stored at this memory address. However, instead of providing both of these words to the requesting entity, memory system 100 uses mux 145 to output only one word, with the other word stored in register 140. Thus, when count 125 causes single-port memory 150 to perform a write in the next clock cycle, count 125 also instructs mux 145 to output the data stored in register 140, thereby outputting the second word retrieved during the previous read cycle. Register 140 thus pre-buffers the data that the requesting entity expects to desire in the next clock cycle. Therefore, the memory system 100 can perform the functions of a dual-port memory for any application where the access patterns for a given port (e.g., the read port and write port of a single-port memory 150) are sequential. Exemplary functions include streaming fast Fourier transforms (FFT) and peak cancellation-crest factor reduction (PC-CFR).

[0016] Although not shown in the diagram, buffer control logic may be provided around the memory system 100 to provide address and interface control logic. From the perspective of an external entity, the memory system 100 functions like a normal dual-port memory, with the only criterion being that the addresses of two words being written to or read from the memory system 100 are contiguous. It is also important to ensure that there are sufficient clock cycles between writing data to a particular address and reading data from that address, in order to ensure that the data is committed to memory before it is read.

[0017] Figure 2 shows an example of parallel reading and writing using a single-port memory. This is a timing diagram of count 125 in Figure 1 for execution. For clarity, Figure 2 is considered in conjunction with the memory system 100 shown in Figure 1. In one embodiment, at startup, count 125 instructs the memory system 100 in Figure 1 to enter read mode. During this read operation, a word of write data is transferred to register 135. Next, Figure 2 begins with cycle 205, where count 125 instructs the memory system 100 to perform a write, during which two words are written to the single-port memory 150. That is, the memory system 100 writes both the write data word received during the previous read operation and the currently received word to the same address location in memory 150.

[0018] In cycle 210, count 125 instructs the memory system 100 to perform a read to single-port memory 150, where two words are read from memory 150, but the memory system 100 outputs only one of those words as read data 155 during cycle 210, while the other retrieved word is stored (or buffered) in a register.

[0019] In parallel with these movements, during cycle 210, the memory system also stores the first word of the write data in register 135. Thus, from the perspective of an external circuit, it appears that memory system 100 reads one word from memory and stores another word of write data in memory during cycle 210. However, in reality, memory system 100 reads two words from single-port memory 150, outputs one of those words to the requesting entity, buffers the other word read from memory 150, and also buffers the word of write data.

[0020] In cycle 215, the count instructs memory system 100 to write to single-port memory 150 the first word of the write data buffered during cycle 210 and the second word of the write data currently being received in memory system 100. Similar to cycle 205, these two words of write data are stored at the same memory address.

[0021] In parallel with the execution of the write operation to single-port memory 150, the memory system also outputs the second word retrieved from memory 150 during the previous cycle 210. That is, count 125 controls mux 145 so that the word of read data buffered in register 140 is now output as read data 155. Thus, from the perspective of an external circuit, when memory system 100 is actually writing two words to single-port memory 150 and outputting the buffered word of read data retrieved in the previous cycle 21, it is performing another read and write in parallel.

[0022] In cycle 220, count 125 again instructs the memory system 100 to perform a read to the single-port memory 150, where two words are read from the memory 150. However, the memory system 100 outputs only one of those words as read data 155 during cycle 210, and the other retrieved word is stored (or buffered) in the register 140.

[0023] In parallel with these operations, the memory system 100 stores the first word of the write data in the register 135. Thus, from the perspective of an external circuit, it appears that the memory system 100 reads one word from the memory and stores another word of the write data in the memory during cycle 220. However, the memory system 100 actually reads two words from the single-port memory 150, outputs one of those words to the requesting entity, buffers the other word read from the memory 150, and also buffers the word of the write data.

[0024] In cycle 225, count 125 again instructs the memory system 100 to write to the single-port memory 150 the first word of the write data buffered during cycle 220 and the second word of the write data currently being received in the memory system 100. These two words of the write data are stored at the same memory address.

[0025] In parallel with the execution of the write operation to the single-port memory 150, the memory system 100 also outputs the second word retrieved from the memory 150 during the previous cycle 220. Thus, from the perspective of an external circuit, when the memory system 100 actually writes two words to the single-port memory 150 and outputs the buffered word of the read data retrieved in the previous cycle 220, it is performing another read and write in parallel.

[0026] In this way, the count 125 can continue to increment between read and write cycles to perform either a 2-word read or a 2-word write using the single-port memory 150 during each cycle. However, to the other circuits in the IC, the memory system 100 appears to perform 1R and 1W in parallel, like a dual-port memory.

[0027] Figure 3 shows a multiport memory system 300 implemented using a single-port memory 150 as an example. Some FFT applications require that the memory system 300 be able to start and stop write operations at any cycle. The memory system 100 in Figure 1 cannot do this because it assumes that each write stores two data words. However, the memory system 300 in Figure 3 enables arbitrary start and stop of writes using write control 320 and read control 315. In particular, Figure 3 does not show the ability to arbitrarily stop read operations, which can be achieved by adding a FIFO to the output of the memory system 100 to hold the read data.

[0028] Figure 3 contains many of the same components as Figure 1, and uses the same reference numerals. These components function similarly to those described above, so they will not be discussed in detail here.

[0029] For any start of a read, the memory system 300 allows access to the single-port memory 150 not to be aligned with the read / write access control performed by count 125. That is, if read enable (en1) is high while the memory system 300 is writing to the single-port memory 150, the system 300 delays the read access by one cycle. This is done by buffering the read address in input register 305 and then reading the memory in the next cycle using the signal generated by read control 315 (when count 125 instructs the system 300 to perform a read of the single-port memory 150). However, this delays the output read data (i.e., read data 155).

[0030] If the FFT application requires a fixed latency, this delay is adjusted by adding a second register 335 to the read data output. Here, both words of the memory output data are captured and output in the next two cycles. Read access is ready. If the inputs are in sequence (for example, no arbitrary start is performed), the read address is not delayed, and the second register 335 is used to delay the output to give a consistent additional cycle delay. In this way, the memory system 300 provides a delay from either the address stored in register 305 or the data output stored in register 335. In other words, there is always an additional delay in either the input or the output, resulting in a fixed delay from the input address to the output data. As an example, when the memory reads when the count is 1, the read control 315 generates 1 when en1 transitions to 1 when the count = 0. This persists until en1 = 0. This causes mux 310 to select register 305, and on the read output, mux 340 is used to select the memory output path without the read data output register 335.

[0031] In the event of any start of a write, the write side of system 300 provides an additional buffer (e.g., register 325) to the input, which allows data to be buffered when count = 1. In the event of any stop of a write, both words can be written, regardless of whether the data for the second item has been input, to ensure that the data for the first item is committed to memory. When writing resumes, the second word can be written together with the previous word stored in register 135. This avoids the need to have a separate write enable on memory, although the use of a separate write enable is an alternative.

[0032] Figure 4 shows an example of a 1W3R memory system 440 implemented using a single-port memory 450. That is, from the perspective of an external entity, the memory system 440 includes only a single-port memory 450 that can perform one write and three reads in parallel, but can perform either a read or a write at any given time. In this example, the single-port memory 450 has a depth of the data word size divided by 4 (W / 4) and a width of four times the data word size (W×4). Thus, each time the memory system 400 writes to the single-port memory 450, it stores four data words at the same memory address, and each time it reads from memory 450, it retrieves four data words.

[0033] The memory system 400 includes a mux405 controlled by a count 410 (which may be a 2-bit count in this case) that cycles through one write and three reads. That is, during the first cycle, the mux405 outputs a write command, but for the next three subsequent cycles, the mux405 outputs a read command. Thus, although from the outside it appears that the memory system 400 performs one write and three reads per cycle, the single-port memory 450 performs one write and three reads over four cycles.

[0034] Count 410 also controls mux 415, which passes the appropriate write address (i.e., addr0) and read addresses (i.e., addr1-3) to single-port memory 450. These addresses are divided by 4 by divider 420, since the address space of memory 450 is divided by 4.

[0035] The write buffer 425 prepares to write four data words to the single-port memory 450 during each write cycle (which occurs every fourth clock cycle). Again, the external circuitry assumes that the memory system 400 performs writes cycle by cycle, so the requesting entity sends a data word to the write buffer 425 each cycle. However, instead of performing writes to memory 450 in each cycle, the write buffer 425 stores the three data words received during the cycle in which memory 450 performs reads in three registers. The multiplexer 405 When a write command is issued, single-port memory 450 receives the data stored in the registers during the previous three read cycles, along with the currently received write data word, and writes the four data words to the same memory address. Thus, to the outside, it appears that memory system 400 writes a data word to memory every cycle, but in reality, memory system 400 writes to memory 450 once every four cycles. Furthermore, it is assumed that the first address in the sequence of four words is aligned (i.e., the first two LSBs are set to 0).

[0036] The memory system 400 includes three read buffers 430 for storing four data words to be read from the single-port memory 450 between each of three sequential read operations. For example, during the first read operation, four data words are read from addr1 / 4 and sent to read buffer 430A; during the second read operation, four data words are read from addr2 / 4 and sent to read buffer 430B; and during the third read operation, four data words are read from addr3 / 4 and sent to read buffer 430C.

[0037] Between each cycle, a data word is read from each of the buffers 430. That is, count 410 acts as a control signal for each mux in read buffers 430A-C, so that each mux outputs one of the data words stored in buffer 430. In other words, a vector for a particular address (i.e., four words stored at each address in single-port memory 150) is buffered in a register in read buffer 430 and then presented to the requesting entity one word at a time over four cycles.

[0038] For full-bandwidth access to memory of one word per cycle, accesses should be aligned and have contiguous addresses. In one embodiment, accesses are aligned by a first address having 00 as the least significant bit and starting synchronously with the memory access pattern. However, any unaligned read access may be supported simply by reading the associated vector and outputting a word from the vector associated with a given word read address. If an access requests a new vector from single-port memory 150, the memory system 400 may stall until the requested vector is read from memory. A signal may be provided to the requesting entity to indicate that the current read operation is stalled.

[0039] If only one word is requested from a specific vector read from memory 450, the maximum data rate is one word every four cycles (or more generally, M cycles for M-port memory). If the reads are consecutive but unaligned, there may be a small stall between the first vector read and the subsequent vector read, but after the first unaligned read, the stall aligns the read address with count 410, and the reads become consecutive. However, this interruption in the read data output can be avoided in subsequent processes by adding a small buffer to the output, delaying the start of the data buffer output, and effectively moving the interruption as a fixed latency delay to the start of the output sequence.

[0040] By using word enable during a write operation, arbitrary unaligned writes can also be supported, and word enable is active only for words written via the write interface until the port is committed to memory 450. In fact, before that commitment, the data can be rewritten to the word buffer (i.e., the same word address).

[0041] If error checking and / or correction is required for a vector stored in single-port memory 450, it may also be necessary to update the check bits associated with the entire vector, so simply updating the memory with word write enable may not be sufficient. However, if the data vector is not completed by the time the port write is scheduled by count 410, error checking and correction can be adjusted by converting the write access by that port into a memory read. The read data can be used directly to expand the write vector and fill in any missing words. When writing a continuous stream, this incomplete write occurs only on the first vector, where the write process started midway through a 4-port sequence. The input can be sufficiently stalled so that subsequent writes are complete vector writes before starting a read-correct write. Similar to read operations, stalls in the input of memory system 400 can be avoided, if necessary, by including a data buffer to absorb the stalls as described above in Figure 3.

[0042] Figure 5 is a diagram of a configurable multiport memory system 500 implemented using a single-port memory, as an example. Generally, Figure 5 shows a configurable multiport system 500 that performs different variations of read and write operations simultaneously, using a single-port memory 450 as shown in Figure 4. Figure 5 is abstracted from Figure 4 to show a block of circuitry that can be selectively used or not used to provide the desired multiport memory. That is, system 500 includes three write registers 520A-C and three read buffers 530A-C, which provide flexibility for the user or application to configure the multiport system 500 to function as a 1R / 3W memory, a 2R / 2W memory, or a 3R / 1W memory. It is also worth noting that some FPGA applications use read-only memory (ROM) from RAM that is initialized by a bitstream (i.e., does not require a write port). In these applications, as with ASICs that have ROM, a ROM that performs read-only operations (e.g., 4R) can be shared using the techniques described herein.

[0043] The memory system 500 includes a controller 505 that outputs an R / W signal 510 and an address signal 515. As in Figure 4, the single-port memory 450 stores four data words at each address (i.e., the memory 450 has an address space that is one-quarter the depth of the address space of the entire multi-port system 500). When configured as a 1R / 3W memory, only one of the read buffers 530 is used, and all three of the write buffers 525 are used. The other two read buffers 530 become inactive and can be powered off. In this case, the controller 505 ensures that the single-port memory performs one read operation and three write operations every four clock cycles. During the read cycle, four data words are read from the single-port memory 450 and stored in one of the read buffers 530. In this way, between each of the three subsequent write operations, the memory 450 and the read buffers 530 output one of the buffered words.

[0044] To write data to memory 450, during each cycle, the external entity provides three data words to the multiport system 500. When single-port memory 450 performs a read operation, the three write words received during that clock cycle are stored (i.e., buffered) in the write buffer 525 (for example, one word in each buffer 525). During the next three cycles in which single-port memory 450 performs a write operation, the three currently received data words, as well as one of the data words stored in the write buffer 525 during the read operation, are used in the single-port memory. It is written to the log memory 450. In this way, between each of the three write cycles, four data words are written to the same address.

[0045] When configured as a 2R / 2W memory, two of the read buffers 530 and two of the write buffers 525 are used. The other read and write buffers are unused and can be powered off. In this case, the controller 505 ensures that the single-port memory 450 performs two read operations and two write operations every four clock cycles. Between the two read cycles, four data words are read from the single-port memory 450 and stored in one of the two used read buffers 530. In this way, between each of the two write operations, the memory 450 and the two read buffers 530 output one of the buffered words.

[0046] In the case of 2R / 2W memory, during each cycle, an external entity provides two data words to the multiport system 500. When single-port memory 450 performs a read operation, the two write words received during that clock cycle are stored in two write buffers 525 (for example, one word in each buffer 525). During the next two cycles in which single-port memory 450 performs a write operation, the two currently received data words, as well as two of the data words stored in the two write buffers 525 during the read operation, are written to single-port memory 450. In this way, during each of the two write cycles, four data words are written to the same address. However, this assumes that the memory is always reading and writing words. In one embodiment, the memory may have the flexibility to skip a read or write in a particular clock cycle, in which case the memory may perform writes to words entered before the memory write slot of the associated port (gate them to memory using word enable). In the case of a read, the memory reads all words from memory when the associated slot occurs, but outputs only those requested words (i.e., the memory system tracks the input read enable but generates a data output enable signal for each word read, which is delayed accordingly).

[0047] When configured as 3R / 1W memory, only three of the read buffers 530 and one of the write buffers 525 are used. The two unused write buffers can be powered off. In this example, the multiport system 500 will operate in the same way as the multiport system 400 in Figure 4.

[0048] In this way, the multiport system 500 includes circuitry that supports various different multiport configurations using the single-port memory 450. At some point in time, the user or application can configure the multiport system 500 as a 1R / 3W memory, but at a later second point in time, the system 500 can be reconfigured as a 3R / 1W memory. Furthermore, the system 500 can support both 1R / W and 3R memory, in which case, for example, the memory is connected to a processor interface capable of performing random reads or writes using one port, while still retaining three read ports for consecutive high-bandwidth reads.

[0049] Figures 6A and 6B illustrate an example of running PC-CFR using different multiport memory systems. Specifically, Figure 6A shows running PC-CFR using multiple multiport memory 605s, and Figure 6B shows running PC-CFR using a single-port memory 650.

[0050] The system 600 shown in Figure 6A differs from the embodiments described above in that it includes four multiport memories 605 capable of performing at least one read and one write in parallel. That is, since the multiport memories 605 have independent read address ports and write address ports, they can perform at least one read and one write in parallel, unlike the embodiments described above in which the multiport system can be implemented using single-port memories. However, the system 640 in Figure 6B shows PC-CFR being implemented using single-port memories 660, which can save space and reduce costs.

[0051] In PC-CFR applications, the peak-to-average power of a signal is reduced by removing peaks by subtracting appropriately scaled predetermined pulses from the signal. These predetermined pulses are stored in memory 605 and can be looked up to cancel peaks by summing the outputs of multiplier 610. System 600 includes four pulse cancellation units, each associated with memory 605. Pulse data readouts are aligned with previously detected peaks (by logic not shown) by delaying the data by half the pulse length. The pulses are read from memory 605, scaled by multiplier 610 using the peak scale value, summed by adder 620, and subtracted from the delayed data by subtractor 625. In this case, there are four pulse cancellation units, but generally, there may be more or fewer pulse cancellation units applied in multiple iterations, the latter of which may be required due to peak regrowth elsewhere.

[0052] Each memory 605 is dual-port to allow pulse updates, and two banks may be implemented to allow updates in parallel with pulse cancellation operations, using bank switching at suitably convenient moments.

[0053] On the other hand, Figure 6B shows that it is possible to use the two-port shared memory described in the previous embodiment to replace the dual-port memory 605 in Figure 6A with a single-port memory 660. This reduces area and power consumption by replacing the dual-port memory with a single-port memory.

[0054] Furthermore, by noting that the pulses are the same in each memory 605 of Figure 6A, it is also possible to reuse the single-port memory 660 to make the same memory contents available to all pulse-canceling units 670. This reduces the total amount of memory bits to 1 / Q, where Q is the number of pulse-canceling units 670 served by the shared M-port memory. This can be interpreted as translating the area to a reduction of 1 / Q, although this may be slightly mitigated by the extra logic for buffering each port and the increased area per bit for memory macros with reduced depth.

[0055] Specifically, system 640 shows replacing a separate dual-port memory 605 with a single shared 8-port memory 660, in which case two ports are used to provide AXl-lite read and write access, and six ports are for read access by pulse-canceling units. Furthermore, two of the ports may reside in another iteration (not shown). Note that the AXl-lite read and write ports may be replaced by a single read / write port to allow for the addition of another pulse-canceling unit. The memory aspect ratio has been changed from 8k × 32 bits to 1k × 256 bits, which can be achieved using one or more physical memory macros (e.g., two 128-bit wide memories). can.

[0056] As a non-limiting example, three 8-port shared multiport memory 650s can replace 18 dual-port memory 605s, resulting in approximately a 7x reduction in memory macro area. Since memory occupies a large portion of the total area, this can reduce the total area to less than 50% compared to using memory 605s.

[0057] This disclosure is not limited to the use cases outlined above and can be applied to any application where the access patterns of a given port are sequential or consistent. Where this condition is met, all of the provided multiports are independent of each other and can be used for reading or writing as desired.

[0058] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to any specific described embodiments. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0059] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, all of which may be commonly referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0060] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections with one or more wires, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that contains or can store programs for use by, or in connection with, an instruction execution system, apparatus, or device.

[0061] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of various forms, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium is not a computer-readable storage medium, but rather a computer-readable signal medium used by an instruction execution system, apparatus, or device. It may be any computer-readable medium on which a program for use in connection with or in connection therewith can be communicated, propagated, or transferred.

[0062] Program code, embodied on a computer-readable medium, can be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0063] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java®, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or fully on a remote computer or server. In the latter scenario, the remote computer may be on a local area network (LAN) or a wide area network (wide User computing over any type of network, including area network (WAN). It may be connected to a data source or to an external computer (for example, via the internet using an Internet service provider).

[0064] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general-purpose computer, a dedicated computer, or another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device create means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0065] These computer program instructions can also be stored on a computer-readable storage medium, which can instruct a computer, a programmable data processing device, and / or other device to function in a particular way, such that the instructions stored on the computer-readable storage medium produce a manufactured article containing instructions that implement the modes of function / action specified in the blocks of a flow diagram and / or block diagram.

[0066] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flow diagram and / or block diagram.

[0067] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of the system, method, and computer program product according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur out of the order shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may execute depending on the functions involved. , or they can be executed in the reverse order. It should also be noted that each block in the block diagram and / or flowchart example, as well as combinations of blocks in the block diagram and / or flowchart example, can be implemented by a dedicated hardware-based system that performs a specified function or action, or combines dedicated hardware with computer instructions.

[0068] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. A multi-port memory system, A single-port memory capable of performing only one read or one write operation at a time, wherein the address space of the single-port memory is less than or equal to half the address space of the multi-port memory system, A divider configured to divide the received read address and write address, A first register is connected to the write data port of the single-port memory and configured to store the received write data word when the single-port memory is performing a read operation. The system comprises a second register, which is coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during the read operation, From the perspective of an external entity, the multiport memory system is a multiport memory system that performs at least one of the following: (i) performing at least one read and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel using the single port memory.

2. The multiport memory system according to claim 1, wherein during a write operation, a plurality of data words are received at the write data port, and one of the plurality of data words includes the write data word stored in the first register during the read operation.

3. The multiport memory system according to claim 1, wherein the single-port memory stores a plurality of data words in each memory location, each of the plurality of data words corresponds to a different address in the address space of the multiport memory system, but the plurality of data words correspond to the same address in the address space of the single-port memory.

4. The multiport memory system according to claim 1, further comprising a multiplexer connected to the read data port at a first input and connected to the output of the second register at a second input, the multiplexer being configured to select, as read data, whether to transmit a second data word read from the single port memory during the read operation or to transmit the first data word previously stored in the second register.

5. The multiport memory system is configured to start and stop data writing at any cycle using write control and read control, and the multiport memory system is configured A first multiplexer connected between the single-port memory and the received read address signal, wherein the selection signal of the first multiplexer is controlled by the read control, A third register, coupled to the input of the first multiplexer and configured to store the received read address signal, A second multiplexer connected between the write data port and the received write data, wherein the selection signal of the second multiplexer is controlled by the write control, A fourth register, coupled to the input of the second multiplexer and configured to store at least a portion of the received write data, A third multiplexer connected between the read output of the multiport memory system and the read data port, wherein the selection signal of the third multiplexer is controlled by the read control, The multiport memory system according to claim 1, further comprising: a fifth register coupled to the input of the third multiplexer and configured to store at least a portion of the read data provided by the read data port.

6. The system further comprises a plurality of read buffers coupled to the read data port, each of the plurality of read buffers configured to store a plurality of data words received from the single port memory during its respective read operation, and each of the plurality of read buffers outputs its respective data word during each read and write operation performed by the single port memory. From the aforementioned viewpoint of the external entity, the multiport memory system according to claim 1, wherein the multiport memory system performs a plurality of read operations in parallel.

7. The single-port memory further comprises a plurality of write buffers coupled to the write data port, each of the plurality of write buffers configured to buffer a plurality of write data words when the single-port memory performs a read operation, and at least one of the plurality of write buffers outputs one of the buffered plurality of write data words to the single-port memory when a write operation is performed. From the aforementioned viewpoint of the external entity, the multiport memory system according to claim 1, wherein the multiport memory system performs a plurality of write operations in parallel.

8. Multiple read buffers coupled to the aforementioned read data port, The multiport memory system according to claim 1, further comprising a plurality of write buffers coupled to the write data port, wherein the multiport memory system can be configured to function as one of 1R / xW, yR / xW, yR / 1W, xW, or yR memory by selectively using a subset of the plurality of read and write buffers, and x and y are integer values ​​of 2 or more.

9. The multiport memory system according to claim 8, wherein the plurality of read buffers and the plurality of write buffers are dynamically selectable, and as a result, the multiport memory system can switch to perform a different number of reads or writes in parallel from one of 1R / xW, yR / xW, yR / 1W, xW, or yR memory.

10. The single-port memory stores pulse data for peak cancellation-crest factor reduction (PC-CFR), and the multi-port memory system, The multiport memory system according to claim 1, comprising a plurality of pulse cancellation units coupled to the single-port memory using a port.

11. A method for performing read and write operations in parallel using single-port memory, During the first cycle, write a first set of data words to the single-port memory using the write data port, During the second cycle, read a second set of data words from the first memory address of the single-port memory using the read data port, During the second cycle, the first data word among the second plurality of data words is stored in the first register coupled to the read data port, During the second cycle, the second data word among the second plurality of data words is output as read data, During the second cycle, the first received word is stored in a second register connected to the write data port of the single-port memory, During the third cycle, the first received word and the second received word are written to the second memory address of the single-port memory using the write data port, A method comprising outputting, during the third cycle, the second data word among the second plurality of data words as read data.

12. The method according to claim 11, wherein, from the perspective of an external entity, the single-port memory is part of a multi-port memory system that performs at least one of the following: (i) performing at least one read and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel.

13. The method according to claim 12, wherein the address space of the single-port memory is less than or equal to half the address space of the multi-port memory system.

14. The method according to claim 13, further comprising dividing the write and read addresses used to perform read and write operations in the single-port memory by an integer value that is 2 or greater and a power of 2.

15. The method according to claim 11, wherein the first, second, and third cycles are consecutive cycles.

16. The method according to claim 11, further comprising adding a delay to the write data port and the read data port of the single-port memory, thereby starting and stopping a write operation at any cycle in the single-port memory.

17. The received read address is stored in a register, The method according to claim 16, further comprising selecting at least one of the received read address or the currently received read address stored in the register in order to perform a read operation in the single-port memory in response to the start or stop of a write operation in any cycle.

18. The method according to claim 11, further comprising configuring the single-port memory to function as one of 1R / xW, yR / xW, yR / 1W, xW, or yR multi-port memory by selectively using a subset of a plurality of read buffers and a plurality of write buffers in a first time, wherein x and y are integer values ​​of 2 or more.

19. The method according to claim 18, further comprising, in a second time after the first time, reconfiguring the single-port memory to function as a different multi-port memory by selectively using different subsets of the plurality of read and write buffers.

20. A multi-port memory system, A single-port memory capable of performing only one read or one write operation at a time, wherein the depth of the multi-port memory system is greater than the depth of the single-port memory, and the width of the multi-port memory system is smaller than the width of the single-port memory, A first register, coupled to the write data port of the single-port memory and configured to store the write data word received when the single-port memory is performing a read operation, The system comprises a second register, which is coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during the read operation, A multiport memory system in which the access pattern corresponding to the multiport system is sequential such that the memory addresses used to perform read and write operations increment according to a fixed amount.

21. The multiport memory system according to claim 20, wherein the single-port memory stores a plurality of data words in each memory location, each of the plurality of data words corresponds to a different address in the address space of the multiport memory system, but the plurality of data words correspond to the same address in the address space of the single-port memory.

22. The multiport memory system according to claim 20, further comprising a multiplexer connected to the read data port at a first input and connected to the output of the second register at a second input, the multiplexer being configured to select, as read data, to transmit a second data word read from the single port memory during the read operation or to transmit the first data word previously stored in the second register.

23. The system further comprises a plurality of read buffers coupled to the read data port, each of the plurality of read buffers configured to store a plurality of data words received from the single port memory during its respective read operation, and each of the plurality of read buffers outputs its respective data word during each read and write operation performed by the single port memory. From the perspective of an external entity, the multiport memory system according to claim 20, wherein the multiport memory system performs multiple read operations in parallel.

24. The single-port memory further comprises a plurality of write buffers coupled to the write data port, each of the plurality of write buffers configured to buffer a plurality of write data words when the single-port memory performs a read operation, and at least one of the plurality of write buffers outputs one of the buffered plurality of write data words to the single-port memory when a write operation is performed. From the perspective of an external entity, the multiport memory system according to claim 20, wherein the multiport memory system performs multiple write operations in parallel.

25. Multiple read buffers coupled to the aforementioned read data port, The multiport memory system according to claim 20, further comprising a plurality of write buffers coupled to the write data port, wherein the multiport memory system can be configured to function as one of 1R / xW, yR / xW, yR / 1W, xW, or yR memory by selectively using a subset of the plurality of read and write buffers, and x and y are integer values ​​of 2 or more.

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