Forcibly terminating and resuming prefetching in the instruction cache.

Abstract

This device provides efficient cache control during instruction cache prefetching. [Solution] In a processor 100 including a hierarchical cache, the memory controller subsystem infers whether a virtual address in the first memory cache is a hit or miss, infers whether virtual addresses 200h to 380h are physical addresses 220 and 225, configures the status to an active state in relation to the hit or miss status and the physical address, reconfigures the status to an inactive state in response to receiving a first indication from the CPU core that no program instructions related to the virtual address are needed, and reconfigures the status to an active state in response to receiving a second indication from the CPU core that a program instruction related to the virtual address is needed.

Description

Technical Field

[0001] Some memory systems include a multi-level cache system. When a memory controller receives from a processor core a request for a particular memory address, the memory controller determines whether data associated with that memory address exists in a first-level cache (L1). If the data exists in the L1 cache, the data is returned from the L1 cache. If the data associated with the memory address does not exist in the L1 cache, the memory controller accesses a second-level cache (L2). Since the L2 is larger than the L1 cache, it can hold more data. If the data exists in the L2 cache, the data is returned from the L2 cache to the processor core, and a copy is also saved in the L1 cache if the same data is requested again. Additional memory level hierarchies are possible.

Summary of the Invention

[0002] In one example, a system includes a processor that includes a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem inferentially determines a hit or miss situation for a virtual address in the first memory cache and inferentially converts the virtual address to a physical address. In relation to the hit or miss situation and the physical address, the memory controller subsystem configures the status to an active state. In response to receiving a first indication from the CPU core that a program instruction associated with the virtual address is not needed, the memory controller subsystem reconfigures the status to an inactive state, and in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is needed, the memory controller subsystem reconfigures the status to an active state without additional access to a TAGRAM or address translation logic.

Brief Description of the Drawings

[0003] [Figure 1] A processor following one example is illustrated.

[0004] [Figure 2] The following diagram illustrates the promotion of an L1 memory cache access to a full L2 cache line access, following an example.

[0005] [Figure 3] This is a flowchart illustrating performance improvement according to one example.

[0006] [Figure 4] This is another flowchart illustrating a different performance improvement following the example.

[0007] [Figure 5] Figure 1 shows the system including the processor. [Modes for carrying out the invention]

[0008] Figure 1 shows an example of a processor 100 including a hierarchical cache subsystem. In this example, the processor 100 includes a central processing unit (CPU) core 102, a memory controller subsystem 101, an L1 data cache (L1D) 115, an L1 program cache (L1P) 130, and an L2 memory cache 155. In this example, the memory controller subsystem 101 includes a data memory controller (DMC) 110, a program memory controller (PMC) 120, and an integrated memory controller (UMC) 150. In this example, at the L1 cache level, data and program instructions are separated into different caches. Instructions executed by the CPU core 102 are stored in the L1P 130 and then provided to the CPU core 102 for execution. Meanwhile, data is stored in the L1D 115. CPU core 102 can read data from and write data to L1D 115, and has read access to L1P 130 (but no write access to L1P 130). L2 memory cache 155 can store both data and program instructions.

[0009] The sizes of L1D 115, L1P 130, and L2 memory cache 155 may vary depending on the implementation, but in one example, the size of L2 memory cache 155 is larger than either L1D 115 or L1P 130. For example, L1D 115 may be 32 kilobytes, L1P may be 32 kilobytes, while L2 memory cache may be 64 kilobytes to 4 MB. Also, the cache line size of L1D 115 is the same as the cache line size of L2 memory cache 155 (e.g., 128), while the cache line size of L1P 130 is even smaller (e.g., 64 bytes).

[0010] When CPU core 102 requires data, DMC 110 receives an access request for the target data from CPU core 102. The access request may include an address (e.g., a virtual address) from CPU core 102. DMC 110 determines whether the target data exists in L1D 115. If the data exists in L1D 115, it is returned to CPU core 102. However, if the data requested by CPU core 102 does not exist in L1D 115, DMC 110 provides an access request to UMC 150. This access request may include a physical address generated by DMC 110 based on the virtual address (VA) provided by CPU core 102. UMC 150 determines whether the physical address provided by DMC 110 exists in L2 memory cache 155. If the data exists in L2 memory cache 155, it is returned from L2 memory cache 155 to CPU core 102, and a copy is stored in L1D 115. Additional hierarchies of the cache subsystem may exist. For example, the L3 memory cache or system memory may be available for access. Therefore, if the data requested by CPU core 102 does not exist in either L1D 115 or L2 memory cache 155, the data may be accessed at an additional cache level.

[0011] With respect to program instructions, when CPU core 102 requires additional instructions to be executed, CPU core 102 provides VA 103 to PMC 120. PMC responds to the VA 103 provided by CPU core 102 by initiating a workflow and returning a prefetch packet 105 of the program instructions to CPU 102 for execution. The size of the prefetch packet varies depending on the implementation, but in one example, the size of the prefetch packet is equal to the size of the L1P 130 cache line. If the L1P cache line size is, for example, 64 bytes, the prefetch packet returned to CPU core 102 may also include a 64-byte program instruction.

[0012] The CPU core 102 also provides a prefetch count 104 to the PMC 120. In some implementations, the prefetch count 104 is provided to the PMC 120 after the CPU core 102 provides the VA 103. The prefetch count 104 indicates the number of prefetch units for program instructions following the prefetch unit that begins at VA 103. For example, the CPU core 102 may provide a VA of 200h. This VA is associated with a 64-byte prefetch unit that begins at virtual address 200h. If the CPU core 102 wants the memory controller subsystem 101 to send additional instructions for execution following the prefetch unit associated with virtual address 200h, the CPU core 102 presents a prefetch count with a value greater than 0. A prefetch count of 0 means that the CPU core 102 does not need any more prefetch units. For example, a prefetch count of 6 requests that CPU core 102 retrieve and send back instructions for an additional 6 prefetch units for execution. The returned prefetch units are shown in Figure 1 as prefetch packets 105.

[0013] Continuing with the example in Figure 1, the PMC120 includes a TAGRAM121, an address converter122, and a register123. The TAGRAM121 contains a list of virtual addresses whose contents (program instructions) are cached in the L1P130. The address converter122 converts virtual addresses to physical addresses (PAs). In one example, the address converter122 generates physical addresses directly from virtual addresses. For example, the lower 12 bits of the PA can be used as the lowest 12 bits of the PA, and the most significant bits of the PA (above the lower 12 bits) are generated based on a set of tables configured in main memory before program execution. In this example, the L2 memory cache155 can be addressed using physical addresses rather than virtual addresses. Register 123 stores a hit / miss indicator 124 from a TAGRAM 121 lookup, a physical address 125 generated by the address converter 122, and a valid bit 126 (also referred to herein as a status bit) indicating whether the corresponding hit / miss indicator 124 and physical address 125 are valid or invalid.

[0014] Upon receiving VA103 from CPU102, PMC120 performs a TAGRAM121 lookup to determine whether L1P130 contains a program instruction associated with its virtual address. The result of the TAGRAM lookup is a hit or miss indicator 124. A hit means that the VA is present at L1P130, and a miss means that the VA is not present at L1P130. In the case of an L1P130 hit, the target prefetch unit is retrieved from L1P130 by PMC120 and returned to CPU core 102 as a prefetch packet 105.

[0015] In the case of an L1P 130 miss, the PA (generated based on the VA) is provided to the UMC150 by the PMC120, as shown in 142. The byte count 140 is also provided to the UMC150 by the PMC120. The byte count indicates the number of bytes in the L2 memory cache 155 to be retrieved (if any), starting with PA 142. In one example, the byte count 140 is a multi-bit signal that encodes the number of bytes desired from the L2 memory cache 155. In one example, the line size of the L2 memory cache is 128 bytes, and each line is divided into an upper half (64 bytes) and a lower half (64 bytes). Therefore, the byte count 140 can encode the number 64 (if only the upper or lower half of 64 bytes is needed from a given L2 memory cache line) or 128 (if the entire L2 memory cache line is needed). In another example, the byte count could be a single bit signal where one state (e.g., 1) implicitly encodes the entire L2 memory cache line, and another state (e.g., 0) implicitly encodes half of the L2 memory cache line.

[0016] UMC150 also includes TAGRAM152. PA142 received from PMC120 by UMC150 is used to perform a lookup to TAGRAM152 to determine whether the target PA is a hit or a miss in L2 memory cache 155. If there is a hit in L2 memory cache 155, target information, which may be half a cache line or the entire cache line depending on the byte count 140, is returned to CPU core 102, a copy of which is stored in L1P 130, from which the same program instruction is provided to CPU 102 the next time CPU core 102 attempts to fetch the same program instruction.

[0017] In the example in Figure 1, CPU core 102 provides VA 103 and prefetch count 104 to PMC 120. PMC 120 initiates the workflow for retrieving prefetch packets from L1P 130 or L2 memory cache 155, as described above. Using prefetch count 104 and the original VA 103, PMC 120 calculates additional virtual addresses and begins retrieving prefetch packets corresponding to those calculated VAs from L1P 130 or L2 memory cache 155. For example, if the prefetch count is 2 and VA 103 from CPU core 102 is 200h, instead of CPU core 102 providing each of those VAs to PMC 120, PMC 120 calculates the next two VAs as 240h and 280h.

[0018] Figure 2 illustrates a specific example of how optimization can lead to improved performance for the processor 100. As mentioned earlier, the line width of the L2 memory cache 155 is greater than the line width of the L1P. In one example, as shown in Figure 2, the width of the L1P is 64 bytes, and the line width of the L2 memory cache 155 is 128 bytes. The L2 memory cache 155 is configured as an upper half 220 and a lower half 225. The UMC 150 can read the entire 128-byte cache line from the L2 memory cache 155, or only half of the L2 memory cache (upper half 220 or lower half 225).

[0019] A given VA can be converted to a specific PA when it resides in the L2 memory cache 155, and this specific PA maps to either the lower half 225 or the upper half 220 of a given line in the L2 memory cache. Based on the addressing scheme used to represent the VA and PA, the PMC 120 can determine whether a given VA maps to the lower half 225 or the upper half 220. For example, a specific bit in the VA (e.g., bit 6) can be used to determine whether the corresponding PA maps to the upper half or the lower half of the line in the L2 memory cache. For example, bit 6 being 0 may indicate the lower half, and bit 6 being 1 may indicate the upper half.

[0020] Reference numeral 202 shows an example of a VA of 200h provided to the PMC120 by the CPU core 102, and the corresponding prefetch count of 6. Reference numeral 210 illustrates that the list of VAs executed via the cache pipeline described above includes 200h (received from the CPU core 102) and the following six consecutive virtual addresses 240h, 280h, 2c0h, 300h, 340h, and 380h (calculated by the PMC120).

[0021] Each address from 200h to 380h is processed as described above. Any or all of the VAs may be misses at L1P 130. PMC120 can combine two consecutive VAs that miss at L1P 130 into a single L2 cache line access attempt. Thus, if both 200h and 240h are misses at L1P 130, and the physical address corresponding to 200h corresponds to the lower half 225 of a particular cache line in L2 memory cache 155, and the physical address corresponding to 240h corresponds to the upper half 225 of the same cache line in L2 memory cache, PMC120 can issue a single PA142 to UMC150 along with a byte count 140 that identifies the entire cache line from L2 memory cache. Thus, two consecutive VA misses at L1P 130 can be promoted to a single full-line L2 memory cache lookup.

[0022] If the last VA in a series of VAs initiated by CPU core 102 (e.g., VA380h in VA series 210) maps to the lower half of the cache line 225 of L2 memory cache 155, then, according to the example described, the entire cache line of L2 memory cache 155 is retrieved, even if only the lower half 225 was needed. The same response occurs when the CPU provides VA103 to PMC120 with a prefetch count of 0, meaning that CPU 102 only needed a single prefetch unit. The additional overhead, time, or power consumption spent to retrieve the entire cache line and provide the entire cache line to L1P 130 is very small, if any. Since program instructions are often executed in linear order, it is generally more likely that program instructions in the upper half 220 will be executed following instructions in the lower half 225 anyway. Therefore, the next instruction set is received at very little cost, and such instructions are likely to be needed anyway.

[0023] Figure 2 illustrates, via arrow 213, that VA380h maps to the lower half 225 of cache line 260 in L2 memory cache 155. PMC120 determines this mapping, for example, by checking one or more bits of the corresponding physical address following a translation by VA or address converter 122. PMC120 promotes the lookup process to the full cache line by UMC150 by presenting the PA associated with VA380h along with a byte count 104 that identifies the entire cache line. The entire 128-byte cache line (if present in L2 memory cache 155) is then retrieved and written to L1P 130 in two separate 64-byte cache lines, as shown in 265.

[0024] However, if the last VA in a series of VAs (or, if there is only one VA for a prefetch count of 0) maps to the upper half 220 of a cache line of the L2 memory cache 155, the PMC 120 requests the UMC 150 to look up within its TAGRAM 152 and return only the upper half of the cache line to the CPU core 102 and the L1P 130. The next PA may be in the lower half 225 of the next cache line of the L2 memory cache 155, and additional time, overhead, and power may be consumed to speculatively retrieve the next cache line, and it is not certain that the CPU core 102 will need to execute these instructions.

[0025] FIG. 3 shows an example of a flowchart 300 for the method described above. The operations may be performed in the order shown or in a different order. Also, the operations may be performed continuously or two or more operations may be performed simultaneously.

[0026] At 302, the method includes receiving, by the memory controller subsystem 101, an access request for N prefetch units of program instructions. In one implementation, this operation is performed by the CPU core 102, and an address and a count value are provided to the PMC 120. The address may be a virtual address or a physical address, and the count value may indicate the number of additional prefetch units required by the CPU core 102.

[0027] At 304, an index value I is initialized to the value 1. This index value is used to determine when the last virtual address in a series of consecutive virtual addresses should be processed by the PMC 120. At 306, the method determines whether the prefetch unit I is a hit or a miss to the L1P 130. This determination is made, in some examples, by determining whether the virtual address exists within the TAGRAM 121 of the PMC. From the determination 306, two results are possible: a hit or a miss.

[0028] If the virtual address is a hit to L1P 130, at 308, the corresponding line of L1P 130 containing the desired prefetch unit is returned from L1P 130 and provided to the CPU core 102 as a prefetch packet 105. Next, at 310, the index is incremented (I = I + 1). If I has not yet reached N+1 (determined by decision operation 312), the VA of the last prefetch unit has not yet been evaluated for hit / miss and the control loop returns to 306 to evaluate the next Ith prefetch unit for hit or miss at L1P 130. When I reaches N+1, all N prefetch units have been evaluated and the corresponding program instructions have been provided to the CPU core 102, and the process is terminated.

[0029] If, for a given I-th prefetch unit, the PMC120 determines in 306 that there is a miss in L1P 130, then in 314, a determination is made as to whether I has reached the value of N. If I is not equal to N (indicating that the last VA in a series of VAs has not been reached), then in 316, this method includes the memory controller subsystem 101 obtaining a program instruction from the L2 memory cache 155 (if it exists there, or if it does not exist, from a third level cache or system memory). The index value I is then incremented in 318 and the control loop returns to the determination in 306.

[0030] If I reaches N in 314 (indicating that the last VA in a series of VAs has reached N), this method includes determining in 320 whether the VA of the Ith prefetch unit maps to the lower or upper half of the cache lines of the L2 memory cache 155. An example of how this determination may be made is described above. If the VA of the Ith prefetch unit maps to the upper half, this method includes obtaining program instructions only from the upper half of the cache lines of the L2 memory cache in 322.

[0031] However, if the VA of the first prefetch unit maps to the lower half, this method involves, in 324, promoting the L2 memory cache access to a full cache line access, and in 326, obtaining a program instruction from the full cache line of the L2 memory cache.

[0032] Referring again to Figure 1, as mentioned above, following the presentation of VA103 from CPU core 102 to PMC120, CPU core 102 can also provide PMC120 with a prefetch count 104. The prefetch count can be 0, which means that CPU core 102 no longer requires any instructions other than those contained in the prefetch unit beginning with VA103. However, between the receipt of VA103 and the subsequent prefetch count, PMC120 performs some work as described below.

[0033] Upon receiving VA103, PMC120 performs a lookup in TAGRAM121 to determine whether the first VA (provided by CPU core 102) is a hit or miss in L1P, and then performs a VA-to-PA conversion using address converter 122. PMC120 also calculates the second VA (the next consecutive VA following the one provided by the CPU core) before receiving the prefetch count 104. PMC120 inferentially accesses TAGRAM121, uses address converter 122 to determine the hit / miss status of the second VA, and populates the hit / miss indication 124 and PA125 in register 123. The valid bit 126 in register 123 is set to valid, thereby enabling further processing of the second VA as described above (e.g., retrieving the corresponding cache line from L1P 130 if present, or from L2 memory cache 155 as needed).

[0034] However, before any further processing of the second VA occurs, the CPU core 102 can send a prefetch count of 0 to the PMC 120, meaning that the CPU core does not need any prefetch units other than the one that started with the original VA 103. At this point, the PMC 120 is provided with a prefetch count of 0 and therefore does not need any prefetch units associated with the second VA. However, the PMC has also already determined the hit / miss status of the second VA and generated the corresponding PA. Both the hit / miss indicator 124 and the PA 125 are stored in register 123 by the time the prefetch count of 0 is received by the PMC 120. The PMC 120 changes the status of the valid bit 126 to indicate the invalid state, thereby eliminating further processing of the second VA. This situation (valid bit set to invalid state) is called "kill," and therefore the PMC 120 terminates processing of the second VA.

[0035] However, in some cases, the CPU core 102 may determine, despite the previous termination, that the prefetch unit associated with the second VA should actually be retrieved from L1P 130 or L2 memory cache 155 as described above. For example, if the CPU core 102 does not have further internal expectation information to inform it of the next requested instruction address, the CPU core 102 informs the PMC 120 that it should continue prefetching, starting linearly from the last requested address. This situation can occur, for example, due to a misprediction in the branch prediction logic of the CPU core 102. Thus, the CPU core 102 issues a restart signal 106 to the PMC 120. The PMC 120 responds to the restart signal by returning the valid bit 126 to the valid state, thereby enabling the continued processing of the second VA through the memory subsystem pipeline as described above. In this way, the CPU 102 does not need to directly present the second VA to the PMC 120. Instead, the PMC120 holds the second VA in register 123, for example, and also holds its hit / miss indicator 124, thereby determining the hit / miss status of the second VA again and avoiding the power consumption and time spent converting the second VA to PA.

[0036] Figure 4 shows an example of a flowchart 400 for initiating, terminating, and resuming a memory address lookup. The operations may be performed in the order shown or in a different order. Operations may also be performed sequentially or two or more operations may be performed simultaneously.

[0037] In 402, this method includes the memory controller subsystem 101 receiving an access request for the first VA. In one implementation, this operation is performed by the CPU core 102 that provides the first VA to the PMC 120. This method includes, in 404, determining whether the first VA is a hit or a miss at L1P30. In one example, this operation is performed by accessing the TAGRAM 121 of the PMC to determine the hit / miss status of the first VA. In 406, the first VA is converted to a first PA, for example, by using the address converter 122.

[0038] In 408, this method includes calculating a second VA based on a first VA. The second VA may be calculated by incrementing the first VA by a certain value to generate the address of a byte that is 64 bytes following the byte associated with the first VA. This method includes determining in 410 whether the second VA is a hit or a miss in L1P30. In one example, this operation is performed by accessing the TAGRAM 121 of the PMC to determine the hit / miss status of the second VA. The second VA is converted to a second PA in 412 by using the address converter 122 as described above. In 414, this method includes updating a register (e.g., register 123) with the hit / miss indicator 124 and the second PA. The valid bit 126 is also configured to be in the valid state.

[0039] Subsequently, the PMC120 receives a prefetch count at 416. Next, if the prefetch count is greater than zero at 418, program instructions from the L1P 130 or L2 memory cache 155 (or additional levels) are retrieved at 420 as described above. However, if the prefetch count is zero, the valid bit 126 is changed to the invalid state at 422. Therefore, even though the PMC120 was provided with a prefetch count of 0, the CPU core 102 may provide the PMC120 with a restart indication (424). At 426, the PMC120 returns the valid bit 126 to the valid state, and then the memory controller subsystem 101 obtains program instructions related to the second PA from the L1P, L2 memory cache, etc., as appropriate (428).

[0040] Figure 5 shows an exemplary use of the processor 100 described herein. In this example, the processor 100 is part of a system-on-a-chip (SoC) 500, which includes the processor 100 and one or more peripheral ports or devices. In this example, the peripherals include a general-purpose asynchronous transmitter (UART) 502, a USB (Universal Serial Bus) port 504, and an Ethernet controller 506. The SoC 500 can perform any of the various functions implemented by program instructions executed by the processor 100, for example. Multiple processors 100 may be provided, and a given processor 100 may include multiple CPU cores 102.

[0041] In this document, the term "connected" means either an indirect or direct wired or wireless connection. Therefore, when a first device connects to a second device, the connection may be via a direct connection or an indirect connection via other devices and connections. Furthermore, in this document, "based on" means "at least partially based on." Thus, when X is based on Y, X can be a function of Y and any number of other factors.

[0042] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a device, Central Processing Unit (CPU) core, A first memory cache for storing instructions to be executed by the CPU core, A second cache for storing instructions for execution by the CPU core, the second cache accessible in response to a miss in the first memory cache, and A memory controller subsystem coupled to the CPU core and the first and second memory caches, Includes, The memory controller subsystem, Determine whether the first virtual address received from the CPU core is a miss or a hit in the first memory cache. A second virtual address is generated based on the first virtual address. Determine whether the second virtual address in the first memory cache is a miss or a hit, The second virtual address is converted to a physical address, The status bits related to the hit or miss determination between the physical address and the second virtual address are set to the enabled state. In response to receiving a count value of zero from the CPU core, the status bit is changed to the disabled state. In response to receiving a restart indication from the CPU core, the status bit is returned to the enabled state. A device configured in such a way.

2. The apparatus according to claim 1, A device in which the memory controller subsystem is configured to retrieve program instructions from a second memory cache using the physical address translated from the second virtual address.

3. The apparatus according to claim 1, A device in which the receipt of the count value occurs after the second virtual address has been converted to the physical address.

4. The apparatus according to claim 1, An apparatus in which the receipt of the count value from the CPU core occurs before the resumption indication is received from the CPU core.

5. The apparatus according to claim 1, The apparatus further comprises a register in which the physical address and the status bit are stored.

6. The apparatus according to claim 5, A device in which the hit or miss indication of the second virtual address in the first memory cache is stored in the register along with the physical address and the status bit.

7. The apparatus according to claim 1, A device in which the first memory cache is for storing program instructions rather than data.

8. It is a device, Central Processing Unit (CPU) core, A first memory cache for storing instructions to be executed by the CPU core, A second cache for storing instructions for execution by the CPU core, wherein the second memory cache retrieves instructions in response to a miss in the first memory cache. A memory controller subsystem coupled to the CPU core and the first and second memory caches, Includes, The memory controller subsystem, The hit or miss status of the first virtual address in the first memory cache is determined by inference. The first virtual address is inferred and converted to a physical address, The status is set to the enabled state in relation to the hit or miss situation and the physical address. In response to receiving a first indication from the CPU core that no program instructions related to the first virtual address are required, the status is reset to disabled. In response to receiving a second indication from the CPU core that a program instruction related to the first virtual address is required, the status is reset to the enabled state. A device configured in such a way.

9. The apparatus according to claim 8, A device in which the memory controller subsystem is configured to infer the first virtual address from a second virtual address transmitted from the CPU core to the memory controller subsystem.

10. The apparatus according to claim 8, A device in which the first indication from the CPU core, which indicates that no program instructions related to the first virtual address are required, includes a count value, and the count value has a value of zero.

11. The apparatus according to claim 8, A device in which the second indication from the CPU core that a program instruction associated with the first virtual address is required includes a signal instructing the memory controller subsystem to continue retrieving a program instruction beginning at the first virtual address.

12. The apparatus according to claim 11, A device in which, upon receiving the second indication, the memory controller subsystem is configured to continue retrieving program instructions beginning at the first virtual address without having to re-determine the hit or miss status of the first virtual address in the first memory cache.

13. The apparatus according to claim 12, A device configured such that, upon receiving the second indication, the memory controller subsystem continues to retrieve program instructions beginning with the first virtual address without converting the first virtual address back to the physical address.

14. The apparatus according to claim 8, A device in which the CPU core is configured to provide the second indication without providing the first virtual address to the memory controller subsystem.

15. The apparatus according to claim 8, A device in which the receipt of the first indication occurs after the inferential determination of the hit or miss situation and the inferential translation of the first virtual address to the physical address.

16. It is a system-on-a-chip (SoC), Input / output devices, and A processor coupled to the aforementioned input / output device, Includes, The aforementioned processor, The system includes a central processing unit (CPU) core, a first memory cache for storing instructions to be executed by the CPU core, a second memory cache, and a memory controller subsystem coupled to the CPU core and the first and second memory caches, wherein the memory controller subsystem The hit or miss status of the first virtual address in the first memory cache is determined by inference. The first virtual address is inferred and converted to a physical address, In relation to the hit or miss situation and the physical address, set the status to the enabled state. In response to receiving a first indication from the CPU core that no program instructions related to the first virtual address are required, the status is reset to disabled. In response to receiving a second indication from the CPU core that a program instruction related to the first virtual address is required, the status is reset to the enabled state. A System of Computers (SoC) configured in such a way.

17. The SoC according to claim 16, A System of Computers (SoC) configured such that the memory controller subsystem infers the first virtual address from a second virtual address transmitted from the CPU core to the memory controller subsystem.

18. The SoC according to claim 16, A SoC in which no program instructions related to the first virtual address are required, and the first indication from the CPU core includes a count value, the count value being zero.

19. The SoC according to claim 16, A device in which the CPU core is configured to provide the second indication without providing the first virtual address to the memory controller subsystem.

20. The SoC according to claim 16, An SoC configured such that, upon receiving the second indication, the memory controller subsystem continues to retrieve program instructions beginning with the first virtual address without again determining the hit or miss status of the first virtual address in the first memory cache, and without again translating the first virtual address back to the physical address.

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