Reference voltage source circuit

Abstract

This enables the output of a reference voltage that is not affected by base current errors. [Solution] Collector current I of the third bipolar transistor 3 C3 The first resistor 11 is supplied with current to the base of the third bipolar transistor 3, while the base of the third bipolar transistor 3 is supplied with current from the output stage Oc2-1 of the second current mirror circuit 102, compensating for the base current, and the base-emitter voltage V of the third bipolar transistor 3 BE3 This results in a voltage that is not affected by base current error, and as a result, a reference voltage that is not affected by base current error is obtained at the output terminal 31.

Description

Technical Field

[0001] The present invention relates to a reference voltage source circuit that enables the supply of a reference voltage used in an analog circuit, and particularly relates to one that improves output voltage characteristics and the like.

Background Art

[0002] It is well known that a reference voltage source circuit is used as a circuit that generates and supplies a reference voltage required in various analog circuits and the like. For example, FIG. 4 shows a circuit configuration example of a conventional reference voltage source circuit. Hereinafter, the conventional circuit will be described while referring to the same figure. This reference voltage source circuit is based on a so-called bandgap reference circuit, and includes first and second transistors Q1p and Q2p whose bases are commonly connected to an output terminal Voutp, and third and fourth transistors Q3p and Q4p that form a current mirror circuit serving as an active load for the first and second transistors Q1p and Q2p as main components. Note that NPN bipolar transistors are used for the first and second transistors Q1p and Q2p, and PNP bipolar transistors are used for the third and fourth transistors Q3p and Q4p, respectively.

[0003] The operation of such a conventional circuit will be described below. First, in an NPN bipolar transistor, it is well known that the following relational expressions hold.

[0004] I =m×Is×exp(V BE / V T ) ··· Equation 1a

[0005] I C =βnI B ··· Equation 1b

[0006] I C +IB =I E ···Formula 1c

[0007] Here, I C is the collector current, m is the normalized emitter area ratio, Is is the saturation current, V BE is the base-emitter voltage, βn is the base current amplification factor, I B is the base current, I E is the emitter current. Also, V T is the thermal voltage, and using the Boltzmann constant k, the absolute temperature T, and the elementary charge q, V T = k × T / q is obtained.

[0008] Next, assuming that the base current amplification factors βn of the above NPN bipolar transistor and βp of the PNP bipolar transistor are sufficiently large, from Formula 1b and Formula 1c, I B ≈ 0, and, I C ≈ I E holds. At this time, by setting the normalized emitter area ratios of the third and fourth transistors Q3p and Q4p, which are PNP bipolar transistors, to be equal, the collector current I C1p of the first transistor Q1p, which is an NPN bipolar transistor, becomes equal to the collector current I C2p of the second transistor Q2p, which is also an NPN bipolar transistor.

[0009] Also, the base current required for the collector currents of the first and second transistors Q1p and Q2p is supplied from the emitter of the fifth transistor Q5p. Therefore, setting the normalized emitter area ratio of the first transistor Q1p and the second transistor Q2p to χ:1 (where χ is a natural number greater than 1), and setting the base-emitter voltage of the first transistor Q1p to V BE1p and the base-emitter voltage of the second transistor Q2p to V BE2p , the current I PTATp flowing through the second resistor R2p can be expressed as in Formula 2 below using the previous Formula 1a.

[0010] I PTATp =(V BE2p -V BE1p ) / R2p={V T ·ln(I C2p / Is)-V T ·ln(I C1p / χIs)} / R2p=(V T / R2p)·ln(χ)···Formula 2

[0011] However, the first resistor R1p has a current I expressed by equation 2. PTATp Because twice the current flows, the output terminal V OUTp The voltage generated is expressed as shown in Equation 3 below.

[0012] V OUTp =V BE1p +{1+(2R1p / R2p)}V T ·ln(χ)···Equation 3

[0013] Incidentally, it is known that the base-emitter voltage of an NPN bipolar transistor has a negative temperature characteristic (see, for example, Non-Patent Document 1). Therefore, in the above equation 3, the first term V BE1p The negative temperature characteristic is given by the thermal voltage V in the second term. T By canceling out the positive temperature characteristic, the output voltage V OUTp This can be made into a voltage that is insensitive to temperature. Such conventional circuits assume that the base current amplification factor βn of the NPN bipolar transistor and the base current amplification factor βp of the PNP bipolar transistor are sufficiently large. In semiconductor manufacturing processes, the base current amplification factor is approximately 100-200 in the case of bipolar processes, so the above assumption was valid. [Prior art documents] [Non-patent literature]

[0014] [Non-Patent Document 1] A. PAUL BROKAW, “A Simple Three-Terminal IC Bandgap Reference”, (USA), DECEMBER. 1974, IEEE Journal of Solid-State Circuits, vol. 6, no. 9, pp.388?393 [Non-Patent Document 2] Michiel AP Pertijs, Johan H. Huijsing, "Precision Temperature Sensors in CMOS Technology", (USA), Springer, 2006 [Overview of the project] [Problems that the invention aims to solve]

[0015] However, in recent years, the base current amplification factor of NPN bipolar transistors formed on high-voltage CMOS processes has decreased to around 5-20, and the base current amplification factor of PNP bipolar transistors has decreased to about a single order of magnitude. As a result, the effect of base current error in the conventional circuits described above can no longer be ignored. The base current amplification factor βn is the output voltage V of the conventional circuit. OUTp The effect on is disclosed, for example, in Non-Patent Document 2, which states that it can be calculated using Equation 4 below.

[0016] V OUTp =V BE1p +{1+(2R1p / R2p)}V T ·ln(χ)+V T · ln [(1+βn)(T / Tr)] XTB / {1+βn(T / Tr) XTB}]...Equation 4

[0017] Here, XTB is a parameter determined by the manufacturing process, and Tr is the reference temperature. Typically, room temperature of 27°C is used as the reference temperature Tr. Thus, the conventional circuit shown in Figure 4 has a fundamental problem: it is inevitably affected by the base current amplification factor.

[0018] This invention has been made in view of the above circumstances, and provides a reference voltage source circuit that is not affected by base current errors and can obtain a stable and reliable reference voltage. [Means for solving the problem]

[0019] To achieve the above-mentioned objectives of the present invention, the reference voltage source circuit according to the present invention is: The normalized emitter area ratio is set to 1:m, and it has a first NPN bipolar transistor and a second NPN bipolar transistor whose bases are interconnected. The collector of the first NPN bipolar transistor is connected to the first input stage of the first current mirror circuit. The collector of the second NPN bipolar transistor is connected to the first output stage of the first current mirror circuit. The emitter of a third NPN bipolar transistor, whose collector and base are interconnected, is grounded, while the collector of the third NPN bipolar transistor is connected to the emitter of the first NPN bipolar transistor via a first resistor, and also connected to the emitter of the second NPN bipolar transistor via the first and second resistors. The collector of the second NPN bipolar transistor is connected to the first input stage of the first voltage-current conversion circuit, and the first output stage of the first voltage-current conversion circuit is connected to the base of the second NPN bipolar transistor. The second output stage of the first current mirror circuit is connected to the collector of a fourth NPN bipolar transistor whose emitter is grounded. The second output stage of the first voltage-current conversion circuit is connected to the collector of the fourth NPN bipolar transistor. The collector of the fourth NPN bipolar transistor is connected to the input stage of the second voltage-current conversion circuit. The first output stage of the second voltage-current conversion circuit is connected to the base of the fourth NPN bipolar transistor. The second output stage of the second voltage-current conversion circuit is connected to the input stage of the second current mirror circuit. The output stage of the second current mirror circuit is connected to the base of the third NPN bipolar transistor. The emitter of the second NPN bipolar transistor is configured to output a reference voltage. [Effects of the Invention]

[0020] According to the present invention, since the circuit configuration is capable of compensating for the base current error of the NPN bipolar transistor, unlike conventional designs, it is possible to output a stable reference voltage that is not affected by the base current error, thus providing a highly reliable reference voltage source circuit. [Brief explanation of the drawing]

[0021] [Figure 1] This is a circuit diagram showing an example of the basic circuit configuration of a reference voltage source circuit in an embodiment of the present invention. [Figure 2] This is a circuit diagram showing a more specific example of the basic circuit shown in Figure 1. [Figure 3] This is a characteristic curve showing the output voltage change characteristics with respect to temperature change of a reference voltage source circuit in an embodiment of the present invention. [Figure 4] This is a circuit diagram showing an example of a conventional reference voltage source circuit configuration. [Figure 5] This is a characteristic curve showing the output voltage change characteristics in response to temperature changes of a conventional circuit. [Modes for carrying out the invention]

[0022] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 3. The components, arrangements, etc., described below are not intended to limit the present invention and can be modified in various ways within the scope of the spirit of the present invention. First, an example of the basic circuit configuration of the reference voltage source circuit in an embodiment of the present invention will be described with reference to Figure 1. The reference voltage source circuit in the embodiment of the present invention is mainly composed of first and second current mirror circuits (denoted as "CM1" and "CM2" in Figure 1, respectively) 101 and 102, first and second voltage-to-current conversion circuits (denoted as "VI1" and "VI2" in Figure 1, respectively) 103 and 104, and first to fourth bipolar transistors (denoted as "Q1," "Q2," "Q3," and "Q4" in Figure 1, respectively) 1 to 4. In this embodiment of the present invention, the first to fourth bipolar transistors 1 to 4 are NPN bipolar transistors.

[0023] The following provides a detailed explanation of the circuit configuration of this basic circuit example. The bases of the first and second bipolar transistors 1 and 2 are interconnected, while the collector of the first bipolar transistor 1 is connected to the input stage Ic1-1 of the first current mirror circuit 101, and the collector of the second bipolar transistor 2 is connected to the first output stage Oc1-1 of the first current mirror circuit 101 and the input stage Iv1-1 of the first voltage-to-current conversion circuit 103, respectively. The first output stage Ov1-1 of the first voltage-current conversion circuit 103 is connected to the bases of the first and second bipolar transistors 1 and 2.

[0024] Furthermore, the second output stage Oc1-2 of the first current mirror circuit 101 and the second output stage Ov1-2 of the first voltage-current conversion circuit 103 are both connected to the input stage Iv2-1 of the second voltage-current conversion circuit 104 and the collector of the fourth bipolar transistor 4. The base of the fourth bipolar transistor 4 is connected to the first output stage Ov2-1 of the second voltage-current conversion circuit 104, while the second output stage Ov2-2 of the second voltage-current conversion circuit 104 is connected to the input stage Ic2-1 of the second current mirror circuit 102. The emitter of the fourth bipolar transistor 4 is connected to ground.

[0025] The output stage Oc2-1 of the second current mirror circuit 102 is connected to the base and collector of the third bipolar transistor 3. The third bipolar transistor 3 has its emitter connected to ground, while its collector is connected to the emitter of the first bipolar transistor 1 via the first resistor 11, and also to the emitter of the second bipolar transistor 2 via the first and second resistors 11 and 12. The emitter of the second bipolar transistor 2 is connected to the output terminal 31, so that a reference voltage can be obtained, as will be described later.

[0026] In this configuration, since the first voltage-current conversion circuit 103 is composed of MOS transistors (details will be described later), no DC current is generated in the first input stage Iv1-1 of the first voltage-current conversion circuit 103. On the other hand, the first output stage Ov1-1 of the first voltage-current conversion circuit 103, which is connected to the bases of the first and second bipolar transistors 1 and 2, receives the base current I of the first and second bipolar transistors 1 and 2. B1 and I B2 Only current equal to the sum of the two values ​​is generated.

[0027] Then, the second output stage Ov1-2 of the first voltage-current conversion circuit 103 receives the current from the first output stage Ov1-1, i.e., the base current I B1 and I B2 A current proportional to the sum of these is generated. Furthermore, since the second voltage-current conversion circuit 104 is also composed of MOS transistors (details will be described later), no DC current is generated in its input stage Iv2-1. Furthermore, the current generated in the second output stage Oc1-2 of the first current mirror circuit 101 is proportional to the current generated in the input stage Ic1-1. As a result, the sum of the current generated in the second output stage Oc1-2 of the first current mirror circuit 101 and the current generated in the second output stage Ov1-2 of the first voltage-current conversion circuit 103 flows directly into the collector of the fourth bipolar transistor 4.

[0028] Furthermore, the current generated in the second output stage Ov2-2 of the second voltage-current conversion circuit 104 is proportional to the current generated in the output stage Ov2-1, and this current is supplied to the input stage Ic2-1 of the second current mirror circuit 102, which is composed of MOS transistors (details will be described later). Meanwhile, the collector and base of the third bipolar transistor 3 are supplied with the sum of the current from the first resistor 11 and the current generated in the output stage Oc2-1 of the second current mirror circuit 102.

[0029] However, the collector current I of the third bipolar transistor 3 C3 The current from the first resistor 11 is supplied to the base, while the base current is supplemented by the current supplied from the output stage Oc2-1 of the second current mirror circuit 102, thus reducing the base-emitter voltage V of the third bipolar transistor 3. BE3 This voltage is unaffected by base current errors.

[0030] Figure 2 shows a specific circuit configuration example of the reference voltage source circuit shown in Figure 1. This specific circuit configuration example will be explained below with reference to the same figure. Note that components identical to those shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. First, the first current mirror circuit 101 is composed of first to third MOS transistors 21 to 23 (labeled "Mp1", "Mp2", and "Mp3" respectively in Figure 2).

[0031] Furthermore, the first voltage-current conversion circuit 103 is composed of fourth and fifth MOS transistors (labeled "Mp4" and "Mp5" respectively in Figure 2) 24 and 25. Furthermore, the second current mirror circuit 102 is composed of sixth and seventh MOS transistors (labeled "Mp6" and "Mp7" respectively in Figure 2) 26 and 27. Furthermore, the second voltage-current conversion circuit 104 is configured to include an eighth MOS transistor (labeled "Mn1" in Figure 2) 28. In this embodiment of the present invention, P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for the first to seventh MOS transistors 21 to 27, and an N-channel MOSFET is used for the eighth MOS transistor 28.

[0032] In the first current mirror circuit 101, the gates of the first and second MOS transistors 21 and 22 are interconnected, and the drain of the first MOS transistor 21 and the gate of the third MOS transistor 23 are connected to each other. Furthermore, the sources of the first to third MOS transistors 21 to 23 are supplied with a positive power supply voltage V DD It is set to be applied. The drain of the first MOS transistor 21 (input stage Ic1-1) is connected to the collector of the first bipolar transistor 1, and the drain of the second MOS transistor 22 (first output stage Oc1-1) is connected to the collector of the second bipolar transistor 2 and the input stage of the first voltage-current conversion circuit 103, which will be described later. Furthermore, the drain of the third MOS transistor 23 (second output stage Oc1-2) is connected to the input stage Iv2-1 of the second voltage-current conversion circuit 104 (described later) and the collector of the fourth bipolar transistor 4.

[0033] Next, in the first voltage-current conversion circuit 103, the gates of the fourth and fifth MOS transistors 24 and 25 are interconnected (input stage Iv1-1), and are connected to the drain of the second MOS transistor 22 and the collector of the second bipolar transistor 2. Furthermore, the sources of the fourth and fifth MOS transistors 24 and 25 are supplied with a positive power supply voltage V DD It is set to be applied. Furthermore, the drain of the fourth MOS transistor 24 (first output stage Ov1-1) is connected to the bases of the first and second bipolar transistors 1 and 2 mentioned above, and the drain of the fifth MOS transistor 25 (second output stage Ov1-2) is connected to the input stage Iv2-1 of the second voltage-current conversion circuit 104.

[0034] Next, in the second voltage-current conversion circuit 104, the gate (input stage Iv2-1) of the eighth MOS transistor 28 is connected to the drains of the third and fifth MOS transistors 23 and 25, and to the collector of the fourth bipolar transistor 4. Furthermore, the drain of the eighth MOS transistor 28 (second output stage Ov2-2) is connected to the input stage of the second current mirror circuit 102, while its source (first output stage Ov2-1) is connected to the base of the fourth bipolar transistor 4.

[0035] Next, in the second current mirror circuit 102, the gates of the sixth and seventh MOS transistors 26 and 27 are interconnected, and the drain (input stage Ic2-1) of the sixth MOS transistor 26 is connected. Furthermore, the drain of the sixth MOS transistor 26 is connected to the drain of the eighth MOS transistor 28. Furthermore, the sources of the sixth and seventh MOS transistors 26 and 27 are supplied with a positive power supply voltage V DD It is set to be applied. The drain of the seventh MOS transistor 27 (output stage Oc2-1) is connected to the base and collector of the third bipolar transistor 3.

[0036] Next, we will explain how this configuration works. First, in the above configuration, the ratio of the channel width W to the channel length L of the first MOS transistor 21, the second MOS transistor 22, and the third MOS transistor 23, i.e., the (W / L) ratio, is set to 1:1:2. Furthermore, the (W / L) ratio of the fourth MOS transistor 24 and the fifth MOS transistor 25 is set to 1:1. Furthermore, the normalized emitter area ratio of the first bipolar transistor 1, the second bipolar transistor 2, the third bipolar transistor 3, and the fourth bipolar transistor 4 is set to 1:m:2:2, where m is a natural number greater than 1.

[0037] Under these conditions, the collector currents I of the first and second bipolar transistors 1 and 2 C1 and I C2 These are equal, and for convenience we can call this I C This will be the notation used. Here, the base-emitter voltages of the first bipolar transistor 1 and the second bipolar transistor 2 are V, respectively. BE1 , V BE2 Therefore, the current I flowing through the second resistor 12 is... PTAT This can be expressed using equation 1a above as shown in equation 5 below.

[0038] I PTAT =(V BE1 -V BE2 ) / R2={V T ·ln(I C1 / Is)-V T ·ln(I C2 / mIs)} / R2=(V T / R2)·ln(m)···Formula 5

[0039] Here, R2 is assumed to be the resistance value of the second resistor 12. As mentioned earlier, the collector currents I of the first and second bipolar transistors 1 and 2 C1 and IC2 Since they are equal, the base currents I of the first and second bipolar transistors 1 and 2 B1 and I B2 These two equal base currents I B1 ,I B2 For convenience, I B This is how it is written. Also, the collector current I of the fourth bipolar transistor 4 C4 This is the sum of the drain currents of the third and fifth MOS transistors 23 and 25, and can be expressed as shown in equation 6 below.

[0040] I C4 =2I C +2I B =2I PTAT ...Formula 6

[0041] In the circuit configuration shown in Figure 2, the source current of the eighth MOS transistor 28 is equal to the base current of the fourth bipolar transistor 4, and this current is generated as the drain current of the eighth MOS transistor 28. Then, the drain current of the eighth MOS transistor 28 is supplied to the third bipolar transistor 3 by the second current mirror circuit 102. The current supplied to the third bipolar transistor 3 by this second current mirror circuit 102 is conveniently referred to as I Bcomp Therefore, in Figure 2, 2I PTAT =βnI Bcomp This is true.

[0042] On the other hand, the current flowing through the second resistor 12 is I PTAT Therefore, this current is also supplied to the third bipolar transistor 3. From the above, the collector current of the third bipolar transistor 3 is 2I PTAT Therefore, the base current required for this is I Bcomp This proves that it is being supplemented in that way.

[0043] Therefore, the base-emitter voltage of the third bipolar transistor 3 is V BE3Assuming that the resistance value of the first resistor 11 is R1, the output voltage V at the output terminal 31 OUT can be expressed as shown in Equation 7 below.

[0044] V OUT =V BE3 +{1+(2R1 / R2)}V T ·ln(m)···Equation 7

[0045] FIG. 3 shows a characteristic diagram of the simulation result of the change characteristic of the output voltage with respect to the temperature change of the reference voltage source circuit in the embodiment of the present invention, and FIG. 5 shows a characteristic diagram of the similar simulation result of the conventional circuit. Hereinafter, these simulation results will be described with reference to the drawings. First, in FIGS. 3 and 5, the horizontal axis represents the ambient temperature change, and the vertical axis represents the output voltage. First, FIG. 3 is a result of simulating the change in the output voltage V with respect to the ambient temperature change of the reference voltage source circuit in the embodiment of the present invention, and the characteristic lines in each case when the base current amplification factor is 5, 10, and 20 are shown. OUT That is, in FIG. 3, the dashed characteristic line represents the case where the base current amplification factor is 5, the solid characteristic line represents the case where the base current amplification factor is 10, and the dotted characteristic line represents the case where the base current amplification factor is 20.

[0046] According to FIG. 3, it can be confirmed that there is no significant difference in the change of the output voltage due to the difference in the base current amplification factor, and it is hardly affected by the base current error.

[0047] On the other hand, FIG. 5 shows the same characteristic lines in each case where the base current amplification factors are 5, 10, and 20, similar to FIG. 3. According to FIG. 5, unlike the reference voltage source circuit in the embodiment of the present invention shown in FIG. 3, the output voltage V OUTp is clearly different due to the difference in the base current amplification factor, and it can be confirmed that the influence of the base current error is large and cannot be ignored.

Industrial Applicability

[0048] It can be applied to reference voltage source circuits where an accurate reference voltage output is desired without being affected by base current errors. [Explanation of Symbols]

[0049] 1…First bipolar transistor 2…Second bipolar transistor 3…The third bipolar transistor 4…The fourth bipolar transistor 101...First current mirror circuit 102...Second current mirror circuit 103...First voltage-current conversion circuit 104...Second voltage-current conversion circuit

Claims

1. The normalized emitter area ratio is set to 1:m, and the device has a first NPN bipolar transistor and a second NPN bipolar transistor whose bases are interconnected. The collector of the first NPN bipolar transistor is connected to the first input stage of the first current mirror circuit. The collector of the second NPN bipolar transistor is connected to the first output stage of the first current mirror circuit. The emitter of a third NPN bipolar transistor, whose collector and base are interconnected, is grounded, while the collector of the third NPN bipolar transistor is connected to the emitter of the first NPN bipolar transistor via a first resistor, and also connected to the emitter of the second NPN bipolar transistor via the first and second resistors. The collector of the second NPN bipolar transistor is connected to the first input stage of the first voltage-current conversion circuit, and the first output stage of the first voltage-current conversion circuit is connected to the base of the second NPN bipolar transistor. The second output stage of the first current mirror circuit is connected to the collector of a fourth NPN bipolar transistor whose emitter is grounded. The second output stage of the first voltage-current conversion circuit is connected to the collector of the fourth NPN bipolar transistor. The collector of the fourth NPN bipolar transistor is connected to the input stage of the second voltage-current conversion circuit. The first output stage of the second voltage-current conversion circuit is connected to the base of the fourth NPN bipolar transistor. The second output stage of the second voltage-current conversion circuit is connected to the input stage of the second current mirror circuit. The output stage of the second current mirror circuit is connected to the base of the third NPN bipolar transistor. A reference voltage source circuit characterized by being able to output a reference voltage to the emitter of the second NPN bipolar transistor.

2. The reference voltage source circuit according to claim 1, characterized in that the first and second current mirror circuits and the first and second voltage-to-current conversion circuits use MOS transistors.

3. The reference voltage source circuit according to claim 2, characterized in that the first voltage-current conversion circuit is configured such that a current proportional to the current generated in the first output stage of the first voltage-current conversion circuit is generated in the second output stage of the first voltage-current conversion circuit.

4. The reference voltage source circuit according to claim 3, characterized in that the second voltage-current conversion circuit is configured such that a current proportional to the current generated in the first output stage of the second voltage-current conversion circuit is generated in the second output stage of the second voltage-current conversion circuit.

Images