Heteroepitacid substrate and method for manufacturing heteroepitacid substrate

Abstract

By implementing specific measures that utilize the brittle-ductile transition (BDT), we provide a heteroepita substrate with enhanced fracture toughness and suppressed cracking, as well as a method for manufacturing the heteroepita substrate. [Solution] A heteroepitographic substrate comprising a base substrate, a dislocation layer on the base substrate which serves as a source of dislocations, and a heteroepitographic layer on the dislocation layer, wherein the base substrate has dislocations originating from the dislocation layer, and these dislocations inhibit the propagation of cracks in the base substrate which are the cause of cracking of the heteroepitographic substrate, thereby increasing its fracture toughness.

Description

Technical Field

[0001] The present invention relates to a heteroepitaxial substrate and a method for manufacturing the heteroepitaxial substrate.

Background Art

[0002] In fields such as the electrification of automobiles and factory automation (FA), the need for power devices has been increasing in a very wide range. Also, energy loss in power semiconductors has become non-negligible, and research on structures with good energy efficiency has been carried out, yielding significant results.

[0003] This energy loss is due to the conversion of electrical energy into heat, and while many measures have been taken for this waste heat, there are also constraints. For example, in-vehicle IGBTs are increasing in HV and EV applications and in the mounting of electronic devices, and the cooling system has become larger for cooling, which is having an impact on the design of automobiles.

[0004] On the other hand, in the field of communication, discussions are being held on communication technologies after the next generation, and it can be easily imagined that the communication frequency will be even higher than the current one.

[0005] Furthermore, the progress of AR and VR technologies is also significant, and the development of small personal displays is being actively carried out.

[0006] With the development of such social infrastructure, for power, communication, and light-emitting devices, substrates other than silicon (also referred to as Si), such as GaN, are expected because of their high characteristics, and numerous studies are being advanced.

[0007] In this context, in addition to devices using a single, freestanding GaN substrate, a great deal of research and development is also being conducted on techniques for epitaxial growth (hereinafter also called epi-growth) on silicon substrates, which are relatively inexpensive materials. In particular, silicon has large apertures among semiconductors, with diameters of 300 mm already in practical use, and if it is possible to fabricate a substrate on which GaN has been grown, it will be a very attractive material, even if there are performance limitations compared to a single substrate.

[0008] One problem with substrates where different materials are grown on a silicon substrate, which holds such promise, is substrate cracking.

[0009] This cracking is caused by growing materials with different properties on a silicon substrate. Therefore, several prior studies and developments exist to address this issue.

[0010] One approach involves focusing on the difference in lattice constants between silicon and the material grown on it, and using a method of lattice relaxation based on the structure.

[0011] For example, Patent Document 1 describes a method for resolving the difference in lattice constants between silicon and the material grown on it by creating a strained superlattice layer.

[0012] Specifically, a first semiconductor layer with a different lattice constant than the substrate and a second semiconductor layer with the same lattice constant as the substrate are alternately stacked and lattice relaxed, and the total thickness of the first semiconductor layer in the strained superlattice layer is set to a thickness exceeding the critical thickness of the first semiconductor layer.

[0013] Furthermore, the invention describes a multilayer semiconductor structure in which, when the lattice constant of the device layer is larger than that of the substrate, the first semiconductor layer has a larger lattice constant than that of the device layer, while when the lattice constant of the device layer is smaller than that of the substrate, the first semiconductor layer has a smaller lattice constant than that of the substrate, thereby achieving a higher dislocation reduction effect without increasing manufacturing costs.

[0014] This essentially involves focusing on the microscopic structure of the crystal structure and using this approach to overcome the differences.

[0015] Furthermore, from a broader perspective, there are examples such as Patent Document 2, which focuses on grain boundaries and attempts to solve the problem from a structural standpoint. Specifically, the heteroepitaxial (hereinafter also referred to as heteroepi) film substrate is one in which a heteroepitaxial film is formed on a substrate via a columnar structure film consisting of numerous columnar bodies extending in a direction nonparallel to the substrate surface. The invention describes a heteroepitaxial film substrate and a method for manufacturing it that effectively relieves the stress on the epitaxial film during and / or after film formation without going through a complex process, thereby growing a high-quality heteroepitaxial film.

[0016] Furthermore, there are examples of solutions that address the growth conditions, such as those described in Patent Document 3. Specifically, when epitaxially growing 3C-SiC or GaN on a Si substrate, in the case of SiC, a buffer layer is epitaxially grown at a temperature of 500 to 900°C and a speed of 0.1 to 1 μm / h, and then the main layer is epitaxially grown on top of it at a temperature of 1000 to 1300°C and a speed of 1 to 15 μm / h. This describes a heteroepitaxial substrate and a method for manufacturing it. This is not limited by the aforementioned structure, but is controlled by the conditions during film formation.

[0017] As described above, various approaches have been taken, and Non-Patent Document 1 further mentions the coefficient of thermal expansion. When stacking GaN (coefficient of thermal expansion: 5.6E-6 / K) on silicon (coefficient of thermal expansion: 2.6E-6 / K), a method is described in which the difference in thermal expansion coefficients is taken into account by using the difference in lattice constants to reduce stress. Specifically, a superlattice structure of GaN and AlN (coefficient of thermal expansion: 6.4E-6 / K) is adopted.

[0018] As described above, conventional solutions have been provided from a microscopic perspective, such as lattice constant differences (Patent Document 1 and Non-Patent Document 1) and grain boundaries (Patent Document 2). However, actual substrate fabrication involves a complex process where epitaxial growth is carried out in a high-temperature environment and then returned to room temperature. Furthermore, it is undeniable that substrates have an outer periphery (edge ​​shape) that differs from the crystal structure, and that there are aspects that are difficult to explain solely by lattice constants and grain boundaries. For this reason, it becomes necessary to define optimal conditions from the growth conditions, as in Patent Document 3.

[0019] On the other hand, according to Non-Patent Literature 2, research on the brittle-ductile transition since 1975 led to the development of the "physics of fracture" around 1986. According to this, while yield stress is the "resistance to plastic flow," brittleness is the "resistance to stress concentration," that is, resistance to cracking and fracture.

[0020] Until now, the only focus on cracking in GaN on Si substrates has been the magnitude of the yield stress, which is in the elastic region. However, the perspective presented in Non-Patent Document 2, which focuses on brittleness—a factor that has not been given much attention until now—represents a completely new approach to preventing substrate cracking and fractures, and has proven to be highly effective.

[0021] In the example of a GaN on Si substrate, the base substrate is silicon. According to Non-Patent Literature 3, in silicon, there is a region, albeit a narrow temperature range, where dislocations occur at the crack tip, preventing crack propagation and seemingly improving ductility. This phenomenon is called brittle-to-ductile transition (BDT). BDT is a phenomenon in which toughness is greatly improved in a certain temperature range, and specifically in silicon, it is said to occur in the range of 1000 to 1300 K, corresponding to the change in strength from glass to SiN.

[0022] Also, this BDT transition varies depending on the load increase rate (i.e., the stress application rate), and it is said that the higher this rate, the more the transition temperature range shifts to the high-temperature region.

[0023] According to Non-Patent Document 3, the mechanism by which the characteristics of this BDT are exhibited is that when cracks occur, dislocations occur at the crack tip (the tip of the crack) so as to inhibit the progress of this crack.

Prior Art Documents

Patent Documents

[0024]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0025]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0026] As described above, although various future developments are expected for heteroepitaxial substrates obtained by growing heterogeneous materials on silicon substrates, there is a problem that the substrates crack.

[0027] The cause of this cracking is clearly due to growing materials with different properties on a silicon substrate, and several prior studies and developments exist to address this issue.

[0028] From a materials science perspective in particular, it is known that cracking is a phenomenon influenced by the properties of the substrate material, such as brittleness and ductility, and there is a strong desire for specific cracking countermeasures that utilize brittle-ductile transition (BDT).

[0029] The present invention was made to solve the above problems, and aims to provide a heteroepita substrate and a method for manufacturing a heteroepita substrate in which fracture toughness is enhanced and cracking is suppressed by implementing specific measures that utilize the brittle-ductile transition (BDT). [Means for solving the problem]

[0030] To solve the above problems, the present invention provides a heteroepita substrate comprising a base substrate, a dislocation layer on the base substrate which serves as a source of dislocations, and a heteroepita layer on the dislocation layer, wherein the heteroepita substrate has dislocations on the base substrate originating from the dislocation layer, and these dislocations inhibit the propagation of cracks in the base substrate which are the cause of cracking of the heteroepita substrate, thereby increasing its fracture toughness.

[0031] In such a heteroepitaxial substrate, a dislocation layer is present between the base substrate and the heteroepitaxial layer. Therefore, when a crack that causes fracture occurs in the base substrate, the dislocations in the base substrate, originating from the dislocation layer, can prevent the crack tip from extending. In other words, the propagation of cracks in the base substrate, which are the cause of fracture in the heteroepitaxial substrate, is inhibited, increasing fracture toughness and resulting in a heteroepitaxial substrate that is less prone to cracking.

[0032] Furthermore, the dislocation density of the base substrate is 1E10 / cm³. 2 It is preferable that the above conditions are met.

[0033] With such a dislocation density, the dislocations can reliably inhibit crack propagation, resulting in a heteroepitographic substrate with increased fracture toughness and suppressed cracking.

[0034] Furthermore, it is preferable that the base substrate is a silicon substrate, the dislocation layer is a 3C-SiC layer, and the heteroepitographic layer is a GaN layer.

[0035] A heteroepitographic substrate made of such a material will definitely have increased fracture toughness and suppressed cracking.

[0036] To solve the above problems, the present invention provides a method for manufacturing a heteroepita substrate, comprising: preparing a base substrate; growing a dislocation layer on the base substrate which serves as a source of dislocations; and growing a heteroepita layer on the dislocation layer at a temperature higher than the brittle-ductile transition temperature of the base substrate, wherein the method involves passing through the brittle-ductile transition temperature of the base substrate during the growth of the heteroepita layer, thereby generating dislocations in the base substrate with the dislocation layer as the source, and these dislocations inhibit the propagation of cracks in the base substrate which are the cause of cracking of the heteroepita substrate, thereby increasing fracture toughness.

[0037] With this method of manufacturing heteroepita substrates, the base substrate passes through its brittle-ductile transition temperature during the growth of the heteroepita layer. This causes dislocations to be generated in the base substrate, originating from the dislocation layer. Therefore, when a crack occurs in the base substrate that could cause fracture, the dislocations can prevent the crack tip from extending. In other words, by inhibiting the propagation of cracks in the base substrate, which are the cause of fracture in heteroepita substrates, it is possible to manufacture heteroepita substrates with increased fracture toughness and suppressed fracture.

[0038] Furthermore, it is preferable to set the cooling temperature after growing the heteroepitar layer to a temperature lower than the brittle-ductile transition temperature of the base substrate, and to allow the cooling to pass through the brittle-ductile transition temperature of the base substrate, thereby generating dislocations in the base substrate with the dislocation layer as the source, and these dislocations inhibit the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepitar substrate, thereby increasing fracture toughness.

[0039] With this method of manufacturing heteroepitaxial substrates, the base substrate passes through its brittle-ductile transition temperature even during cooling after epitaxial growth. This causes dislocations to be generated in the base substrate, originating from the dislocation layer. Therefore, when cracks that cause fracture occur in the base substrate, the dislocations can prevent the crack tips from extending. In other words, by inhibiting the propagation of cracks in the base substrate, which are the cause of fracture in heteroepitaxial substrates, fracture toughness can be increased, and heteroepitaxial substrates with suppressed fracture can be manufactured.

[0040] Furthermore, the dislocation density generated in the base substrate is 1E10 / cm³. 2 It is preferable to keep the above in place.

[0041] With such a dislocation density, the dislocations can reliably inhibit crack propagation, thus increasing fracture toughness and enabling the production of heteroepitographic substrates with suppressed cracking.

[0042] Furthermore, it is preferable that the base substrate is a silicon substrate, the dislocation layer is a 3C-SiC layer, the heteroepitar layer is a GaN layer, and the growth temperature of the GaN layer is 950 to 1250 K (677 to 977 °C).

[0043] With such materials and growth temperatures, it is possible to reliably pass through the brittle-ductile transition temperature of the base substrate, thereby increasing fracture toughness and producing heteroepitaxial substrates with suppressed cracking. [Effects of the Invention]

[0044] In the heteroepitaxial substrate of the present invention, since there is a dislocation layer between the base substrate and the heteroepitaxial layer, when a crack that causes fracture occurs in the base substrate, the dislocations in the base substrate, originating from the dislocation layer, can prevent the tip of the crack from extending. In other words, the propagation of cracks in the base substrate, which are the cause of fracture in the heteroepitaxial substrate, is inhibited, thereby increasing fracture toughness and resulting in a heteroepitaxial substrate in which fracture is suppressed.

[0045] Furthermore, with the heteroepita substrate manufacturing method of the present invention, by passing the brittle-ductile transition temperature of the base substrate during the growth of the heteroepita layer, dislocations are generated in the base substrate with the dislocation layer as the source. Therefore, when a crack that causes fracture occurs in the base substrate, the dislocations can prevent the tip of the crack from extending. In other words, by inhibiting the propagation of cracks in the base substrate, which are the cause of fracture in heteroepita substrates, fracture toughness can be increased, and a heteroepita substrate with suppressed fracture can be manufactured.

[0046] Furthermore, conventional heteroepitaxial substrates have a cracking problem, making it difficult to increase their diameter. However, the heteroepitaxial substrate of the present invention suppresses cracking, making it possible to increase its diameter. This increase in diameter leads to higher productivity and lower costs.

[0047] Furthermore, since the heteroepitographic substrate of the present invention has suppressed cracking, it does not require, for example, the base substrate to be made extra thick, as was done conventionally to prevent cracking. Therefore, it is a very effective technology from the standpoint of resource conservation. [Brief explanation of the drawing]

[0048] [Figure 1] This is a schematic diagram of a heteroepitographic substrate in one embodiment of the present invention. [Figure 2] This is an XRT image from Example 1. [Figure 3] This is the XRT image from Comparative Example 2. [Modes for carrying out the invention]

[0049] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0050] Conventional methods for preventing cracking in heteroepitaxial substrates have relied solely on the yield stress of the base substrate. However, the actual strength of a material in a broad sense is not determined solely by this yield stress. In particular, for heteroepitaxial substrates using silicon substrates, cracking is a problem, and countermeasures are needed from the perspective of brittleness and toughness, which are more important than yield stress.

[0051] As mentioned above, there was a need to provide a heteroepita substrate and a method for manufacturing a heteroepita substrate in which fracture toughness is enhanced and cracking is suppressed by implementing specific measures that utilize the brittle-ductile transition (BDT).

[0052] Therefore, the inventors conducted diligent research and discovered that by selecting an epitaxial temperature suitable for the brittle-ductile transition temperature of the base substrate during epitaxial growth, and by preparing a dislocation source in advance to more effectively exert the ductility effect, the propagation of cracks, which are the cause of cracking, is inhibited, thereby increasing fracture toughness. This led to the completion of the present invention. This method is based on the fundamentals of materials science, and it is possible to implement efficient crack prevention measures based on the same idea regardless of the material.

[0053] In other words, the heteroepita substrate of the present invention is a heteroepita substrate comprising a base substrate, a dislocation layer on the base substrate which serves as a source of dislocations, and a heteroepita layer on the dislocation layer, wherein the base substrate has dislocations originating from the dislocation layer, and these dislocations inhibit the propagation of cracks in the base substrate which are the cause of cracking of the heteroepita substrate, thereby increasing its fracture toughness.

[0054] Furthermore, the present invention provides a method for manufacturing a heteroepita substrate, comprising: preparing a base substrate; growing a dislocation layer on the base substrate which serves as a source of dislocations; and growing a heteroepita layer on the dislocation layer at a temperature higher than the brittle-ductile transition temperature of the base substrate, wherein the process passes through the brittle-ductile transition temperature of the base substrate during the growth of the heteroepita layer, thereby generating dislocations in the base substrate with the dislocation layer as the source, and these dislocations inhibit the propagation of cracks in the base substrate which are the cause of cracking of the heteroepita substrate, thereby increasing fracture toughness.

[0055] Embodiments of the present invention will be described below with reference to the drawings.

[0056] Figure 1 is a schematic diagram of a heteroepitographic substrate in one embodiment of the present invention.

[0057] The heteroepitographic substrate 1 comprises a base substrate 2, a dislocation layer 3 on the base substrate 2 which serves as a source of dislocations, and a heteroepitographic layer 4 on the dislocation layer 3. The heteroepitographic substrate 1 has dislocations (not shown) in the base substrate 2 originating from the dislocation layer 3, and these dislocations inhibit the propagation of cracks (not shown) in the base substrate 2, which are the cause of cracking of the heteroepitographic substrate 1, thereby increasing its fracture toughness.

[0058] In such a heteroepitographic substrate 1, a dislocation layer 3 is present between the base substrate 2 and the heteroepitographic layer 4. Therefore, when a crack that causes fracture occurs in the base substrate 2, the dislocations in the base substrate 2, originating from the dislocation layer 3, can prevent the crack tip from extending. In other words, the propagation of the crack in the base substrate 2, which is the cause of fracture in the heteroepitographic substrate 1, is inhibited, increasing the fracture toughness and resulting in a heteroepitographic substrate 1 in which fracture is suppressed.

[0059] What is important here is that, before epitaxially growing the desired material (heteroepitar layer 4) on the base substrate 2, a dislocation layer 3, which will serve as the source of dislocations, is inserted.

[0060] Furthermore, although not particularly limited, layers similar to the dislocation layer can also be placed on the edges and back surface of the base substrate. In other words, it is important to have a dislocation source in the base substrate and then grow the desired epitaxial layer.

[0061] Furthermore, although not specifically limited, the dislocation density of the base substrate 2 is 1E10 / cm³. 2 It is preferable that the above conditions are met.

[0062] Dislocation density is 1E10 / cm³ 2 If the above conditions are met, dislocations can reliably inhibit crack propagation, resulting in a heteroepitographic substrate 1 with enhanced fracture toughness and suppressed cracking.

[0063] Furthermore, although not particularly limited, it is preferable that the base substrate 2 is a silicon substrate, the dislocation layer 3 is a 3C-SiC layer, and the heteroepitar layer 4 is a GaN layer.

[0064] A heteroepitographic substrate 1 made of such a material will reliably increase fracture toughness and suppress cracking.

[0065] Thus, after understanding the properties of the base substrate 2 (for example, a silicon substrate), it is preferable to select appropriate materials for the dislocation layer 3 and heteroepitar layer 4 in order to further actively exert the effect of inhibiting crack propagation by dislocations (dislocations preventing the crack tip from extending).

[0066] Furthermore, this dislocation layer 3 may be a single layer or multiple layers, and is not particularly limited.

[0067] Next, a method for manufacturing a heteroepita substrate according to one embodiment of the present invention will be described with reference to the schematic diagram of the heteroepita substrate shown in Figure 1.

[0068] The method for manufacturing a heteroepita substrate in this embodiment involves preparing a base substrate 2, growing a dislocation layer 3 on the base substrate 2 which serves as a source of dislocations, and growing a heteroepita layer 4 on the dislocation layer 3 at a temperature higher than the brittle-ductile transition temperature of the base substrate 2. By passing through the brittle-ductile transition temperature of the base substrate 2 during the growth of the heteroepita layer 4, dislocations (not shown) are generated in the base substrate 2 with the dislocation layer 3 as the source. These dislocations inhibit the propagation of cracks (not shown) in the base substrate 2, which are the cause of cracking in the heteroepita substrate 1, thereby increasing the fracture toughness.

[0069] With this method of manufacturing heteroepita substrates, the base substrate 2 passes through its brittle-ductile transition temperature during the growth of the heteroepita layer 4. As a result, dislocations are generated in the base substrate 2, originating from the dislocation layer 3. Therefore, when a crack occurs in the base substrate 2 that could cause fracture, the dislocations can prevent the crack tip from extending. In other words, the propagation of cracks in the base substrate 2, which are the cause of fracture in the heteroepita substrate 1, is inhibited, thereby increasing fracture toughness and enabling the production of a heteroepita substrate 1 with suppressed fracture.

[0070] Furthermore, although not particularly limited, it is preferable to set the cooling temperature after growing the heteroepitar layer 4 to a temperature lower than the brittle-ductile transition temperature of the base substrate 2, and to allow the cooling to pass through the brittle-ductile transition temperature of the base substrate 2, thereby generating dislocations in the base substrate 2 with the dislocation layer 3 as the source. These dislocations inhibit the propagation of cracks in the base substrate 2, which are the cause of cracking in the heteroepitar substrate 1, and thereby increase fracture toughness.

[0071] With this method of manufacturing heteroepita substrates, the base substrate 2 passes through its brittle-ductile transition temperature even during cooling after epitaxy growth. This causes dislocations to be generated in the base substrate 2, originating from the dislocation layer 3. Therefore, when a crack occurs in the base substrate 2 that could cause fracture, the dislocations can prevent the crack tip from extending. In other words, the propagation of cracks in the base substrate 2, which are the cause of fracture in the heteroepita substrate 1, is inhibited, thereby increasing fracture toughness and enabling the production of a heteroepita substrate 1 with suppressed fracture.

[0072] Furthermore, although not particularly limited, the dislocation density generated in the base substrate 2 is 1E10 / cm³. 2 It is preferable to keep the above in place.

[0073] With such a dislocation density, the dislocations can reliably inhibit crack propagation, thus increasing fracture toughness and enabling the production of a heteroepitographic substrate 1 with suppressed cracking.

[0074] Furthermore, although not particularly limited, it is preferable that the base substrate 2 is a silicon substrate, the dislocation layer 3 is a 3C-SiC layer, the heteroepitar layer 4 is a GaN layer, and the growth temperature of the GaN layer is, although not particularly limited, 950 to 1250 K (677 to 977 °C).

[0075] With such materials and growth temperatures, it is possible to reliably pass through the brittle-ductile transition temperature of the base substrate 2, thereby increasing fracture toughness and producing a heteroepitographic substrate 1 with suppressed cracking.

[0076] Here, we will further explain the relationship between the brittle-ductile transition (BDT) temperature of the base substrate 2 (silicon substrate) and the growth temperature of the heteroepitar layer 4 (GaN layer) in this embodiment.

[0077] In other words, while epitaxial growth of the GaN layer is carried out at high temperatures, in order to generate dislocations in the base silicon substrate, the growth temperature of the GaN layer must be higher than the BDT temperature, allowing it to pass through the temperature range in which BDT occurs during growth.

[0078] Generally, the temperature range in which BDT occurs in silicon is considered to be between 1000 and 1300K. Initially, it was thought that the growth temperature of the GaN layer should be set to a temperature exceeding 1300K in order to reliably pass through this temperature range. However, after further investigation by the inventors, it was confirmed that dislocations in the silicon substrate could be generated very effectively by setting the growth temperature of the GaN layer to 950 to 1250K (677 to 977°C).

[0079] Therefore, it can be estimated that the temperature at which BDT occurs in silicon is somewhat lower, for example, at 900K.

[0080] Generally, lower growth temperatures result in lower power consumption and shorter times for temperature rise and cooling. Therefore, while the growth temperature of the GaN layer does not necessarily need to exceed 1300K compared to the temperature at which BDT occurs in silicon (900K), and is not particularly limited, a temperature of 950 to 1250K (677 to 977°C) is preferable from a productivity standpoint.

[0081] Furthermore, setting the GaN layer growth temperature to 950 to 1250 K (677 to 977 °C) is preferable because it not only passes through the temperature at which BDT occurs (900 K) during growth, but also passes through this temperature range during cooling after epitaxial growth, allowing for more efficient dislocation generation on the base silicon substrate.

[0082] While not strictly limited, it is preferable that the cooling temperature after epitaxy be below 900K, for example, between 300K and 800K.

[0083] Furthermore, according to Non-Patent Literature 3, BDT occurs in the high-temperature range as the load change becomes steeper, but setting the load is difficult. In actual epitaxial circuits, cooling from higher temperatures is thought to result in greater changes in stress on the substrate, and because the actual load changes due to the finite form of the substrate (edge ​​shape, etc.), it is difficult to determine it quantitatively, and we believe that it is not very useful.

[0084] From a materials science perspective, even without preparing a dislocation source, dislocations will occur as cracks propagate, resulting in a certain degree of ductility enhancement. However, in this invention, by preparing a dislocation source in advance, the tip cracks caused by the cracks are stopped by the dislocations, maximizing ductility enhancement, increasing fracture toughness, and suppressing cracking.

[0085] In the case of a GaN on Si substrate, when growing GaN(0001) on a silicon(111) substrate, the GaN growth process uses a high temperature of around 1100°C, making it easy to pass through the BDT temperature during both epitaxial growth and cooling.

[0086] Furthermore, it is preferable, though not particularly limited, to grow a 3C-SiC dislocation layer of approximately 100 nm before epitaxial growth. When a substrate with such a dislocation layer is used, due to the passage through the BDT transition temperature range and the effect of the 3C-SiC dislocation layer, a large number of dislocations are actually generated in the base silicon substrate after epitaxial growth (see Figure 2). Dislocations are also present at the tips of cracks before they form, and these dislocations inhibit crack propagation, resulting in a substrate that does not crack. [Examples]

[0087] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0088] (Example 1) A silicon (111) substrate with a diameter of 300 mm is prepared, and a GaN on 3C-SiC on Si substrate is fabricated using 3C-SiC as the dislocation layer.

[0089] First, a 775 μm thick, 300 mm diameter (111) boron-doped high-resistance single-crystal silicon substrate, which is the standard thickness, was prepared as the base substrate. The wafer was then placed on a susceptor in the reactor of a reduced-pressure CVD apparatus and subjected to H2 annealing at 1080°C for 1 minute.

[0090] Next, to grow the dislocation layer, trimethylsilane gas was introduced at a growth temperature of 900°C and a growth pressure of 5 Torr (666.6 Pa) to perform the SiC nucleation process and grow a 3C-SiC single crystal film. After 10 minutes of growth, the film thickness was increased to 100 nm.

[0091] Subsequently, the substrate was introduced into the reaction furnace of the MOCVD apparatus, and nitrogen was used to purge the atmosphere and remove oxygen and moisture. Next, the furnace pressure was reduced to 50 mbar (5000 Pa), the temperature was raised to 1050°C, and the surface was cleaned by holding it in a hydrogen atmosphere for 10 minutes.

[0092] Next, in order to grow a gallium nitride (GaN) layer as a heteroepita layer, the furnace pressure was maintained at 200 mbar and the substrate temperature at 1120°C, and trimethylgallium and ammonia were introduced into the furnace to deposit a 900 nm GaN film.

[0093] Figure 2 shows the XRT image of the base silicon substrate used for the heteroepitographic substrate fabricated as described above.

[0094] For evaluation purposes, only about a quarter of the substrate is shown, but a very large number of dislocations are observed throughout the substrate, clearly indicating that crack propagation is inhibited by the dislocations and that the dislocation layer is functioning effectively. In the figure, the thick, dark lines represent cracks, and the numerous thin, narrow lines represent dislocations. The dislocation density in this case is 1E10 / cm³. 2 That was the case.

[0095] (Comparative Example 1) To serve as a control example for Example 1, a silicon (111) substrate with a diameter of 300 mm was prepared, and a GaN on Si substrate was fabricated.

[0096] First, a 775 μm thick, 300 mm diameter (111) boron-doped high-resistance single-crystal silicon substrate, which is the standard thickness, was prepared as the base substrate. This substrate was then introduced into the reaction furnace of the MOCVD apparatus, and nitrogen was used to purge the system and remove oxygen and moisture from the atmosphere.

[0097] Next, the furnace pressure was reduced to 50 mbar (5000 Pa), then the temperature was raised to 1050°C, and the surface was cleaned by holding it in a hydrogen atmosphere for 10 minutes.

[0098] Unlike Example 1, in order to grow a gallium nitride layer as a heteroepitographic layer without providing a dislocation layer, the furnace pressure was maintained at 200 mbar and the substrate temperature at 1120°C, and trimethylgallium and ammonia were introduced into the furnace to start GaN growth. However, the substrate was damaged inside the furnace during the growth process, and growth could not be completed.

[0099] (Comparative Example 2) Next, we abandoned the idea of ​​using a silicon substrate with a standard thickness of 775 μm and prepared a silicon (111) substrate with a diameter of 300 mm and a thickness of 1.5 mm, which we thought would be less prone to cracking. We then began fabricating the GaN on Si substrate.

[0100] First, a 1.5 mm thick, 300 mm diameter (111) boron-doped high-resistance single-crystal silicon substrate was prepared as the base substrate. This substrate was then introduced into the reaction furnace of the MOCVD apparatus, and nitrogen was used to purge the atmosphere and remove oxygen and moisture.

[0101] Next, the furnace pressure was reduced to 50 mbar (5000 Pa), then the temperature was raised to 1050°C, and the surface was cleaned by holding it in a hydrogen atmosphere for 10 minutes.

[0102] Unlike Example 1, a dislocation layer was not provided, and a gallium nitride layer was grown as a heteroepitographic layer. Therefore, the furnace pressure was maintained at 200 mbar and the substrate temperature at 1120°C, and trimethylgallium and ammonia were introduced into the furnace to start GaN growth.

[0103] As a result, the substrate was successfully removed from the growth furnace without cracking. However, when the substrate was placed on the stage for XRT measurement, a crack occurred.

[0104] When XRT images of relatively large areas within the fractured substrate were measured, the results shown in Figure 3 were obtained, revealing numerous very long cracks, while no dislocations were observed in the underlying silicon substrate.

[0105] Unlike Example 1, this is thought to be because, as a 3C-SiC dislocation layer was not prepared, dislocations did not occur in the base silicon substrate, and therefore the dislocations could not inhibit crack propagation, leading to cracking.

[0106] In summary, unlike Comparative Examples 1 and 2, the heteroepitac substrate of Example 1 has a dislocation layer (3C-SiC layer) between the base silicon substrate and the heteroepitac layer (GaN layer). Therefore, when a crack that causes fracture occurs in the silicon substrate, the dislocations in the silicon substrate, originating from the dislocation layer, can prevent the crack from extending. Thus, it has been proven that the heteroepitac substrate of Example 1 has enhanced fracture toughness and suppressed cracking by inhibiting the propagation of cracks caused by dislocations.

[0107] The present invention encompasses the following aspects. [1]: A heteroepitographic substrate comprising a base substrate, a dislocation layer on the base substrate which serves as a source of dislocations, and a heteroepitographic layer on the dislocation layer, The dislocation layer has dislocations in the base substrate, which is the source of the dislocations. A heteroepitaxial substrate characterized in that the dislocation inhibits the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepitaxial substrate, thereby increasing its fracture toughness. [2]: The dislocation density of the base substrate is 1E10 / cm³ 2The heteroepitographic substrate described above [1], characterized in that it is as described above. [3]: The aforementioned base substrate is a silicon substrate. The aforementioned dislocation layer is a 3C-SiC layer. The heteroepitographic substrate according to [1] or [2] above, characterized in that the heteroepitographic layer is a GaN layer. [4]: Prepare the base circuit board, A dislocation layer, which serves as a source of dislocations, is grown on the aforementioned base substrate. A method for manufacturing a heteroepitographic substrate, comprising growing a heteroepitographic layer on the dislocation layer at a temperature higher than the brittle-ductile transition temperature of the base substrate, By passing the brittle-ductile transition temperature of the base substrate during the growth of the heteroepitographic layer, dislocations are generated in the base substrate with the dislocation layer as the source. A method for manufacturing a heteroepitaxial substrate, characterized in that the dislocations inhibit the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepitaxial substrate, thereby increasing its fracture toughness. [5]: The cooling temperature after growing the heteroepitar layer is set to a temperature lower than the brittle-ductile transition temperature of the base substrate. By passing through the brittle-ductile transition temperature of the base substrate during cooling, dislocations are generated in the base substrate with the dislocation layer as the source. The method for manufacturing a heteroepita substrate according to [4] above, characterized in that the dislocations inhibit the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepita substrate, thereby increasing fracture toughness. [6]: The density of dislocations occurring in the base substrate is 1E10 / cm³. 2 A method for manufacturing a heteroepitographic substrate according to [4] or [5] above, characterized in that the above is achieved. [7]: The base substrate is a silicon substrate, The dislocation layer is a 3C-SiC layer, The heteroepitac layer is a GaN layer, A method for manufacturing a heteroepitographic substrate according to any one of the above [4] to [6], characterized in that the growth temperature of the GaN layer is 950 to 1250 K (677 to 977 °C).

[0108] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that has substantially the same technical idea as described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0109] 1...heteroepitacid substrate, 2...base substrate, 3...dislocation layer, 4...heteroepitacid layer.

Claims

1. A heteroepitographic substrate comprising a base substrate, a dislocation layer on the base substrate which serves as a source of dislocations, and a heteroepitographic layer on the dislocation layer, The dislocation layer has dislocations in the base substrate, which is the source of the dislocations. A heteroepitaxial substrate characterized in that the dislocation inhibits the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepitaxial substrate, thereby increasing its fracture toughness.

2. The dislocation density of the base substrate is 1E10 / cm³ ２ The heteroepitac substrate according to claim 1, characterized in that it is as described above.

3. The aforementioned base substrate is a silicon substrate. The dislocation layer is a 3C-SiC layer, The heteroepitographic substrate according to claim 1 or 2, characterized in that the heteroepitographic layer is a GaN layer.

4. Prepare the base circuit board, A dislocation layer, which serves as a source of dislocations, is grown on the aforementioned base substrate. A method for manufacturing a heteroepitographic substrate, comprising growing a heteroepitographic layer on the dislocation layer at a temperature higher than the brittle-ductile transition temperature of the base substrate, By passing the brittle-ductile transition temperature of the base substrate during the growth of the heteroepitographic layer, dislocations are generated in the base substrate with the dislocation layer as the source. A method for manufacturing a heteroepitaxial substrate, characterized in that the dislocations inhibit the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepitaxial substrate, thereby increasing its fracture toughness.

5. The cooling temperature after growing the heteroepitar layer is set to a temperature lower than the brittle-ductile transition temperature of the base substrate. By passing through the brittle-ductile transition temperature of the base substrate during cooling, dislocations are generated in the base substrate with the dislocation layer as the source. The method for manufacturing a heteroepita substrate according to claim 4, characterized in that the dislocation inhibits the propagation of cracks in the base substrate, which are the cause of cracking of the heteroepita substrate, thereby increasing its fracture toughness.

6. The density of dislocations occurring in the base substrate is 1E10 / cm³. ２ The method for producing a heteroepitographic substrate according to claim 4, characterized in that the above is achieved.

7. The base substrate is a silicon substrate, The dislocation layer is a 3C-SiC layer, The heteroepitac layer is a GaN layer, A method for manufacturing a heteroepitographic substrate according to any one of claims 4 to 6, characterized in that the growth temperature of the GaN layer is 950 to 1250 K (677 to 977 °C).

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