Semiconductor memory device for HBM and method for manufacturing the same

Abstract

The present invention provides a semiconductor memory device for HBM that can suppress cracking and has improved heat dissipation characteristics. [Solution] A semiconductor memory device for HBM having a substrate and a semiconductor memory element made of silicon on the substrate, wherein the substrate comprises a first substrate made of silicon and a second substrate made of 3C-SiC on the first substrate, or is made of 3C-SiC only.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device for HBM (High Bandpass Memory) and a method for manufacturing the same, and more particularly, to a semiconductor memory device for HBM installed inside a GPU and used in a server for generative AI, and a method for manufacturing the same.

Background Art

[0002] In the 2000s, the demand for AI servers exploded, such as machine learning a large number of data on servers and dramatically improving the accuracy of image recognition. Furthermore, in recent years, generating data based on machine-learned data, known as generative AI, has become mainstream. Although search results could be output based on the results of machine learning in the past, generative AI, which will attract attention in the future, outputs new results. As an example of this, as in the case where a large number of patents were filed by SoftBank (registered trademark) in a short period recently, it is something that greatly changes the conventional social structure (Non-Patent Document 1).

[0003] Also, in machine learning and generative AI, since the data to be learned is considered to naturally have different contents, the importance of AI servers replacing conventional general-purpose servers for further machine learning and further generative AI is considered to increase more and more in the future (the era of artificial intelligence).

[0004] The GPUs used in AI servers have a structure in which the main core of the processor is connected to HBM via a silicon interposer. As a heat countermeasure, a heat sink is installed on the processor and HBM. For this reason, the height of HBM must be the same as that of the processor (Non-Patent Document 2).

[0005] HBMs have a stacked structure of DRAM (Dynamic Random Access Memory) chips (DRAM dies). To improve performance, the number of stacks needs to be increased, but due to height constraints, the height of individual DRAM chips must be reduced (thinner). As mentioned in Non-Patent Document 2 above, as the DRAM chips become thinner, the substrate strength of the DRAM chip decreases, leading to problems such as cracking defects due to crack formation and bonding defects due to warping.

[0006] Furthermore, the issue of heat generation associated with high-speed operation has been pointed out (Non-Patent Literature 2). Stacking degrades heat dissipation characteristics. This deterioration in heat dissipation characteristics requires further consideration and countermeasures as the number of layers increases. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] Nomura Research Institute, Center for Future Innovation Research Report Vol. 10, "The Future Landscape Transformed by Generative AI: What You Need to Know About the Suddenly Appearing 'Generative AI'," December 2023. [Non-Patent Document 2] ADMETAPlus2024, Tutorial "Metallization for Memory Devices - Challenging High Bandwidth Memory," Naoki Yokoi, Micron Memory Japan, KK [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention was made to solve the above problems and aims to provide a semiconductor memory device for HBM that can suppress cracking and has improved heat dissipation characteristics. [Means for solving the problem]

[0009] To achieve the above objective, the present invention comprises a substrate portion and a semiconductor memory element portion made of silicon on the substrate portion. The present invention provides a semiconductor memory device for HBM, characterized in that the substrate comprises a first substrate made of silicon and a second substrate made of 3C-SiC on the first substrate, or is made of 3C-SiC alone.

[0010] In the semiconductor memory device for HBM of the present invention, the substrate portion (which comprises a first substrate portion made of silicon and a second substrate portion made of 3C-SiC, or which consists only of 3C-SiC) includes at least a portion made of 3C-SiC as described above. In this way, by utilizing (1) the prevention of cracking due to 3C-SiC having a higher Young's modulus compared to silicon, and (2) the heat dissipation effect due to the high thermal conductivity of 3C-SiC compared to silicon, the semiconductor memory device for HBM is capable of simultaneously suppressing cracking and improving heat dissipation characteristics. Therefore, without causing problems such as cracking, the semiconductor memory device for HBM can be made even thinner, enabling higher performance in HBM (increasing the number of layers of semiconductor memory device for HBM).

[0011] In this case, the second substrate portion made of 3C-SiC, or the substrate portion made solely of 3C-SiC, may have a thickness of 100 nm or more.

[0012] If the 3C-SiC portion has the above thickness, cracking can be suppressed more reliably and effectively, and heat dissipation characteristics can be improved.

[0013] The present invention also relates to a method for manufacturing a semiconductor memory device for HBM, comprising forming a silicon layer on a silicon substrate by epitaxial growth, forming a semiconductor memory element on the silicon layer, and subjecting it to a thin-film treatment. In the deposition of the silicon layer, a 3C-SiC layer is first deposited on the silicon substrate by epitaxial growth, and then the silicon layer is deposited on the 3C-SiC layer. The present invention provides a method for manufacturing a semiconductor memory device for HBM, characterized by removing part or all of the silicon substrate during the thin-film treatment.

[0014] With the manufacturing method for HBM semiconductor memory devices of the present invention, by forming a 3C-SiC layer as described above, it is possible to manufacture an HBM semiconductor memory device that can achieve both crack suppression and improved heat dissipation characteristics. Consequently, it is possible to thin the HBM semiconductor memory device without causing problems such as cracking, increase the number of layers in the HBM, and improve the performance of the HBM.

[0015] In this case, when forming the 3C-SiC layer, the thickness of the formed film can be 100 nm or more.

[0016] By setting the thickness of the 3C-SiC layer to the above thickness, cracking can be suppressed more reliably and effectively, and heat dissipation characteristics can be improved.

[0017] Furthermore, when forming the silicon layer, the thickness of the formed film can be adjusted according to the thickness of the semiconductor memory device for HBM being manufactured.

[0018] In HBM fabrication, when attempting to increase the number of stacked semiconductor memory devices for HBM while considering the thickness limitations of the HBM, it is necessary to reduce the thickness of each individual HBM semiconductor memory device. Therefore, it is best to appropriately adjust the thickness of the silicon layer considering the required thickness of the HBM semiconductor memory device. [Effects of the Invention]

[0019] The present invention provides a semiconductor memory device for HBM and a method for manufacturing the same, which utilizes 3C-SiC, a material with a high Young's modulus and high thermal conductivity compared to silicon, resulting in improved heat dissipation. This allows for thinner films than conventional HBM semiconductor memory devices, increasing the number of layers in the HBM, and thereby improving the performance of the HBM.

Brief Description of the Drawings

[0020] [Figure 1] It is a schematic explanatory diagram showing an example of a semiconductor memory device for HBM of the present invention. [Figure 2] It is a graph showing the results of bending tests (relationship between displacement amount and applied stress) for a silicon substrate (without 3C-SiC film) and a silicon substrate (with 3C-SiC film). [Figure 3] It is a schematic explanatory diagram showing an example of another aspect of the semiconductor memory device for HBM of the present invention. [Figure 4] It is a process flow diagram showing an example of a manufacturing method of the semiconductor memory device for HBM of the present invention.

Embodiments for Carrying Out the Invention

[0021] Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto. As described above, although thinning of individual DRAM chips (semiconductor memory devices for HBM) in HBM and an increase in the number of their laminations are required, cracking due to thinning and deterioration of heat dissipation characteristics due to lamination become problems.

[0022] Therefore, as a result of intensive research by the present inventors, it has a substrate portion and a semiconductor memory element portion made of silicon on the substrate portion, and the substrate portion includes a first substrate portion made of silicon and a second substrate portion made of 3C-SiC on the first substrate portion, or is made of only 3C-SiC. For a semiconductor memory device for HBM, it has been found that it is possible to suppress cracking and improve heat dissipation characteristics by utilizing the heat dissipation effect due to the high Young's modulus and high thermal conductivity of 3C-SiC, and the present invention has been completed.

[0023] Furthermore, the present invention was found to be a method for manufacturing an HBM semiconductor memory device in which a silicon layer is formed on a silicon substrate by epitaxial growth, a semiconductor memory element is formed on the silicon layer, and a thin-film treatment is performed, wherein in the silicon layer formation, a 3C-SiC layer is first formed on the silicon substrate by epitaxial growth, the silicon layer is formed on the 3C-SiC layer, and in the thin-film treatment, part or all of the silicon substrate is removed, thereby obtaining an HBM semiconductor memory device that exhibits the above-mentioned excellent effects, and thus the present invention was completed.

[0024] Figure 1 shows an example of a semiconductor memory device for HBM according to the present invention. As shown in Figure 1, the semiconductor memory device for HBM (hereinafter also simply referred to as memory device) 1 of the present invention has a substrate 2 and a semiconductor memory element 3. The base portion 2 comprises a first base portion 2A made of silicon and a second base portion 2B made of 3C-SiC located on the first base portion 2A. Furthermore, the semiconductor memory element section 3 is made of silicon. More specifically, a desired semiconductor memory element is formed on a silicon layer. The semiconductor memory element can be anything that performs an appropriate role as a DRAM, such as a capacitor or a transistor, and is not particularly limited.

[0025] Here, we will explain the significance of the second substrate portion 2B, which is made of 3C-SiC. The Young's modulus of 3C-SiC is 450 GPa (Proceedings of the 2016 Spring Meeting of the Japan Society for Precision Engineering, 723 (2016)). On the other hand, the Young's modulus of silicon (for example, a silicon single crystal with a (100) orientation) is 130 GPa (The Science of Silicon, p. 989 (1996)). Thus, it can be seen that 3C-SiC has a higher Young's modulus than silicon, resulting in greater rigidity and durability.

[0026] Therefore, the following tests were conducted to assess the effectiveness of the rigidity of this 3C-SiC. First, two identical silicon substrates (300 mm in diameter) were prepared. One silicon substrate was left as is, while 3C-SiC was epitaxially grown on the other silicon substrate to a thickness of 100 nm. For each sample, a bending test was performed by setting the temperature to 22°C, supporting the left and right sides of the substrate, and pressing down on the center of the substrate from above with an indenter, and then measuring the relationship between the displacement and the applied stress. The test results are shown in Figure 2. The solid line represents the results for substrates with the 3C-SiC film, and the dashed line represents the results for substrates without the 3C-SiC film. It can be seen that the substrate with the 3C-SiC film exhibits smaller displacement for the same stress value, indicating increased rigidity. Therefore, 3C-SiC is effective in preventing cracking.

[0027] Furthermore, regarding thermal conductivity, 3C-SiC has a thermal conductivity of 500 Wm². -1 K -1 (Z. Cheng et. al., Nature communications, 13, 7201 (2022)) However, the thermal conductivity of silicon with a crystal orientation of (100) is 67 Wm². -1 K -1 (From "The Science of Silicon," pp. 992, 1005 (1996)) Thus, 3C-SiC has a significantly higher thermal conductivity than silicon. Therefore, when assembled in the manufacturing of HBM, heat can be effectively transferred through the bump metal to the heat sink via the 3C-SiC, making it an effective thermal management tool.

[0028] As described above, 3C-SiC has a higher Young's modulus and higher thermal conductivity compared to silicon. Therefore, the memory device 1 of the present invention, which has a part made of 3C-SiC such as the second substrate part 2B, can suppress the occurrence of cracks and has improved heat dissipation characteristics, making it extremely superior. It can adequately address the challenges associated with further thinning and an increase in the number of layers that have been required in recent years.

[0029] The thickness of the substrate portion 2 and the semiconductor memory element portion 3 is not particularly limited and can be determined as appropriate. For example, the thickness of each portion can be determined according to the overall thickness of the memory device 1 in accordance with the requirements for thinning. The thinner the material, the thinner the overall thickness of the memory device 1 becomes, which is preferable because it allows for an increase in the number of layers in the manufacturing of HBM.

[0030] Furthermore, the thickness of the second substrate portion 2B, which is made of 3C-SiC, is not particularly limited, but a thickness of 100 nm or more is preferable because it is more effective in suppressing cracking and improving heat dissipation characteristics. If necessary, it can be, for example, 125 nm or more, or even 150 nm or more. As an upper limit, a value of, for example, around 200 nm is generally considered sufficient, but it is not limited to this, and can be determined while comparing the above effects with the overall thickness of the memory device 1, etc.

[0031] Furthermore, Figure 3 shows an example of another embodiment of the semiconductor memory device for HBM of the present invention. As shown in Figure 3, in the memory device 10 of this embodiment, the substrate portion 20 is made only of 3C-SiC. To put it another way, in comparison to Figure 1, in Figure 3 there is no substrate portion 2A (silicon) corresponding to Figure 1, and it is composed only of the second substrate portion 2B (3C-SiC) corresponding to Figure 1. Therefore, the memory device 10 of the embodiment in Figure 3 can be made even thinner overall than the memory device 1 of the embodiment in Figure 1. Furthermore, as described above, the effectiveness of the 3C-SiC in the substrate 20 is such that the same cracking and heat dissipation characteristics as in the embodiment shown in Figure 1 can be obtained.

[0032] Next, the method for manufacturing a semiconductor memory device for HBM according to the present invention will be described. Figure 4 shows an example of the process flow of the manufacturing method according to the present invention. As shown in Figure 4, the process consists of (Step 1) preparation of a silicon substrate, (Step 2) hydrogen baking, (Step 3) deposition of a 3C-SiC layer, (Step 4) deposition of a silicon layer, (Step 5) formation of a semiconductor memory element, and (Step 6) thin-film processing. Each step will be described in detail below.

[0033] (Step 1) Preparation of the silicon substrate First, a single-crystal silicon substrate is prepared. A silicon ingot can be manufactured using methods such as the Czochralski process or the floating zone process, and then cut into wafers. These wafers can then be prepared by performing various processes such as grinding, etching, and polishing. The diameter and surface orientation are not particularly limited.

[0034] (Step 2) Hydrogen baking Next, a vacuum CVD apparatus is prepared (an apparatus similar to the one used conventionally can be prepared), a single-crystal silicon substrate is placed inside the apparatus, and the native oxide film on the surface is removed by hydrogen baking (H2 annealing). By removing the native oxide film from the surface of the single-crystal silicon substrate in advance, the formation of SiC nuclei on the single-crystal silicon substrate in the next step can be performed more reliably. The H2 annealing at this time is preferably performed at a temperature of, for example, 1000°C to 1200°C, but there are no particular restrictions on the pressure or time of the H2 annealing, as long as the native oxide film is removed.

[0035] (Step 3) Deposition of the 3C-SiC layer Next, a 3C-SiC layer is formed by epitaxial growth (SiC nucleation and 3C-SiC layer formation). This formed 3C-SiC layer corresponds to the second substrate portion 2B in Figure 1 (substrate portion 20 in Figure 3). For example, in a vacuum CVD apparatus, a single-crystal silicon substrate is subjected to SiC nucleation by introducing monomethylsilane or trimethylsilane as a raw material gas, at a temperature of 300°C to 1100°C. SiC nucleation can be performed on the surface of a single-crystal silicon substrate if the pressure is 100 Torr or less (13332 Pa or less) and the temperature is 300°C or higher.

[0036] Furthermore, to efficiently perform epitaxial growth of SiC, it is preferable to set the temperature to 800°C or higher. Also, by setting the temperature during SiC nucleation to 800°C or higher, SiC nucleation and 3C-SiC single crystal layer formation can be performed under the same conditions. The growth pressure during 3C-SiC single crystal layer formation is preferably, for example, 100 Torr or less (13332 Pa or less). This is to effectively prevent polycrystallization of 3C-SiC. On the other hand, under conditions where the pressure is 10 Torr or less (1333 Pa or less), more preferably 1 Torr or less (133 Pa or less), vacancies are formed directly beneath the 3C-SiC single crystal layer, and the effect of relaxing the stress on the entire epitaxial layer can be obtained.

[0037] At this time, the film thickness deposited depends on the pressure and temperature, so the deposition time is appropriately set based on the pressure and temperature conditions set to achieve the desired film thickness. The thickness of the 3C-SiC single crystal layer is not particularly limited, but it is preferably 100 nm or more. As mentioned above, this is because it is more effective in suppressing cracking and improving the heat dissipation characteristics of the final manufactured memory device. Furthermore, it can be, for example, 125 nm or more, 150 nm or more, and around 200 nm is sufficient.

[0038] (Step 4) Formation of the silicon layer On the 3C-SiC single crystal layer grown as described above, a single-crystal silicon layer is deposited by growing silicon using a CVD apparatus. At this time, there is no restriction on whether a vacuum CVD apparatus or an atmospheric pressure CVD apparatus is used, but especially when growing a layer thicker than the 3C-SiC, an atmospheric pressure CVD apparatus is preferable because it allows for a higher growth rate. In this process, the above-mentioned single-crystal silicon layer can be formed by introducing, for example, monosilane or trichlorosilane into the CVD apparatus and setting the temperature to approximately 1000°C to 1200°C.

[0039] At this time, by taking into consideration the final overall thickness of the memory device in advance, it is advisable to appropriately adjust the thickness of the silicon layer so that it falls within that overall thickness range after the subsequent thinning process.

[0040] (Step 5) Formation of semiconductor memory elements Then, the desired semiconductor memory elements are formed on the deposited single-crystal silicon layer. Using techniques such as photolithography, a DRAM consisting of capacitors that serve as memory elements and transistors that serve as switches can be fabricated. The fabrication of this DRAM itself can be carried out in basically the same way as in the past. The silicon layer on which the semiconductor memory element is formed in this manner corresponds to the semiconductor memory element section 3 in Figure 1 (the semiconductor memory element section 30 in Figure 3).

[0041] (Step 6) Thinning treatment Then, part or all of the silicon substrate is removed. The removal method itself is not particularly limited and can be carried out as appropriate using grinding, polishing, etching, etc., and may be the same as conventional methods. Furthermore, if only a portion is removed, the remaining silicon substrate corresponds to the first substrate portion 2A in Figure 1. The combined portion of this remaining silicon substrate (corresponding to the first substrate portion 2A) and the aforementioned 3C-SiC layer (corresponding to the second substrate portion 2B) corresponds to substrate portion 2 in Figure 1. Moreover, the entire remaining portion after this thinning process corresponds to memory device 1 in Figure 1. On the other hand, if the entire silicon substrate is removed, as mentioned above, the 3C-SiC layer corresponds to the substrate portion 20 consisting only of 3C-SiC in Figure 3. The entire remaining portion after the thin-film treatment corresponds to the memory device 10 in Figure 3. Removing the entire silicon substrate allows for even thinner film construction, enabling further thinning of the HBM layer and an increase in the number of DRAM chips, which is preferable.

[0042] The manufacturing method of the present invention described above makes it possible to manufacture a memory device that has both crack suppression and improved heat dissipation characteristics by utilizing the properties of 3C-SiC (high Young's modulus and heat dissipation effect due to high thermal conductivity). For this reason, even if the memory device is made thinner than conventionally, it is less prone to cracking and warping. In addition, even if the number of layers of memory devices is increased in the manufacturing of HBM, deterioration of heat dissipation characteristics can be prevented. Therefore, it is possible to improve the performance of HBM by increasing the number of layers.

[0043] In the fabrication of HBM, the semiconductor memory device for HBM according to the present invention is diced into a chip (DRAM chip), and multiple DRAM chips (memory dies) prepared in this way are stacked vertically and connected to each other with through-electrodes to manufacture HBM. This HBM is then connected to a silicon interposer, and a processor is connected to the silicon interposer, making it usable in AI servers and the like. [Examples]

[0044] The present invention will be described more specifically below with reference to examples of the present invention, but the present invention is not limited to these examples. (Examples) The semiconductor memory device 1 for HBM according to the present invention was manufactured as follows, following the flow chart in Figure 4. A standard single-crystal silicon substrate with a diameter of 300 mm, a thickness of 750 μm, a crystal orientation of (100), and boron doping was prepared (Step 1). A single-crystal silicon substrate was placed on a susceptor in the reactor of a commercially available general-purpose reduced-pressure CVD apparatus, and H2 annealing was performed at 1080°C for 1 minute (Step 2). Subsequently, trimethylsilane gas was introduced at a growth temperature of 900°C and a growth pressure of 5 Torr (667 Pa) to perform the SiC nucleation process and epitaxial growth of a 3C-SiC single crystal layer. After 20 minutes of growth, a 3C-SiC single crystal layer with a thickness of 100 nm was formed (Step 3). Subsequently, H2 annealing was performed at 1130°C for 1 minute in a commercially available, standard atmospheric pressure epitaxial growth furnace. Next, the growth temperature was set to 1080°C, trichlorosilane gas was introduced, and a silicon epitaxial layer of 2 μm was grown (Step 4).

[0045] A semiconductor memory element (DRAM) was formed on this silicon epitaxial layer using photolithography (Step 5). Subsequently, for use with HBM, the single-crystal silicon substrate was polished to a thickness of approximately 78 μm to create a thin film, bringing the total thickness to 80 μm (Step 6), thereby obtaining the HBM semiconductor memory device 1 of the present invention.

[0046] Afterward, multiple DRAM chips were obtained by dicing. Then, bumps were formed on the back surface and the four DRAM chips were bonded together, but no cracks occurred.

[0047] (Comparative example) A standard single-crystal silicon substrate with a diameter of 300 mm, a thickness of 750 μm, a crystal orientation of (100), and boron doping was prepared for use as a resistor. In the same atmospheric pressure epitaxial growth furnace as in the example, H2 annealing was performed at 1130°C for 1 minute. Subsequently, the growth temperature was increased to 1080°C, trichlorosilane gas was introduced, and a silicon epitaxial layer of 2 μm was grown. A semiconductor memory element (DRAM) was formed on this silicon epitaxial layer using photolithography. Subsequently, for use with HBM, the single-crystal silicon substrate was polished to a thickness of approximately 78 μm to create a thin film, resulting in an overall thickness of 80 μm and obtaining a semiconductor memory device for HBM. Thus, semiconductor memory devices for HBM were manufactured in the same manner as in the examples, except that a 3C-SiC single crystal layer was not formed.

[0048] Afterward, multiple DRAM chips were obtained by dicing. Then, bumps were formed on the back surface and four DRAM chips were bonded together. In this case, cracks occurred in all chips, starting from the bumps.

[0049] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that has substantially the same technical idea as described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0050] 1, 10... The present invention provides a semiconductor memory device for HBM, 2, 20...base part, 2A...first base part, 2B...second base part, 3, 30... Semiconductor memory element section.

Claims

1. It has a substrate and a semiconductor memory element made of silicon on the substrate. The semiconductor memory device for HBM is characterized in that the substrate portion comprises a first substrate portion made of silicon and a second substrate portion made of 3C-SiC on the first substrate portion, or is made of 3C-SiC only.

2. The semiconductor memory device for HBM according to claim 1, characterized in that the second substrate portion made of 3C-SiC, or the substrate portion made solely of 3C-SiC, has a thickness of 100 nm or more.

3. A method for manufacturing a semiconductor memory device for HBM, comprising forming a silicon layer on a silicon substrate by epitaxial growth, forming a semiconductor memory element on the silicon layer, and subjecting it to a thin-film treatment, In the deposition of the silicon layer, a 3C-SiC layer is first deposited on the silicon substrate by epitaxial growth, and then the silicon layer is deposited on the 3C-SiC layer. A method for manufacturing a semiconductor memory device for HBMs, characterized in that, in the thin-film treatment, a part or all of the silicon substrate is removed.

4. The method for manufacturing a semiconductor memory device for HBM according to claim 3, characterized in that when the 3C-SiC layer is formed, the thickness of the formed film is 100 nm or more.

5. The method for manufacturing a semiconductor memory device for HBM according to claim 3 or 4, characterized in that when forming the silicon layer, the thickness of the formed film is adjusted according to the thickness of the semiconductor memory device for HBM to be manufactured.

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