Method for manufacturing a template substrate and a method for manufacturing a semiconductor epitaxial substrate

Abstract

The present invention provides a method for manufacturing a template substrate and a method for manufacturing a semiconductor epitaxial substrate that can suppress the reduction in yield caused by the presence of group III nitride deposition areas on the back surface of the substrate. [Solution] The method for manufacturing a template substrate according to the present invention includes a growth step of supplying a raw material gas to the surface of a substrate supported by a susceptor to grow a group III nitride layer whose main surface is the C-plane; an inspection step of checking whether or not a precipitate of group III nitride has been formed on the back surface of the substrate on which the group III nitride layer has been grown; and an immersion step of immersing the substrate on which the precipitate of group III nitride has been formed on the back surface in an alkaline solution, wherein the alkaline solution selectively etches the A-plane, R-plane, and M-plane of the group III nitride.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a template substrate and a method for manufacturing a semiconductor epitaxial substrate. [Background technology]

[0002] A method for manufacturing wafers has been known in which a group III nitride layer is grown by supplying a raw material gas to the surface of a substrate supported by a susceptor. Patent Document 1 discloses this type of wafer manufacturing method.

[0003] In the wafer manufacturing method described in Patent Document 1, a susceptor is prepared on which a coating layer containing at least one element of Al, Ga, and In and N is formed on the mounting surface on which a substrate constituting the wafer is placed. The substrate is placed on the side of the coating layer opposite to the mounting surface, and each layer constituting the wafer is grown on the side of the substrate opposite to the coating layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-127115 [Overview of the project] [Problems that the invention aims to solve]

[0005] According to the wafer manufacturing method described in Patent Document 1, the formation of a coating layer on the susceptor mounting surface can suppress the formation of unintended crystals on the back surface of the substrate. However, even with the wafer manufacturing method described in Patent Document 1, it is difficult to completely prevent the growth of unintended crystals on the back surface of the substrate. If products such as light-emitting elements are manufactured using a substrate on which unintended crystals have grown on the back surface, the yield may decrease.

[0006] The present invention aims to provide a method for manufacturing a template substrate and a semiconductor epitaxial substrate that can suppress the reduction in yield caused by the presence of group III nitride deposition areas on the back surface of the substrate. [Means for solving the problem]

[0007] The gist of the present invention is as follows:

[0008] (1) A growth process in which a source gas is supplied to the surface of a substrate supported by a susceptor to grow a group III nitride layer whose main surface is the C plane, An inspection step to check whether or not a group III nitride precipitate has formed on the back surface of the substrate on which the group III nitride layer has grown, The process includes an immersion step of immersing a substrate on which the group III nitride precipitate is formed on the back surface in an alkaline solution. The aforementioned alkaline solution selectively etches the A-side, R-side, and M-side of a group III nitride, and is a method for manufacturing a template substrate.

[0009] (2) The method for manufacturing a template substrate according to (1), wherein the alkaline solution is any of TMAH solution, KOH solution, NaOH solution, or a mixture of at least two of these.

[0010] (3) The method for manufacturing a template substrate according to (1) or (2), wherein the temperature of the alkaline solution in which the substrate is immersed is 50°C or higher and 90°C or lower.

[0011] (4) The method for manufacturing a template substrate according to any one of (1) to (3), wherein the concentration of the alkaline solution in which the substrate is immersed is 1% by mass or more and 10% by mass or less.

[0012] (5) A method for manufacturing a template substrate according to any one of (1) to (4), wherein the time for immersing the substrate in the alkaline solution is 0.5 hours or more and 2 hours or less.

[0013] (6) Further include a heat treatment step of heat-treating the group III nitride layer between after the growth step and before the immersion step, and the full width at half maximum of the X-ray rocking curve of the (10-12) plane of the group III nitride layer after the heat treatment step is 300 arcsec or less. The method for manufacturing a template substrate according to any one of (1) to (5) above.

[0014] (7) The group III nitride layer is an AlN layer. The method for manufacturing a template substrate according to any one of (1) to (6) above.

[0015] (8) A method for manufacturing a semiconductor epitaxial substrate, including an epitaxial growth step of forming a group III nitride laminate on the surface of a template substrate manufactured by the method for manufacturing a template substrate according to any one of (1) to (7) above.

Effect of the Invention

[0016] According to the present invention, it is possible to provide a method for manufacturing a template substrate that can suppress a decrease in yield due to the presence of a deposition portion of a group III nitride on the back surface of the substrate.

Brief Description of the Drawings

[0017] [Figure 1] It is a diagram showing an example of a template substrate manufacturing apparatus used in the method for manufacturing a template substrate according to the present invention. [Figure 2] It is a diagram showing the susceptor alone shown in FIG. 1. [Figure 3] It is a diagram showing an example of a template substrate manufactured using the method for manufacturing a template substrate according to the present invention. [Figure 4] It is a diagram showing an example of a semiconductor epitaxial substrate manufactured using the method for manufacturing a semiconductor epitaxial substrate according to the present invention. [Figure 5] It is a flowchart showing an example of the method for manufacturing a template substrate and the method for manufacturing a semiconductor epitaxial substrate according to the present invention. s [Figure 6]This is a diagram for explaining the mechanism by which a deposition portion of a group III nitride is formed on the back surface of a substrate. [Figure 7] In Example 1, this is an example of a photograph showing the state where concentrated light is irradiated on the back surface of an AlN template substrate after the immersion process is performed. [Figure 8] In Example 1, this is an example of a photograph showing the state where concentrated light is irradiated on the back surface of an AlN template substrate immediately before the immersion process is performed.

Mode for Carrying Out the Invention

[0018] Prior to the description of the embodiments according to the present invention, the following points will be explained in advance while referring to the reference numerals of the configurations and processes illustrated in FIGS. 1 to 6.

[0019] The "deposit of group III nitride" in the present embodiment means something that can be discriminated in the inspection process S2 described later. Specifically, in the inspection process S2, concentrated light is irradiated on the back surface 1b of the substrate 1 to observe the appearance. When there is no deposit on the back surface 1b of the substrate 1, the concentrated light is not reflected, so the substrate 1 is colorless and transparent. However, when there is a deposit, the concentrated light is diffusely reflected, so it becomes opaque (cloudy state). Further, in the inspection process S2, when it is difficult to determine whether the deposit is formed on the back surface 1b or the front surface of the substrate 1, the substrate 1 is observed with a metallurgical microscope for determination. That is, the "deposit of group III nitride" in the present embodiment means the crystal of group III nitride adhering to the back surface 1b of the substrate 1 that changes the substrate 1, which was colorless and transparent immediately before the growth process S1 described later, to become opaque (cloudy state) immediately after the growth process S1 described later when concentrated light is irradiated on the back surface 1b of the substrate 1, or the crystal of group III nitride adhering to the back surface 1b of the substrate 1 that can be observed with a metallurgical microscope.

[0020] In this embodiment, "selective etching" means that the etching rate for a specific plane orientation is high, but the etching rate for other plane orientations is sufficiently low. In this invention, "selective etching of the A, R, and M planes of a group III nitride" means that the A, R, and M planes of a hexagonal group III nitride are etched because their etching rates are high, but the C plane of the group III nitride (especially the group III polar plane described later) is not etched. Not etching means that the etching rate is 1 nm / min or less.

[0021] In this embodiment, "immersion" means immersing the substrate 1 in the liquid so that the entire substrate 1 is submerged in the liquid. In other words, "immersion" in this embodiment does not include applying the liquid to only a part of the substrate 1 (for example, only the back surface 1b of the substrate 1).

[0022] In this embodiment, "central film thickness" refers to the thickness of each layer at the center of the template substrate 100. The central film thickness is measured using an optical interference film thickness analyzer (for example, NanoSpec M6100A manufactured by Nanometrics).

[0023] In this embodiment, the X-ray rocking curve is measured by ω scanning using an X-ray diffractometer (for example, a D8 DISCOVER AUTOWAFS manufactured by Bruker AXS). The detector side of the X-ray diffractometer is an open slit, and the aperture width of the detector is set to 0.5°.

[0024] Hereinafter, embodiments of the method for manufacturing a template substrate and a semiconductor epitaxial substrate according to the present invention will be illustrated with reference to the drawings. In each figure, identical components are denoted by the same reference numerals.

[0025] <Manufacturing equipment 300> First, with reference to Figures 1 and 2, a manufacturing apparatus 300, which is an example of a manufacturing apparatus for a template substrate 100 used in the method for manufacturing a template substrate according to the present invention, will be described.

[0026] As shown in Figure 1, the manufacturing apparatus 300 comprises a chamber 310, a susceptor 320, a rotating shaft 330, and a heater 340. The chamber 310 partitions a reaction space 311 inside. The reaction space 311 contains the susceptor 320, the rotating shaft 330, and the heater 340. In addition to the manufacturing apparatus 300, Figure 1 also shows a substrate 1 placed on the susceptor 320.

[0027] As shown in Figures 1 and 2, the susceptor 320 has a mounting surface 321 on which the substrate 1 can be placed. In this specification, the direction perpendicular to the mounting surface 321 is referred to as the "upper direction A". Furthermore, within the upper direction A, the side on which the substrate 1 is placed relative to the mounting surface 321 is referred to as the "upper side", and the opposite side is referred to as the "lower side". In addition, the upper surface of the substrate 1 when placed on the mounting surface 321 is referred to as the "front surface 1a of the substrate 1", and the lower surface of the substrate 1 when placed on the mounting surface 321 is referred to as the "back surface 1b of the substrate 1".

[0028] As shown in Figure 2, the susceptor 320 has a flattened, disc-shaped outer shape in the vertical direction A. The upper surface 323 of the susceptor 320 has at least one recess 322 that is recessed downwards. The susceptor 320 shown in Figure 1 has multiple recesses 322. In Figure 2, for ease of explanation, only one recess 322 is shown.

[0029] The substrate 1 can be placed in the recess 322. Specifically, the bottom surface of the recess 322 is the mounting surface 321 described above. In other words, the substrate 1 is placed in the recess 322 by being placed on the mounting surface 321. The upper surface 323 of the susceptor 320 is configured to form a substantially flat surface with the surface 1a of the substrate 1 that is placed in the recess 322 (i.e., placed on the mounting surface 321).

[0030] The side surface of the recess 322 is configured to form a gap between it and the side surface of the substrate 1 placed in the recess 322. The user can place the substrate 1 in the recess 322 and remove the substrate 1 from the recess 322 by inserting tweezers or the like into this gap. A groove connected to the recess 322 may be formed on the surface of the susceptor 320. In this case, the user can also perform the above-described placement and removal by inserting tweezers or the like into this groove.

[0031] In the examples shown in Figures 1 and 2, the mounting surface 321 may have a circular outer shape when viewed from above. The side surface of the recess 322 is a circumferential surface that rises upward from the outer edge of the mounting surface 321, which serves as the bottom surface. However, the shape of the susceptor 320 is not limited to the configuration of this example and may be appropriately changed according to the shape of the substrate 1, etc.

[0032] In the example shown in Figure 1, the rotating shaft 330 is connected to the lower end of the susceptor 320. The rotating shaft 330 rotates about a central axis O that extends parallel to the vertical direction A, causing the susceptor 320 to rotate. The rotating shaft 330 is connected to a drive mechanism and is configured to rotate by receiving rotational force from the drive mechanism.

[0033] In the example shown in Figure 1, the heater 340 is located below the susceptor 320 and heats the substrate 1 via the susceptor 320. For example, an electric heater that generates heat when energized can be used as the heater 340.

[0034] In the example shown in Figure 1, the chamber 310 has a supply port 312 for supplying raw material gas to the reaction space 311 and an outlet port 313 for discharging the raw material gas from the reaction space 311 to the outside. The supply port 312 is located above the susceptor 320. The outlet port 313 is located below the susceptor 320.

[0035] <Template board 100> Next, with reference to Figure 3, a template substrate 100 will be described as an example of a template substrate manufactured by the method for manufacturing a template substrate and a semiconductor epitaxial substrate according to the present invention. As shown in Figure 3, the template substrate 100 has a substrate 1 and a group III nitride layer 11 formed on the surface 1a of the substrate 1. As the substrate 1, a known substrate capable of epitaxial growth of group III nitride can be used. Specifically, as the substrate 1, for example, a sapphire substrate, an AlN substrate, a GaN substrate, a SiC substrate, etc. can be used.

[0036] The group III nitride layer 11 is a hexagonal group III nitride layer, and may be, for example, an AlGaN layer. However, from the viewpoint of efficiency in the immersion process S3 described later, the group III nitride layer 11 preferably has an Al composition of 20% or more, more preferably 60% or more, and most preferably 100%, i.e., the group III nitride layer 11 is an AlN layer, so that the etching rate on the A and M planes is sufficiently large. Furthermore, the crystal orientation of the main plane of the group III nitride layer 11 is preferably the C plane, which is a group III polar plane. Note that the "group III polar plane" is the surface of the group III nitride layer on the C plane located on the crystal growth direction side, and is not the group V polar plane that is exposed when the substrate 1 is removed. Furthermore, the crystal orientation of the main plane of the group III nitride layer 11 being the C plane can be confirmed by 2θ-ω measurement using an X-ray diffractometer.

[0037] In the example shown in Figure 3, substrate 1 is a sapphire substrate, and the group III nitride layer 11 is an AlN layer. In the example shown in Figure 3, the surface 1a of substrate 1 is a hexagonal C-plane, and the surface of the group III nitride layer 11, i.e., the main surface, is also a hexagonal C-plane. Hereafter, a substrate 1 with an AlN layer formed as the group III nitride layer 11 on its surface 1a will be referred to as an AlN template substrate.

[0038] <Semiconductor epitaxial substrate 200> Next, with reference to Figure 4, a semiconductor epitaxial substrate 200, as an example of a semiconductor epitaxial substrate manufactured by the semiconductor epitaxial substrate manufacturing method according to the present invention, will be described. As shown in Figure 4, the semiconductor epitaxial substrate 200 has a template substrate 100 and a group III nitride laminate 50 containing at least Al formed on the surface of the template substrate 100.

[0039] More specifically, in the example shown in Figure 4, the group III nitride laminate 50 comprises a buffer layer 2, an n-type semiconductor layer 3, an emissive layer 4, and a p-type semiconductor layer 55. The buffer layer 2, n-type semiconductor layer 3, emissive layer 4, and p-type semiconductor layer 55 are laminated in this order on the AlN layer which is the surface of the AIN template substrate. The p-type semiconductor layer 55 may optionally have an i-type guide layer 5, a p-type electron blocking layer 6, a p-type cladding layer 7, and a p-type contact layer 8.

[0040] The buffer layer 2 is located between the AlN layer and the n-type semiconductor layer 3 on the substrate 1, and is a layer that mitigates the lattice constant difference between the substrate 1 and the AlN layer and the n-type semiconductor layer 3. The buffer layer 2 is preferably composed of a layer formed by stacking multiple AlGaN layers with different Al compositions, or a layer with a gradient of Al compositions. Furthermore, the buffer layer 2 is preferably undoped. In the example shown in Figure 4, the buffer layer 2 is shown as a layer formed by stacking a first buffer layer 21 and a second buffer layer 22, which are AlGaN layers with different Al compositions.

[0041] n-type semiconductor layer 3 has an Al composition ratio x. x Ga 1-x This layer contains an n-type dopant such as Si in N and functions as an n-type semiconductor. On the n-type semiconductor layer 3, an n-type guide layer 31 may be formed, which is an n-type semiconductor layer containing an n-type dopant such as Si in AlGaN having the same Al composition ratio as the n-type semiconductor layer 3, and is thinner than the n-type semiconductor layer 3.

[0042] The light-emitting layer 4 is a layer that includes a layer made of AlGaN. The light-emitting layer 4 has a plurality of well layers 41 and a plurality of barrier layers 42, which are stacked alternately. That is, the light-emitting layer 4 has well layers 41 having an Al composition ratio corresponding to the emission center wavelength, and barrier layers 42 sandwiching the well layers 41, and has a configuration in which one or more pairs of combinations of well layers 41 and barrier layers 42 are repeated.

[0043] The i-type guide layer 5 is an i-type layer having a higher Al composition ratio than the barrier layer 42. The Al composition ratio of the i-type guide layer 5 is preferably higher than the Al composition ratio y of the p-type electron blocking layer described later, and most preferably AlN.

[0044] The p-type electron blocking layer 6 is made of Al having an Al composition ratio y. y Ga 1-y This layer functions as a p-type semiconductor composed of N. The p-type dopant (p-type impurity) doped into the p-type electron blocking layer 6 is, for example, Mg.

[0045] The p-type cladding layer 7 is made of Al having an Al composition ratio z. z Ga 1-z This layer functions as a p-type semiconductor composed of N. The p-type dopant doped into the p-type cladding layer 7 is, for example, Mg.

[0046] The p-type contact layer 8 is a p-type semiconductor made of AlGaN containing a high concentration of p-type dopant, for example, GaN, and is a layer for making ohmic contact with the electrode. The p-type dopant doped into the p-type contact layer 8 is, for example, Mg. The three layers, the p-type electron blocking layer 6, the p-type cladding layer 7, and the p-type contact layer 8, may each be a single layer or have a superlattice structure. The p-type cladding layer 7 may be omitted, in which case the p-type contact layer 8 may be in contact with the p-type electron blocking layer 6.

[0047] <Method for manufacturing a template substrate> Next, an example of a method for manufacturing a template substrate according to the present invention will be described with reference to the flowchart in Figure 5. As shown in Figure 5, the method for manufacturing a template substrate according to the present invention includes a growth step S1, an inspection step S2, and an immersion step S3. In this example, the growth step S1 is performed using the manufacturing apparatus 300 described above.

[0048] In growth step S1, a raw material gas is supplied to the surface 1a of the substrate 1 supported by the susceptor 320 to grow the group III nitride layer 11. That is, growth step S1 may be carried out using MOCVD (Metal Organic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy), or the like. However, it is preferable that growth step S1 be carried out using the MOCVD method.

[0049] In the growth process S1 of this example, the temperature of the substrate 1 supported by the susceptor 320 is raised using the heater 340 to a temperature suitable for the growth of the group III nitride layer 11. Then, while rotating the susceptor 320 via the rotating shaft 330, a raw material gas containing group V element gas (NH3) and group III element gas (TMA) is supplied from the supply port 312 to the reaction space 311 of the chamber 310, thereby forming the group III nitride layer 11 on the surface 1a of the substrate 1.

[0050] In the growth process S1, the main surface of the sapphire substrate of the template substrate 100 is a surface on which the group III nitride layer 11 can be epitaxially grown, and is preferably a chamfered surface. In addition to being a chamfered surface, it may also have an off-angle. For example, it may be tilted with an off-angle θ of 0.02° to 2.0°, or with an off-angle θ of 0.02° to 0.35°. Furthermore, the central film thickness of the group III nitride layer 11 of the template substrate 100 may be 0.30 μm to 1.0 μm. Moreover, the growth temperature in the chamber 310 may be 1000°C to 1400°C. Furthermore, the growth pressure in the chamber 310 may be 10 Torr to 760 Torr. Furthermore, the raw material gas flow rate is preferably set appropriately according to the growth temperature and growth pressure, but for example, the flow rate of group V element gas (NH3) may be set to 100 sccc cm or more and 1000 sccm or less, and the flow rate of group III element gas (TMA) may be set to 20 sccm or more and 200 sccm or less.

[0051] Here, as shown in Figure 6, when the group III nitride layer 11 grows on the surface 1a of the substrate 1 during the growth process S1, warping of the substrate 1 may occur due to differences in lattice constants and thermal expansion coefficients. Specifically, there are cases where the substrate 1 warps so that it is convex downwards (see Figure 6) and cases where the substrate 1 warps so that it is convex upwards. When the substrate 1 warps so that it is convex downwards, as shown in Figure 6, a void X is formed between the back surface 1b of the substrate 1 and the mounting surface 321 of the susceptor 320, and the raw material gas can enter this void X. When the substrate 1 warps so that it is convex upwards, a void X is also formed between the back surface 1b of the substrate 1 and the mounting surface 321 of the susceptor 320. The raw material gas can then enter this void X, for example, by passing through the orientation flat of the substrate 1.

[0052] The raw material gas that enters the void X may cause the formation of group III nitride precipitates on the back surface 1b of the substrate 1. When a product such as a light-emitting element is manufactured using a template substrate 100 on which group III nitride precipitates have formed on the back surface 1b of the substrate 1, the yield may decrease. In contrast, according to the method for manufacturing a template substrate according to the present invention, by performing the inspection step S2 and the immersion step S3, which will be described later, after the growth step S1, the decrease in yield due to the presence of group III nitride precipitates on the back surface 1b of the substrate 1 can be suppressed.

[0053] In inspection step S2, it is checked whether or not group III nitride precipitates have formed on the back surface 1b of the substrate 1 on which the group III nitride layer 11 has grown.

[0054] Specifically, inspection step S2 can be a step in which the substrate 1 is inspected by, for example, irradiating the back surface 1b of the substrate 1 with concentrated light and observing its appearance. If there are no deposits on the back surface 1b of the substrate 1, the concentrated light will not be reflected, and the substrate 1 will be colorless and transparent. However, if there are deposits, the concentrated light will be scattered, making it opaque (cloudy). Note that depending on the angle at which the concentrated light is applied, the deposits may not be visible, so it is preferable to observe by irradiating the substrate with concentrated light from various angles. Also, if it is difficult to determine whether the deposits are formed on the back surface 1b or the front surface of the substrate 1, it is preferable to observe and determine this using a metallurgical microscope.

[0055] In inspection step S2, if it is determined that no group III nitride precipitates have formed on the back surface 1b of substrate 1, the template substrate 100 is completed. On the other hand, in inspection step S2, if it is determined that group III nitride precipitates have formed on the back surface 1b of substrate 1, the immersion step S3 is performed on the substrate 1, and then the template substrate 100 is completed.

[0056] In this way, by performing the inspection step S2, substrates 1 that do not have group III nitride precipitates formed on their back surface can be excluded from the immersion step S3. This reduces the number of substrates 1 that are subjected to the immersion step S3 compared to when the inspection step S2 is not performed. As a result, the efficiency of the immersion step S3 can be improved.

[0057] In the immersion step S3, the substrate 1, on which a group III nitride precipitate has formed on its back surface, is immersed in an alkaline solution. This alkaline solution is designed to selectively etch the A, R, and M surfaces of the group III nitride. As described above, in the immersion step S3, "selective etching" means that the etching rates of the A, R, and M surfaces are high, but the etching rate of the group III polar surface is low, with the etching rate of the group III polar surface being 1 nm / min or less. By using such a solution, it is possible to selectively etch and remove the group III nitride precipitate formed on the back surface 1b of the substrate 1 while suppressing the etching of the group III nitride layer 11 formed on the surface 1a of the substrate 1.

[0058] Specifically, the alkaline solution into which the substrate 1 is immersed is one of the following: TMAH solution, KOH solution, or NaOH solution, or a mixture of at least two of these. Among these, TMAH solution is preferred. This is because TMAH is easier to handle than other strong alkalis and does not contain metal ions like KOH or NaOH, making cleaning easier.

[0059] Even when using the alkaline solution described above, dislocations may be etched and form etch pits. Therefore, it is preferable to adjust the temperature range, concentration range, and immersion time range of the alkaline solution to such an extent that etch pits do not occur or expand. Specifically, the temperature of the alkaline solution into which the substrate 1 is immersed is preferably 50°C to 90°C, more preferably 55°C to 75°C, and even more preferably 58°C to 65°C. The concentration of the alkaline solution into which the substrate 1 is immersed (the value obtained by dividing the total mass of TMAH, KOH, and NaOH contained in the alkaline solution by the mass of the alkaline solution) is preferably 1.0% by mass to 10% by mass, and more preferably 1.5% by mass to 5.0% by mass. If the alkaline solution is a TMAH solution, the concentration of the TMAH solution as the alkaline solution is even more preferably 2.0% by mass to 3.0% by mass. The time for immersing the substrate 1 in the alkaline solution is preferably 0.5 hours or more and 2 hours or less, more preferably 0.7 hours or more and 1.5 hours or less, and even more preferably 0.8 hours or more and 1.2 hours or less.

[0060] In addition, from the viewpoint of suppressing the occurrence of etch pits, it is more preferable that the group III nitride layer 11 has good crystallinity and few dislocations. This is because it suppresses the formation of etch pits or depressions due to the enlargement of etch pits on the surface of the group III nitride layer 11 during the immersion process S3, and allows for a wider range of control over the concentration, temperature, and immersion time of the alkaline solution used.

[0061] The method for manufacturing a template substrate according to the present invention may include a heat treatment step after the growth step described above, in which the group III nitride layer 11 is heat-treated at a high temperature to reduce the transition size and decrease the full width at half maximum of the X-ray rocking curves of the (0002) plane and (10-12) plane of the group III nitride layer. It is preferable to perform this heat treatment step between the growth step and the immersion step. The heat treatment step may be performed between the growth step S1 and the inspection step S2, or between the inspection step S2 and the immersion step S3. For example, it is preferable that the full width at half maximum of the X-ray rocking curve of the (10-12) plane after the heat treatment step is 300 arcsec or less.

[0062] Various conditions in the heat treatment process may be changed as appropriate, but the heat treatment is carried out in an inert gas atmosphere such as nitrogen. For example, the heating temperature may be between 1400°C and 1750°C, and the heating time may be between 1 hour and 10 hours.

[0063] <Method for manufacturing semiconductor epitaxial substrates> Next, the method for manufacturing a semiconductor epitaxial substrate according to the present invention will be described with reference to the flowchart in Figure 5. As shown in Figure 5, the method for manufacturing a semiconductor epitaxial substrate according to the present invention includes the growth step S1, inspection step S2, immersion step S3, and an epitaxial growth step S4 performed following these steps. The growth step S1, inspection step S2, and immersion step S3 are the same as those for manufacturing a template substrate described above, so their explanation will be omitted. In the epitaxial growth step S4 according to this example, a group III nitride laminate 50 is formed on the surface of the template substrate 100 manufactured through the growth step S1, inspection step S2, and immersion step S3 (i.e., the template substrate 100 manufactured by the method for manufacturing a template substrate according to the present invention). Specifically, when manufacturing the semiconductor epitaxial substrate 200 shown in Figure 4, a buffer layer 2, an n-type semiconductor layer 3, an emissive layer 4, and a p-type semiconductor layer 55 are formed on the surface of the template substrate 100 in this order.

[0064] As described above, according to the method for manufacturing a template substrate and a semiconductor epitaxial substrate according to the present invention, the efficiency of the immersion process S3 can be improved by performing the inspection process S2 for the reasons mentioned above. Furthermore, by performing the immersion process S3 on a substrate 1 on which group III nitride precipitates are formed on the back surface 1b, the precipitates on the back surface 1b of the substrate 1 can be etched and removed. This suppresses the reduction in yield caused by the presence of group III nitride precipitates on the back surface 1b of the substrate 1.

[0065] <Examples> The present invention will be described in more detail below with reference to examples, but the present invention is not limited in any way to the following examples.

[0066] (Example 1) First, the growth process was carried out. Specifically, a sapphire substrate with a C-plane tilted at an off-angle θ of 0.11° was placed on a susceptor, and an AlN layer with a central thickness of 0.60 μm was grown on the surface of the sapphire substrate by MOCVD. The main surface of the AlN layer was the Group III polar plane of the C-plane. At this time, the growth temperature was 1330°C, and the growth pressure in the chamber was 10 Torr. The flow rate of the Group V element gas (NH3) supplied as the raw material gas was 250 sccc cm, and the flow rate of the Group III element gas (TMA) was 43 sccm.

[0067] Next, a heat treatment process was carried out. Specifically, the AlN template substrate, after the AlN layer was formed and removed from the MOCVD apparatus, was placed in a heat treatment furnace. After reducing the pressure to 10 Pa and purging nitrogen gas to atmospheric pressure, the furnace was filled with nitrogen gas to create a nitrogen atmosphere. Then, the temperature inside the furnace was raised to heat-treat the AlN template substrate. At this time, the heating temperature was 1620°C and the heating time was 5 hours. In this way, the AlN template substrate according to Example 1 was prepared.

[0068] Next, the inspection process was carried out. Specifically, concentrated light was shone onto the AlN template substrate and its appearance was observed. If there were no deposits on the back surface of the AlN template substrate, the concentrated light would not be reflected, and the template substrate would be colorless and transparent. However, if deposits were present, the concentrated light would be scattered, resulting in an opaque (cloudy) appearance. Since deposits may not be visible depending on the angle from which the concentrated light is shone, observations were made by shining concentrated light from various angles.

[0069] Next, an immersion process was performed on the AlN template substrates that were found to have precipitates on the back surface during the inspection process. Specifically, the AlN template substrates with precipitates on the back surface, as identified in the inspection process, were immersed in a 2.38 wt% TMAH aqueous solution (AZ 300MIF DEVELOPER (2.38%), manufactured by Merck Electronics K.K.) at a temperature of 60°C for 60 minutes. After that, the AlN template substrates were washed with pure water and dried. Furthermore, the immersion process was not performed on AlN template substrates that were determined not to have precipitates formed on their back surface during the inspection process.

[0070] (Comparative Example 1) An AlN template substrate was prepared in the same manner as in Example 1, except that the immersion process was not performed on the AlN template substrate that was determined to have precipitates formed on its back surface during the inspection process.

[0071] <Rating> The AlN template substrate obtained by performing the immersion process of Example 1 and the AlN template substrate obtained by Comparative Example 1, which did not undergo the immersion process and had precipitates on its back surface, were evaluated as follows.

[0072] (Evaluation 1: Check for the presence or absence of deposits on the back surface of the template substrate) The presence or absence of precipitates was confirmed by irradiating the back surface of the AlN template substrate with concentrated light and visually observing for surface clouding. Figure 7 is an example of a photograph showing the back surface of the AlN template substrate irradiated with concentrated light after the immersion process was performed on the substrate shown in Figure 8 in Example 1, and Figure 8 is an example of a photograph showing the back surface of the AlN template substrate irradiated with concentrated light immediately before the immersion process was performed in Example 1. As shown in Figure 7, no precipitates were observed on the back surface of the AlN template substrate after the immersion process according to Example 1. Similar to the precipitates observed immediately before the immersion process in Example 1 shown in Figure 8, precipitates were observed on the back surface of the AlN template substrate that had not undergone the immersion process according to Comparative Example 1.

[0073] (Evaluation 2: Evaluation of the crystallinity of the AlN layer) The X-ray rocking curve was measured by ω scanning using an X-ray diffractometer (D8 DISCOVER AUTOWAFS; Bruker AXS). The detector side of the X-ray diffractometer was an open slit, and the detector aperture width was set to 0.5°. As a result, the full width at half maximum (FWHM) in the (0002) plane of the AlN layer after the heat treatment process was 51.8 arcsec, and the FWHM in the (10-12) plane was 200.5 arcsec. The crystallinity of the group III nitride layer in the AlN template substrates of Example 1 and Comparative Example 1 was good.

[0074] (Evaluation 3: Check for any damage to the surface of the template substrate) Before and after performing the immersion process of Example 1, AFM (atomic force microscope) images were acquired on the surface of the AlN layer of the AlN template substrate using an AFM device (Nanoscope V; Bruker) to check for any damage to the surface of the AlN layer of the AlN template substrate. In this case, the conditions for no damage were defined as the absence of an increase in the number of pits, no enlargement of pits, and no disturbances in the edges of the steps in the AFM image acquired in a 5.0 μm × 2.5 μm area. As a result, it was confirmed that the immersion process in Example 1 did not damage the surface of the template substrate.

[0075] (Evaluation 4: Confirmation of the surface condition of the semiconductor epitaxial substrate after epitaxial growth) In the AlN template substrates where precipitates were determined to have formed on the back surface during the inspection process, the AlN template substrates from Example 1, which underwent the immersion process, and Comparative Example 1, which did not undergo the immersion process, were again placed on a susceptor. Semiconductor epitaxial substrates were then fabricated by epitaxial growth of a group III nitride laminate on the surface of each AlN layer using the MOCVD method, and the surface condition was confirmed. Specifically, surface flatness Ra and R were determined by visual observation using focused light and AFM (atomic force microscope) images. max Measurements were taken of Ra and R. max The value was automatically calculated using the application software attached to the AFM apparatus in an AFM image acquired in a 5.0 μm × 2.5 μm area. The results are shown in Table 1. When the AlN template substrate of Comparative Example 1 was used, for reasons that are not clear, it became clear that precipitates on the back surface affected crystal growth on the AlN layer on the main surface side, roughening the surface of the group III nitride laminate and causing clouding. Furthermore, the surface condition after epitaxial growth when using the AlN template substrate of the example in which the immersion process was performed was almost the same as when using the AlN template substrate in which there were no precipitates on the back surface during the inspection process. In other words, it was found that by performing the immersion process, it can be used in the same way as the AlN template substrate in which there were no precipitates on the back surface.

[0076] (Rating 5: Evaluation of appearance yield) In Evaluation 4, the semiconductor epitaxial substrates were assembled into individual light-emitting element chips, and the yield was evaluated by visual inspection. The visual yield was calculated using the following relational formula. The results are shown in Table 1. (Appearance Yield) = (Number of light-emitting elements that pass appearance inspection) ÷ (Total number of light-emitting elements that can be obtained from one semiconductor epitaxial substrate according to the design)

[0077] [Table 1] TIFF2026078982000002.tif30170

[0078] (comprehensive evaluation) As shown in Table 1, when using a template substrate that has been subjected to the immersion process even if deposits are found on the back surface in the inspection process, no surface cloudiness occurred even when the group III nitride laminate was epitaxially grown on the AlN layer. However, when using a template substrate that has not been subjected to the immersion process, surface cloudiness occurred. Also, the values of Ra and R were larger when using a template substrate that has not been subjected to the immersion process than when using a template substrate that has been subjected to the immersion process. From the presence or absence of surface cloudiness and the values of Ra and R, it was confirmed that the quality of the semiconductor epitaxial substrate can be improved by performing the inspection process and the immersion process. Furthermore, when using a template substrate that has been subjected to the immersion process, the appearance yield was 80%, but when using a template substrate that has not been subjected to the immersion process, the appearance yield was 63%. That is, it was confirmed that the decrease in yield can be suppressed by performing the inspection process and the immersion process. max of the values became larger. From the presence or absence of surface cloudiness and the values of Ra and R max of the values, it was confirmed that the quality of the semiconductor epitaxial substrate can be improved by performing the inspection process and the immersion process. Furthermore, when using a template substrate that has been subjected to the immersion process, the appearance yield was 80%, but when using a template substrate that has not been subjected to the immersion process, the appearance yield was 63%. That is, it was confirmed that the decrease in yield can be suppressed by performing the inspection process and the immersion process.

[0079] The method for manufacturing a template substrate and the method for manufacturing a semiconductor epitaxial substrate according to the present invention are not limited to the specific configurations and processes shown in the above-described embodiments, and various modifications, changes, and combinations are possible without departing from the scope of the claims.

Industrial Applicability

[0080] The present invention relates to a method for manufacturing a template substrate and a method for manufacturing a semiconductor epitaxial substrate.

Explanation of Signs

[0081] 1: Substrate 1a: Surface of the substrate 1b: Back surface of the substrate 2: Buffer layer 3: n-type semiconductor layer 4: Light-emitting layer 5: i-type guide layer 6: p-type electron blocking layer 7: p-type cladding layer 8: Contact layer 11: Group III nitride layer 21: First buffer layer 22: Second buffer layer 31: n-type guide layer 41: Well layer 42: Barrier layer 50: Group III Nitride Laminate 55: p-type semiconductor layer 100: Template board 200: Semiconductor epitaxial substrate 300: Manufacturing equipment 310: Chamber 311: Reaction space 312: Supply port 313: Outlet 320: Susceptor 321: Mounting surface 322: Recess 323: Top of the susceptor 330: Rotation axis 340: Heater A: Vertical direction S1: Growth process S2: Inspection process S3: Soaking process S4: Epitaxial growth process O: Central axis X: void

Claims

1. A growth process involves supplying a raw material gas to the surface of a substrate supported by a susceptor to grow a group III nitride layer whose main surface is the C plane, An inspection step to check whether or not precipitates of group III nitride are formed on the back surface of the substrate on which the group III nitride layer has grown, The process includes an immersion step of immersing a substrate on which the group III nitride precipitate is formed on the back surface in an alkaline solution. The aforementioned alkaline solution selectively etches the A-side, R-side, and M-side of a group III nitride, and is a method for manufacturing a template substrate.

2. The method for producing a template substrate according to claim 1, wherein the alkaline solution is any of TMAH solution, KOH solution, NaOH solution, or a mixture of at least two of these.

3. The method for manufacturing a template substrate according to claim 1 or 2, wherein the temperature of the alkaline solution in which the substrate is immersed is 50°C or higher and 90°C or lower.

4. The method for manufacturing a template substrate according to claim 1 or 2, wherein the concentration of the alkaline solution in which the substrate is immersed is 1% by mass or more and 10% by mass or less.

5. The method for manufacturing a template substrate according to claim 1 or 2, wherein the time for immersing the substrate in the alkaline solution is 0.5 hours or more and 2 hours or less.

6. A method for manufacturing a template substrate according to claim 1 or 2, further comprising a heat treatment step of heat-treating the group III nitride layer between the growth step and the immersion step, wherein the full width at half maximum of the X-ray rocking curve of the (10-12) plane of the group III nitride layer after the heat treatment step is 300 arcsec or less.

7. The method for manufacturing a template substrate according to claim 1 or 2, wherein the group III nitride layer is an AlN layer.

8. A method for manufacturing a semiconductor epitaxial substrate, comprising an epitaxial growth step of forming a group III nitride laminate on the surface of a template substrate manufactured by the method for manufacturing a template substrate according to claim 1 or 2.

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