Semiconductor memory devices

Abstract

This reduces defective bits in semiconductor memory devices, such as those in SILC mode. [Solution] The semiconductor memory device comprises a plurality of memory cells formed on a semiconductor substrate. Each memory cell includes a first floating-gate transistor (TFG1), a second floating-gate transistor (TFG2), a first erase element, a second erase element, and a memory cell selection transistor. The gate of TFG1 is connected to the gate of the first erase element. The gate of TFG2 is connected to the gate of the second erase element. The source of TFG1 is connected to the drain of the memory cell selection transistor. The source of TFG2 is connected to the drain of the memory cell selection transistor or the drain of TFG1.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device.

Background Art

[0002] Semiconductor memory devices are used in various electronic devices. For example, nonvolatile memory (NVM) is widely used in portable devices and the like.

[0003] Generally, NVM is classified into a multi-time programmable (MTP) memory and a one-time programmable (OTP) memory. The MTP memory can be read multiple times and written multiple times. Also, in OTP, an erase operation is not required, but in MTP, an erase operation is required.

[0004] As a type of NVM, single-poly NVM that can reduce additional manufacturing processes has been proposed. In single-poly NVM, a charge storage floating gate having a single layer of polysilicon is formed. Since single-poly NVM can be manufactured in a normal CMOS (Complementary Metal Oxide Semiconductor) manufacturing process, it is applied as an embedded memory in a microcontroller or the like.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The non-volatile memory with the above configuration includes a transistor with a floating gate (FG) as the gate electrode. Non-volatile data is stored by utilizing the difference in transistor current caused by the presence or absence of charge accumulation in the floating gate (FG).

[0007] In such memory devices, if the gate oxide film becomes thinner due to miniaturization requirements, or if defects occur in the gate oxide film, the charge accumulated in the floating gate may be lost. This is known as the SILC (Stress-induced leakage current) mode. When this situation occurs, the correct memory state cannot be maintained, and bad bits may result. This failure occurs with a very low probability, and the temperature dependence of the retention time is often small. Therefore, screening is difficult, and recovering bad bits through screening is also difficult. Furthermore, the number of bad bits tends to increase with retention time. Predicting after 10 years, the chip failure rate could reach around 1000 ppm, which could become a reliability issue.

[0008] In light of the above, the purpose of this disclosure is to reduce defective bits caused by defects such as SILC mode in semiconductor memory devices. [Means for solving the problem]

[0009] The semiconductor memory device of this disclosure comprises a plurality of memory cells formed on a semiconductor substrate. Each of the memory cells comprises a first floating-gate transistor, a second floating-gate transistor, a first erase element, a second erase element, and a memory cell selection transistor. The gate of the first floating-gate transistor is electrically connected to the gate of the first erase element. The gate of the second floating-gate transistor is electrically connected to the gate of the second erase element. The source of the first floating-gate transistor is electrically connected to the drain of the memory cell selection transistor. The source of the second floating-gate transistor is electrically connected to the drain of the memory cell selection transistor or the drain of the first floating-gate transistor. [Effects of the Invention]

[0010] According to the semiconductor memory device of this disclosure, since one memory cell is stored using multiple floating gate transistors, even if a SILC mode failure occurs in one floating gate transistor, the memory cell can maintain correct storage, thereby reducing bit failures. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 shows the circuit configuration of an exemplary semiconductor memory device according to the first embodiment. [Figure 2] Figure 2 is a plan view illustrating the layout of the semiconductor memory device shown in Figure 1. [Figure 3] Figure 3 shows the bit error rate over time in a semiconductor memory device according to the first embodiment. [Figure 4] Figure 4 shows the bit error rate over time in a comparative example semiconductor memory device. [Figure 5] Figure 5 is a plan view illustrating the layout of a semiconductor memory device in a modified example of the first embodiment. [Figure 6]Figure 6 shows the circuit configuration of an exemplary semiconductor memory device according to the second embodiment. [Figure 7] Figure 7 is a plan view illustrating the layout of the semiconductor memory device shown in Figure 6. [Figure 8] Figure 8 shows the circuit configuration of an exemplary semiconductor memory device according to the third embodiment. [Figure 9] Figure 9 is a plan view illustrating the layout of the semiconductor memory device shown in Figure 8. [Modes for carrying out the invention]

[0012] The embodiments will be described below with reference to the drawings. The following description is illustrative and not limiting. Furthermore, modifications can be made as appropriate within the scope of achieving the desired effect.

[0013] (First embodiment) A first embodiment of this disclosure will be described with reference to the drawings. Figure 1 is a diagram showing an exemplary circuit configuration of a semiconductor memory device according to the first embodiment. Figure 2 is a plan view illustrating the layout of the semiconductor memory device of this embodiment.

[0014] The circuit configuration will be described with reference to Figure 1. Figure 1 shows a circuit corresponding to one memory cell 50. The memory cell 50 comprises a memory cell selection gate unit 10, a program element unit 20, an erase element unit 30, and an assist element unit 40.

[0015] The program element unit 20 has a configuration in which a transistor TFG1 (floating gate transistor) with a first floating gate FG1 as its gate node and a transistor TFG2 with a second floating gate FG2 as its gate node are connected in parallel. In other words, the sources of transistors TFG1 and TFG2 are connected to each other, and the drains are also connected to each other.

[0016] Also, for the transistors TFG1 and TFG2, the source side is connected to the drain of the selection transistor TSG1 provided in the selection gate part 10, and the drain side is connected to the bit line BL. The source side of the selection transistor TSG1 is connected to the source signal SL (set voltage VSS), and the gate of the selection transistor TSG1 is connected to the selection gate signal SG.

[0017] The erasing element part 30 includes erasing elements TER1 and TER2. The erasing element TER1 includes a first erasing gate and a first erasing element impurity region provided on the semiconductor substrate. The erasing element TER2 includes a second erasing gate and a second erasing element impurity region provided on the semiconductor substrate.

[0018] The floating gate FG1 is connected to the gate of the erasing element TER1, and the floating gate FG2 is connected to the gate of the erasing element TER2. The nodes of the first erasing element impurity region in the erasing element TER1 and the second erasing element impurity region in the erasing element TER2 are connected to the erasing node ER. The erasing elements TER1 and TER2 are charge control elements that control the charges in the floating gates FG1 and FG2, and erase the information stored in the program element part 20.

[0019] The assist element part 40 includes assist elements TAS1 and TAS2. The assist element TAS1 includes a first assist gate and a first assist element impurity region provided on the semiconductor substrate. The assist element TAS2 includes a second assist gate and a second assist element impurity region provided on the semiconductor substrate.

[0020] The floating gate FG1 is connected to the assist element TAS1, and the floating gate FG2 is connected to the assist element TAS2. The assist elements TAS1 and TAS2 are potential control elements that control the potentials of the floating gates FG1 and FG2, and improve the efficiency of the programming operation and / or erasing operation in the program element part 20.

[0021] In this embodiment, the first assist element impurity region and the second assist element impurity region of the assist elements TAS1 and TAS2 are connected to the bit line BL as nodes. However, these nodes can also be controlled by independent nodes.

[0022] Figure 2 illustrates a layout corresponding to the circuit diagram in Figure 1. It shows the active region 61 (indicated by widely spaced diagonal lines from the upper left to the lower right) provided on the semiconductor substrate, various gate sections 62 (indicated by narrowly spaced diagonal lines from the upper right to the lower left), and the metal wiring layer 63 (indicated by dots). The memory cell 50, memory cell selection gate section 10, program element section 20, erase element section 30, and assist element section 40 all correspond to those in Figure 1. For example, the circuit in Figure 1 can be realized using the layout in Figure 2.

[0023] Next, the program operation, erase operation, and read operation of the semiconductor memory device of this embodiment will be described.

[0024] During program operation (writing), the selection transistor TSG1 is turned on, and a high voltage is applied to both bit lines BL to generate hot carriers in transistors TFG1 and TFG2, which constitute the program element section 20. The charge of the hot carriers passes through the insulating film and enters the floating gates FG1 and FG2. As a result, the thresholds of transistors TFG1 and TFG2 become high, and no current flows. This puts the system into the programmed state.

[0025] In this case, a high voltage is applied to the bit line BL, which increases the potential of the floating gates FG1 and FG2 from the assist element section 40, thereby improving the efficiency of the program.

[0026] Furthermore, a voltage is applied to the nodes ER of the erase elements TER1 and TER2 of the erase element unit 30 that does not trigger an erase operation (i.e., a voltage lower than that used during an erase operation). This also improves the efficiency of the program.

[0027] During the erase operation, the selection transistor TSG1 is turned off, and the bit line BL is set to ground voltage bell or floating state, while a high voltage is applied to the erase node ER. This draws out the charge accumulated in the floating gates FG1 and FG2. As a result, the threshold voltages of transistors TFG1 and TFG2 are lowered, allowing current to flow. This completes the erase operation.

[0028] During read operation, the selection transistor TSG1 is turned on, and a voltage is applied that does not trigger program operation (i.e., a voltage lower than that used during program operation). In this state, the current flowing through the bit line BL is used to determine whether the device is on or off. In other words, a judgment current value is set as the criterion for on / off, and the device is determined to be on when the current flowing through the bit line BL is greater than the judgment current value, and off when it is less than the judgment current value. During read operation, the erase node ER is set to ground voltage.

[0029] The program state and erase state may be verified by a read operation, and additional program operations and additional erase operations may be performed to ensure that the cell current is at an appropriate level.

[0030] --Reducing defects in memory cells-- Next, we will explain how the semiconductor memory device of this embodiment can reduce overall defects in the memory cell 50 even when defects such as SILC mode occur.

[0031] In devices that store data based on the presence or absence of charge accumulation in a floating gate (FG), if the charge accumulated in the floating gate is lost, the correct memory state cannot be maintained, resulting in a bad bit. In particular, when the charge is lost due to the thinness or defects of the gate insulating film, it is called SILC mode. SILC mode defects (hereinafter also referred to as SILC defects) can occur in each floating gate.

[0032] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 is provided with two transistors TFG1 and TFG2 connected in parallel. A single selection transistor TSG1 in the memory cell selection gate section 10 corresponds to these two transistors. Transistors TFG1 and TFG2 each have floating gates FG1 and FG2 as gate nodes.

[0033] This configuration allows the memory cell 50 to retain correct data even if a failure occurs in one of the two floating gates FG1 and FG2. Therefore, the occurrence of bad bits can be significantly reduced. In other words, if the failure rate of the chip is about 1000 ppm when a failure occurs in one floating gate with a certain probability, the probability of the chip becoming defective due to the same probability of SILC failure occurring in both floating gates FG1 and FG2 of the memory cell 50 is about 1 ppm.

[0034] In order for the memory cell 50 to retain correct data even if a SILC failure occurs in one floating gate, the current values ​​in transistors TFG1 and TFG2, and the on / off determination current value in the memory cell 50 must be set. This will be explained further below.

[0035] Table 1 shows the current values ​​for each state for transistors TFG1 and TFG2, and for the entire program element section 20. Each state refers to the initial state, the programmed state, the SILC failure state during programming, the erase state, and the SILC failure state during erasure. The SILC failure state refers to a state where a SILC failure occurs in one of the transistors (transistor TFG1). Note that the situation is essentially the same even if the SILC failure occurs in transistor TFG2 instead of TFG1.

[0036] [Table 1]

[0037] In the example in Table 1, when transistors TFG1 and TFG2 are in their initial state, the current flowing through them during readout is assumed to be 3 μA. The initial state refers to the state in the semiconductor memory device manufacturing process when each element is formed and the floating gates FG1 and FG2 are stable (a state in which no charge injection has been performed).

[0038] In a programmed (written) state where no SILC failures occur, the current values ​​in transistors TFG1 and TFG2 are set to 0 μA. Since the two transistors TFG1 and TFG2 are connected in parallel, the total current value of the programmed element section 20 (hereinafter also referred to as the total current) is 0 μA in the programmed state.

[0039] Furthermore, in the erase state where no SILC defects occur, the current values ​​in transistors TFG1 and TFG2 are 15 μA, and the total current is 30 μA.

[0040] Furthermore, generally speaking, when a SILC failure occurs in a transistor and charge is lost from the floating gate, the floating gate transistor approaches its initial state. Therefore, in the SILC failure state during programming and the SILC failure state during erasure, the current value in the faulty transistor TFG1 will be the same as the initial state, 3μA.

[0041] From the above, in the SILC faulty state during programming, the total current is 3μA, which is the sum of 0μA and 3μA. Also, in the SILC faulty state during erasure, the total current is 18μA, which is the sum of 15μA and 3μA.

[0042] In this case, the judgment current value that serves as the criterion for turning the memory cell 50 on and off is set to, for example, 5 μA. This value is between the total current (3 μA and 18 μA) in the SILC fault state during programming and the SILC fault state during erasure.

[0043] In this way, the total current in a program state without defects is 0 μA, which is smaller than the judgment current value (5 μA), so it is determined to be in a program state. Also, even in a SILC defect state during programming, the total current is 3 μA, which is smaller than the judgment current value, so it can be correctly determined to be in a program state.

[0044] Next, the total current in the erase state is 30 μA, which is greater than the judgment current value, so it is determined to be in the erase state. Also, even in the SILC fault state during erasure, the total current is 18 μA, which is greater than the judgment current value, so it can be correctly determined to be in the erase state.

[0045] As described above, the semiconductor memory device of this embodiment can correctly determine the program state and erase state even when a SILC mode failure occurs in transistor TFG1. Furthermore, even if a SILC mode failure occurs in transistor TFG2 instead of transistor TFG1, the total current in each state is the same as the values ​​shown in Table 1, and the same correct determination can be made.

[0046] The judgment current value should be greater than half of the total current (6μA) when transistors TFG1 and TFG2 are in their initial state. In the example in Table 1, this value should be greater than 3μA.

[0047] Therefore, the configuration of this embodiment is suitable when the initial current value is small. This is because a smaller initial current value results in a smaller lower limit for the judgment current value, thus widening the range in which the judgment current value can be set. The initial current value is determined by various factors, but it can be adjusted by the assist element unit 40. In this embodiment, it may be appropriate to set the effect of the assist element unit 40 to a relatively small level. Alternatively, a configuration without the assist element unit 40 is also possible.

[0048] Furthermore, the determination current value is preferably less than half of the total current value when transistors TFG1 and TFG2 are in the erase state. In the example in Table 1, it should be less than 15 μA.

[0049] The judgment current value may be the total current in the initial state (6 μA in the example in Table 1). Furthermore, considering that the current of the memory cell 50 decreases when it is turned on (erased) at high temperatures, and that there may be variations in the current for each memory cell 50, it is also preferable to use a value slightly lower than the total current in the initial state, which is 5 μA in the example of this embodiment.

[0050] Figure 3 shows the bit error rate over time under various temperature conditions for the semiconductor memory device of this embodiment. The graph shows time on the horizontal axis and the bit error rate on the vertical axis, demonstrating that the occurrence of defective bits is suppressed even as time passes.

[0051] Figure 4 shows a similar bit error rate for a semiconductor memory device equipped with a conventional memory cell using a single transistor (with a floating gate as the gate node) as a comparative example. This semiconductor memory device does not include the transistor TFG2, floating gate FG2, assist element TAS2, or erase element TER2 as shown in Figure 1. In this case, the bit error increases over time.

[0052] In the case of Figure 4, a temperature dependence is observed, with a tendency for the number of defects to increase with higher temperatures. However, SILC mode defects show little temperature dependence. Therefore, accelerated evaluation and screening at high temperatures are difficult.

[0053] The semiconductor memory device disclosed herein can reduce defects even without an ECC (error correction code) circuit to address SILC mode defects. However, it is certainly possible to include an ECC circuit for safety in various situations.

[0054] (Modified version of the first embodiment) A modified version of the first embodiment will be described with reference to Figure 5. Figure 5 is a plan view showing the layout of the semiconductor memory device in this modified version, and corresponds to Figure 2 in the first embodiment. Furthermore, Figure 5 has a different layout from Figure 2, which realizes the circuit diagram of Figure 1.

[0055] Comparing the layout of Figure 5 with that of Figure 2, the assist elements TAS1 and TAS2 of the assist element section 40 are different. Specifically, the assist effect is improved by making the gate ring-shaped and by placing the active region 61 at the bottom of the assist gate.

[0056] Furthermore, in the layout of Figure 2, the two bit lines within the same cell are not connected by the active region 61, but are connected by the metal wiring layer 63. In contrast, in the layout of Figure 5, the two bit lines are directly connected by the active region 61, and the additional active region 61 is also potentialally connected to the bit lines by metal.

[0057] This layout allows for a larger capacitance between the floating gate and the bit line. As a result, the potential of the floating gate can be increased during program operation, improving program efficiency and consequently shortening the program time. Furthermore, during erase operation, increasing the capacitance of the assist element in the assist element section 40 makes it less likely for the potential of the floating gate to float. This increases the potential difference actually applied to the erase elements TER1 and TER2 during erase, thereby shortening the erase time.

[0058] Thus, with this modified layout, performance can be improved without increasing the cell size compared to the layout in Figure 2.

[0059] (Second embodiment) A second embodiment of this disclosure will be described with reference to the drawings. Figure 6 is a diagram showing an exemplary circuit configuration of a semiconductor memory device according to the second embodiment. Figure 7 is a plan view illustrating the layout of the semiconductor memory device of this embodiment.

[0060] Comparing the circuit diagram in Figure 6 with the circuit diagram in Figure 1, which is from the first embodiment, the program element section 20 is different, while the memory cell selection gate section 10, erase element section 30, and assist element section 40 are the same. The differences will be explained below.

[0061] In Figure 2, transistors TFG1 and TFG2 are connected in parallel, whereas in this embodiment, these transistors are connected in series. Specifically, the source of transistor TFG1 is connected to the drain of transistor TFG2. The drain of transistor TFG1 is connected to the bit line BL. The source side of transistor TFG2 is connected to the drain of the selection transistor TSG1 of the memory cell selection gate unit 10.

[0062] Transistors TFG1 and TFG2 have floating gates FG1 and FG2 as gate nodes, respectively. As in the first embodiment, the erasure element TER1 and assist element TAS1 are connected to floating gate FG1, and the erasure element TER2 and assist element TAS2 are connected to floating gate FG2. In this embodiment, the impurity regions of assist elements TAS1 and TAS2 are connected as nodes to the bit line BL. However, these nodes can also be controlled by independent nodes.

[0063] Figure 7 illustrates a layout corresponding to the circuit diagram in Figure 6. In Figure 7, the active region 61 and the gate portion 62 are also shown. The memory cell 50, memory cell selection gate portion 10, program element portion 20, erase element portion 30, and assist element portion 40 all correspond to those in Figure 6. For example, the circuit in Figure 5 can be realized using the layout in Figure 6.

[0064] Next, the program operation, erase operation, and read operation of the semiconductor memory device of this embodiment will be described.

[0065] During program operation, the selection transistor TSG1 is turned on, and a high voltage is applied to both the TSG1 and TFG2 bit lines BL to generate hot carriers in the TSG1 and TFG2 transistors that constitute the program element section 20. When the hot carriers enter the floating gates FG1 and FG2, the thresholds of transistors TFG1 and TFG2 become high, and no current flows. This puts the system into the programmed state.

[0066] In this case, a high voltage is applied to the bit line BL, which increases the potential of the floating gates FG1 and FG2 from the assist element section 40, thereby improving the efficiency of the program.

[0067] Furthermore, a voltage is applied to the nodes ER of the erase elements TER1 and TER2 of the erase element unit 30 that does not trigger an erase operation (i.e., a voltage lower than that used during an erase operation). This also improves the efficiency of the program.

[0068] During the erase operation, the selection transistor TSG1 is turned off, and the bit line BL is set to ground voltage bell or floating state, while a high voltage is applied to the erase node ER. This draws out the charge accumulated in the floating gates FG1 and FG2. As a result, the threshold voltages of transistors TFG1 and TFG2 are lowered, allowing current to flow. This completes the erase operation.

[0069] During read operation, the selection transistor TSG1 is turned on, and a voltage low enough to prevent program operation (i.e., lower than during program operation) is applied to the bit line BL. In this state, the current flowing through the bit line BL is used to determine whether the device is on or off. In other words, a judgment current value is set as the criterion for on / off, and the device is determined to be on when the current flowing through the bit line BL is greater than the judgment current value, and off when it is less than the judgment current value. During read operation, the erase node ER is set to ground voltage.

[0070] The program state and erase state may be verified by a read operation, and additional program operations and additional erase operations may be performed to ensure that the cell current is at an appropriate level.

[0071] --Reducing defects in memory cells-- Next, we will explain how the semiconductor memory device of this embodiment can reduce overall defects in the memory cell 50 even when defects such as SILC mode occur.

[0072] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 is provided with two transistors TFG1 and TFG2 connected in series. A single selection transistor TSG1 in the memory cell selection gate section 10 corresponds to these two transistors. Transistors TFG1 and TFG2 each have floating gates FG1 and FG2 as their gate nodes.

[0073] This configuration, like the first embodiment, can significantly reduce the occurrence of bad bits. To achieve this, the current values ​​in transistors TFG1 and TFG2, and the on / off determination current value in memory cell 50 are set. This will be explained further below.

[0074] Table 2 shows the current values ​​for each state for transistors TFG1 and TFG2, and for the entire program element section 20. Each state is the initial state, the programmed state, the SILC failure state during programming, the erase state, and the SILC failure state during erasure. The SILC failure state is a state in which a SILC failure occurs in one of the transistors (transistor TFG1).

[0075] [Table 2]

[0076] In the example in Table 2, when transistors TFG1 and TFG2 are in their initial state, the current flowing through them during the readout operation is assumed to be 15 μA.

[0077] In a programmed (written) state where no SILC failures occur, the current values ​​in transistors TFG1 and TFG2 are set to 0 μA. Since the two transistors TFG1 and TFG2 are connected in series, the total current value of the programmed element section 20 as a whole is 0 μA in the programmed state.

[0078] Furthermore, in the erase state where no SILC defects occur, the current value in the series-connected transistors TFG1 and TFG2 is 30 μA, and the total current is 30 μA.

[0079] Furthermore, in the case of a faulty SILC state during programming and during erasure, the current value at the faulty transistor TFG1 will be 15μA, the same as the initial state.

[0080] From the above, in the SILC faulty state during programming, the current values ​​of the series-connected transistors TFG1 and TFG2 are 15μA and 0μA respectively, so the total current is 0μA. Also, in the SILC faulty state during erasure, the current values ​​of the series-connected transistors TFG1 and TFG2 are 15μA and 30μA respectively, so the total current is 15μA.

[0081] In this case, the judgment current value is set to, for example, 12 μA. This value is between the total current (15 μA and 0 μA) in the SILC fault state during programming and the SILC fault state during erasure.

[0082] In this way, the total current is 0 μA in both the programmed state and the SILC failure state during programming, which is smaller than the judgment current value of 12 μA, so the programmed state can be correctly determined.

[0083] Furthermore, the total current in the erasure state without defects is 30 μA, which is greater than the judgment current value, so it is determined to be in the erasure state. Moreover, even in the case of a SILC defect during erasure, the total current is 15 μA, which is greater than the judgment current value, so it is correctly determined to be in the erasure state.

[0084] As described above, the semiconductor memory device of this embodiment can correctly determine the program state and erase state even when a SILC mode failure occurs in transistor TFG1. Furthermore, even if a SILC mode failure occurs in transistor TFG2 instead of transistor TFG1, the total current in each state is the same as the values ​​shown in Table 2, and the same correct determination can be made.

[0085] The judgment current value shall be a value smaller than the total current value that flows when transistors TFG1 and TFG2 are in their initial state.

[0086] The configuration of this embodiment is suitable when the initial current value is large and ON-side SILC mode failures are unlikely to occur. The initial current value is determined by various factors, but it can be adjusted by the assist element section 40. In this embodiment, it may be appropriate to set the effect of the assist element section 40 to be relatively large. Furthermore, it may be appropriate to configure the assist element section 40 to be controlled using a signal other than the signal from the bit line BL in order to increase the assist effect. However, the effect of the assist element section 40 should be within a range that does not result in a programmed state during read operations.

[0087] (Third embodiment) A third embodiment of this disclosure will be described with reference to the drawings. Figure 8 is a diagram showing an exemplary circuit configuration of a semiconductor memory device according to the third embodiment. Figure 9 is a plan view illustrating the layout of the semiconductor memory device of this embodiment.

[0088] Comparing the circuit diagram in Figure 8 with the circuit diagram in Figure 1 of the first embodiment, it is similar in that it includes a memory cell selection gate unit 10, a program element unit 20, an erase element unit 30, and an assist element unit 40. Furthermore, the configuration of the memory cell selection gate unit 10 is the same.

[0089] The program element section 20 comprises six transistors TFG1 to TFG6. The source of transistor TFG1 is connected to the drain of transistor TFG5. The source of transistor TFG2 is connected to the drain of transistor TFG6. The source of transistor TFG3 is connected to the drain of transistor TFG4.

[0090] As described above, pairs of transistors connected in series are connected in parallel to each other to form the program element section 20. Specifically, the sources of transistors TFG4, TFG6, and TFG5 are connected to each other and also to the drain of the selection transistor TSG1. In addition, the drains of transistors TFG3, TFG2, and TFG1 are connected to each other and also to the bit line BL.

[0091] The assist element section 40 is equipped with three assist elements TAS1, TAS2, and TAS3. Assist element TAS3 has the same configuration as assist elements TAS1 and TAS2, and includes a third assist gate and a third assist element impurity region.

[0092] In this embodiment, the impurity regions in the assist elements TAS1, TAS2, and TAS3 are connected to the bit line BL as nodes. However, these nodes can also be controlled by independent nodes.

[0093] The erasure element section 30 is equipped with three erasure elements TER1, TER2, and TER3. Erasure element TER3 has the same configuration as erasure elements TER1 and TER2, and is equipped with a third erasure gate and a third erasure impurity region.

[0094] Each impurity region in the erasure elements TER1, TER2, and TER3 is connected to the erasure node ER as a node.

[0095] It is also equipped with three floating gates, FG1, FG2, and FG3.

[0096] The floating gate FG1 is connected to the gates of transistors TFG1 and TFG4, the erase element TER3, and the assist element TAS3.

[0097] The floating gate FG2 is connected to the gates of transistors TFG2 and TFG5, the erase element TER2, and the assist element TAS2.

[0098] The floating gate FG3 is connected to the gates of transistors TFG3 and TFG6, the erase element TER3, and the assist element TAS3.

[0099] Figure 9 illustrates a layout corresponding to the circuit diagram in Figure 8. In Figure 9, the active region 61, gate portion 62, and metal wiring layer 63 are also shown. The memory cell 50, memory cell selection gate portion 10, program element portion 20, erase element portion 30, and assist element portion 40 all correspond to those in Figure 8. For example, the circuit in Figure 8 can be realized using the layout in Figure 9.

[0100] Next, the program operation, erase operation, and read operation of the semiconductor memory device of this embodiment will be described.

[0101] During program operation, the selection transistor TSG1 is turned on, and a high voltage is applied to both the selection transistor TSG1 and the bit line BL to generate hot carriers in the transistors TFG1 to TFG6 that constitute the program element section 20. When the hot carriers enter the floating gates FG1 and FG2, the threshold voltage of transistors TFG to TFG6 rises, and no current flows. This puts the system into the programmed state.

[0102] In this case, a high voltage is applied to the bit line BL, which increases the potential of the floating gates FG1 to FG3 from the assist element section 40, thereby improving the efficiency of the program.

[0103] During the erase operation, the selection transistor TSG1 is turned off, and the bit line BL is set to ground voltage bell or floating state, while a high voltage is applied to the erase node ER. This draws out the charge accumulated in the floating gates FG1 to FG3. As a result, the threshold voltages of transistors TFG1 to TFG6 are lowered, allowing current to flow. This completes the erase operation.

[0104] During read operations, the selection transistor TSG1 is turned on, and a voltage low enough to prevent program operation (i.e., lower than during program operation) is applied to the bit line BL. In this state, the current flowing through the bit line BL is used to determine whether it is in the on or off state. During read operations, the erase node ER is set to ground voltage.

[0105] The program state and erase state may be verified by a read operation, and additional program operations and additional erase operations may be performed to ensure that the cell current is at an appropriate level.

[0106] --Reducing defects in memory cells-- Next, we will explain how the semiconductor memory device of this embodiment can reduce overall defects in the memory cell 50 even when defects such as SILC mode occur.

[0107] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 comprises six transistors TFG1 to TFG6 connected as described above, and one selection transistor TSG1 in the memory cell selection gate section 10 corresponds to these transistors TFG1 to TFG6.

[0108] This configuration significantly reduces the occurrence of bad bits even if a failure occurs in any of the floating gates FG1 to FG3. To achieve this, the current values ​​in transistors TFG1 to TFG6 and the on / off determination current value in memory cell 50 are set. This will be explained further below.

[0109] Table 3 shows the current values ​​for each state for three pairs of transistors connected in series, namely transistors TFG1 / TFG4, transistors TFG2 / TFG5, and transistors TFG3 / TFG6, and the entire program element section 20. Each state is the initial state, the programmed state, the SILC fault state during programming, the erase state, and the SILC fault state during erasure. The SILC fault state is defined as the state in which a SILC fault occurs in the floating gate FG1 (in other words, in either transistor TFG1 or TFG4).

[0110] Note that the current values ​​in the two transistors connected in series are simplified values ​​and are not necessarily accurate. This is because using simplified values ​​makes the following explanation clearer and more concise than using accurate values, and the use of simplified values ​​has little impact on the explanation of the invention's structure and effects.

[0111] [Table 3]

[0112] In the example in Table 3, the initial current values ​​of transistors TFG1 to TFG6 are all 3 μA. Therefore, the total current (the current value for the entire program element section 20) is the sum of the currents in the three sets of transistors connected in parallel, which is 9 μA.

[0113] In this embodiment as well, if a SILC failure occurs in the transistor and charge is lost from the floating gate, the floating gate transistor approaches its initial state (current value of 3 μA).

[0114] In a program state where no SILC failures occur, the current values ​​in transistors TFG1 to TFG6 are set to 0 μA. Therefore, the total current is also 0 μA.

[0115] During a SILC failure in the programmed state, the thresholds of transistors TFG1 and TFG4, which are connected to the floating gate FG1, fluctuate, and a current of 3 μA may flow through each. However, since transistor TFG5 is connected in series to transistor TFG1 and transistor TFG3 is connected in series to transistor TFG4, the current for each of these pairs is 0 μA. Therefore, in a SILC failure in the programmed state, the total current is 0 μA. Consequently, the memory cell 50 is not considered defective.

[0116] Furthermore, in the erase state where no SILC defects occur, the current values ​​in transistors TFG1 to TFG6 are set to 10 μA each. Therefore, the total current is 30 μA.

[0117] In the case of a SILC failure during erasure, the threshold values ​​of transistors TFG1 and TFG4 connected to the floating gate FG1 fluctuate, and the current flowing through them changes from 10 μA (current value during erasure) to 3 μA.

[0118] In this case, of the three series-connected transistor pairs, the current value in two pairs, including transistor TFG1 or TFG4, is 3μA. The remaining pair, transistors TFG2 and TFG3, maintains a current of 10μA. Since the three pairs are connected in parallel, the total current is the sum of these, which is 16μA.

[0119] Here, if the determination current value is set to a value between 0μA and 16μA, for example 5μA, even if a SILC defect occurs in some floating gates, it can be determined to be in an erased state, and the memory cell 50 will not be considered defective.

[0120] The judgment current value is set to a range that is smaller than the total current in the SILC faulty state during erasure, and larger than the total current in the programmed state.

[0121] According to the configuration of this embodiment, regardless of the current value in the initial state, failures as memory cells can be reduced and on / off status can be reliably determined. The above explanation described the case where a SILC mode failure occurs in floating gate FG1 as an example. However, even if a SILC mode failure occurs in another floating gate (FG2 or FG3), the total current in each state is the same as the value shown in Table 3, and a similarly correct determination can be made.

[0122] The first embodiment primarily addresses the effects of ON-side failures, while the second embodiment primarily addresses the effects of OFF-side failures. In contrast, this embodiment can similarly address the effects of either ON-side or OFF-side failures.

[0123] On the other hand, in the configurations of the first and second embodiments, the number of transistors, erase elements, and assist elements provided in the program element section 20, erase element section 30, and assist element section 40 is smaller than in the configuration of the third embodiment. Therefore, the first or second embodiment allows for a smaller memory cell size or a larger cell current in a memory cell 50 of the same size.

[0124] The above explanation described the case where various elements are constructed within the same well using only N-channel transistors. However, this is not the only option; it is also possible to construct them using P-channel transistors.

[0125] Furthermore, as a third embodiment, a configuration in which three pairs of transistors connected in series are connected in parallel (a 2x3 configuration) was described, but the invention is not limited to this, and configurations such as 3x2 and 3x4 are also acceptable.

[0126] The embodiments described above may be modified in form and detail, provided that they do not deviate from the spirit of the claims. Furthermore, the contents of each embodiment can be combined and substituted as appropriate, as long as they do not impair the functions covered by this disclosure. [Industrial applicability]

[0127] The semiconductor memory device disclosed herein can significantly improve the occurrence of defects such as SILC mode, and is also useful as a semiconductor memory device equipped with non-volatile memory. [Explanation of Symbols]

[0128] 10 Selection Gate Section 20 Programming element section 30 Erasing element section 40 Assist element section 50 memory cells 61 Active region 62 Gate section 63 Metal wiring layer SG Select Gate Signal SL Source Signal (Ground Voltage VSS) BL bit signal line ER erase signal line FG1~FG3 Floating Gates TSG1 Memory cell selection transistor TFG1~TFG6 Transistors (Floating Gate Transistors) TER1~TER3 Eradication Elements TAS1~TAS3 Assist Elements

Claims

1. Multiple memory cells are formed on a semiconductor substrate. Each of the memory cells comprises a first floating-gate transistor, a second floating-gate transistor, a first erase element, a second erase element, and a memory cell selection transistor. The gate of the first floating-gate transistor is electrically connected to the gate of the first erasing element. The gate of the second floating-gate transistor is electrically connected to the gate of the second erasing element. The source of the first floating gate transistor is electrically connected to the drain of the memory cell selection transistor. A semiconductor memory device characterized in that the source of the second floating-gate transistor is electrically connected to the drain of the memory cell selection transistor or the drain of the first floating-gate transistor.

2. In claim 1, A first assist element for controlling the gate potential of the first floating gate transistor, A semiconductor memory device characterized by comprising a second assist element for controlling the gate potential of the second floating-gate transistor.

3. In claim 1, The source of the first floating-gate transistor and the source of the second floating-gate transistor are electrically connected. The drain of the first floating-gate transistor and the drain of the second floating-gate transistor are electrically connected. A semiconductor memory device characterized in that the source of the second floating-gate transistor is electrically connected to the drain of the memory cell selection transistor.

4. In claim 3, The first erasing element comprises a first erasing gate and a first impurity region formed on the semiconductor substrate. The second erasing element comprises a second erasing gate and a second impurity region formed on the semiconductor substrate. A semiconductor memory device characterized in that the first impurity region and the second impurity region are electrically connected.

5. In claim 1, The source of the first floating-gate transistor and the drain of the second floating-gate transistor are electrically connected. A semiconductor memory device characterized in that the source of the second floating-gate transistor is electrically connected to the drain of the memory cell selection transistor.

6. In claim 5, The first erasing element comprises a first erasing gate and a first impurity region formed on the semiconductor substrate. The second erasing element comprises a second erasing gate and a second impurity region formed on the semiconductor substrate. A semiconductor memory device characterized in that the first impurity region and the second impurity region are electrically connected.

7. In claim 1, The device further comprises a third floating-gate transistor, a fourth floating-gate transistor, a fifth floating-gate transistor, and a sixth floating-gate transistor, and a third erasure element. The gate of the third floating-gate transistor is electrically connected to the gate of the third erasing element. The gate of the fourth floating-gate transistor is electrically connected to the gate of the first erasing element. The gate of the fifth floating-gate transistor is electrically connected to the gate of the second erasing element. The gate of the sixth floating-gate transistor is electrically connected to the gate of the third erasing element. The source of the first floating-gate transistor is electrically connected to the drain of the fifth floating-gate transistor instead of the drain of the memory cell selection transistor. The source of the second floating-gate transistor is electrically connected to the drain of the sixth floating-gate transistor, instead of the drain of the memory cell selection transistor or the drain of the first floating-gate transistor. The source of the third floating-gate transistor is electrically connected to the drain of the fourth floating-gate transistor. The drains of the first floating-gate transistor, the drain of the second floating-gate transistor, and the drain of the third floating-gate transistor are electrically connected to each other. A semiconductor memory device characterized in that the source of the fourth floating-gate transistor, the source of the fifth floating-gate transistor, and the source of the sixth floating-gate transistor are electrically connected to the drain of the memory cell selection transistor.

8. In claim 7, The first erasing element comprises a first erasing gate and a first impurity region formed on the semiconductor substrate. The second erasing element comprises a second erasing gate and a second impurity region formed on the semiconductor substrate. The third erasure element comprises a third erasure gate and a third impurity region formed on the semiconductor substrate. A semiconductor memory device characterized in that the first impurity region, the second impurity region, and the third impurity region are electrically connected.

9. In claim 3, A semiconductor memory device characterized in that the determination current value for determining whether the memory cell is in an on state or an off state exceeds half of the total current value when both the first floating-gate transistor and the second floating-gate transistor are in their initial state.

10. In claim 3, A semiconductor memory device characterized in that the determination current value for determining whether the memory cell is in an on state or an off state is less than half of the total current value when both the first floating-gate transistor and the second floating-gate transistor are in an erase state.

11. In claim 5, A semiconductor memory device characterized in that the determination current value for determining whether the memory cell is in an on state or an off state is smaller than the total current value when both the first floating-gate transistor and the second floating-gate transistor are in their initial state.

12. In claim 5, A semiconductor memory device characterized in that the determination current value for determining whether the memory cell is in an on state or an off state is greater than the total current value when both the first floating-gate transistor and the second floating-gate transistor are in a programmed state.

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