A memory operation method, a memory, and a memory system

Abstract

The application discloses an operating method of a memory, a memory and a memory system. When a reset operation is performed on a target storage unit in a plurality of storage units, a first voltage sequentially increasing in value is applied to a target word line coupled with the target storage unit in a first stage of the reset operation, and a second voltage is applied to a target bit line coupled with the target storage unit, then a second stage of the reset operation is performed after the first stage, a third voltage is applied to the target word line, and a fourth voltage is applied to the target bit line, wherein the voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage, so that the voltage difference between the two ends of the storage unit is greatly reduced in the reset operation, the "surge" current introduced by the voltage mutation is effectively reduced, and the reliability of the memory device is improved.

Description

Technical Field

[0001] This application relates to the field of memory technology, specifically to a memory operation method, a memory, and a memory system. Background Technology

[0002] Phase change memory (PCM) can store information by utilizing the reversible phase transition between amorphous and crystalline states of materials, and has advantages such as high stability, low power consumption, and high storage density.

[0003] During a write-to-zero (Reset) operation on a phase-change memory (PCM), a high-intensity but short-duration electrical pulse is applied to the PCM material. Under Joule heating, once the temperature rises above the material's melting point, a rapid heat release process causes the material to transition directly from a crystalline to an amorphous state. Currently, the Reset operation method for PCM generates a significant inrush current, impacting the reliability of the PCM. Summary of the Invention

[0004] To address the problems of the prior art, this application provides an operation method for a memory, a memory, and a memory system, the technical solution of which is as follows: On one hand, a method for operating a memory is provided, the memory including multiple word lines, multiple bit lines, and multiple memory cells located between the multiple word lines and the multiple bit lines, the method comprising: When performing a reset operation on a target memory cell among the plurality of memory cells, in the first stage of the reset operation, a first voltage with a sequentially increasing voltage value is applied to the target word line coupled to the target memory cell, and a second voltage is applied to the target bit line coupled to the target memory cell. After the first stage, a second stage of the reset operation is performed, in which a third voltage is applied to the target word line and a fourth voltage is applied to the target bit line; the voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage.

[0005] In some embodiments, the method further includes: In the first stage, a first current is applied to the target storage cell; In the second stage, a second current is applied to the target storage cell; Wherein, the first current is greater than the holding current of the target memory cell and less than the second current.

[0006] In some implementations, applying a third voltage to the target word line includes: During the second phase of the reset operation, a third voltage with a different value is applied to the target word line according to the position of the target memory cell relative to the drive circuit of the memory.

[0007] In some embodiments, applying a third voltage with a different value to the target word line based on the position of the target memory cell relative to the driving circuit of the memory includes: If the distance between the target memory cell and the driving circuit is less than or equal to a preset distance threshold, then a third voltage of the first target voltage value is applied to the target word line; If the distance between the target storage cell and the driving circuit is greater than the preset distance threshold, a third voltage of the second target voltage value is applied to the target word line; the first target voltage value is less than the second target voltage value.

[0008] In some implementations, the voltage value of the third voltage is greater than the maximum voltage value among the first voltages.

[0009] In some implementations, the voltage value in the first voltage increases by an equal increment.

[0010] In some implementations, the first voltage and the third voltage are positive voltages, and the second voltage and the fourth voltage are negative voltages.

[0011] In some implementations, the storage unit includes a phase-change storage unit.

[0012] On the other hand, a memory is provided, comprising: multiple word lines, multiple bit lines, multiple memory cells located between the multiple word lines and the multiple bit lines, and a driving circuit coupled to the memory cells; wherein, The driving circuit is configured to perform the memory operation method of any of the foregoing aspects of the embodiments of this application.

[0013] On the other hand, a memory system is provided, including: a memory according to any of the foregoing aspects of the embodiments of this application, and a memory controller coupled to the memory for controlling the memory.

[0014] This application embodiment addresses a memory comprising multiple word lines, multiple bit lines, and multiple memory cells located between the word lines and bit lines. When performing a reset operation on a target memory cell, in the first stage of the reset operation, a first voltage with sequentially increasing voltage values ​​is applied to the target word line coupled to the target memory cell, and a second voltage is applied to the target bit line coupled to the target memory cell. Following this first stage, a second stage of the reset operation is performed, applying a third voltage to the target word line and a fourth voltage to the target bit line. The third voltage is greater than or equal to the first voltage, and the fourth voltage is greater than the second voltage. This significantly reduces the voltage difference across the memory cell during the reset operation, effectively reducing the surge current introduced by voltage fluctuations between the two stages. It also mitigates the damage to the memory cell caused by heat accumulation and thermal crosstalk from multiple reset operations, thereby improving the reliability of the memory device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a Reset waveform provided in one implementation method; Figure 2 This is a cross-sectional view of a phase-change memory provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a memory operation method provided in an embodiment of this application; Figure 4 This is a schematic diagram of a Reset waveform provided in an embodiment of this application; Figure 5 This is a structural block diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0019] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0020] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0021] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0022] Phase-change memory (PCM) is a type of non-volatile memory device. Its core principle is to store data by utilizing the significant resistance difference exhibited by phase-change materials during their reversible transition between crystalline and amorphous states. Specifically, PCM cells typically use phase-change materials such as chalcogenides. Through precisely controlled electrothermal effects, the material is rapidly heated and quenched, allowing it to switch between a crystalline (low resistance) and an amorphous (high resistance) state. Based on this physical mechanism, PCM can encode binary information into two distinct resistance states: the low-resistance crystalline state is typically defined as logic "1," or the "Set" state, while the high-resistance amorphous state is defined as logic "0," or the "Reset" state.

[0023] Phase-change memory (PCM) cells can be in different threshold voltage states depending on the data stored. Specifically, their threshold voltages can be characterized as a first threshold voltage and a second threshold voltage, corresponding to the "Set" and "Reset" states of the PCM cell, respectively. To identify the current resistance state of the PCM cell for data reading, a read voltage is typically applied and compared with the threshold voltage of the PCM cell. The resistance state is then determined based on the comparison result.

[0024] For the write-0 operation (i.e., Reset), a high-intensity but short-duration electrical pulse is applied to the phase change material. Under Joule heating, the temperature of the phase change material rises above the melting temperature, and then it is rapidly cooled, which can realize the transformation of the phase change material from a crystalline to an amorphous state, that is, the transformation from the "1" state to the "0" state. For the write-1 operation (i.e., Set), a long and medium-intensity programming pulse is applied to raise the temperature of the phase change material to below the melting temperature but above the crystallization temperature, and it is held for a period of time to promote the growth of crystal nuclei, thereby realizing the transformation of the phase change material from an amorphous to a crystalline state, that is, the transformation from the "0" state to the "1" state.

[0025] In the reset operation of phase-change memory, a large current pulse is required to Joule heat the phase-change material to achieve its transformation from a crystalline (low resistance) to an amorphous (high resistance) state. Especially during the repeated reset operation, the heat generated by the memory cell will affect the memory cell itself and adjacent cells. The heat accumulation effect on the memory cell can cause the phase-change memory cell to deviate from its device parameters or even fail. The heat generated can diffuse to adjacent cells, causing them to partially crystallize and thus change their resistance. This may even lead to read errors when reading data, which greatly affects the reliability of the device.

[0026] Currently, the reset operation for phase-change memory is typically based on... Figure 1The Reset waveform shown employs a two-stage operation. The first stage selects and activates the memory cell, while the second stage heats the activated cell to write a "0". Specifically, as shown... Figure 1 The diagram shows a Reset waveform provided in one embodiment, where WL represents the voltage curve applied to the word line coupled to the selected phase-change memory cell; BL represents the voltage curve applied to the bit line coupled to the selected phase-change memory cell; and the current curve represents the reset current pulse applied to the selected phase-change memory cell. Figure 1 It is known that during the reset operation of the selected phase-change memory cell, the bit line voltage BL and the reset current remain constant. In the first stage, a relatively low voltage Vphase1 is applied to the word line to turn on the memory cell with a small voltage. Then, in the second stage, a higher voltage Vphase2 is applied to the word line to provide the large current and heat required for the RESET operation.

[0027] However, when the operation switches instantaneously from the first stage to the second stage, a huge voltage jump occurs due to the word line voltage changing from Vphase1 to Vphase2 (voltage difference ΔV = Vphase2 - Vphase1). This voltage jump induces a very large instantaneous current, or "inrush current," at the moment the memory cell is turned on. The magnitude of the inrush current is directly related to the amplitude of the voltage jump (i.e., the voltage difference ΔV); the larger the voltage difference, the higher the peak value of the inrush current. This large transient current not only significantly increases the instantaneous power of the memory cell, generating additional heat and exacerbating the aforementioned heat accumulation and thermal crosstalk problems, but also further affects the lifespan and reliability of the memory device.

[0028] In view of this, embodiments of this application provide an operation method for a memory, the memory including multiple word lines, multiple bit lines, and multiple memory cells located between the multiple word lines and multiple bit lines. When performing a reset operation on a target memory cell among the multiple memory cells, in the first stage of the reset operation, a first voltage with sequentially increasing voltage values ​​is applied to the target word line coupled to the target memory cell, and a second voltage is applied to the target bit line coupled to the target memory cell. Then, after the first stage, the second stage of the reset operation is performed, in which a third voltage is applied to the target word line, and a fourth voltage is applied to the target bit line. The voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage. This greatly reduces the voltage difference across the memory cell during the reset operation, effectively reducing the surge current introduced by voltage change between the two stages, mitigating the damage to the memory cell caused by heat accumulation and thermal crosstalk from multiple RESET operations, and improving the reliability of the memory device.

[0029] The memory in this application embodiment can be a phase-change memory, such as a three-dimensional phase-change memory, in which multiple memory cells are arranged in an array to form a memory array, and these multiple memory cells may include phase-change memory cells. Please refer to... Figure 2 The diagram shown is a cross-sectional view of a phase-change memory provided in an embodiment of this application, as follows: Figure 2 As shown, the phase-change memory 200 may include multiple bit lines 210, a memory array, and multiple word lines 230.

[0030] The multiple bit lines 210 extend along a first direction (e.g., the X direction) and are spaced apart from each other in a second direction (e.g., the Y direction) that intersects the first direction; the multiple word lines 230 extend along the second direction (e.g., the Y direction) and are spaced apart from each other in the first direction (e.g., the X direction). The materials of both the bit lines 210 and the word lines 230 may include metals, conductive metal nitrides, conductive metal oxides, or combinations thereof; for example, both the bit lines 210 and the word lines 230 may be made of tungsten.

[0031] The memory array includes multiple memory cells 220 arranged in an array. Each memory cell 220 is located between multiple bit lines 210 and multiple word lines 230 at their intersection. Voltage can be applied to any memory cell 220 in the memory array through the multiple bit lines 210 and multiple word lines 230 to perform write operations (including write 0 operations and write 1 operations) or read operations on any memory cell 220 in the memory array. Specifically, by selecting one of the multiple word lines 230 and one of the multiple bit lines 210, any memory cell 220 in the memory array can be addressed, and by applying voltage between the selected word line 230 and the selected bit line 210, logical operations can be performed on the corresponding memory cell 230.

[0032] For example, the memory cell 220 may include a phase-change memory cell, which may include at least a phase-change memory layer, a gating layer, and multiple electrode layers stacked in a third direction, wherein the third direction is perpendicular to both the first and second directions, such as the Z direction. For example, refer to... Figure 2 The storage unit 220 may include a bottom electrode layer 221, a gate layer 222, an intermediate electrode layer 223, a phase change storage layer 224 and a top electrode layer 225 stacked sequentially along the Z direction.

[0033] Phase change storage layers can be chalcogenides, such as germanium. antimony Tellurium (Ge Sb Te (GST) or indium antimony Tellurium (In) Sb Te, IST), etc., specifically, for example, the phase change storage layer can be... , , or wait.

[0034] The gating layer can include any appropriate bidirectional threshold switch (OTS), such as , , or When a voltage lower than the threshold voltage of the gating layer is applied, the gating layer can maintain a high-resistance state where almost no current flows; when a voltage higher than its threshold voltage is applied, the gating layer can enter a low-resistance state (also known as a conducting state), allowing current to flow. Furthermore, when the current flowing through the gating layer is less than its holding current, the gating layer can switch to a high-resistance state, where the holding current represents the current required to keep the gating layer in the conducting state.

[0035] Multiple electrode layers can be used as current paths and may include metallic materials such as tungsten, as well as carbon-based materials such as amorphous carbon.

[0036] Please see Figure 3 The diagram illustrates a flowchart of a memory operation method according to an embodiment of this application. Each memory cell can be programmed to a set or reset state. It should be noted that this operation method can be executed by a controller, which can be a memory controller. Figure 3 As shown, the operation method of this memory may include: In step S301, when performing a reset operation on a target memory cell among the plurality of memory cells, in the first stage of the reset operation, a first voltage with sequentially increasing voltage values ​​is applied to the target word line coupled to the target memory cell, and a second voltage is applied to the target bit line coupled to the target memory cell.

[0037] The target storage unit can be at least one of multiple storage units. For ease of explanation, this application embodiment takes the operation performed on a target storage unit as an example. It can be understood that the operation performed on the target storage unit can be two or more operations performed simultaneously on multiple storage units.

[0038] The first stage of the reset operation is used to turn on the selected target memory cell. For phase change memory cells, this first stage can enable the selection layer of the phase change memory cell to enter a low resistance state and turn on.

[0039] Specifically, the first voltage with sequentially increasing voltage values can cause the first voltage to increase step by step. For example, the first voltage can include 3 to 5 voltage steps. If there are 4 voltage steps, they are V1 < V2 < V3 < V4 in sequence, so that surge current can be effectively suppressed without significantly sacrificing speed.

[0040] In practical applications, the number of voltage steps of the first voltage can be a preset fixed value or a dynamically adjustable value. For example, according to the different cumulative numbers of write operations performed on the target storage unit, the starting voltage value V1 and the number of voltage steps of the first voltage can be adjusted to reduce the influence of parameter drift.

[0041] In step S303, after the first stage, a second stage of performing the reset operation is carried out, a third voltage is applied to the target word line, and a fourth voltage is applied to the target bit line; the voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage.

[0042] Among them, the second stage of the reset operation is used to heat the target storage unit to achieve the writing of logic "0". For a phase change memory cell, through this second stage, the phase change memory layer can be changed from a crystalline state to an amorphous state.

[0043] In the technical solution of the embodiment of the present application, in the first stage of the reset operation, a relatively low second voltage is applied to the target bit line, and at the same time, the first voltage on the target word line is gradually increased, so that the voltage difference across the target storage unit is gradually established by the small-step increase of the first voltage, and the voltage mutation of each step is very small, so the generated surge current is extremely small; after the target storage unit is fully turned on, by applying a relatively high fourth voltage to the target bit line in the second stage of the reset operation and cooperating with the third voltage applied to the target word line, the maximum working voltage difference required to complete the Reset is formed to provide the final Reset energy, making the entire voltage difference establishment process smoother, maximizing the suppression of the peak value and duration of the surge current, and improving the reliability of the storage device.

[0044] In some embodiments, the voltage values in the first voltage applied to the target word line can increase in equal amplitude, so that the voltage change across the target storage unit is uniform and predictable. This not only helps to simplify the design of the voltage generation circuit and the control logic, but also the uniform voltage steps make the process of each storage unit entering the conduction state more consistent, contributing to reducing the performance fluctuations between different storage units and between different reset operations, and improving the operation reliability and durability of the storage device.

[0045] It can be understood that in other embodiments, the voltage values in the first voltage applied to the target word line may also increase non-uniformly, such as increasing or decreasing in increasing amplitude, to adapt to the response characteristics of different memory devices.

[0046] In practical applications, the duration corresponding to each voltage value in the first voltage may be the same or different. For example, the duration corresponding to a higher voltage value may be shorter to optimize energy consumption and speed.

[0047] In some embodiments, the third voltage applied to the target word line in the second stage of the reset operation is greater than the maximum voltage value in the first voltage applied to the target word line in the first stage, so that after the target memory cell is fully turned on, the thermal energy required for Reset can be generated in a short time, making the reset operation more efficient.

[0048] In some embodiments, the first voltage and the third voltage applied to the target word line are positive voltages, and the second voltage and the fourth voltage applied to the target bit line are negative voltages, so that the operation window and anti-interference ability of the memory device are significantly improved through the reverse bias mode during the reset operation.

[0049] To facilitate understanding of the technical solutions of the embodiments of the present application, the following Figure 4 exemplarily describes the operation method of the memory according to the embodiments of the present application.

[0050] Refer to Figure 4 , the reset operation of the target memory cell includes a first stage phase1 and a second stage phase2. The phase1 stage is used to turn on the target memory cell, and the phase2 stage is used to write "0" to achieve the final Reset operation. Among them, WL in the voltage curve represents the voltage curve applied to the target word line coupled to the target memory cell; BL represents the voltage curve applied to the target bit line coupled to the target memory cell.

[0051] As Figure 4 shown, in the first stage phase1 of this reset operation: first apply a lower second voltage Va to the target bit line, and then gradually increase the voltage value of the first voltage applied to the target word line, so that the voltage value of the first voltage rises step by step, that is, V1<V2<V3<V4, so that the pressure difference ( - ) between the two ends of the target memory cell gradually increases, and the target memory cell is turned on. After this first stage phase1, the second stage phase2 of this reset operation is executed: apply a higher fourth voltage Vb (Vb>Va) to the target bit line, and apply a higher third voltage V5 (V5>V4) to the target word line, so as to provide sufficient Reset energy for writing "0".

[0052] It can be seen that in the above reset operation, when the first voltage increases to V1, the target memory cells with low threshold voltages will conduct. Subsequently, the first voltage is switched to V2, and the voltage difference in this switching process is V2 - V1. Then, the first voltage gradually increases to V3, V4, and V5. In this process, the voltage differences across the target memory cells are V2 - V1, V3 - V2, V4 - V3, and V5 - V4 respectively, which are obviously much smaller than the voltage difference V5 - V1 when directly switching from V1 to V5. Thus, it can effectively reduce the "surge" current introduced by the voltage mutation across the memory cells, mitigate the thermal accumulation and thermal crosstalk generated by multiple Reset operations on the memory cells, and improve the reliability of the memory device.

[0053] It can be understood that Figure 4 the four voltage steps of V1 < V2 < V3 < V4 included in the above-mentioned first voltage are only examples and do not constitute specific limitations to this application.

[0054] In some embodiments, in order to further reduce the "surge" current introduced by voltage mutation between two stages, before the reset operation switches from its first stage to the second stage, a fourth voltage can be applied to the target bit line first, and when the reset operation switches to the second stage, a third voltage is applied to the target sub-line. That is to say, the duration of the second voltage applied to the target bit line in the first stage of the reset operation can be slightly less than the overall duration of this first stage, and there can be a time difference between them , and the duration of the fourth voltage applied to the target bit line in the second stage of the reset operation can be the sum of this time difference and the overall duration of this second stage. As Figure 4 shown in [reference], the time point of applying Vb to the target bit line is before entering phase2 and close to phase2. When entering phase2, a third voltage with a voltage value of V5 is applied to the target word line.

[0055] In some embodiments, during the process of performing a reset operation on the target memory cell, a reset current pulse with a fixed current value can also be applied to the target memory cell.

[0056] In other embodiments, in order to further reduce the influence of the surge current, the method can further include: applying a first current to the target memory cell in the first stage of the reset operation; applying a second current to the target memory cell in the second stage of the reset operation; wherein, the first current is greater than the holding current of the target memory cell and less than the second current.

[0057] Here, the holding current of the target memory cell represents the minimum current required to maintain its conduction. In specific implementations, the first current can be slightly larger than the holding current of the target memory cell, for example, the first current is 1.2 to 2 times the holding current, to maintain conduction; while the second current is a typical reset operation current, such as 5 times the first current. See also... Figure 4 The current curves represent the reset current pulses applied to the target memory cell. Ireset1 indicates that a first current is applied to the target memory cell in the first phase 1 of the reset operation, and Ireset2 indicates that a second current is applied to the target memory cell in the second phase 2 of the reset operation.

[0058] Considering that the duration of the surge current generated at the moment the memory cell is turned on is related to the current in the first stage of the reset operation, the smaller the current in the first stage and the shorter the duration, the smaller the impact of the surge current. Therefore, controlling the first current applied to the target memory cell in the first stage to be slightly greater than the holding current of the target memory cell can reduce the duration of the surge current and further improve the reliability of the memory device.

[0059] In specific implementation, in order to achieve precise current control, a current mirror can be integrated on the target bit line. The current mirror is used to control the application of a first current to the target memory cell in the first stage of the reset operation and a second current to the target memory cell in the first stage of the reset operation. The first current is greater than the holding current of the target memory cell and less than the second current.

[0060] In some implementations, to further reduce the surge current introduced by voltage fluctuations between the two stages, the timing of applying the second current to the target memory cell may be later than the start time of the second stage of the reset operation, and a time difference may exist between the two. In other words, the duration of the first current applied to the target memory cell can be greater than the overall duration of the first phase of the reset operation, where the overall duration of the first phase is equal to the duration of the second phase. The sum of the duration of the first current applied to the target memory cell is equal to the total duration of the second stage. The difference. For example... Figure 4 As shown, the second current Ireset2 is applied to the target memory cell after entering phase 2 and close to phase 2, and the first current Ireset1 is applied continuously before that.

[0061] Considering that in the actual physical layout of a memory array, the spatial distance between different memory cells and driving circuits (such as word line driving circuits) leads to significant differences in the parasitic resistance of their interconnect lines, this mismatch in line resistance directly affects the effective voltage actually applied to both ends of the memory cell during the reset operation, resulting in differences in the energy requirements for writing "0" to memory cells at different locations in the memory array. Specifically, distant memory cells require a higher third voltage to obtain sufficient reset energy to ensure they are fully reset due to the larger line voltage drop; however, if this high voltage is uniformly applied to near-end memory cells, it will generate excessively high operating energy due to overdrive, which not only easily causes write disturbances but also accelerates device aging, leading to a decrease in reliability. Therefore, in some embodiments, the operation method of this application, when applying a third voltage to the target word line, may include: during the second stage of performing the reset operation, applying a third voltage with different values ​​to the target word line according to the position of the target memory cell relative to the driving circuit of the memory. By applying a third voltage with a different value to the target word line based on the position of the target memory cell relative to the driving circuit in the second stage of the reset operation, precise energy control of memory cells in different regions can be achieved. This ensures the success rate of the reset operation while effectively avoiding the reliability risks caused by overvoltage, and further improves the reliability of the memory device.

[0062] In some specific embodiments, applying a third voltage with a different voltage value to the target word line according to the position of the target memory cell relative to the driving circuit of the memory includes: if the distance between the target memory cell and the driving circuit is less than or equal to a preset distance threshold, then applying a third voltage with a first target voltage value to the target word line; if the distance between the target memory cell and the driving circuit is greater than the preset distance threshold, then applying a third voltage with a second target voltage value to the target word line; wherein the first target voltage value is less than the second target voltage value.

[0063] Specifically, the preset distance threshold can be a preset row and column address, which can be configured during the testing phase. For example, during the testing phase, the Reset success rate of different row and column address units can be measured to find the voltage inflection point required for the success rate to exceed the success rate threshold (such as 99.9%), and then the row and column address can be set as the threshold.

[0064] The first target voltage value can be set as the minimum voltage value that ensures the near-end memory cell can still complete a 100% reset, even considering its small line voltage drop, in order to minimize overstress on the near-end memory cell. The second target voltage value is greater than the first target voltage value. Specifically, the second target voltage value can be the first target voltage value plus a line voltage drop compensation value. The voltage drop compensation value of this line It can be obtained from simulation or test data of the farthest storage unit.

[0065] In specific implementation, when a reset operation needs to be performed on the target memory cell, the row and column address of the target memory cell can be compared with a preset row and column address to determine whether the target memory cell is located in the near-end region close to the driving circuit or in the far-end region far from the driving circuit. If the comparison result indicates that it is in the near-end region, it is determined that a third voltage of the first target voltage value needs to be applied to the target word line during the second stage of the reset operation; conversely, if the comparison result indicates that it is in the far-end region, it is determined that a third voltage of the second target voltage value needs to be applied to the target word line during the second stage of the reset operation.

[0066] Understandably, in practical applications, two or more different preset distance thresholds can be set, thus forming N(N) The third voltage can include multiple different target voltage values, each corresponding to one of the N preset distance ranges. Therefore, when applying different third voltage values ​​to the target word line based on the position of the target memory cell relative to the drive circuit of the memory, the target preset distance range into which the distance between the target memory cell and the drive circuit falls can be determined. The target voltage value corresponding to this target preset distance range is then applied to the target word line. This improves the reliability of the memory device and enables more precise control of memory cells in different areas.

[0067] Based on a concept similar to the above-described memory operation method, this application embodiment also provides a memory, including: multiple word lines, multiple bit lines, multiple memory cells located between the multiple word lines and the multiple bit lines, and a driving circuit coupled to the memory cells; wherein, the driving circuit is configured to execute any one of the memory operation methods in the embodiments of this application.

[0068] For example, the memory in the embodiments of this application may include a phase change memory, such as a three-dimensional phase change memory.

[0069] Based on a similar inventive concept, embodiments of this application also provide a memory system, such as... Figure 5 The diagram shown is a block diagram of a memory system provided in an embodiment of this application. The memory system 500 includes any type of memory 510 in the embodiments of this application; and a memory controller 520 coupled to the memory 510 for controlling the memory 510.

[0070] The memory system 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The memory system 500 may include one or more memories 510.

[0071] Memory controller 520 is coupled to memory 510 and configured to control memory 510. In some examples, memory controller 520 is also coupled to a host, which may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), such as an application processor (AP). Memory controller 520 can provide an interface with memory 510 to manage data stored in memory 510 and can communicate with the host via at least one of various interface protocols, such as USB, MMC, PCIe, Serial ATA, Parallel ATA, and SCSI. Memory controller 520 can be implemented as a standalone chip or integrated with memory 510. Memory controller 520 can be implemented on a motherboard and can be implemented as an integrated memory controller (IMC) within a microprocessor.

[0072] The memory controller 520 can be configured to control the operation of the memory 510, such as read, erase, and program operations. The memory controller 520 can also be configured to manage various functions related to data stored or to be stored in the memory 510, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some examples, the memory controller 520 is also configured to handle error correction codes (ECCs) related to data read from or written to the memory 510.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0074] The above provides a detailed description of the operation method, memory, and memory system of a memory provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for operating a memory, characterized in that, The memory includes multiple word lines, multiple bit lines, and multiple memory cells located between the multiple word lines and the multiple bit lines. The method includes: When performing a reset operation on a target memory cell among the plurality of memory cells, in the first stage of the reset operation, a first voltage with a sequentially increasing voltage value is applied to the target word line coupled to the target memory cell, and a second voltage is applied to the target bit line coupled to the target memory cell. After the first stage, a second stage of the reset operation is performed, in which a third voltage is applied to the target word line and a fourth voltage is applied to the target bit line; the voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage.

2. The method according to claim 1, characterized in that, The method further includes: In the first stage, a first current is applied to the target storage cell; In the second stage, a second current is applied to the target storage cell; Wherein, the first current is greater than the holding current of the target memory cell and less than the second current.

3. The method according to claim 1, characterized in that, Applying a third voltage to the target word line includes: During the second phase of the reset operation, a third voltage with a different value is applied to the target word line according to the position of the target memory cell relative to the drive circuit of the memory.

4. The method according to claim 3, characterized in that, Applying a third voltage with a different value to the target word line based on the position of the target memory cell relative to the driving circuit of the memory includes: If the distance between the target memory cell and the driving circuit is less than or equal to a preset distance threshold, then a third voltage of the first target voltage value is applied to the target word line; If the distance between the target storage cell and the driving circuit is greater than the preset distance threshold, a third voltage of the second target voltage value is applied to the target word line; the first target voltage value is less than the second target voltage value.

5. The method according to claim 1, characterized in that, The voltage value of the third voltage is greater than the maximum voltage value among the first voltages.

6. The method according to claim 1, characterized in that, The voltage value in the first voltage increases by an equal increment.

7. The method according to claim 1, characterized in that, The first voltage and the third voltage are positive voltages, and the second voltage and the fourth voltage are negative voltages.

8. The method according to any one of claims 1 to 6, characterized in that, The storage unit includes a phase-change storage unit.

9. A memory, characterized in that, include: Multiple word lines, multiple bit lines, multiple memory cells located between the multiple word lines and the multiple bit lines, and driving circuitry coupled to the memory cells; wherein, The driving circuit is configured to perform the memory operation method as described in any one of claims 1 to 8.

10. A memory system, characterized in that, include: The memory as described in claim 9; And a memory controller coupled to the memory for controlling the memory.

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