Memory system

Abstract

This provides a memory system that suppresses the increase in latency. [Solution] The memory system 1 comprises a memory cell array, peripheral circuits for controlling the memory cell array, and a memory controller including a main memory. The main memory includes a first memory area, which is the unit of access by the memory controller. The memory controller classifies the multiple word lines provided by the memory cell array into word line groups, stores first information including the program status of the non-volatile memory cell group connected to the first word line group including the first word line, and a first candidate value in the first memory area, decides whether or not to execute a first read operation according to the first information, and if it decides to execute, sends a first read command to the peripheral circuit. In response to receiving the first read command, the peripheral circuit performs a sense operation using the first candidate value from the first non-volatile memory cell connected to the first word line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] A memory system including a non-volatile memory such as a NAND flash memory and a memory controller that controls the non-volatile memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a memory system capable of suppressing an increase in latency.

Means for Solving the Problems

[0005] According to one embodiment, the memory system comprises a memory cell array, peripheral circuits, main memory, and a memory controller. The peripheral circuits control the memory cell array. The memory controller is electrically connected to the peripheral circuits. The main memory is included in or electrically connected to the memory controller. The memory cell array comprises a plurality of word lines and a plurality of non-volatile memory cells connected to the plurality of word lines. The main memory includes a first memory area, which is the unit of access by the memory controller. The memory controller classifies the plurality of word lines into at least one word line group. The first word line group of the at least one word line group includes a first word line from the plurality of word lines. The plurality of non-volatile memory cells include a first non-volatile memory cell group connected to the first word line group. The first word line is connected to a first non-volatile memory cell from the first non-volatile memory cell group. The memory controller stores first information, including the program status of the first non-volatile memory cell group, and first candidate values ​​in a first memory area. The memory controller determines whether or not to perform a first read operation according to the first information. Upon deciding to perform a first read operation, the memory controller sends a first read command to the peripheral circuit instructing it to perform a sense operation using the first candidate value. Upon receiving the first read command from the memory controller, the peripheral circuit performs a sense operation from the first non-volatile memory cell using the first candidate value. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the configuration of the memory system according to the first embodiment. [Figure 2] Figure 2 shows the circuit configuration of the block according to the first embodiment. [Figure 3] Figure 3 shows the threshold voltage distribution of the memory cell transistor MT according to the first embodiment. [Figure 4] Figure 4 shows an example of the classification of word line groups according to the first embodiment. [Figure 5]Figure 5 shows a word line group assignment table according to the first embodiment. [Figure 6] Figure 6 shows a shift table according to the first embodiment. [Figure 7] Figure 7 shows a history value table according to the first embodiment. [Figure 8] Figure 8 is a flowchart showing an example of a read sequence according to the first embodiment. [Figure 9] Figure 9 is a flowchart showing an example of the end word line determination operation according to the first embodiment. [Figure 10] Figure 10 is a flowchart showing an example of the history value read operation according to the first embodiment. [Figure 11] Figure 11 is a flowchart showing an example of the learning lead operation according to the first embodiment. [Figure 12] Figure 12 is a flowchart showing an example of the light processing according to the first embodiment. [Figure 13] Figure 13 shows a history value table according to the second embodiment. [Figure 14] Figure 14 shows an example of the transition of the number of unprogrammed word lines according to the second embodiment. [Figure 15] Figure 15 is a flowchart showing an example of the end word line determination operation according to the second embodiment. [Figure 16] Figure 16 is a flowchart showing an example of the light processing according to the second embodiment. [Figure 17] Figure 17 shows a history value table according to the third embodiment. [Figure 18] Figure 18 shows an example of the transition in the number of unprogrammed cell units according to the third embodiment. [Figure 19] Figure 19 is a flowchart showing an example of a read sequence according to the third embodiment. [Figure 20] Figure 20 is a flowchart showing an example of the end word line determination operation according to the third embodiment. [Figure 21] Figure 21 is a flowchart showing an example of the light processing according to the third embodiment.

Best Mode for Carrying Out the Invention

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant descriptions may be omitted. The description of one embodiment applies to the description of another embodiment as well, unless explicitly or implicitly excluded.

[0008] Note that the sizes of the figures in the drawings or the size relationships between the figures do not indicate the sizes or size relationships of the configurations and data shown by those figures.

[0009] Each functional block can be realized as either hardware, computer software, or a combination of both. For this reason, it is generally described from the perspective of those functions so that it is clear that each functional block is any of these. Also, it is not essential that the functional blocks be distinguished as in the following examples. For example, some functions may be executed by a functional block different from the exemplified functional block. Further, the exemplified functional block may be divided into finer functional sub-blocks.

[0010] Also, any step in the flow of the method of the embodiment is not limited to the exemplified order, and can be executed in an order different from the exemplified order and / or in parallel with another step, unless otherwise indicated.

[0011] 1. First Embodiment A memory system according to the first embodiment will be described below. In the following description, NAND flash memory as a non-volatile memory and a memory system equipped with said NAND flash memory will be used as examples, but the invention is not limited to these. That is, it is also possible to use a memory other than NAND flash memory, such as ReRAM (Resistance Random Access Memory) or FeRAM (Ferroelectric Random Access Memory), as the non-volatile memory. Furthermore, it is not essential that the non-volatile memory is a semiconductor memory, and this embodiment can be applied to various storage media other than semiconductor memory.

[0012] 1.1 Memory System Configuration First, an overview of the configuration of the memory system according to this embodiment will be described with reference to Figure 1.

[0013] As shown in Figure 1, the memory system 1 comprises a non-volatile memory (NAND flash memory) 100 and a memory controller 200. The memory system 1 may be composed of multiple semiconductor chips. The NAND flash memory 100 and the memory controller 200 may be combined to form a single memory system 1, for example. Examples include UFS (Universal Flash Storage) devices and SD TM Examples include memory cards, SSDs (Solid State Drives), and eMMCs (embedded Multi Media Cards).

[0014] The NAND flash memory 100 has multiple memory cells (hereinafter also referred to as memory cell transistors MT) and stores data nonvolatilously. The NAND flash memory 100 may have a structure in which, for example, a memory chip MC and a CMOS chip CC are bonded together.

[0015] The memory controller 200 is connected to the NAND flash memory 100 by a NAND bus and to the host 300 by a host bus. The memory controller 200 controls the NAND flash memory 100. The memory controller 200 also accesses the NAND flash memory 100 in response to requests received from the host 300.

[0016] Host 300 can be, for example, a mobile phone, tablet, personal computer, server, or automobile. Host 300 can be, for example, an SD card. TM Interfaces: SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), PCIe TM (PCI Express TM (Peripheral Component Interconnect express), or NVMe TM (NVM Express TM It conforms to (Non-Volatile Memory express)).

[0017] The NAND bus transmits and receives signals according to the NAND interface. Signals transmitted and received by the NAND bus include commands (CMD), addresses (ADD), and data (DAT), such as write data and read data.

[0018] 1.2 Memory Controller Configuration Next, the configuration of the memory controller 200 will be described. Note that each function of the memory controller 200 may be implemented by a dedicated circuit, or it may be implemented by the processor 260 executing firmware. Furthermore, some of the components of the memory controller 200 may be located outside the memory controller 200, provided they are electrically connected to at least one of the other components of the memory controller 200.

[0019] The memory controller 200 is, for example, a System-on-a-Chip (SoC). The memory controller 200 may be composed of multiple semiconductor chips. The memory controller 200 includes a host interface circuit (host I / F) 210, a NAND interface circuit (NAND I / F) 220, main memory 230, buffer memory 240, an ECC (Error Checking and Correction) circuit 250, and a processor 260.

[0020] The host interface circuit 210 is connected to the host 300 via the host bus. The host interface circuit 210 forwards requests and data received from the host 300 to the processor 260 and the buffer memory 240, respectively. The host interface circuit 210 also forwards data in the buffer memory 240 to the host 300 in response to instructions from the processor 260.

[0021] The NAND interface circuit 220 is connected to the NAND flash memory 100 via the NAND bus and is responsible for communication with the NAND flash memory 100. Based on instructions received from the processor 260, the NAND interface circuit 220 outputs signals to the NAND flash memory 100. During write operations, the NAND interface circuit 220 transfers the program command and program target address issued by the processor 260, as well as the write data in the buffer memory 240, to the NAND flash memory 100. During read operations, the NAND interface circuit 220 transfers the sense command and sense target address issued by the processor 260 to the NAND flash memory 100. Furthermore, the NAND interface circuit 220 receives read data from the NAND flash memory 100 and transfers it to the buffer memory 240.

[0022] The main memory 230 is, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). The main memory 230 temporarily stores, for example, firmware for managing the NAND flash memory 100, as well as the address table AT, word line group assignment table WT, shift table ST, and history value table HT. The address table AT is a table for managing the storage address (logical address) of data specified by the host 300 and the corresponding location (physical address) in the NAND flash memory 100. Details of the word line group assignment table WT, shift table ST, and history value table HT will be described later.

[0023] Buffer memory 240 is, for example, DRAM. Buffer memory 240 temporarily stores write data and read data.

[0024] The ECC circuit 250 performs error correction coding or error correction decoding on the data. These are processes necessary for error detection and correction. Specifically, in the write process, the ECC circuit 250 performs error correction coding on the data written to the NAND flash memory 100. In the error correction coding process, data containing error correction information is generated from the write data based on the error correction code generation method. In the read process, the ECC circuit 250 performs error correction decoding on the data read from the NAND flash memory 100. In the error correction decoding process, the ECC circuit 250 detects errors in the read data and attempts to correct errors if they are present.

[0025] The processor 260 controls the overall operation of the memory controller 200. The processor 260 is, for example, a CPU (Central Processing Unit). The processor 260 performs various processes, for example, by executing firmware.

[0026] The processor 260 includes a cache memory 270. The cache memory 270 is, for example, SRAM. Access to the cache memory 270 by the processor 260 is faster than access to the main memory 230, and the processor 260 uses the cache memory 270 as a workspace. For example, the processor 260 transfers at least a portion of various tables stored in the main memory 230 to the cache memory 270 and uses them to execute various processes. Hereinafter, the transfer of data stored in the main memory 230 by the processor 260 to the cache memory 270 may simply be described as "the processor 260 retrieves the data."

[0027] The cache memory 270 includes multiple cache lines. Each cache line is a memory area capable of storing a predetermined number of bits (e.g., 512 bits) of data. Hereafter, the size of the data that can be stored in a single cache line may be referred to as the cache line size.

[0028] The processor 260 accesses the main memory 230 in units of a memory area the size of a cache line, and retrieves data from the main memory 230 by storing the data stored in that memory area in a cache line. In this case, for example, if multiple data items are stored in that memory area of ​​the main memory 230, the processor 260 can retrieve all of those multiple data items in a single access.

[0029] The cache memory 270 may be located outside the processor 260.

[0030] The processor 260 functions as a write control unit 262, a read control unit 264, and an erase control unit 266. The processor 260 functions as each of these units, for example, by executing firmware.

[0031] The write control unit 262 performs processing to write data to the NAND flash memory 100 based on a write request received from the host 300. Specifically, when the write control unit 262 receives a write request, it determines the location in the NAND flash memory 100 where the write data will be stored (the program target address). The program target address includes, for example, the block address and the page address. The write control unit 262 instructs the NAND flash memory 100 to execute a program operation for the write data at the program target address via the NAND interface circuit 220. The write control unit 262 also updates the address table AT stored in the main memory 230. Specifically, the write control unit 262 updates the address table AT so that, for example, the logical address that received the write request (the write request address) is associated with the physical address where the write data is stored (the program target address).

[0032] The read control unit 264 performs processing to read data from the NAND flash memory 100 based on a read request received from the host 300. Specifically, when the read control unit 264 receives a read request, it refers to the address table AT and determines the physical address (sense target address) corresponding to the logical address (read request address) that received the read request. The sense target address includes, for example, block addresses and page addresses. The read control unit 264 also determines the read method to be executed in the read process. In the read process, the read control unit 264 instructs the NAND flash memory 100 to perform a sense operation from the sense target address via the NAND interface circuit 220. Details of the read method will be described later. Note that the series of processes performed by the memory system 1 after receiving a read request from the host 300 is sometimes called a read sequence.

[0033] The erase control unit 266 performs processing to erase data in the NAND flash memory 100 based on a request received, for example, from the host 300. Specifically, when the erase control unit 266 receives a request to erase data, for example, it refers to the address table AT to determine the location in the NAND flash memory 100 that is subject to the erasure process (the address to be erased). The erase control unit 266 then instructs the NAND flash memory 100 to perform a data erasure operation for the address to be erased.

[0034] Furthermore, the write, read, and erase requests mentioned above are not limited to requests originating from host 300. In other words, these requests also include write, read, and erase requests that arise in connection with the execution of processes such as garbage collection, refresh, and patrol reads.

[0035] 1.3 Configuration of NAND flash memory Next, the configuration of the NAND flash memory 100 will be described. As shown in Figure 1, the NAND flash memory 100 includes a memory cell array 110 and peripheral circuits 120.

[0036] The memory cell array 110 stores data provided by the memory controller 200. The memory cell array 110 comprises multiple block BLKs, each containing multiple non-volatile memory cells associated with rows and columns. Data stored in the memory cell array 110 is erased on a block BLK basis. Figure 1 shows four block BLKs, BLK0 to BLK3, as an example. The target block BLK for each operation is specified by the block address included in the address ADD received from the memory controller 200.

[0037] The peripheral circuit 120 performs a program operation to write data to the memory cell array 110 based on a program command received from the memory controller 200. The peripheral circuit 120 also performs a data sensing operation from the memory cell array 110 based on a sense command from the memory controller 200, and transfers the sensed data to the memory controller 200 as read data.

[0038] Next, the circuit configuration of the block blackboard will be explained with reference to Figure 2. Figure 2 is a circuit diagram of one of the block blackboards.

[0039] As shown in Figure 2, block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU contains multiple NAND strings NS.

[0040] Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. Each memory cell transistor MT comprises a control gate and a charge storage layer, and stores data nonvolatilically. Each memory cell transistor MT is connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. Each memory cell transistor MT can store two or more bits of data.

[0041] The gates of the selection transistors ST1 included in each of the multiple NAND strings NS of string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors ST2 included in each of the multiple NAND strings NS of string units SU0 to SU3 are connected in common to, for example, the select gate line SGS. Alternatively, the gates of the selection transistors ST2 included in each of the multiple NAND strings NS of string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 (not shown) for each string unit. Furthermore, the control gates of the memory cell transistors MT0 to MT7 included in multiple NAND strings NS within the same block BLK are connected in common to word lines WL0 to WL7, respectively.

[0042] Furthermore, within the memory cell array 110, the drains of the selection transistors ST1 of NAND strings NS located in the same row within multiple block BLKs are commonly connected to the bit line BL (BL0 to BLm, where m is a natural number greater than or equal to 1). In other words, the bit line BL commonly connects NAND strings NS located in the same row across multiple block BLKs. In addition, the sources of multiple selection transistors ST2 are commonly connected to the source line SL.

[0043] A set of multiple memory cell transistors MT that are contained within the same string unit SU and connected to the same word line WL is called, for example, a cell unit CU. A cell unit CU contains N pages, which are storage areas, corresponding to the number of bits N of cell data stored by each memory cell transistor MT. For example, one page stores a set of 1-bit data at the same bit position in the cell data stored by each memory cell transistor MT in the cell unit CU. Hereinafter, the storage capacity of one page will be referred to as the page size.

[0044] In the data programming operation to the memory cell array 110, for example, the data stored in each of the N pages contained in the cell unit CU is programmed into the cell unit CU at once. The data sensing operation from the memory cell array 110 is performed page by page. The page to be programmed is specified by the program target address received from the memory controller 200. Hereinafter, the page specified as the target page for programming may be referred to as the program target page. Similarly, the page to be sensed is specified by the sense target address received from the memory controller 200. Hereinafter, the page specified as the target page for sensed operation may be referred to as the sense target page.

[0045] The memory controller 200 may classify the word lines WL included in the memory cell array 110 into at least one group of word lines WL (hereinafter referred to as word line group WLG), and perform various processing or data management on a unit basis for each word line group WLG.

[0046] The NAND flash memory 100 may have a circuit configuration other than those described above. For example, the number of block BLKs in the NAND flash memory 100, the number of string units SU included in the block BLKs, and the number of memory cell transistors MT and selection transistors ST1 and ST2 included in the NAND strings NS can be designed to any number. Furthermore, the NAND flash memory 100 may have a three-dimensional NAND structure.

[0047] 1.4 Threshold voltage distribution of memory cell transistors MT Next, the threshold voltage distribution of the memory cell transistor MT will be explained using Figure 3. Figure 3 shows the threshold voltage distribution of the memory cell transistor MT according to this embodiment. Figure 3(a) is a diagram showing an example of a bit assignment table set for a memory cell transistor MT using the TLC (Triple Level Cell) method. The TLC method is a method in which 3 bits of data are stored in one memory cell transistor MT. Figure 3(b) is a diagram showing an example of the threshold voltage distribution and word line voltage of the memory cell transistor MT when a program is performed using the bit assignment shown in Figure 3(a). In the threshold distribution shown in Figure 3(b), the vertical axis corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT.

[0048] As shown in Figure 3(b), in the TLC method, multiple memory cell transistors MT are programmed to form eight threshold voltage distributions. Each state of the threshold voltage distribution (Er state to G state in Figure 3(b)) is assigned data as shown in Figure 3(a). Specifically, in the example in Figure 3, 111 is assigned to the Er state, 110 to the A state, 100 to the B state, 000 to the C state, 010 to the D state, 011 to the E state, 001 to the F state, and 101 to the G state.

[0049] In the following, the most significant bit of the data stored in the memory cell transistor MT using the TLC method is called the upper bit. The page in the cell unit CU where the upper bit set is stored is called the upper page. The second most significant bit of the data stored in the memory cell transistor MT using the TLC method is called the middle bit, and the page where the middle bit set is stored is called the middle page. The least significant bit of the data stored in the memory cell transistor MT using the TLC method is called the lower bit, and the page where the lower bit set is stored is called the lower page.

[0050] Between adjacent threshold voltage distributions, a word line voltage is set for use in each sense operation. Specifically, for example, between the Er state and the A state, a word line voltage VA is set to determine whether the threshold voltage of the memory cell transistor MT is included in the Er state or in the A state or higher. Hereinafter, the sense operation for determining whether the threshold voltage of the memory cell transistor MT is included in the Er state or in the A state or higher is referred to as A-state sense SenA. In A-state sense SenA, the word line voltage VA is used. Similarly, a word line voltage VB is set between the A state and the B state and is used in B-state sense SenB. Also, a word line voltage VC is set between the B state and the C state and is used in C-state sense SenC. Furthermore, a word line voltage VD is set between the C state and the D state and is used in D-state sense SenD. Also, a word line voltage VE is set between the D state and the E state and is used in E-state sense SenE. Furthermore, a word line voltage VF is set between the E state and the F state and is used in F-state sense SenF. Furthermore, a word line voltage VG is set between the F state and the G state and is used in the G state sense SenG. The sense path voltage Vpass is set to a voltage value higher than the maximum threshold voltage in the highest threshold voltage distribution (e.g., the G state). The memory cell transistor MT connected to the word line WL to which the sense path voltage Vpass is applied turns ON regardless of the programmed data.

[0051] In sense operation, the peripheral circuit 120 applies a selected word line voltage Vsel to the word line WL corresponding to the sense target address (hereinafter referred to as the selected word line SelWL) in order to determine the state to which each memory cell transistor MT constituting the sense target page belongs. Here, as shown in Figure 3(c), in sense operation, a set of word line voltages composed of different word line voltages is used as the selected word line voltage Vsel, depending on the page type of the sense target page. Specifically, for example, in upper page sense operation, a set of word line voltages composed of word line voltage VC and word line voltage VG is used as the selected word line voltage Vsel to determine the upper bit of the data stored in the memory cell transistor MT. In middle page sense operation, a set of word line voltages composed of word line voltage VB, word line voltage VD, and word line voltage VF is used to determine the middle bit of the data stored in the memory cell transistor MT. Furthermore, in lower page sense operation, a set of word line voltages composed of word line voltage VA and word line voltage VE is used to determine the lower bit of the data stored in the memory cell transistor MT.

[0052] Furthermore, the word line WL corresponding to the program target address in program operation may also be referred to as the selected word line SelWL.

[0053] 1.5 About the Lead Method Next, the read method implemented in the memory system according to this embodiment will be described.

[0054] As described above, each state from Er state to G state can be distinguished by a sense operation using word line voltages VA to VG. However, if the threshold voltage distribution of the memory cell transistor MT changes due to factors such as the passage of time, temperature, and read disturbance after data programming, the data may not be sensed correctly under fixed sense conditions (e.g., the voltage value of the word line voltage).

[0055] To address such situations, the memory controller 200 is configured to execute several read methods involving changes in sense conditions. Specifically, a change in sense conditions is, for example, a shift in the word line voltage. The memory controller 200 can execute, for example, a learning read and a history value read as read methods involving a shift in word line voltage. However, the read methods that the memory controller 200 can execute are not limited to these. In this embodiment, changing the word line voltage is referred to as shifting the word line voltage. The shifted voltage amount is referred to as the shift amount. Furthermore, below, a read process based on a learning read may simply be referred to as a learning read. Similarly, a read process based on a history value read may simply be referred to as a history value read.

[0056] The learning read is a read method that reads data while learning the word line voltage that successfully reads the data. "Successful read processing" means that the data that is correctly sensed during the read processing is acquired as read data. Furthermore, "successful read processing" also includes the restoration of the original data by performing error correction decoding processing on the read data by the ECC circuit 250. In learning read processing, the memory controller 200 performs one or more reads using the word line voltage shifted as the selected word line voltage Vsel, for example, and learns the amount of word line voltage shift when the data read is successful as a history value for the selected word line SelWL. The history value becomes a candidate for the amount of word line voltage shift applied to the selected word line SelWL in subsequent sense operations. The learned history value is stored in association with the selected word line SelWL in the history value table HT.

[0057] In this embodiment, the case in which the memory controller 200 performs a learning read using a shift table ST as the learning read will be explained as an example. The shift table ST is a table for managing sets of information that represent the amount of shift of the word line voltage used in the sense operation.

[0058] The history value read is a read method that uses a word line voltage shifted based on the history value learned in the learning read as the selected word line voltage Vsel. In this embodiment, the memory controller 200 can use the history value learned for a certain word line WL as the history value for a larger area unit. For example, a word line group WLG can be used as the range in which the history value is shared. In this embodiment, an example in which the memory controller 200 uses the history value learned for a certain word line WL as the history value for the word line group WLG that includes that word line WL will be described.

[0059] Here, an example of word line group WLG classification will be explained with reference to Figures 4 and 5. Figure 4 is a diagram showing an example of word line group WLG classification when the memory cell array 110 has a 16-layer 3D NAND structure. Figure 5 is an example of a word line group assignment table WT corresponding to the word line group WLG classification shown in Figure 4. In learning reads and history value reads, the memory controller 200 refers to the word line group assignment table WT shown in Figure 5 to identify the word line group WLG to which each word line WL belongs. In the example in Figures 4 and 5, word lines WL0 to WL2 are classified into word line group WLG0, word lines WL3 to WL5 are classified into word line group WLG1, word lines WL6 to WL7 are classified into word line group WLG2, word lines WL8 to WL10 are classified into word line group WLG3, word lines WL11 to WL13 are classified into word line group WLG4, and word lines WL14 to WL15 are classified into word line group WLG5.

[0060] In a memory cell array having a three-dimensional NAND structure, memory cells connected to two close word lines WL in the stacking direction of the word lines WL tend to have similar trends in the change of their threshold voltage distribution. Therefore, the memory controller 200 can, for example, use the history value obtained from a learning read for word line WL0 as the history value for word line WL1 or word line WL2, thereby enabling relatively reliable sensing of data from pages corresponding to these word lines WL. In this way, the memory controller 200 can improve the reliability of history value reads by reusing history values ​​by classifying the word lines WL such that each word line WL included in the word line group WLG is adjacent to one of the other word lines WL included in the word line group WLG. Note that in this explanation, "adjacent" does not necessarily mean that the two elements are in contact.

[0061] However, in classifying word lines WL into a word line group WLG, the word lines WLs classified into the same word line group WLG do not necessarily have to be adjacent to each other. In other words, the classification of word lines WL into a word line group WLG can be arbitrarily set from the perspective of the characteristics of each word line WL and the characteristics of the memory cells connected to each word line WL. Furthermore, word lines WL may be classified so that the number of word lines WLs included in each word line group WLG is equal. Also, the configuration of the word line group WLG may differ for each block BLK. Hereinafter, the number of word lines WLs included in a word line group WLG may be expressed as the Quantity in Word Line Group (Nwl).

[0062] In Figure 4, SUB represents the substrate. Also in Figure 4, each MP represents a memory pillar. Each memory pillar MP is formed, for example, by extending in a direction perpendicular to the substrate SUB. Furthermore, as shown in Figure 4, the word lines WL are stacked, for example, in a direction perpendicular to the substrate SUB, spaced apart from each other. Also, as shown in Figure 4, the intersection of the memory pillar MP and the word line WL constitutes the memory cell transistor MT. Other reference numerals in Figure 4 are as explained using Figure 2.

[0063] Furthermore, in the configuration shown in Figure 4, for example, data is programmed into the memory cells connected to each word line WL in the order of the stacking sequence of the word lines WL (i.e., WL0, WL1, ..., WL15). In this embodiment, for simplicity, it is assumed that in each block BLK, the stacking sequence of the word lines WL corresponds to the word line number, and data is programmed into the memory cells connected to the word lines WL in ascending order of the word line number.

[0064] In Figure 5, the word lines WL included in each word line group WLG are defined by a start word line and an end word line, but this is not limited to this. That is, in the word line group assignment table WT, the word lines WL included in each word group may be defined by a start word line and the number of word lines WL included. Alternatively, the numbers of the word lines WL included in the word line group WLG may be listed and stored.

[0065] Next, the determination of the read method will be explained. The read control unit 264 determines the read method to be executed in the read process. Here, the learning read is more reliable than the history value read, but it takes longer to complete than the history value read. Therefore, when a read request is made, the read control unit 264 first considers the history value read, which uses the available history values ​​for the selected word line SelWL, as a candidate read method and makes a decision on whether to execute the history value read. If the read control unit 264 decides to execute the history value read in the decision on whether to execute the history value read, it executes the read process based on the history value read. On the other hand, if the read control unit 264 decides to skip the history value read in the decision on whether to execute the history value read, it skips the history value read and executes the read process based on the learning read. Note that "higher reliability" means that the bit error rate of the sensed data is lower.

[0066] In determining whether to perform a history value read, the read control unit 264 refers, for example, to the data programming status of the memory cell in the block BLK to be read. Hereinafter, a memory cell is said to be programmed if it has been programmed with data. For example, if the programming process for one memory cell is performed in at least two or more steps, "programmed" may refer to the state in which the programming of data to the memory cell is complete, or it may refer to the state in which at least one programming step has been performed on the memory cell. In addition, the programming status can also be defined individually according to the number of bits of data written to the memory cell. Furthermore, there are cases where all memory cells connected to a certain word line WL are programmed, and there are cases where all word lines included in a certain word line group WLG are programmed, and there are cases where the word line group WLG is programmed.

[0067] If the programming for a block BLK is incomplete, that is, if there are unprogrammed memory cells in the block BLK, the effective threshold voltage of the memory cells connected to the word line WL, for example, near the unprogrammed memory cells in the block BLK, may change, and the reliability of history value reads using history values ​​may decrease. In a read sequence where the page corresponding to such a word line WL is the page to be sensed, the read control unit 264 skips the history value read. In this embodiment, an example in which the read control unit 264 refers to the programming status of memory cells connected to a word line WL adjacent to the selected word line SelWL when deciding whether to perform a history value read will be described below. Hereinafter, memory cells connected to a word line WL adjacent to a certain word line WL may be referred to as peripheral memory cells of that word line WL.

[0068] Here, one possible method for the memory controller 200 to manage the program status of peripheral memory cells for each word line WL is to store a table in the main memory 230. However, if the history value table HT and the table for the program status of peripheral memory cells are stored in different memory areas within the main memory 230 (especially two or more memory areas where the processor 260 cannot acquire data in a single cache line), then a cache line or memory area in the main memory 230 corresponding to the number of blocks in the NAND flash memory 100 will be occupied to store the program status of the peripheral memory cells. Furthermore, in such a configuration, the read control unit 264 may have to access the main memory 230 separately to acquire the history value after deciding to perform a history value read by referring to the program status of the peripheral memory cells, which can lead to increased latency.

[0069] Therefore, in the memory system according to this embodiment, when the memory controller 200 stores the program status and history values ​​of peripheral memory cells in the main memory 230, it places them in a memory area within the main memory 230 that allows the data to be acquired together in the same cache line. Specifically, the memory controller 200 stores the program status and history values ​​of peripheral memory cells in a memory area within the main memory 230 that has a size less than or equal to the cache line size and has contiguous addresses. This suppresses the number of cache lines reserved for storing the program status while suppressing the increase in latency due to multiple accesses to the main memory 230. In this embodiment, the history value table HT stores the program status of peripheral memory cells in addition to the history values.

[0070] Hereafter, a memory area within main memory 230 where data can be retrieved together on the same cache line within cache memory 270 may be referred to as an aligned area. In other words, when the processor 260 retrieves data from main memory 230, it accesses main memory 230 in units of aligned areas. Note that the aligned area may be a fixed memory area associated with each cache line, or it may be fluid relative to each cache line.

[0071] Furthermore, the processor 260 does not necessarily have to update the history value table HT stored in the main memory 230 every time at least some of the information stored in the history value table HT is updated. That is, for example, when there is an update to the program status, only the program status stored in the cache line in the cache memory 270 may be updated, and then the update to the program status may be reflected in the history value table HT stored in the main memory 230 at an appropriate time.

[0072] 1.6 About the Management Table Next, the details of the various management tables used in the memory system according to this embodiment will be described with reference to Figures 6 and 7.

[0073] 1.6.1 Shift Table Figure 6 shows an example of a shift table ST used in the memory system according to this embodiment. The shift table ST is stored in the main memory 230. The shift table ST is managed, for example, for each block BLK. Note that a common shift table ST may be used among multiple block BLKs. In the example in Figure 6, the shift table ST for block #0 is shown. As shown in Figure 6, each shift table ST has m+1 entries, where m is an integer of 1 or more. Note that the number of entries in the shift table ST may differ for each block BLK. Each entry is assigned an index from #0 to #m (hereinafter also called a shift index). Each entry stores information about the shift amount of the word line voltage VA to VG. In the example in Figure 6, each entry stores a voltage level value (hereinafter called a DAC value) corresponding to the shift amount of the word line voltage. That is, in read processing, determining the shift index in the shift table ST means that the shift amount of the word line voltage used in sense operation is determined.

[0074] In a learning read using the shift table ST, the memory controller 200 performs the read operation using the DAC values ​​associated with the shift index, for example, in ascending order of the shift index in the shift table ST (#0, #1, #2, etc.). Specifically, the memory controller 200 instructs the NAND flash memory 100 to perform a sense operation using the DAC value associated with the selected shift index. The shift index when the read operation is successful is then learned as a history value. The learned history values ​​are stored in the history value table HT.

[0075] In the example in Figure 6, each index is associated with a shift amount of word line voltages VA to VG, but this is not limited to this. That is, for example, each index may be associated with a shift amount of the word line voltage set used for sensing lower pages, middle pages, or upper pages. In this case, the memory controller 200 can learn history values ​​for each page, for example. Also, when the memory controller 200 learns history values ​​for each page, the memory controller 200 can reuse the history values ​​learned for one page type (e.g., lower pages) for other page types (e.g., upper pages).

[0076] Furthermore, the shift amount information stored in the shift table ST may be a pre-set fixed value, or it may be changed according to the results of learning reads, etc.

[0077] 1.6.2 History Value Table Figure 7 shows an example of a history value table HT used in the memory system according to this embodiment. In particular, Figure 7 shows an example of a history value table HT in a word line group WLG configuration as shown in Figures 4 and 5. The history value table HT is stored in the main memory 230. The history value table HT is managed, for example, for each block BLK, and has a number of entries corresponding to the number of word line group WLGs classified in the block BLK, with an index assigned to each. In this embodiment, the index is the number of the word line group WLG corresponding to each entry.

[0078] Each entry in the history value table HT stores a history value and the program status of the word line group WLG. In this embodiment, the shift index is stored as the history value. The program status of the word line group WLG stores the program status of the word lines WL included in the word line group WLG. More specifically, the program status of the word line group WLG stores the number of word lines WL included in the word line group WLG that have not been programmed. Hereinafter in this embodiment, the number of word lines WL included in a word line group WLG that have not been programmed is referred to as the number of unprogrammed word lines NupWL for that word line group WLG.

[0079] In Figure 7, "NULL" indicates that no data exists. In other words, in the example in Figure 7, there is no history value corresponding to index #2, which means that no history values ​​have been obtained by the learning read for any of the word lines WL included in the word line group WLG2.

[0080] In this embodiment, the number of unprogrammed word lines NupWL can take an integer value between 0 and the number of word line groups Nwl. A NupWL of 0 indicates that all word lines WL included in the word line group WLG are programmed. Conversely, a NupWL equal to the number of word line groups Nwl indicates that none of the word lines WL included in the word line group WLG are programmed.

[0081] For example, when a program operation is performed in which one of the word lines WL included in a certain word line group WLG is selected as the word line SelWL, the memory controller 200 decrements the number of unprogrammed word lines NupWL corresponding to that word line group WLG by 1. In this embodiment, the memory controller 200 may consider that "a program operation has been performed" when "the NAND flash memory 100 has been instructed to execute a program operation."

[0082] If a block BLK has been erased, the number of unprogrammed word lines NupWL stored in the history value table HT corresponding to that block BLK will all be equal to the number of word line groups Nwl. In other words, when an erase operation is performed on a block BLK, the program status stored in the history value table HT corresponding to that block BLK is initialized to the number of word line groups Nwl. In addition to initializing the program status, the history values ​​stored in the history value table HT may also be initialized to "NULL". These initialization processes are performed, for example, by the erase control unit 266.

[0083] The example in Figure 7 corresponds to a state where word lines WL0 to WL9 are programmed in the word line group WLG configuration shown in Figures 4 and 5. For word line groups WLG0 to WLG2, the number of unprogrammed word lines NupWL is 0, which indicates that all word lines WL (WL0 to WL7) included in word line groups WLG0 to WLG2 are programmed. For word line group WLG3, word lines WL8 and WL9 are programmed, excluding WL10, which is the last word line in ascending order of word line number. Furthermore, for word line groups WLG4 and WLG5, the number of unprogrammed word lines NupWL is equal to the number of word line groups Nwl, which indicates that none of the word lines WL (WL11 to WL15) included in word line groups WLG4 and WLG5 are programmed.

[0084] In the following, as shown in the example of word line WL9 in Figure 7, the word line WL that is the last to be programmed in block BLK during programming may be referred to as an end word line or end WL. The memory cells surrounding an end word line include at least unprogrammed memory cells. In this embodiment, the read control unit 264 determines whether the selected word line SelWL is an end word line when deciding whether to execute a history value read. If the selected word line SelWL is an end word line, the read control unit 264 skips the execution of the history value read in that read sequence.

[0085] As shown in Figure 7, each entry in the history value table HT corresponds to one aligned area. That is, as described above, the data corresponding to each entry (history value and program status) is stored in the same aligned area in main memory 230. Note that there may be multiple entries corresponding to one aligned area. In this case, the data corresponding to multiple entries is stored in a single aligned area.

[0086] In Figure 7, a NULL value is stored to indicate that no history value exists, but this is not the only option. That is, the memory controller 200 may, for example, use a table such as the word line group allocation table WT to manage a flag indicating whether or not a history value exists for each word line group WLG, and store data in the history value table HT only for word line groups WLGs that have a history value or program status.

[0087] Furthermore, each entry in the history value table HT may store, for example, the history values ​​and program status corresponding to each word line group WLG for multiple block BLKs. In this case, for example, one history value table HT is stored for a block group that comprises multiple block BLKs. Then, each entry in the history value table HT corresponding to a certain block group stores the same number of history values ​​and program status for the word line group WLG corresponding to the entry as the number of block BLKs included in that block group.

[0088] Furthermore, while Figure 7 shows the shift index as a history value, it is not limited to this. That is, for example, the voltage value of the word line voltage or the shift amount may be stored as a history value. In addition, depending on the sense conditions learned in the learning read, information that can identify those sense conditions may be stored as a history value in the history value table HT.

[0089] Furthermore, while Figure 7 shows the number of unprogrammed word lines as the program status for the word line group WLG, it is not limited to this. That is, for example, the number of programmed word lines WL in the word line group WLG may be stored as the program status. Alternatively, the number of the last programmed word line WL in the word line group WLG, or information listing whether each word line WL is programmed or not, may be stored as the program status. The program status stored in the history value table HT can be any information that can identify the program status of the surrounding memory cells for each word line WL included in the word line group WLG.

[0090] 1.7 Operation Next, the operation of the memory system according to this embodiment will be described.

[0091] 1.7.1 Read Sequence First, an example of a read sequence in this embodiment will be described with reference to Figure 8. The memory controller 200 starts the read sequence, for example, when it receives a data read request from the host 300.

[0092] In step S100, the memory controller 200 identifies the address to be sensed from the read request address received from the host 300. The memory controller 200 identifies the address to be sensed, for example, by referring to the address table AT. The read request address is received from the host 300 either following the read request or included in the read request.

[0093] In step S102, the memory controller 200 identifies the word line number of the selected word line SelWL and the corresponding word line group WLG (hereinafter also referred to as the target word line group) based on the sense target address identified in step S100. The memory controller 200 identifies, for example, the word line group allocation table WT to be referenced from the block address included in the sense target address, and identifies the word line group WLG by referring to the identified word line group allocation table WT.

[0094] In step S104, the memory controller 200 refers to the history value table HT to obtain the history value and program status of the word line group WLG identified in step S102. Specifically, in this embodiment, the memory controller 200 obtains the shift index as the history value and the number of unprogrammed word lines NupWL as the program status. The memory controller 200 identifies the history value table HT to be referenced from, for example, the block address included in the sense target address.

[0095] In step S200, the memory controller 200 determines whether the selected word line SelWL is an end word line (hereinafter also referred to as end word line determination) based on the number of unprogrammed word lines NupWL obtained in step S104. Details of the end word line determination will be described later. If the end word line determination determines that the selected word line SelWL is an end word line (Yes in step S106), this operation proceeds to step S400. On the other hand, if the end word line determination determines that the selected word line SelWL is not an end word line (No in step S106), this operation proceeds to step S108.

[0096] In step S108, the memory controller 200 determines whether or not a history value exists for the target word line group. For example, the memory controller 200 determines whether or not the value of the history value obtained in step S104 is a NULL value. If the obtained history value is not a NULL value, that is, if a history value exists (Yes in step S108), the operation proceeds to step S300. On the other hand, if the obtained history value is a NULL value, that is, if a history value does not exist (No in step S108), the operation proceeds to step S400.

[0097] In step S300, the memory controller 200 performs a history value read based on the history value acquired in step S104. Details of the history value read will be described later. The read data received from the NAND flash memory 100 during the history value read is temporarily stored, for example, in the buffer memory 240. If the memory controller 200 succeeds in the history value read (Yes in step S110), the operation proceeds to step S116. On the other hand, if the memory controller 200 fails to succeed in the history value read (No in step S110), the operation proceeds to step S400.

[0098] In step S400, the memory controller 200 performs a learning read. Details of the learning read will be described later. The read data received from the NAND flash memory 100 during the learning read is temporarily stored, for example, in the buffer memory 240. If the memory controller 200 succeeds in this learning read (Yes in step S112), the operation proceeds to step S114. On the other hand, if the memory controller 200 fails to succeed in this learning read (No in step S112), a read error is notified to the host 300 (step S118), and the operation ends.

[0099] In step S114, the memory controller 200 updates the history value table HT based on the history values ​​learned in step S400. Specifically, the memory controller 200 stores, for example, the shift index acquired as a history value in the learning read of step S400 into the entry in the history value table HT corresponding to the target word line group.

[0100] In step S116, the read data is sent to the host 300, and this operation ends.

[0101] In step S114, the memory controller 200 may decide whether or not to update the history value table HT depending on whether the selected word line SelWL on which the learning read was performed is an end word line. That is, for example, the memory controller 200 may not update the history value table HT with the learned history value if the selected word line SelWL is an end word line, and may update the history value table HT with the learned history value if the selected word line SelWL is not an end word line.

[0102] 1.7.1.1 End word line detection Next, a specific example of the end word line determination flow in this embodiment will be described with reference to Figure 9. Figure 9 shows the end word line determination flow in particular when the history value table HT, as described using Figure 7, is used. Steps S202 to S218 below correspond to step S200 in Figure 8.

[0103] When the end word line determination is initiated, in step S202, the read control unit 264 determines whether all word lines WL included in the target word line group are programmed. Specifically, for example, the read control unit 264 determines whether the acquired number of unprogrammed word lines NupWL is 0. If the acquired number of unprogrammed word lines NupWL is 0, that is, if all word lines WL included in the target word line group are programmed (Yes in step S202), this operation proceeds to step S208. On the other hand, if the acquired number of unprogrammed word lines NupWL is not 0, that is, if there are word lines WL included in the target word line group that are not programmed (No in step S202), this operation proceeds to step S204.

[0104] In step S204, the read control unit 264 identifies the end word line in the block BLK to be sensed. Specifically, for example, the read control unit 264 identifies the word line number of the end word line as end WL number = WLGmax - NupWL, where WLGmax is the number of the end word line of the target word line group.

[0105] In step S206, the read control unit 264 determines whether the selected word line SelWL is the end word line identified in step S204. Specifically, for example, the read control unit 264 determines whether the SelWL number equals the end WL number. If the SelWL number equals the end WL number, that is, if the selected word line SelWL is the end word line identified in step S204 (Yes in step S206), the operation proceeds to step S216. On the other hand, if the SelWL number does not equal the end WL number, that is, if the selected word line SelWL is not the end word line identified in step S204 (No in step S206), the operation proceeds to step S218.

[0106] In step S208, the read control unit 264 determines whether the selected word line SelWL is the last word line WL to be programmed in the target word line group. Specifically, for example, the read control unit 264 determines whether the SelWL number is equal to WLGmax. If the SelWL number is equal to WLGmax, that is, if the selected word line SelWL is the last word line WL to be programmed in the target word line group (Yes in step S208), the operation proceeds to step S210. On the other hand, if the SelWL number is not equal to WLGmax, that is, if the selected word line SelWL is not the last word line WL to be programmed in the target word line group (No in step S208), the operation proceeds to step S218.

[0107] In step S210, the read control unit 264 determines whether the selected word line SelWL is the last word line WL to be programmed in block BLK. Specifically, for example, the read control unit 264 determines whether the SelWL number is equal to WLmax. Here, WLmax is the word line number with the largest value among the word line numbers of the word lines WL included in block BLK. If the SelWL number is equal to WLmax, that is, if the selected word line SelWL is the last word line WL to be programmed in block BLK (Yes in step S210), the operation proceeds to step S218. On the other hand, if the SelWL number is not equal to WLmax, that is, if the selected word line SelWL is not the last word line WL to be programmed in block BLK (No in step S210), the operation proceeds to step S212.

[0108] In step S212, the read control unit 264 refers to the history value table HT to obtain the number of unprogrammed word lines NupWL (and the history value) of the next word line group WLG# of the target word line group. Note that the next word line group WLG# of the target word line group is a word line group WLG including the word line WL that has been programmed next to the target word line group. Similarly hereinafter, a word line group WLG including the word line WL that has been programmed next to a certain word line group WLG may be referred to as the next word line group WLG# of the certain word line group WLG. In step S212, specifically, when the target word line group is the word line group WLGn (n is an integer of 0 or more), the read control unit 264 obtains the number of unprogrammed word lines NupWL (and the history value) of the word line group WLG(n + 1). Hereinafter, the obtained number of unprogrammed word lines NupWL and history value of the next word line group WLG# may be described as the number of unprogrammed word lines NupWL# and history value#.

[0109] In step S214, the read control unit 264 determines whether there is a word line WL that has been programmed in the word line WLs included in the next word line group WLG# based on the number of unprogrammed word lines NupWL# obtained in step S212. Specifically, for example, the read control unit 264 determines whether NupWL# < Nwl#. Here, Nwl# is the number of word lines WLs included in the next word line group WLG#. If NupWL# < Nwl#, that is, if there is a word line WL that has been programmed in the word line WLs included in the next word line group WLG# (Yes in step S214), this operation proceeds to step S2I8. On the other hand, if NupWL# < Nwl# is not satisfied, that is, if there is no word line WL that has been programmed in the word line WLs included in the next word line group WLG# (No in step S214), this operation proceeds to step S216.

[0110] In step S216, the read control unit 264 determines that the selected word line SelWL is an end word line, and this operation ends.

[0111] In step S218, the lead control unit 264 determines that the selected word line SelWL is not an end word line, and this operation ends.

[0112] In the above description, the read control unit 264 determines whether the selected word line SelWL is the last word line WL to be programmed in the block BLK (step S210), but is not limited to this. That is, for example, instead of the above determination, a step of determining whether the block BLK to be sensed is programmed may be incorporated into the end word line determination flow. In this case, the read control unit 264, for example, performs the step of determining whether the block BLK to be sensed is programmed before step S202, and if the block BLK to be sensed is programmed, skips steps S202 to S206 and determines that the selected word line SelWL is not an end word line. In this description, "the block BLK is programmed" means that all memory cells contained in the block BLK are programmed.

[0113] 1.7.1.2 Historical Value Read Next, a specific example of the history value read flow in this embodiment will be described with reference to Figure 10. Figure 10 shows an example of the history value read flow when the shift table ST, as described with reference to Figure 6, and the history value table HT, as described with reference to Figure 7, are used. Steps S302 to S312 below correspond to step S300 in Figure 8.

[0114] In step S302, the read control unit 264 identifies the shift amount corresponding to the shift index acquired as a history value in step S104, as described with reference to Figure 8, by referring to the shift table ST.

[0115] In step S304, the read control unit 264 instructs the NAND flash memory 100 to perform a sense operation based on the shift amount identified in step S302. Specifically, the read control unit 264 instructs the NAND flash memory 100 to perform a sense operation using the identified shift amount from the address to be sensed. In the instruction to perform the sense operation, the identified shift amount is transferred to the NAND flash memory 100 as part of the sense command, or together with the sense command. The read data sensed in the NAND flash memory 100 is sent to the memory controller 200 and temporarily stored, for example, in the buffer memory 240.

[0116] In step S306, the ECC circuit 250 performs error correction decoding on the read data received from the NAND flash memory 100. If the ECC circuit 250 is successful in the error correction decoding process (Yes in step S308), the operation proceeds to step S310. On the other hand, if the ECC circuit 250 fails in the error correction decoding process (No in step S308), the operation proceeds to step S312.

[0117] In step S310, the read control unit 264 determines that the history value read was successful, and this operation ends.

[0118] In step S312, the read control unit 264 determines that the history value read has failed, and this operation ends.

[0119] 1.7.1.2 Learning Lead Next, a specific example of the learning read flow in this embodiment will be described with reference to Figure 11. Figure 11 shows an example of the learning read flow when the shift table ST, as described using Figure 6, and the history value table HT, as described using Figure 7, are used. Steps S402 to S416 below correspond to step S400 in Figure 8.

[0120] In step S402, the read control unit 264 sets the shift index to its initial value in the shift table ST. In the example in Figure 11, the shift index is set to 0.

[0121] In step S403, the read control unit 264 refers to the shift table ST and identifies the shift amount corresponding to the set shift index.

[0122] In step S404, the read control unit 264 instructs the NAND flash memory 100 to perform a sense operation based on the shift amount identified in step S403. The specific processing is the same as in step S304 in Figure 10.

[0123] In step S406, the ECC circuit 250 performs error correction decoding on the read data received from the NAND flash memory 100. If the ECC circuit 250 succeeds in the error correction decoding process (Yes in step S408), the operation proceeds to step S414. On the other hand, if the ECC circuit 250 fails in the error correction decoding process (No in step S408), the operation proceeds to step S410.

[0124] In step S410, the read control unit 264 determines whether the current shift index is the last shift index specified in the shift table ST. In the example in Figure 11, the read control unit 264 determines whether the current shift index is the maximum value in the shift table ST. If the current shift index is the maximum value (Yes in step S410), the operation proceeds to step S416. On the other hand, if the current shift index is not the maximum value (No in step S410), the operation proceeds to step S412.

[0125] In step S412, the read control unit 264 changes the shift index to the next value to be specified. In the example in Figure 11, the shift index is incremented by 1. The operation then returns to step S404.

[0126] In step S414, the read control unit 264 determines that the learning read was successful, and this operation ends.

[0127] In step S416, the read control unit 264 determines that the learning read has failed, and this operation ends.

[0128] In the above description of history value read and learning read, the read control unit 264 identifies the shift amount from the shift index and transfers the shift amount to the NAND flash memory 100 in the sense operation instruction, but is not limited to this. That is, for example, the read control unit 264 may calculate the voltage value of the voltage applied to the selected word line SelWL from the identified shift amount and transfer the calculated voltage value. Alternatively, for example, instead of transferring the shift amount for each sense operation instruction, the read control unit 264 may transfer the shift amount when the shift amount used in the sense operation is changed. Alternatively, for example, the read control unit 264 may instruct the NAND flash memory 100 to change the shift amount by a command that instructs a change in the shift amount, separate from the sense operation instruction.

[0129] The read sequence in this embodiment is merely an example and is not limited to the flow described above. For example, different read methods may be executed before or after history value reads or learning reads. Also, if the selected word line is an end word line, a read process using a shifted value corrected from the history value may be executed instead of a learning read. Furthermore, as a learning read, other read methods such as tracking reads may be executed instead of a read using a shift table ST.

[0130] 1.7.2 Light Processing Next, an example of write processing in this embodiment will be described with reference to Figure 12. Figure 12 shows the flow of write processing when the memory system 1 uses the history value table HT as described with reference to Figure 7. The memory controller 200 starts write processing, for example, when it receives a data write request from the host 300.

[0131] In step S500, the memory controller 200 receives write data from the host 300. The received write data is temporarily stored, for example, in the buffer memory 240. The write data undergoes error correction coding processing by the ECC circuit 250.

[0132] In step S502, the memory controller 200 determines the program target address where the write data should be stored.

[0133] In step S504, the memory controller 200 instructs the NAND flash memory 100 to execute a program operation to write data to the program target address determined in step S502.

[0134] In step S506, the memory controller 200 updates the address table AT based on the program target address determined in step S502.

[0135] In step S508, the memory controller 200 identifies the word line number of the selected word line SelWL and the corresponding word line group WLG (hereinafter also referred to as the target word line group) based on the program target address determined in step S502. The memory controller 200 identifies the word line group allocation table WT to be referenced from the block address included in the program target address, and identifies the target word line group by referring to the identified word line group allocation table WT.

[0136] In step S510, the memory controller 200 updates the program status in the history value table HT for the target word line group identified in step S508. Specifically, the memory controller 200 decrements the number of unprogrammed word lines in the target word line group, NupWL, by 1, for example, when the selected word line SelWL becomes programmed.

[0137] Light processing is complete.

[0138] The flow from step S506 onward may be performed individually for each instruction to execute a program operation in step S504, or it may be performed collectively for multiple instructions to execute program operations, such as for each write request.

[0139] The memory controller 200 may, for example, instruct the execution of a program operation for each page-sized data, or for each data having a size corresponding to one cell unit CU. Alternatively, it may instruct the execution of a program operation for each data having a size corresponding to the total capacity of all memory cells connected to a single word line WL. When instructing the execution of a program operation for each page-sized data or for each data having a size corresponding to one cell unit CU, the memory controller 200 performs the processing in step S510, for example, when the program target address is the last page or cell unit CU to be programmed on the selected word line SelWL.

[0140] In this embodiment, the memory controller 200 refers to the program status of the data for the memory cell when determining whether to perform a history value read, but is not limited to this. That is, the memory controller 200 can store other information that can estimate the reliability of a history value read in the history value table HT, either in place of the program status or in addition to the program status, and use this information to determine whether to perform a history value read.

[0141] 1.8 Effects In the memory system according to this embodiment, the program status of peripheral memory cells and their history values ​​are stored in the main memory in such a way that they can be read into the same cache line within the cache memory.

[0142] As a result, in the memory system according to this embodiment, there is no need to separately allocate a cache line or memory area in the main memory for storing information used to determine whether to perform a history value read, thus reducing the number of cache lines and memory area required to perform the read operation.

[0143] Furthermore, in the memory system according to this embodiment, since there is no need to access main memory separately to acquire the history value after deciding to perform a history value read, an increase in latency can be suppressed.

[0144] In this embodiment, an example was described in which the memory controller 200 includes one cache memory, but this is not the only example. That is, in addition to the cache memory 270, another cache memory may be provided. In this case, for example, the cache memory 270 is used as the primary cache memory, and the additional cache memory is used as the secondary cache memory. Even with such a configuration, the above-described effects can be obtained with the same configuration as the one described in this embodiment.

[0145] 2. Second Embodiment Next, a memory system according to the second embodiment will be described. In the first embodiment, the history value table HT stores the program status of the word line WL included in the word line group WLG as the program status of the word line group WLG. In this configuration, as shown in Figure 9, the memory controller 200 may not be able to determine whether the selected word line SelWL is an end word line unless it refers to the program status of the next word line group WLG# (steps S208 to S214 in Figure 9).

[0146] In the second embodiment, the program status of the word line group WLG in the history value table HT includes the program status of at least one word line WL that is not included in the word line group WLG (hereinafter also referred to as the reference word line refWL of the word line).

[0147] In the following, we will describe an example in which the program status of a word line group WLG in the history value table HT includes the program status of the word line WL that will be programmed next to the word line group WLG. That is, in the following, the word line WL that will be programmed next to a certain word line group WLG is the reference word line refWL of that word line group WLG. For example, in the configuration of word line groups WLG shown in Figure 5, the reference word line refWL of word line group WLG0 is word line WL3, and the reference word line refWL of word line group WLG1 is WL6.

[0148] Note that descriptions of configurations and operations equivalent to those of the first embodiment may be omitted below.

[0149] 2.1 Historical Value Table Figure 13 shows an example of a history value table HT used in the memory system according to this embodiment. In particular, Figure 13 shows an example of a history value table HT in the configuration of a word line group WLG as shown in Figures 4 and 5.

[0150] In this embodiment, each entry in the history value table HT stores a shift index as a history value, and stores the number of unprogrammed word lines WL among the word lines WL included in the word line group WLG and the reference word line refWL of the word line group WLG as the program status for the word line group WLG. For example, in Figure 13, the entry corresponding to word line group WLG0 stores the number of unprogrammed word lines WL among the word lines WL0 to WL2 included in word line group WLG0 and the reference word line refWL, which is WL3. Similarly, the entry corresponding to word line group WLG1 stores the number of unprogrammed word lines WL among the word lines WL3 to WL6. Hereinafter in this embodiment, the number of unprogrammed word lines WL among the word lines WL included in a certain word line group WLG and the reference word line refWL of that word line group WLG is referred to as the number of unprogrammed word lines NupWL for that word line group WLG.

[0151] Furthermore, the correspondence between the word line group WLG and the reference word line refWL is not limited to the example described in this embodiment, and can be arbitrarily set from the viewpoint of the characteristics of the word line WL included in the word line group WLG. In addition, there may be a word line group WLG that does not have a reference word line refWL.

[0152] In this embodiment, the number of unprogrammed word lines NupWL can take an integer value between 0 and the number of word line groups Nwl+1. A NupWL of 0 indicates that all word lines WL included in the word line group WLG are programmed, and the reference word line refWL of the word line group WLG is programmed. A NupWL of 0 indicates that neither the word lines WL included in the word line group WLG nor the reference word line refWL of the word line group WLG are programmed. A NupWL of 1 indicates that all word lines WL included in the word line group WLG are programmed, but the reference word line refWL of the word line group WLG is not programmed.

[0153] In this embodiment, the word line group WLG that is the last to be programmed in block BLK does not have a reference word line refWL. That is, the number of unprogrammed word lines NupWL corresponding to the word line group WLG that is the last to be programmed in block BLK indicates the programming status of the word lines WL included in the word line group WLG. Specifically, if the word line group WLG is not programmed, (the number of unprogrammed word lines WL included in the word line group WLG) + 1 is stored as the number of unprogrammed word lines NupWL, and if the word line group WLG is programmed, 0 is stored as the number of unprogrammed word lines NupWL. In other words, in this embodiment, the number of unprogrammed word lines NupWL for the word line group WLG that is the last to be programmed in block BLK can take the values ​​of 0 and integer values ​​between 2 and the number of word line groups Nwl + 1. In Figure 13, for example, the entry corresponding to word line group WLG5 stores the number of unprogrammed word lines NupWL. If word line group WLG5 is not programmed, it stores (the number of unprogrammed word lines WL14 to WL15) + 1, and if word line group WLG5 is programmed, it stores 0.

[0154] If a block BLK has been erased, the number of unprogrammed word lines NupWL stored in the history value table HT corresponding to that block BLK will all be equal to the number of corresponding word line groups Nwl+1. In other words, when an erase operation is performed on a block BLK, the program status stored in the history value table HT corresponding to that block BLK is initialized to the number of word line groups Nwl+1. These initialization processes are performed, for example, by the erase control unit 266.

[0155] The example in Figure 13 corresponds to a state where word lines WL0 to WL6 are programmed in the WLG word line group configuration shown in Figures 4 and 5. For word line groups WLG0 to WLG1, the number of unprogrammed word lines NupWL is 0, which indicates that all word lines WL and reference word lines refWL (WL0 to WL6) included in word line groups WLG0 to WLG1 are programmed. For word line group WLG2, the number of unprogrammed word lines NupWL is 2, which is 1 less than the initial value of 3. This indicates that of the word lines WL and reference word lines refWL (WL6 to WL8) included in word line group WLG2, only WL6, which is programmed first, is programmed. Furthermore, for word line groups WLG3 to WLG4, the number of unprogrammed word lines NupWL is equal to the number of word line groups Nwl+1, which indicates that none of the word lines WL and reference word lines refWL (WL8 to WL14) included in word line groups WLG3 to WLG4 are programmed. Furthermore, for word line group WLG5, the number of unprogrammed word lines NupWL is equal to the number of word line groups Nwl+1, which indicates that none of the word lines WL (WL14~WL15) included in word line group WLG5 are programmed.

[0156] Here, with reference to Figure 14, an example of the transition of the number of unprogrammed word lines NupWL in the history value table HT will be explained. Figure 14 shows an example of the transition of the number of unprogrammed word lines NupWL for word line groups WLG0 and WLG1 in the configuration of word line group WLG shown in Figures 4 and 5. In the table shown in Figure 14, each cell corresponds to one word line WL.

[0157] In Figure 14, a blank cell indicates that the corresponding word line WL is not programmed, while a hatched cell indicates that the corresponding word line WL is programmed. As mentioned above, in this embodiment, for simplicity, it is assumed that in block BLK, word lines are programmed in ascending order of word line number. In Figure 14, the uppermost word line WL among the hatched word lines WL is the end word line.

[0158] As shown in Figure 14(a), if block BLK has been cleared, the number of unprogrammed word lines NupWL corresponding to word line groups WLG0 and WLG1 is the initial value of 4. Specifically, for example, the number of unprogrammed word lines NupWL corresponding to word line group WLG0 is 4, which is the total number of word lines WL0 to WL2 and word line WL3.

[0159] Next, as shown in Figure 14(b), when word line WL0 is programmed, the number of unprogrammed word lines in the word line group WLG0, NupWL, is 3 (=4-1). Note that since word line WL0 is an end word line, in a read sequence where word line WL0 is selected as word line SelWL, the execution of history value reads is skipped.

[0160] Next, as shown in Figure 14(c), when word lines WL1 and WL2 are further programmed, the number of unprogrammed word lines NupWL in the word line group WLG0 becomes 1 (=4-3). In this state, since word line WL2 is an end word line, the execution of the history value read is skipped in a read sequence where word line WL2 is selected as the word line SelWL. On the other hand, in a read sequence where word line WL0 or WL1 is selected as the word line SelWL, if a history value corresponding to the word line group WLG0 exists, the history value read is executed. In the state shown in Figure 14(c), the word line group WLG0 is programmed.

[0161] Furthermore, as shown in Figure 14(d), when word line WL3 is further programmed, the number of unprogrammed cell units NupCU in word line group WLG0 becomes 0 (=4-4). At this time, none of the word lines WL (WL0~WL2) included in word line group WLG0 are end word lines. Also, the number of unprogrammed word lines NupWL in word line group WLG1 becomes 3 (=4-1).

[0162] Similar to the first embodiment, each entry in the history value table HT corresponds to one aligned area.

[0163] Furthermore, in the history value table HT, for example, the number of programmed word lines WL and reference word lines refWL included in the word line group WLG may be stored as the program status. Alternatively, the program status may include the number of the last word line WL to be programmed, or information listing whether each word line WL is programmed or not.

[0164] As described above, in the history value table HT of this embodiment, the program status (number of unprogrammed word lines NupWL) stored in correspondence with the word line group WLG includes the program status of the word line WL (reference word line refWL) that will be programmed next to the word line group WLG. Therefore, even when the memory controller 200 performs an end word line determination for the word line WL that will be programmed last in the word line group WLG, it does not need to refer to the program status of the next word line group WLG# of the target word line group, and the increase in the number of accesses to the main memory 230 can be suppressed.

[0165] 2.2 Operation Next, the operation of the memory system according to this embodiment will be described. The example of the read sequence in this embodiment is the same as that of the first embodiment (described with reference to Figure 8), so the description will be omitted. The example of the history value read and learning read flows in this embodiment is the same as that of the first embodiment (described with reference to Figures 10 and 11, respectively), so the description will be omitted.

[0166] 2.2.1 End word line detection First, a specific example of the endpoint word line determination flow in this embodiment will be explained with reference to Figure 15. Figure 15 shows the endpoint word line determination flow, in particular, when the history value table HT, as explained using Figure 13, is used. Steps S602 to S606, S216, and S218 below correspond to step S200 in Figure 8.

[0167] When the end word line determination is initiated, in step S602, the read control unit 264 determines whether all of the target word line group and the reference word lines refWL of the target word line group are programmed. Specifically, for example, the read control unit 264 determines whether the acquired number of unprogrammed word lines NupWL is 0. If the acquired number of unprogrammed word lines NupWL is 0, that is, if all of the target word line group and the reference word lines refWL of the target word line group are programmed (Yes in step S602), the operation proceeds to step S218. On the other hand, if the acquired number of unprogrammed word lines NupWL is not 0, that is, if either the target word line group or the reference word lines refWL of the target word line group are not programmed (No in step S602), the operation proceeds to step S604.

[0168] In step S604, the read control unit 264 identifies the end word line in the block BLK to be sensed. Specifically, for example, the read control unit 264 identifies the word line number of the end word line as end WL number = WLGmax - NupWL + 1. Here, WLGmax is the number of the end word line of the target word line group.

[0169] In step S606, the read control unit 264 determines whether the selected word line SelWL is the end word line identified in step S604. Specifically, for example, the read control unit 264 determines whether the SelWL number equals the end WL number. If the SelWL number equals the end WL number, that is, if the selected word line SelWL is the end word line identified in step S604 (Yes in step S606), the operation proceeds to step S216. On the other hand, if the SelWL number does not equal the end WL number, that is, if the selected word line SelWL is not the end word line identified in step S604 (No in step S606), the operation proceeds to step S218.

[0170] In step S216, the lead control unit 264 determines that the selected word line SelWL is an end word line, and this operation ends.

[0171] In step S218, the lead control unit 264 determines that the selected word line SelWL is not an end word line, and this operation ends.

[0172] In step S602, the read control unit 264 performs a determination by treating, for example, the number of unprogrammed word lines NupWL as a boolean value. In this case, if the number of unprogrammed word lines NupWL indicates False, the read control unit 264 determines that step S602 is Yes, and if the number of unprogrammed word lines NupWL indicates True, it determines that step S602 is No. Determining by treating the value as a boolean value is faster than determining by treating the value as a numerical value, and can reduce latency in end word line determination.

[0173] 2.2.2 Light Processing Next, an example of the write process in this embodiment will be described with reference to Figure 16. Figure 16 shows the flow of the write process when the memory system 1 uses the history value table HT as described with reference to Figure 13. For steps in Figure 16 that are numbered the same as the steps in the first embodiment (Figure 12), the same processing as described in the first embodiment is performed. The explanation of those steps (steps S500 to S508) will be omitted.

[0174] In step S710, the memory controller 200 updates the program status in the history value table HT for the target word line group identified in step S508. Specifically, the memory controller 200 decrements the number of unprogrammed word lines in the target word line group, NupWL, by 1, for example, when the selected word line SelWL becomes programmed.

[0175] In step S712, the memory controller 200 determines whether the selected word line SelWL is the last word line WL to be programmed in the block BLK. Specifically, for example, the memory controller 200 determines whether the SelWL number is equal to WLmax. Here, WLmax is the word line number with the largest value among the word line numbers of the word lines WL included in the block BLK. If the SelWL number is equal to WLmax, that is, if the selected word line SelWL is the last word line WL to be programmed in the block BLK (Yes in step S712), the operation proceeds to step S714. On the other hand, if the SelWL number is not equal to WLmax, that is, if the selected word line SelWL is not the last word line WL to be programmed in the block BLK (No in step S712), the operation proceeds to step S716.

[0176] In step S714, the memory controller 200 updates the program status in the history value table HT for the target word line group. Specifically, the memory controller 200 sets the number of unprogrammed word lines NupWL for the target word line group to 0. As a result of this step, for the word line group WLG that will be the last to be programmed in block BLK, the number of unprogrammed word lines NupWL will become 0 when all word lines WL included in the word line group WLG have been programmed.

[0177] In step S716, the memory controller 200 determines whether the selected word line SelWL is the first word line WL to be programmed in the target word line group. Specifically, for example, the read control unit 264 determines whether the SelWL number is equal to WLGmin. Here, WLGmin is the number of the starting word line in the target word line group. If the SelWL number is equal to WLGmin, that is, if the selected word line SelWL is the first word line WL to be programmed in the target word line group (Yes in step S716), the operation proceeds to step S718. On the other hand, if the SelWL number is not equal to WLGmin, that is, if the selected word line SelWL is not the first word line WL to be programmed in the target word line group (No in step S716), the operation ends.

[0178] In step S718, the memory controller 200 determines whether the selected word line SelWL is the first word line WL to be programmed in block BLK. Specifically, for example, the memory controller 200 determines whether the SelWL number is equal to WLmin. Here, WLmin is the word line number with the smallest value among the word line numbers of the word lines WL included in block BLK. If the SelWL number is equal to WLmin, that is, if the selected word line SelWL is the first word line WL to be programmed in block BLK (Yes in step S718), this operation ends. On the other hand, if the SelWL number is not equal to WLmin, that is, if the selected word line SelWL is not the first word line WL to be programmed in block BLK (No in step S718), this operation proceeds to step S720.

[0179] In step S720, the memory controller 200 updates the number of unprogrammed word lines NupWL of the previous word line group WLGpre of the target word line group. Note that the previous word line group WLGpre of the target word line group is the word line group WLG that has the first programmed word line WL in the target word line group as the reference word line refWL. Specifically, in step S720, for example, if the target word line group is the word line group WLGn (where n is an integer of 1 or more), the memory controller 200 decrements the number of unprogrammed word lines NupWL of the word line group WLG(n-1) by 1. As a result of this step, the program status of the reference word line refWL of the word line group WLG is reflected in the program status of the word line group WLG stored in the history value table HT.

[0180] Light processing is complete.

[0181] In step S712, the memory controller 200 determines whether the selected word line SelWL is the last word line WL to be programmed in the target word line group, but it is not limited to this. That is, for example, the memory controller 200 may also determine whether the target word line group is the last word line group WLG to be programmed in block BLK, and whether the selected word line SelWL is the last word line WL to be programmed in the target word line group.

[0182] Furthermore, in step S716, the memory controller 200 determines whether the selected word line SelWL is the first word line WL to be programmed in the target word line group, but is not limited to this. That is, for example, instead of the above determination, the memory controller 200 may determine whether the target word line group is the first word line group WLG to be programmed in block BLK. In this case, for example, the memory controller 200 determines whether the target word line group is WLG0.

[0183] Furthermore, during the write process, the memory controller 200 updates the program status of the target word line group if the selected word line SelWL is the last word line WL to be programmed in the block BLK (Yes in step S712), but is not limited to this. That is, for example, instead of incorporating the above step into the write process, a step to determine whether or not the block BLK to be sensed is programmed may be incorporated into the end word line determination. In this case, for the word line group WLG that is the last word line to be programmed in the block BLK, if the word line group WLG is programmed, 1 is stored as the number of unprogrammed word lines NupWL.

[0184] 2.3 Effects In the memory system according to this embodiment, the program status of the word line group WLG in the history value table HT includes the program status of at least one word line WL (reference word line refWL) that is not included in the word line group WLG. Specifically, in this embodiment, for example, the program status of the word line WL that will be programmed next to the word line group WLG is included.

[0185] As a result, in the memory system according to this embodiment, when deciding whether to perform a history value read, the memory controller does not need to refer to the program status stored in multiple different entries of the history value table, thus suppressing the increase in latency caused by accessing main memory.

[0186] 3. Third Embodiment Next, a memory system according to the third embodiment will be described. In the first and second embodiments, the memory controller 200 stores the program status in units of memory cells connected to word lines WL and uses this program status to determine whether to perform a history value read. In the third embodiment, the memory controller 200 stores the program status in units smaller than the word lines WL and uses this to determine whether to perform a history value read. In the following, the case in which the memory controller 200 stores the program status in units of cell units CU and uses this to determine whether to perform a history value read will be described in comparison with the second embodiment. Note that in the following, descriptions of configurations and operations equivalent to those in the second embodiment may be omitted.

[0187] 3.1 Historical Value Table First, the history value table HT according to the third embodiment will be described with reference to Figures 17 and 18. Figure 17 is a diagram showing an example of the history value table HT used in the memory system according to this embodiment. In particular, Figure 17 shows an example of the history value table HT in the configuration of the word line group WLG shown in Figures 4 and 5.

[0188] In this embodiment, each entry in the history value table HT stores a shift index as a history value, and the number of unprogrammed cell units CU (hereinafter also referred to as the number of unprogrammed cell units NupCU) among the cell units CU connected to the word line group WLG and its reference word line refWL is stored as the program status for the word line group WLG. In this description, "a cell unit CU is programmed" means that all memory cells corresponding to that cell unit CU are programmed.

[0189] In this embodiment, the number of unprogrammed cell units NupCU can be an integer value between 0 and (number of word line groups Nwl + 1) × number of string units Nsu. The number of string units Nsu is the number of string units SU included in block BLK. The number of string units Nsu is equal to the number of cell units CU connected to one word line WL. For example, when a program operation is performed on either a word line group WLG or a cell unit CU connected to the reference word line refWL of the word line group WLG, the memory controller 200 decrements the number of unprogrammed cell units NupCU corresponding to the word line group WLG by 1.

[0190] If a block BLK has been erased, the number of unprogrammed cell units NupCU stored in the history value table HT corresponding to that block BLK will all be equal to the corresponding (number of word line groups Nwl+1) × number of string units Nsu. In other words, when an erase operation is performed on a block BLK, the program status stored in the history value table HT corresponding to that block BLK is initialized to (Nwl+1) × Nsu. Specifically, for example, in the configuration of the word line group WLG shown in Figures 4 and 5, the number of unprogrammed cell units NupCU for word line group WLG0 is initialized to 12 (=(3+1)×3). Also, the number of unprogrammed cell units NupCU for word line group WLG2 is initialized to 9 (=(2+1)×3). These initialization processes are performed, for example, by the erase control unit 266.

[0191] Here, with reference to Figure 18, an example of the transition of the number of unprogrammed cell units NupCU in the history value table HT will be explained. Figure 18 shows an example of the transition of the number of unprogrammed cell units NupCU in word line groups WLG0 and WLG1 in the configuration of word line group WLG shown in Figures 4 and 5. In the table shown in Figure 18, each cell corresponds to one cell unit CU, the columns represent the string unit SU corresponding to each cell unit CU, and the rows represent the word line WL corresponding to each cell unit CU.

[0192] Furthermore, as shown in each cell of Figure 18, the memory controller 200 assigns a cell unit number to each cell unit CU within the word line group WLG. Specifically, the memory controller 200 assigns the cell unit number (Nsu × (i - WLGmin) + j) to the cell unit CU that corresponds to the word line WLi and the string unit SUj. Here, WLGmin is the number of the starting word line of the corresponding word line group WLG. For example, the cell unit CU corresponding to word line WL1 and string unit SU2 is assigned cell unit number 5 (= 3 × (1 - 0) + 2). Similarly, the cell unit CU corresponding to word line WL4 and string unit SU1 is assigned cell unit number 4 (= 3 × (4 - 3) + 1). Hereafter, a cell unit CU connected to the word line group WLGn and assigned cell unit number m may simply be referred to as CU(n,m).

[0193] The memory controller 200 may store the cell unit number corresponding to each cell unit CU in the word line group WLG as a table associated with the word line number. Alternatively, the memory controller 200 may calculate the cell unit number from the corresponding word line number and string unit number using the above formula or other calculation formulas.

[0194] In Figure 18, a blank cell indicates that the corresponding cell unit CU is not programmed, while a hatched cell indicates that the corresponding cell unit CU is programmed. In this embodiment, cell units CU connected to the same word line WL are programmed in ascending order of the corresponding string unit SU number. That is, in block BLK of this embodiment, programming is performed in ascending order of cell unit number.

[0195] Furthermore, in the following, the cell unit CU that was last programmed in the string unit SU may be referred to as an end cell unit or end CU. Similar to end word lines, the memory cells surrounding the end cell unit include at least some unprogrammed memory cells. In this embodiment, the read control unit 264 determines whether the cell unit CU corresponding to the sense target address (hereinafter also referred to as the sense target cell unit) is an end cell unit when deciding whether to execute a history value read. If the sense target cell unit is an end cell unit, the read control unit 264 skips the execution of the history value read in that read sequence. In Figure 18, among the hatched cell unit CUs, the cell unit CU located at the top of each row is the end cell unit.

[0196] As shown in Figure 18(a), if block BLK has been cleared, the number of unprogrammed cell units NupCU corresponding to word line groups WLG0 and WLG1 is the initial value of 12. Specifically, for example, the number of unprogrammed cell units NupCU corresponding to word line group WLG0 is 12, which is the sum of 9 cell units CU(0,0) to CU(0,8) connected to word lines WL0 to WL2 and 3 cell units CU(1,0) to CU(1,2) connected to word line WL3.

[0197] Next, as shown in Figure 18(b), when cell units CU(0,0) to CU(0,2) are programmed, the number of unprogrammed cell units NupCU in the word line group WLG0 is 9 (=12-3). Note that since cell units CU(0,0) to CU(0,2) are end cell units, the execution of history value reads is skipped in read sequences that use these cell units CU as the sense target cell units.

[0198] Next, as shown in Figure 18(c), when cell units CU(0,3) and CU(0,4) are further programmed, the number of unprogrammed cell units NupCU in the word line group WLG0 becomes 7 (=12-5). In this state, since cell units CU(0,2) to CU(0,4) are end cell units, the execution of history value reads is skipped in read sequences that use these cell units CU as the sensed cell units. On the other hand, since cell units CU(0,0) to CU(0,1) are not end cell units, in read sequences that use these cell units CU as the sensed cell units, if a history value corresponding to the word line group WLG0 exists, the history value read is executed.

[0199] Furthermore, as shown in Figure 18(d), when cell units CU(0,5) to CU(0,8) are further programmed, the number of unprogrammed cell units NupCU in the word line group WLG0 becomes 3 (=12-9). In the state shown in Figure 18(d), all cell units CU connected to the word line group WLG0 are programmed.

[0200] Furthermore, as shown in Figure 18(e), when cell unit CU(1,0) is further programmed, the number of unprogrammed cell units NupCU in word line group WLG0 becomes 2 (=12-10). Also, the number of unprogrammed cell units NupCU in word line group WLG1 becomes 11 (=12-1).

[0201] Furthermore, as shown in Figure 18(f), when cell units CU(1,1) and CU(1,2) are also programmed, the number of unprogrammed cell units NupCU in word line group WLG0 becomes 0 (=12-12). At this time, none of the cell units CU connected to word line group WLG0 are end cell units. Also, the number of unprogrammed cell units NupCU in word line group WLG1 becomes 9 (=12-3).

[0202] As described above, in this embodiment, the number of unprogrammed cell units NupCU corresponding to the word line group WLG can take an integer value between 0 and (Nwl+1) × Nsu, depending on the programming status of block BLK. A number of unprogrammed cell units NupCU of 0 indicates that all cell units CU connected to the word line group WLG are programmed, and all cell units CU connected to the reference word line refWL of the word line group WLG are programmed. A number of unprogrammed cell units NupCU equal to (Nwl+1) × Nsu indicates that neither the word line group WLG nor any cell units CU connected to the reference word line refWL of the word line group WLG are programmed. Furthermore, a number of unprogrammed cell units NupCU equal to the number of string units Nsu indicates that all cell units CU connected to the word line group WLG are programmed, but none of the cell units CU connected to the reference word line refWL of the word line group WLG are programmed.

[0203] Furthermore, for the word line group WLG that is the last to be programmed in block BLK, the number of unprogrammed cell units NupCU indicates the programming status of the cell units CU connected to the word line group WLG. Specifically, if any of the cell units CU connected to the word line group WLG are not programmed, (the number of cell units CU connected to the word line group WLG that are not programmed) + Nsu is stored as the number of unprogrammed cell units NupCU. If all cell units CU connected to the word line group WLG are programmed, 0 is stored as the number of unprogrammed cell units NupCU. In other words, in this embodiment, the number of unprogrammed cell units NupCU for the word line group WLG that is the last to be programmed in block BLK can take the values ​​of 0 and integer values ​​between Nsu+1 and (Nwl+1)×Nsu.

[0204] Returning to Figure 17, let's explain an example of the history value table HT. The example in Figure 17 corresponds to the program status shown in Figure 18(f). For word line group WLG0, the number of unprogrammed cell units NupCU is 0, which indicates that all cell units CU connected to word line group WLG0 and its reference word lines refWL(WL0~WL3) are programmed. For word line group WLG1, the number of unprogrammed word lines NupWL is 9, which is 3 less than the initial value of 12. This indicates that among the cell units CU connected to the word lines WL and reference word lines refWL(WL3~WL6) included in word line group WLG1, the first to third programmed cell units CU(1,0)~CU(1,2) are programmed. Furthermore, for word line groups WLG2 to WLG4, the number of unprogrammed cell units NupCU is equal to the initial value (Nwl+1) × Nsu, which indicates that none of the cell units CU connected to word line groups WLG2 to WLG4 and their reference word lines refWL (WL6 to WL14) are programmed. Similarly, for word line group WLG5, the number of unprogrammed cell units NupCU is equal to the initial value (Nwl+1) × Nsu, which indicates that none of the cell units CU connected to the word lines (WL14 to WL15) included in word line group WLG5 are programmed.

[0205] Similar to the second embodiment, each entry in the history value table HT corresponds to one alignment area.

[0206] Furthermore, while the number of unprogrammed cell units (NupCU) is stored as the program status in the history value table HT shown in Figure 17, this is not the only way to store it. For example, the number of programmed cell units (CU) among the cell units (CU) connected to the word line group WLG and the reference word line refWL of the word line group WLG may be stored as the program status. Alternatively, the number of the word line WL that was last programmed among those cell units (CU), or information listing whether each cell unit (CU) is programmed or not, may be stored as the program status.

[0207] Furthermore, while the history value table HT shown in Figure 17 stores one history value for each word line group WLG, this is not limited to this. That is, for example, a number of history values ​​corresponding to the number of string units Nsu may be stored for each word line group WLG. In this case, the memory controller 200 can select a history value for each string unit containing a cell unit CU and use it for history value reading.

[0208] 3.2 Operation Next, the operation of the memory system according to this embodiment will be described. The examples of the history value read and learning read flows in this embodiment are the same as those in the first embodiment (described with reference to Figures 10 and 11, respectively), so the explanation will be omitted.

[0209] 3.2.1 Read Sequence First, an example of the read sequence in this embodiment will be described with reference to Figure 19. For steps in Figure 19 that are numbered the same as those in the first embodiment (Figure 8), the same processing as described in the first embodiment is performed. The description of these steps will be omitted.

[0210] In step S804, the memory controller 200 refers to the history value table HT to obtain the history value and program status of the word line group WLG identified in step S102. Specifically, in this embodiment, the memory controller 200 obtains the shift index as the history value and the number of unprogrammed cell units NupCU as the program status. The memory controller 200 identifies the history value table HT to be referenced from, for example, the block address included in the sense target address.

[0211] In step S900, the memory controller 200 determines whether the cell unit to be sensed is an end cell unit (hereinafter also referred to as end cell unit determination) based on the number of unprogrammed cell units NupCU obtained in step S804. Details of the end cell unit determination will be described later. If the end cell unit determination determines that the cell unit to be sensed is an end cell unit (Yes in step S806), this operation proceeds to step S400. On the other hand, if the end cell unit determination determines that the cell unit to be sensed is not an end cell unit (No in step S806), this operation proceeds to step S108.

[0212] 3.2.2 End cell unit determination Next, a specific example of the end cell unit determination flow in this embodiment will be described with reference to Figure 20. Figure 20 shows the end cell unit determination flow in particular when the history value table HT, as described with reference to Figure 17, is used. Steps S902 to S918 below correspond to step S900 in Figure 19.

[0213] When the terminal cell unit determination is initiated, in step S902, the read control unit 264 determines whether all cell units CU connected to the target word line group and the reference word line refWL of the target word line group are programmed. Specifically, for example, the read control unit 264 determines whether the acquired number of unprogrammed cell units NupCU is 0. If the acquired number of unprogrammed cell units NupCU is 0, that is, if all cell units CU connected to the target word line group and the reference word line refWL of the target word line group are programmed (Yes in step S902), the operation proceeds to step S918. On the other hand, if the acquired number of unprogrammed cell units NupCU is not 0, that is, if any of the cell units CU connected to the target word line group and the reference word line refWL of the target word line group are not programmed (No in step S902), the operation proceeds to step S904.

[0214] In step S904, the read control unit 264 identifies the range of end cell units in the target word line group. Specifically, for example, the read control unit 264 identifies the minimum value of the cell unit number of the end cell unit as edgeCUmin = Nwl × Nsu - NupCU. Also, for example, the read control unit 264 identifies the maximum value of the cell unit number of the end cell unit as edgeCUmax = edgeCUmin + Nsu - 1. Note that Nwl × Nsu is equal to the number of cell units CU included in the target word line group. The memory controller 200 may store this value for each word line group WLG, or it may calculate it in step S904. Alternatively, the memory controller 200 may calculate the maximum value of the cell unit number of the end cell unit as edgeCUmax = (Nwl + 1) × Nsu - NupCU - 1.

[0215] In step S906, the read control unit 264 determines whether the cell unit to be sensed is included in the range of edge cell units identified in step S904. Specifically, for example, the read control unit 264 determines whether edgeCUmin ≤ cell unit number to be sensed ≤ edgeCUmax. If edgeCUmin ≤ cell unit number to be sensed ≤ edgeCUmax, that is, if the cell unit to be sensed is included in the range of edge cell units identified in step S904 (Yes in step S906), the operation proceeds to step S908. On the other hand, if edgeCUmin ≤ cell unit number to be sensed ≤ edgeCUmax is not true, that is, if the cell unit to be sensed is not included in the range of edge cell units identified in step S904 (No in step S906), the operation proceeds to step S918.

[0216] In step S908, the read control unit 264 determines whether the selected word line SelWL is the last word line WL to be programmed in block BLK. Specifically, for example, the read control unit 264 determines whether the SelWL number is equal to WLmax. Here, WLmax is the word line number with the largest value among the word line numbers of the word lines WL included in block BLK. If the SelWL number is equal to WLmax, that is, if the selected word line SelWL is the last word line WL to be programmed in block BLK (Yes in step S908), the operation proceeds to step S918. On the other hand, if the SelWL number is not equal to WLmax, that is, if the selected word line SelWL is not the last word line WL to be programmed in block BLK (No in step S908), the operation proceeds to step S916. Note that this step may only be performed if the target word line group is the word line group WLG to be programmed in block BLK.

[0217] In step S916, the read control unit 264 determines that the cell unit to be sensed is an end cell unit, and this operation ends.

[0218] In step S918, the read control unit 264 determines that the cell unit to be sensed is not an end cell unit, and this operation ends.

[0219] 3.2.3 Light Processing Next, an example of the write process in this embodiment will be described with reference to Figure 21. Figure 21 shows the flow of the write process when the memory system 1 uses the history value table HT as described with reference to Figure 17. For steps in Figure 21 that are numbered the same as the steps in the first embodiment (Figure 12), the same processing as described in those embodiments is performed. The description of those steps (steps S500 to S508) will be omitted. Also, for steps in Figure 21 that are numbered the same as the steps in the second embodiment (Figure 16), a detailed explanation may be omitted.

[0220] In step S1010, the memory controller 200 updates the program status in the history value table HT for the target word line group identified in step S508. Specifically, the memory controller 200 decrements the number of unprogrammed cell units NupCU of the target word line group by 1, for example, when a cell unit CU to be programmed becomes programmed.

[0221] In step S712, the memory controller 200 determines whether the selected word line SelWL is the last word line WL to be programmed in block BLK. If the selected word line SelWL is the last word line WL to be programmed in block BLK (Yes in step S712), the operation proceeds to step S1013. On the other hand, if the selected word line SelWL is not the last word line WL to be programmed in block BLK (No in step S712), the operation proceeds to step S716.

[0222] In step S1013, the memory controller 200 determines whether all cell units CU of the target word line group have been programmed. Specifically, for example, the memory controller 200 determines whether the number of unprogrammed cell units NupCU ≤ Nsu. However, this number of unprogrammed cell units NupCU is the value after it was updated in step S1010. If NupCU ≤ Nsu, that is, if all cell units CU of the target word line group have been programmed (Yes in step S1013), the operation proceeds to step S1014. On the other hand, if NupCU ≤ Nsu, that is, if any of the cell units CU of the target word line group have not been programmed (No in step S1013), the operation ends.

[0223] In step S1014, the memory controller 200 updates the program status in the history value table HT for the target word line group. Specifically, the memory controller 200 sets the number of unprogrammed cell units NupCU for the target word line group to 0. As a result of this step, for the word line group WLG that is the last to be programmed in block BLK, the number of unprogrammed cell units NupCU becomes 0 when all cell units CU included in the word line group WLG have been programmed.

[0224] In step S716, the memory controller 200 determines whether the selected word line SelWL is the first word line WL to be programmed in the target word line group. If the selected word line SelWL is the first word line WL to be programmed in the target word line group (Yes in step S716), the operation proceeds to step S718. On the other hand, if the selected word line SelWL is not the first word line WL to be programmed in the target word line group (No in step S716), the operation terminates.

[0225] In step S718, the memory controller 200 determines whether the selected word line SelWL is the first word line WL to be programmed in block BLK. If the selected word line SelWL is the first word line WL to be programmed in block BLK (Yes in step S718), this operation terminates. On the other hand, if the selected word line SelWL is not the first word line WL to be programmed in block BLK (No in step S718), this operation proceeds to step S1020.

[0226] In step S1020, the memory controller 200 updates the number of unprogrammed cell units NupCU of the previous word line group WLGpre of the target word line group. Specifically, in step S1020, if the target word line group is word line group WLGn (where n is an integer of 1 or more), the memory controller 200 decrements the number of unprogrammed cell units NupCU of word line group WLG(n-1) by 1. This step ensures that the program status of the cell unit CU connected to the reference word line refWL of the word line group WLG is reflected in the program status of the word line group WLG stored in the history value table HT.

[0227] Light processing is complete.

[0228] In the write process, the memory controller 200 updates the program status of the target word line group if the selected word line SelWL is the last word line WL to be programmed in the word line group WLG, and all cell units CU of the target word line group have been programmed (Yes in step S1013), but it is not limited to this. That is, for example, instead of incorporating the above step into the write process, a step to determine whether or not the sense target block BLK is programmed may be incorporated into the end word line determination. In this case, for the word line group WLG that is the last to be programmed in block BLK, if the word line group WLG is programmed, Nsu is stored as the number of unprogrammed cell units NupCU.

[0229] 3.4 Effects In the memory system according to this embodiment, the program status is stored in the history value table HT in units smaller than the word line WL, and the execution decision for reading history values ​​is made in those units. Specifically, in this embodiment, the program status is stored in units of cell units CU, and the execution decision for reading history values ​​is made in units of cell units CU.

[0230] This allows the memory controller to make decisions about performing history value reads based on a more detailed reference to the status of surrounding memory cells.

[0231] In this embodiment, an example was described in which the memory controller 200 stores the program status in units of cell units CU and uses this for determining whether to perform a history value read, but this is not limited to this. That is, the memory controller 200 may, for example, store the program status in units of pages and use this for determining whether to perform a history value read.

[0232] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0233] 1...Memory system, 100...NAND flash memory, 110...Memory cell array, 120...Peripheral circuitry, 200...Memory controller, 210...Host interface circuitry, 220...NAND interface circuitry, 230...Main memory, 240...Buffer memory, 250...ECC circuitry, 260...Processor, 262...Write control unit, 264...Read control unit, 266...Erase control unit, 270...Cache memory, 300...Host, AT...Address table, HT...History value table, ST...Shift table, WT...Word line group assignment table

Claims

1. Memory cell array and A peripheral circuit that controls the memory cell array, A memory controller electrically connected to the aforementioned peripheral circuit, Main memory included in or electrically connected to the memory controller, It is equipped with, The memory cell array is Multiple word lines, Multiple non-volatile memory cells connected to the aforementioned multiple word lines, Equipped with, The main memory includes a first memory region which is the unit of access by the memory controller. The aforementioned memory controller The plurality of word lines are configured to be classified into at least one group of word lines, The first word line group among the at least one word line group includes the first word line among the plurality of word lines, The plurality of non-volatile memory cells include a first group of non-volatile memory cells connected to the first group of word lines, The first word line is connected to the first non-volatile memory cell of the first non-volatile memory cell group, The aforementioned memory controller further, The first information, including the program status of the first non-volatile memory cell group, and the first candidate value are stored in the first memory area. Based on the first information, it is determined whether or not to perform the first read operation. In response to the decision to perform the first read operation, A first read command is sent to the peripheral circuit to instruct it to perform a sense operation using the first candidate value. The aforementioned peripheral circuitry is Upon receiving the first read command from the memory controller, The system is configured to perform a sense operation from the first non-volatile memory cell using the first candidate value. Memory system.

2. The first group of word lines further includes a second word line among the plurality of word lines, The second word line is connected to the second non-volatile memory cell of the first non-volatile memory cell group, The aforementioned memory controller Based on the first information, it is determined whether or not to perform the second read operation. In accordance with the decision to perform the second read operation, A second read command is sent to the peripheral circuit to instruct it to perform a sense operation using the first candidate value. The aforementioned peripheral circuitry is Upon receiving the second read command from the memory controller, The system is further configured to perform a sense operation from the second non-volatile memory cell using the first candidate value. The memory system according to claim 1.

3. The aforementioned memory controller After programming data into the first non-volatile memory cell, data is programmed into the second non-volatile memory cell. The system is configured to decide to perform the first read operation if the first information indicates that the second non-volatile memory cell is programmed. The memory system according to claim 2.

4. The aforementioned memory controller If the first information indicates that the second non-volatile memory cell is not programmed, it is configured to decide to perform a learn read on the first word line. The memory system according to claim 3.

5. The plurality of word lines further include a third word line that is not included in the first group of word lines, The third word line is connected to the third non-volatile memory cell among the plurality of non-volatile memory cells, The first information further includes the program status of the third non-volatile memory cell. The memory system according to claim 3.

6. The aforementioned memory controller The system is configured to change the first information in response to any of the first nonvolatile memory cells being programmed. The memory system according to claim 5.

7. The aforementioned memory controller The third non-volatile memory cell is further configured to modify the first information in response to being programmed. The memory system according to claim 6.

8. The aforementioned memory controller After programming data into the second non-volatile memory cell, data is programmed into the third non-volatile memory cell. The system is configured to decide to perform the second read operation if the first information indicates that the third non-volatile memory cell is programmed. The memory system according to claim 7.

9. The aforementioned memory controller If the first information indicates that the third non-volatile memory cell is not programmed, it is configured to decide to perform a learn read on the second word line. The memory system according to claim 8.

10. The second word line is adjacent to the first word line, The third word line is adjacent to the second word line. The memory system according to claim 9.

11. The memory cell array includes a first block which is the unit of data erasure operation, The plurality of non-volatile memory cells and the plurality of word lines are included in the first block. The aforementioned memory controller The system is configured to change the first information to a first initial value in response to the erasure operation performed on the first block. The memory system according to claim 8.

12. The first group of word lines includes n word lines (where n is an integer of 2 or more) from among the plurality of word lines, The memory system according to claim 11, wherein each of the n word lines is adjacent to any of the other n-1 word lines included in the first group of word lines.

13. The first non-volatile memory cell group includes n non-volatile memory cells, one connected to each of the n word lines. The first piece of information is an integer value, The first initial value is n+1, The aforementioned memory controller Depending on whether any of the n nonvolatile memory cells is programmed, the first information is decremented by 1. In response to the third non-volatile memory cell being programmed, the first information is decremented by 1. If the first piece of information is 0, It is decided to perform the first read operation described above, The system is configured to decide to perform the second read operation described above. The memory system according to claim 12.

14. The first block includes k string units (where k is an integer of 2 or more) each containing the plurality of nonvolatile memory cells. The first non-volatile memory cell, the second non-volatile memory cell, and the third non-volatile memory cell are included in the first string unit among the k string units. The memory system according to claim 12.

15. The aforementioned plurality of non-volatile memory cells are n × k non-volatile memory cells connected to each of the n word lines, k non-volatile memory cells connected to the third word line, Includes, The n × k non-volatile memory cells are each contained in the k string units, The k non-volatile memory cells connected to the third word line are each included in the k string units, The first piece of information is an integer value, The first initial value is (n+1) × k, The aforementioned memory controller Depending on whether any of the n × k nonvolatile memory cells is programmed, the first information is decremented by 1. Depending on whether any of the k non-volatile memory cells connected to the third word line is programmed, the first information is decremented by 1. If the first piece of information is 0, It is decided to perform the first read operation described above, The system is configured to decide to perform the second read operation described above. The memory system according to claim 14.

16. The first candidate value is a value that indicates the conditions under which a sense operation from any of the first non-volatile memory cells in the group of non-volatile memory cells was successful. The memory system according to any one of claims 2 to 15.

17. The first candidate value is a shift amount that indicates a first voltage applied to one of the word lines in the first group of word lines connected to one of the nonvolatile memory cells when a sense operation from one of the nonvolatile memory cells is successful. The memory system according to claim 16.

18. The aforementioned peripheral circuitry is Upon receiving the first read command from the memory controller, By applying the first voltage to the first word line, a sense operation is performed from the first non-volatile memory cell. Upon receiving the second read command from the memory controller, The system is configured to perform a sense operation from the second non-volatile memory cell by applying the first voltage to the second word line. The memory system according to claim 17.

19. The memory cell array is circuit board and A memory pillar is provided extending in a first direction perpendicular to the substrate, It further includes, The plurality of word lines are stacked spaced apart from each other in the first direction, The plurality of non-volatile memory cells are located at the intersection of the memory pillar and the plurality of word lines, The first word line, the second word line, and the third word line are stacked in the order of the first word line, the second word line, and the third word line, starting from the side closest to the substrate, or in the order of the third word line, the second word line, and the first word line. The memory system according to any one of claims 5 to 15.

20. The aforementioned memory controller includes cache memory, The cache memory includes a plurality of cache lines, each capable of storing data having a first size, The access speed of the memory controller to the cache memory is greater than the access speed of the memory controller to the main memory. The first memory area is capable of storing data having the first size, The aforementioned memory controller The data stored in the first memory area is further configured to be stored in the first cache line among the plurality of cache lines. The memory system according to any one of claims 1 to 15.

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