Method for selecting light-emitting diodes

Abstract

This provides an innovative method for sorting light-emitting diodes. [Solution] A method for selecting light-emitting diodes is provided, comprising the steps of: S01 preparing a wafer having multiple light-emitting diode structures; S03 performing a wafer-level electrostatic discharge test on the light-emitting diode structures on the wafer; S03 performing a wafer-level decay voltage test on the light-emitting diode structures on the wafer; S03 performing a wafer-level photoelectric characteristics test on the light-emitting diode structures on the wafer; S04 dividing the light-emitting diode structures on the wafer to form multiple light-emitting diode dies; and S06 removing abnormal light-emitting diode dies from among the light-emitting diode dies. The abnormalities include electrostatic discharge test abnormalities, decay voltage test abnormalities, photoelectric characteristics test abnormalities, or appearance abnormalities.

Description

Technical Field

[0001] The present invention relates to a method for sorting light-emitting diodes, and particularly to a method for reducing the detection leakage rate of defective dies in the process of sorting light-emitting diodes.

Background Art

[0002] Light-emitting diodes (LEDs) have advantages such as high optical efficiency, long lifespan, small size, and specific spectral distribution, and are widely applied in optical fields such as lighting and displays. Therefore, for LED chip manufacturers, improving production efficiency, reducing the defective rate, and ensuring that the final products provided to downstream module manufacturers meet the acceptance criteria have become urgent goals that the industry should currently achieve.

[0003] FIG. 1 is a flowchart of a conventional method for sorting LED chips. In this manufacturing process, mainly all LED structures that are not yet divided but already formed on the wafer are subjected to a full inspection of their optoelectronic characteristics. These inspections include VF (Forward Voltage), IF (Forward Current), VR (Reverse Voltage), IR (Reverse Current), WLD (Wavelength of Dominant Emission), LOP (Light Output Power), etc. These inspections are the main quality control means for evaluating the optoelectronic performance of LEDs. After the optoelectronic characteristics inspection is completed, a cutting and dividing process is carried out to form individual dies, and then inspections such as electrostatic discharge (ESD) are performed.

[0004] Current ESD testing methods involve sampling tests after LED dies have been packaged in TO CAN (Transistor Outline Package) form. Due to the limitations of TO CAN packaging, the ESD testing process is redundant, and conventional manufacturing processes cannot perform 100% inspection on all produced LED dies; testing can only be done using a sampling method. This increases the likelihood that defective LED chips will be shipped downstream in the supply chain. Therefore, reducing the defect rate of LED products supplied downstream in the supply chain is an urgent issue that needs to be addressed now. [Overview of the project]

[0005] The main objective of the present invention is to provide an innovative method for sorting light-emitting diodes. Through the improved sorting process, the present invention can perform 100% inspection of all LED structures or LED dies before and after splitting, including electrostatic discharge tests and collapse voltage tests, thereby reducing the number of defective LED dies that flow into subsequent processes and improving production efficiency.

[0006] To achieve the above objective, the present invention provides a method for selecting light-emitting diodes, comprising the following steps: First, a wafer having multiple light-emitting diode structures is prepared. Next, a wafer-level electrostatic discharge test is performed on the light-emitting diode structures on the wafer. Next, a wafer-level decay voltage test is performed on the light-emitting diode structures on the wafer. A wafer-level photoelectric characteristics test is performed on the light-emitting diode structures on the wafer. The light-emitting diode structures on the wafer are divided to form multiple light-emitting diode dies. Finally, any abnormal light-emitting diode dies are removed from the light-emitting diode dies. The abnormalities include electrostatic discharge test abnormalities, decay voltage test abnormalities, photoelectric characteristics test abnormalities, or appearance abnormalities.

[0007] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a semi-cutting step of forming a plurality of cut lines between each adjacent light-emitting diode structure before performing a wafer-level electrostatic discharge test.

[0008] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a step of performing an electrostatic discharge capability test on a portion of the light-emitting diode structure to determine the electrostatic discharge capability level of the portion of the light-emitting diode structure, prior to the step of performing a wafer-level electrostatic discharge test.

[0009] In the light-emitting diode selection method of the embodiment of the present invention, the step of performing a wafer-level electrostatic discharge test is performed on each light-emitting diode structure based on the electrostatic discharge capability level.

[0010] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a step of performing a decay voltage capability test on a portion of the light-emitting diode structure to determine the decay voltage capability level of the portion of the light-emitting diode structure, prior to the step of performing a wafer-level decay voltage test.

[0011] In the light-emitting diode selection method of the embodiment of the present invention, the step of performing a wafer-level decay voltage test is performed on each light-emitting diode structure based on its decay voltage capability level.

[0012] To achieve the above objective, the present invention provides a method for selecting light-emitting diodes, comprising the following steps: First, a wafer having multiple light-emitting diode structures is prepared. Next, the light-emitting diode structures on the wafer are divided to form multiple light-emitting diode dies. Next, a die-level electrostatic discharge test is performed on each light-emitting diode die, a die-level decay voltage test is performed on each light-emitting diode die, and a die-level photoelectric characteristic test is performed on each light-emitting diode die. Finally, any abnormal light-emitting diode dies are removed from the list of abnormal light-emitting diode dies. The abnormalities include electrostatic discharge test abnormalities, decay voltage test abnormalities, photoelectric characteristic test abnormalities, or appearance abnormalities.

[0013] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a semi-cutting step of forming a plurality of cut lines between adjacent light-emitting diode structures, prior to the step of dividing the light-emitting diode structure on the wafer.

[0014] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a step of performing an electrostatic discharge capability test on a portion of the light-emitting diode dies to determine the electrostatic discharge capability level of the portion of the light-emitting diode dies, prior to the step of performing a die-level electrostatic discharge test.

[0015] In the method for selecting light-emitting diodes according to the embodiment of the present invention, the step of performing a die-level electrostatic discharge test involves performing a test on each light-emitting diode die based on its electrostatic discharge capability level.

[0016] The method for selecting light-emitting diodes according to an embodiment of the present invention further includes a step of performing a decay voltage capability test on a portion of the light-emitting diode dies to determine the decay voltage capability level of the portion of the light-emitting diode dies, prior to the step of performing a die-level decay voltage test.

[0017] In the method for selecting light-emitting diodes according to an embodiment of the present invention, the step of performing a die-level decay voltage test involves performing a test on each light-emitting diode die based on its decay voltage capability level.

[0018] Those skilled in the art will be able to understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described later. [Brief explanation of the drawing]

[0019] [Figure 1] Flowchart of a conventional method for sorting light-emitting diode chips [Figure 2] Flowchart of a method for selecting light-emitting diodes in an embodiment of the present invention [Figure 3] Detailed flowchart of step S03 in Figure 2 in an embodiment of the present invention [Figure 4A]Top surface image of a light-emitting diode die that passed the test [Figure 4B] Scanning electron microscope image of the peripheral cross-section of a light-emitting diode die that passed the test [Figure 4C] Top surface image of a light-emitting diode die that failed the test [Figure 4D] Scanning electron microscope image of the peripheral cross-section of a light-emitting diode die that failed the test [Figure 5A] Top surface image of a light-emitting diode die that passed the test [Figure 5B] Scanning electron microscope image of the central cross-section of a light-emitting diode die that passed the test [Figure 5C] Top surface image of a light-emitting diode die that failed the test [Figure 5D] Scanning electron microscope image of the central cross-section of a light-emitting diode die that failed the test [Figure 6] Flowchart of the method for sorting light-emitting diodes according to another embodiment of the present invention [Figure 7] Detailed flowchart of step S14 in FIG. 6 according to another embodiment of the present invention

Mode for Carrying Out the Invention

[0020] Hereinafter, the content of the present invention will be described through examples. Note that the examples of the present invention are examples of embodiments, and are not intended to be limited to the environments, applications, or specific aspects as described in the examples. Therefore, the description of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and the drawings, components not directly related to the present invention are omitted and not shown. The dimensional relationships of the components in the drawings are for facilitating understanding and do not limit the actual dimensions.

[0021] Figure 2 is a flowchart of a method for selecting light-emitting diodes in an embodiment of the present invention. As shown in the figure, in step S01, a wafer is prepared. This wafer has already undergone compound semiconductor epitaxial processes such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), as well as subsequent processes such as patterning and metallization. Multiple light-emitting diode structures are present on the wafer before cutting and splitting. In step S02, the wafer is partially cut to form multiple cutting lines between adjacent light-emitting diode structures on the wafer. Next, in step S03, a wafer-level electrostatic discharge (ESD) test and a wafer-level Zener Breakdown Voltage (Vz) test are performed on all pre-cutting and splitting light-emitting diode structures between each cutting line on the wafer. After these two tests are completed, a wafer-level photoelectric properties test is similarly performed on all pre-cutting and splitting light-emitting diode structures. The photoelectric properties test includes inspections of VF, IF, VR, IR, WLD, LOP, etc. Note that "wafer level" refers to the light-emitting diode structure that has not yet been cut or divided on the wafer.

[0022] Refer to Figure 3 for explanation. Process S03 is divided into four sub-processes. In process S03-1, a wafer-level electrostatic discharge capability test is performed. This ESD capability test is not performed on all light-emitting diode structures on the wafer, but only on a portion of the light-emitting diode structures on the wafer. Based on the test results, the electrostatic discharge capability level that the tested light-emitting diode structure can withstand and not be destroyed by electrostatic discharge is determined. Once the ESD capability test is completed, the electrostatic discharge capability level of the light-emitting diode structures on this wafer can be determined, and this will be used as the standard for the subsequent 100% inspection ESD test.

[0023] In step S03-2, a wafer-level decay voltage capability test is performed. Similarly, this step performs a Vz capability test on only a portion of the light-emitting diode (LED) structures on the wafer. Based on the test results, the decay voltage capability level that the LED structure under test can withstand and that will not be destroyed by reverse voltage is determined. This determines the decay voltage capability level and serves as the basis for the Vz test during subsequent full inspection.

[0024] In step S03-3, wafer-level electrostatic discharge testing and wafer-level decay voltage testing are performed on all light-emitting diode (LED) structures on the wafer. In other words, based on the electrostatic discharge capability level and decay voltage capability level determined in the previous two steps, 100% ESD testing and 100% Vz testing are performed on all LED structures.

[0025] In process S03-4, a 100% wafer-level photoelectric characteristics inspection is performed on all light-emitting diode (LED) structures on the wafer. The inspection includes VF, IF, VR, IR, WLD, LOP, etc. These inspections reveal the electrical performance and photoelectric characteristics of the LEDs and allow for the identification of the location of defective LED structures on the wafer.

[0026] As shown in Figure 2, in step S04, after completing 100% inspection of ESD, Vz, and photoelectric characteristics for multiple light-emitting diode structures, the wafer is cut and divided along the cutting line to form multiple light-emitting diode dies. Next, in step S05, light-emitting diode dies are sorted based on the photoelectric characteristic results tested in the previous step, and automated optical inspection (AOI) is performed. Also, after the ESD and Vz tests in step S03, defective products that fail the test (No Good) have abnormal appearances. Subsequently, in step S06, all defective products with abnormalities are removed by automated optical inspection or visual inspection. Abnormalities refer to abnormalities in the electrostatic discharge test, decay voltage test, photoelectric characteristic test, appearance, or a combination thereof. Finally, in step S07, after removing the unacceptable products, light-emitting diode dies that pass the tests can be selected.

[0027] The following explanation will be given with reference to Figures 4A, 4B, 4C, and 4D. Figure 4A is a top view image of a light-emitting diode die that passed the test. Figure 4B is a scanning electron microscope (SEM) image of the peripheral cross-section within the frame of the die that passed the test in Figure 4A. Figure 4C is a top view image of a light-emitting diode die that failed the test. Figure 4D is a scanning electron microscope image of the peripheral cross-section of the failed die. The frames in Figures 4C and 4D clearly show defects caused by electrostatic discharge damage to the die's periphery. The following explanation will also be given with reference to Figures 5A, 5B, 5C, and 5D. Figure 5A is a top view image of a light-emitting diode die that passed the test. Figure 5B is a scanning electron microscope image of the central cross-section within the frame of the die that passed the test in Figure 5A. Figure 5C is a top view image of a light-emitting diode die that failed the test. Figure 5D is a scanning electron microscope image of the central cross-section of the failed die. The frames in Figures 5C and 5D clearly show defects caused by electrostatic discharge damage to the center of the die. In steps S05 and S06, this defect is identified by AOI or visual inspection. Then, unacceptable dies are selected and removed.

[0028] Figure 6 is a flowchart of a light-emitting diode sorting method in another embodiment of the present invention. This embodiment is almost identical to the embodiment shown in Figure 2. The only difference is that in the embodiment shown in Figure 2, the object being tested for ESD, Vz, and photoelectric characteristics is a light-emitting diode structure at the wafer stage, whereas in the embodiment shown in Figure 6, the object being tested for ESD, Vz, and photoelectric characteristics is a light-emitting diode die at the die stage. Details are as follows.

[0029] As shown in the figure, a wafer is prepared in step S11. This wafer has already undergone compound semiconductor epitaxial processes such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), as well as subsequent patterning and metallization processes. Therefore, multiple uncut light-emitting diode structures exist on the wafer. In step S12, the wafer is partially cut. Multiple cutting lines are formed between each adjacent light-emitting diode structure on the wafer. In step S13, the wafer is cut and divided along the cutting lines to form multiple light-emitting diode dies.

[0030] Next, in process S14, die-level electrostatic discharge testing and die-level collapse voltage testing are performed on all light-emitting diode dies. After these two tests are completed on all dies, die-level photoelectric characteristic testing is performed on all light-emitting diode dies. The tests include inspection of VF, IF, VR, IR, WLD, LOP, etc. Note that "die level" refers to the light-emitting diode die whose die structure has already been cut and divided.

[0031] This will be explained with reference to Figure 7. In Figure 7, process S14 is further divided into four sub-processes. In process S14-1, a die-level electrostatic discharge capability test is performed. This ESD capability test is not performed on all light-emitting diode dies, but only on a subset of them. Based on the test results, the electrostatic discharge capability level that these tested light-emitting diode dies can withstand and that will not be destroyed by electrostatic discharge is determined. Once the ESD capability test is completed, the electrostatic discharge capability level of the light-emitting diode dies can be determined. This level will serve as the standard for subsequent ESD tests during 100% inspection.

[0032] In process S14-2, a die-level decay voltage capability test is performed. This process performs a Vz capability test on only some of the light-emitting diode dies. Based on the test results, the decay voltage capability level that these tested light-emitting diode dies can withstand and that will not be destroyed by reverse voltage is determined. The determined decay voltage capability level will be used as the basis for the Vz test during the 100% inspection of all subsequent dies.

[0033] In step S14-3, die-level electrostatic discharge testing and die-level decay voltage testing are performed on all light-emitting diode dies. In other words, based on the electrostatic discharge capability level and decay voltage capability level determined in the previous two steps, 100% ESD testing and 100% Vz testing are performed on all light-emitting diode dies.

[0034] In process S14-4, a 100% die-level photoelectric characteristics inspection is performed on all light-emitting diode dies. The inspection includes test items to understand the electrical performance and photoelectric characteristics of the light-emitting diode, such as VF, IF, VR, IR, WLD, and LOP.

[0035] The contents of steps S15, S16, and S17 are substantially the same as those of steps S05, S06, and S07. Please refer to the contents described above. They will not be repeated here. Furthermore, when implementing an established manufacturing process for light-emitting diodes, if the business operator is familiar with the photoelectric characteristics of the product and can determine the electrostatic discharge capability level and decay voltage capability level of the product in advance, the process of determining the ESD capability level and Vz capability level in steps S03-1 and S03-2 in Figure 3, or in steps S14-1 and S14-2 in Figure 7, can be omitted in the sorting procedure, and 100% inspection of ESD, Vz, and photoelectric characteristics can be performed directly. On the other hand, if it is found that the overall product defect rate has increased after performing steps S05 and S06 in Figure 2, or steps S14-1 and S14-2 in Figure 6, then it is necessary to repeat steps S03-1 and S03-2 in Figure 3, or steps S14-1 and S14-2 in Figure 7, and repeat the process of determining the ESD capability level and Vz capability level. Subsequently, based on the preferred ESD capability level and Vz capability level, the products should be re-selected to prevent defective products from being shipped downstream in the supply chain.

[0036] Specific examples of the LED sorting method of the present invention will be described with reference to Table 1 below. Table 1 shows the results of performing different ESD capability level tests at 2100 to 2600 V on approximately 72,000 LED dies and applying a reverse current of 100 μA and 25 V. According to the test results, the rejection rate detected by 100% inspection of ESD, Vz capability level, and photoelectric characteristics was 1.329% to 1.552%. The number of rejects was 959 to 1121. When products that passed the initial sorting were subjected to three more ESD tests at 2000 V to confirm the results of the initial sorting, Table 1 shows that the rejection rate due to ESD inspection decreased significantly to 0.006% to 0.015%. The number of rejects was only 4 to 11. In other words, there are only a very small number of rejects among the products that passed the initial sorting. In contrast, in the control group that did not employ the present invention, after checking the results following the initial sorting, a rejection rate of 1.423% was found, with more than 300 rejected items being discovered. Compared to conventional methods, the present invention can effectively remove rejected items, prevent them from entering the downstream supply chain, and improve the yield of shipped products. [Table 1]

[0037] In summary, the present invention's light-emitting diode sorting method allows for rigorous electrostatic discharge testing and collapse voltage testing of all LED structures or LED dies before and after splitting. Through this rigorous 100% inspection process, defective products are completely eliminated, reducing the number of unacceptable dies that flow into subsequent processes, thereby significantly improving production efficiency. The present invention overcomes the problem that conventional sorting methods can only perform sample inspections due to the constraints of LED packaging, reducing the rate of undetected defects and thereby improving the yield of products supplied to the supply chain.

[0038] The above-described embodiments illustrate embodiments of the present invention and describe the characteristic configuration of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the claims. [Explanation of Symbols]

[0039] S01,S02,S03,S03-1,S03-2,S03-3,S03-4,S04,S05,S06,S07,S11,S12,S13,S14,S,14-1,S14-2,S14-3,S14-4,S15,S16,S17 Process

Claims

1. A method for selecting light-emitting diodes, A process for preparing a wafer having multiple light-emitting diode structures, A step of performing a wafer-level electrostatic discharge test on the light-emitting diode structure on the wafer, A step of performing a wafer-level decay voltage test on the light-emitting diode structure on the wafer, A step of performing a wafer-level photoelectric characteristics test on the light-emitting diode structure on the wafer, A step of dividing the light-emitting diode structure on the wafer to form a plurality of light-emitting diode dies, The process includes removing any defective light-emitting diode dies from the aforementioned light-emitting diode dies, A method for selecting light-emitting diodes, wherein the abnormality includes an abnormality in the electrostatic discharge test, an abnormality in the decay voltage test, an abnormality in the photoelectric characteristics test, or an abnormality in appearance.

2. The method for selecting light-emitting diodes according to claim 1, further comprising a semi-cutting step of forming a plurality of cut lines between each adjacent light-emitting diode structure before the step of performing a wafer-level electrostatic discharge test.

3. The method for selecting light-emitting diodes according to claim 1, further comprising the step of performing an electrostatic discharge capability test on a portion of the light-emitting diode structure before performing a wafer-level electrostatic discharge test, and determining the electrostatic discharge capability level of the portion of the light-emitting diode structure.

4. The method for selecting light-emitting diodes according to claim 3, characterized in that the step of performing a wafer-level electrostatic discharge test is performed on each of the light-emitting diode structures based on the electrostatic discharge capability level.

5. The method for selecting light-emitting diodes according to claim 1, further comprising the step of performing a decay voltage capability test on a portion of the light-emitting diode structure before performing a wafer-level decay voltage test, and determining the decay voltage capability level of the portion of the light-emitting diode structure.

6. The method for selecting light-emitting diodes according to claim 5, characterized in that the step of performing a wafer-level decay voltage test is performed on each light-emitting diode structure based on the decay voltage capability level.

7. A method for selecting light-emitting diodes, A process for preparing a wafer having multiple light-emitting diode structures, A step of dividing the light-emitting diode structure on the wafer to form a plurality of light-emitting diode dies, A step of performing a die-level electrostatic discharge test on each of the light-emitting diode dies, A step of performing a die-level collapse voltage test on each of the light-emitting diode dies, A step of performing a die-level photoelectric characteristic test on each of the light-emitting diode dies, The process includes removing any defective light-emitting diode dies from the aforementioned light-emitting diode dies, A method for selecting light-emitting diodes, wherein the abnormality includes an abnormality in the electrostatic discharge test, an abnormality in the decay voltage test, an abnormality in the photoelectric characteristics test, or an abnormality in appearance.

8. The method for selecting light-emitting diodes according to claim 7, further comprising a semi-cutting step of forming a plurality of cutting lines between adjacent light-emitting diode structures before the step of dividing the light-emitting diode structure on the wafer.

9. The method for selecting light-emitting diodes according to claim 7, further comprising the step of performing an electrostatic discharge capability test on a portion of the light-emitting diode die before performing a die-level electrostatic discharge test, thereby determining the electrostatic discharge capability level of the portion of the light-emitting diode die.

10. The method for selecting light-emitting diodes according to claim 9, characterized in that the step of performing a die-level electrostatic discharge test is performed on each of the light-emitting diode dies based on the electrostatic discharge capability level.

11. The method for selecting light-emitting diodes according to claim 7, further comprising the step of performing a decay voltage capability test on a portion of the light-emitting diode die before performing a die-level decay voltage test, and determining the decay voltage capability level of the portion of the light-emitting diode die.

12. The method for selecting light-emitting diodes according to claim 11, characterized in that the step of performing a die-level collapse voltage test is performed on each of the light-emitting diode dies based on the collapse voltage capability level.

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