Semiconductor devices, electronic equipment

Abstract

It suppresses malfunctions caused by switching noise. [Solution] The semiconductor device 10 includes, for example, a first analog circuit 16 that operates in synchronization with a first clock CLK1 having a first frequency f1, and a second analog circuit 17 configured to operate in synchronization with a second clock CLK2 having a second frequency f2. The second frequency f2 is the same as or a constant multiple of the first frequency f1. The timing at which the logic level of the first clock CLK1 switches is different from the timing at which the logic level of the second clock CLK2 switches.

Description

Technical Field

[0007] , , [Figure 4] , , , , ,

[0001] The present disclosure relates to a semiconductor device and an electronic device.

Background Art

[0002] An analog circuit that operates in synchronization with a clock can be integrated in a semiconductor device.

[0003] As an example of the prior art related to the above, Patent Document 1 can be cited.

Prior Art Document

Patent Document

[0004]

Patent Document 1

[0005] [Summary] However, there has been room for improvement in countermeasures against switching noise in analog circuits in conventional semiconductor devices.

[0006] The semiconductor device according to the present disclosure includes a first analog circuit configured to operate in synchronization with a first clock having a first frequency, and a second analog circuit configured to operate in synchronization with a second clock having a second frequency, where the second frequency is the same as or an integer multiple of the first frequency, and the timing at which the logic level of the first clock switches is different from the timing at which the logic level of the second clock switches.

Brief Description of Drawings

[0007] [Figure 1] FIG. 1 is a diagram showing the overall configuration of an electronic device. [Figure 2] FIG. 2 is a diagram showing a configuration example of an auto-zero amplifier. [Figure 3] FIG. 3 is a diagram showing a configuration example of a charge pump. [Figure 4]Figure 4 shows a first example of operation of the semiconductor device 10. [Figure 5] Figure 5 shows a second example of operation of the semiconductor device 10.

[0008] [Detailed explanation] <Electronic equipment> Figure 1 shows the overall configuration of electronic device 1. In this example, electronic device 1 comprises a semiconductor device 10, a switch output stage 20, a motor 30, and various discrete components, in this figure, capacitors C1 and C2, and a sense resistor Rcs. Electronic device 1 may, for example, be an in-vehicle device.

[0009] The semiconductor device 10 generates the drive signals for the switch output stage 20, namely the upper gate signals G1H and G2H and the lower gate signals G1L and G2L. The semiconductor device 10 can be understood as a so-called pre-driver IC (integrated circuit).

[0010] The semiconductor device 10 is equipped with external terminals T1 to T18 as means for establishing an electrical connection with the outside of the device. An external power supply voltage VCC may be applied to external terminal T1. An ECU (electronic control unit) not shown may be connected to external terminal T2. Multiple external terminals T2 may be provided depending on the communication protocol. A reference voltage REF may be applied to external terminal T3. An analog output signal AOUT may be applied to external terminal T4. A ground voltage GND may be applied to external terminal T5.

[0011] A capacitor C2 may be connected between external terminals T6 and T7. An external power supply voltage VB may be applied to external terminal T6. The external power supply voltage VB may be the battery voltage. A boost voltage VCP may be applied to external terminal T7.

[0012] A capacitor C1 may be connected between external terminals T8 and T9. Capacitor C1 may be understood as a flying capacitor. An upper charge pump voltage CPH may be applied to external terminal T8. A lower charge pump voltage CPL may be applied to external terminal T9.

[0013] The upper gate signal G1H may be applied to external terminal T10. The upper gate signal G2H may be applied to external terminal T11. The output signal OUT1 may be applied to external terminal T12. The output signal OUT2 may be applied to external terminal T13. The lower gate signal G1L may be applied to external terminal T14. The lower gate signal G2L may be applied to external terminal T15.

[0014] A sense resistor Rcs may be connected between external terminals T16 and T17. A positive analog input signal AINP may be applied to external terminal T16. A negative analog input signal AINN may be applied to external terminal T17. The analog input signal AIN (=AINP-AINN), obtained by subtracting the negative analog input signal AINN from the positive analog input signal AINP, can be understood as a current detection signal (=I20×Rcs) corresponding to the drive current I20 flowing from the switch output stage 20 through the sense resistor Rcs. The power system ground voltage PGND may be applied to external terminals T17 and T18. In other words, the negative analog input signal AINN may also be the ground voltage PGND.

[0015] The switch output stage 20 includes upper switches 21 and 22 and lower switches 23 and 24. Each of the switches 21 to 24 may be, for example, an N-channel type MOSFET [metal-oxide-semiconductor field effect transistor].

[0016] The drains of upper switches 21 and 22 can be connected to the application terminal of the power system's external power supply voltage PVDD. The gate of upper switch 21 can be connected to external terminal T10. The gate of upper switch 22 can be connected to external terminal T11. The source of upper switch 21 can be connected to external terminal T12. The source of upper switch 22 can be connected to external terminal T13.

[0017] The drain of the lower switch 23 may be connected to external terminal T12. The drain of the lower switch 24 may be connected to external terminal T13. The gate of the lower switch 23 may be connected to external terminal T14. The gate of the lower switch 24 may be connected to external terminal T15. The sources of the lower switches 23 and 24, respectively, may be connected to external terminal T16.

[0018] Thus, the switch output stage 20 can be understood as a so-called H-bridge circuit. The upper switch 21 and the lower switch 23 can be understood as the first phase half-bridge output stage. On the other hand, the upper switch 22 and the lower switch 24 can be understood as the second phase half-bridge output stage.

[0019] The motor 30 can be understood as a load driven by the switch output stage 20. The motor 30 is connected between external terminals T12 and T13. The motor 30 is used, for example, to drive windows, seats, seat belts, mirrors, or wipers mounted on a vehicle. The motor 30 may be, for example, a brushed DC motor.

[0020] <Semiconductor device> The internal configuration of the semiconductor device 10 will now be explained with reference to Figure 1. The semiconductor device 10 may integrate the following: the upper driver 11H and lower driver 11L for the first phase, the upper driver 12H and lower driver 12L for the second phase, a controller 13, a regulator 14, an oscillator 15, an auto-zero amplifier 16, and a charge pump 17. The semiconductor device 10 may also integrate abnormal protection circuits and other components not shown.

[0021] The upper driver 11H generates an upper gate signal G1H according to the upper control signal S1H to drive the upper switch 21. Speaking in accordance with this figure, the upper driver 11H includes transistors M1 and M2 and driver D1H. The transistor M1 may be, for example, a P-channel type. The transistor M2 may be, for example, an N-channel type.

[0022] The source of the transistor M1 is connected to the application terminal of the boosted voltage VCP. The drains of the transistors M1 and M2 are each connected to the external terminal T10, that is, the application terminal of the upper gate signal G1H. The source of the transistor M2 is connected to the external terminal T12, that is, the application terminal of the output signal OUT1. The gates of the transistors M1 and M2 are each connected to the driver D1H.

[0023] The driver D1H drives the gates of the transistors M1 and M2 respectively according to the upper control signal S1H, so as to turn the transistors M1 and M2 on or off. For example, when the transistor M1 is on and the transistor M2 is off, the upper gate signal G1H becomes a high level (≈VCP). On the other hand, when the transistor M1 is off and the transistor M2 is on, the upper gate signal G1H becomes a low level (≈OUT1).

[0024] The lower driver 11L generates a lower gate signal G1L according to the lower control signal S1L to drive the lower switch 23. Speaking in accordance with this figure, the lower driver 11L includes transistors M3 and M4 and driver D1L. The transistor M3 may be, for example, a P-channel type. The transistor M4 may be, for example, an N-channel type.

[0025] The source of transistor M3 is connected to the terminal where the constant voltage VGL is applied. The drains of transistors M3 and M4 are connected to the external terminal T14, i.e., the terminal where the lower gate signal G1L is applied. The source of transistor M4 is connected to the external terminal T18, i.e., the terminal where the ground voltage PGND is applied. The gates of transistors M3 and M4 are connected to the driver D1L.

[0026] The driver D1L drives the gates of transistors M3 and M4 respectively in response to the lower control signal S1L, thereby turning transistors M3 and M4 on or off. For example, when transistor M3 is on and transistor M4 is off, the lower gate signal G1L is high level (≒VGL). On the other hand, when transistor M3 is off and transistor M4 is on, the lower gate signal G1L is low level (≒PGND).

[0027] The upper driver 12H drives the upper switch 22 by generating an upper gate signal G2H corresponding to the upper control signal S2H. Referring to this figure, the upper driver 12H includes transistors M5 and M6 and driver D2H. Transistor M5 may be, for example, a P-channel type. Transistor M6 may be, for example, an N-channel type.

[0028] The source of transistor M5 is connected to the application terminal of the boost voltage VCP. The drains of transistors M5 and M6 are connected to external terminal T11, i.e., the application terminal of the upper gate signal G2H. The source of transistor M6 is connected to external terminal T13, i.e., the application terminal of the output signal OUT2. The gates of transistors M5 and M6 are connected to driver D2H.

[0029] The driver D2H drives the gates of transistors M5 and M6 respectively in response to the upper control signal S2H, thereby turning transistors M5 and M6 on or off. For example, when transistor M5 is on and transistor M6 is off, the upper gate signal G2H is high level (≒VCP). On the other hand, when transistor M5 is off and transistor M6 is on, the upper gate signal G2H is low level (≒OUT2).

[0030] The lower driver 12L drives the lower switch 24 by generating a lower gate signal G2L corresponding to the lower control signal S2L. Referring to this figure, the lower driver 12L includes transistors M7 and M8 and driver D2L. Transistor M7 may be, for example, a P-channel type. Transistor M48 may be, for example, an N-channel type.

[0031] The source of transistor M7 is connected to the terminal where the constant voltage VGL is applied. The drains of transistors M7 and M8 are connected to the external terminal T15, i.e., the terminal where the lower gate signal G2L is applied. The source of transistor M8 is connected to the external terminal T18, i.e., the terminal where the ground voltage PGND is applied. The gates of transistors M7 and M8 are connected to the driver D2L.

[0032] The driver D2L drives the gates of transistors M7 and M8 respectively in response to the lower control signal S2L, thereby turning transistors M7 and M8 on or off. For example, when transistor M7 is on and transistor M8 is off, the lower gate signal G2L is high level (≒VGL). On the other hand, when transistor M7 is off and transistor M8 is on, the lower gate signal G2L is low level (≒PGND).

[0033] The controller 13 operates by receiving the internal power supply voltage VREG. The controller 13 controls the drive of the switch output stage 20 in response to instructions from the ECU received via the external terminal T2.

[0034] For example, when the controller 13 drives the motor 30 in the forward direction, it generates upper control signals S1H and S2H and lower control signals S1L and S2L, respectively, to turn on the upper switch 21 and the lower switch 24 and turn off the upper switch 22 and the lower switch 23. On the other hand, when the controller 13 drives the motor 30 in the reverse direction, it generates upper control signals S1H and S2H and lower control signals S1L and S2L, respectively, to turn off the upper switch 21 and the lower switch 24 and turn on the upper switch 22 and the lower switch 23.

[0035] Furthermore, the controller 13 divides the reference clock CLK0 to generate clocks CLK1 and CLK2, respectively. Clock CLK1 can be understood as the first clock output to the auto-zero amplifier 16. Clock CLK2 can be understood as the second clock output to the charge pump 17.

[0036] The reference clock CLK0, as well as clocks CLK1 and CLK2, are each square wave signals that can take on binary logic levels, i.e., high and low levels.

[0037] The regulator 14 generates an internal power supply voltage VREG from an external power supply voltage VCC or VB. The regulator 14 may be, for example, a linear regulator or a bandgap reference voltage source.

[0038] Oscillator 15 generates a reference clock CLK0 with a reference frequency f0. The reference frequency f0 may be, for example, 20 MHz. In other words, the reference period (1 / f0) of the reference clock CLK0 may be, for example, 50 ns.

[0039] The auto-zero amplifier 16 amplifies the analog input signal AIN to generate the analog output signal AOUT while correcting the input offset OFS in synchronization with the clock CLK1. The auto-zero amplifier 16 can be understood as an example of a first analog circuit that operates in synchronization with the clock CLK1. As shown in this figure, the auto-zero amplifier 16 includes amplifiers A1 and A2. The configuration and operation of the auto-zero amplifier 16 will be described in detail later.

[0040] The charge pump 17 generates a boosted voltage VCP higher than the external power supply voltage VB by driving capacitor C1 in synchronization with the clock CLK2. The charge pump 17 can be understood as an example of a second analog circuit operating in synchronization with the clock CLK2. The boosted voltage VCP can be used as the drive voltage for the upper drivers 11H and 12H, respectively.

[0041] <Auto Zero Amplifier> Figure 2 shows an example configuration of the auto-zero amplifier 16. In this example configuration, the auto-zero amplifier 16 includes resistors R1 to R6 in addition to the amplifiers A1 and A2 mentioned earlier. The resistance values ​​of resistors R1 and R2, and resistors R4 and R5 may be adjusted by trimming or other means.

[0042] Resistor R1 is connected between the non-inverting input terminal (+) of amplifier A1 and the external terminal T16. Resistor R2 is connected between the inverting input terminal (-) of amplifier A1 and the external terminal T17. Resistor R3 is connected between the inverting input terminal (-) of amplifier A1 and the output terminal of amplifier A1. The output terminal of amplifier A1 is connected to the external terminal T4.

[0043] Resistor R4 is connected between the external terminal T3 and the non-inverting input terminal (+) of amplifier A2. Resistor R5 is connected between the non-inverting input terminal (+) and the ground terminal of amplifier A2. The inverting input terminal (-) of amplifier A2 is connected to the output terminal of amplifier A2. Resistor R6 is connected between the output terminal of amplifier 2 and the non-inverting input terminal (+) of amplifier A1.

[0044] According to the auto-zero amplifier 16 in this configuration example, the analog input signal AIN (=AINP-AINN) can be amplified to generate the analog output signal AOUT.

[0045] Furthermore, amplifier A1 has a function to correct the input offset OFS in synchronization with the clock CLK1. For example, amplifier A1 acquires a sample / hold value of the input offset OFS at the timing when the clock CLK1 rises from a low level to a high level. The input offset OFS is then corrected according to the above sample / hold value. Well-known techniques can be applied to the correction process of the input offset OFS.

[0046] The auto-zero amplifier 16 can contribute to improved input offset OFS and reduced circuit area compared to a typical linear amplifier.

[0047] <Charge pump> Figure 3 shows an example configuration of the charge pump 17. In this example configuration, the charge pump 17 includes, in addition to the previously mentioned capacitors C1 and C2, a capacitor C3, transistors M11 to M14, and a control circuit 171. Transistors M11 and M13 may be, for example, P-channel type. Transistors M12 and M14 may be, for example, N-channel type. Capacitor C3 may be externally connected between external terminals T6 and T5, that is, between the terminal to which the external power supply voltage VB is applied and the terminal to which the ground voltage GND is applied.

[0048] The source of transistor M11 is connected to external terminal T7, i.e., the application terminal for the boost voltage VCP. The drains of transistors M11 and M12 are connected to external terminal T8, i.e., the application terminal for the upper charge pump voltage CPH. The source of transistor M12 is connected to external terminal T6, i.e., the application terminal for the external power supply voltage VB.

[0049] The source of transistor M13 is connected to the application terminal of the internal power supply voltage VREG. The drains of transistors M13 and M14 are connected to the external terminal T9, i.e., the application terminal of the lower charge pump voltage CPL. The source of transistor M14 is connected to the external terminal T5, i.e., the application terminal of the ground voltage GND.

[0050] The control circuit 171 drives the gates of transistors M11 to M14 in synchronization with the clock CLK2, thereby turning each of the transistors M11 to M14 on or off. For example, in the first phase φ1, which is set in synchronization with the clock CLK2, transistors M12 and M14 are turned on, and transistors M11 and M13 are turned off. At this time, the upper charge pump voltage CPH becomes low (≒VB), and the lower charge pump voltage CPL becomes low (≒GND). As a result, capacitor C1 is charged until the voltage VC across its terminals matches the external power supply voltage VB.

[0051] On the other hand, in the second phase φ2, which is set in synchronization with the clock CLK2, transistors M12 and M14 are turned off and transistors M11 and M13 are turned on. At this time, the lower charge pump voltage CPL rises from a low level (≒GND) to a high level (≒VREG), and according to the charge conservation law of capacitor C1, the upper charge pump voltage CPH also rises from a low level (≒VB) to a high level. That is, the high level of the upper charge pump voltage CPH is a voltage (≒VREG+VC) that is higher than the high level of the lower charge pump voltage CPL (≒VREG) by the voltage VC (≒VB) across capacitor C1. The upper charge pump voltage CPH is output as a boosted voltage VCP.

[0052] Thus, the charge pump 17 can generate a boosted voltage VCP that is higher than the external power supply voltage VB.

[0053] <Considerations regarding switching noise> Incidentally, in the semiconductor device 10, multiple clocks CLK1 and CLK2 are used within a single chip. Therefore, the characteristics of the analog circuit may deteriorate due to the effects of switching noise. For example, as mentioned above, the auto-zero amplifier 16 samples the input offset OFS in synchronization with clock CLK1. Therefore, if the logic level of clock CLK2 switches immediately before sampling, the correct sampling result may not be obtained due to the effects of switching noise, which may interfere with the correction process of the input offset OFS.

[0054] In light of the above considerations, the following proposes an example of operation for the semiconductor device 10 that is less susceptible to switching noise.

[0055] <Example of operation> Figure 4 shows a first example of operation of the semiconductor device 10. In this figure, the clock CLK1, clock CLK2, upper charge pump voltage CPH, and lower charge pump voltage CPL are depicted from top to bottom.

[0056] The frequency f1 of clock CLK1 may be, for example, 320kHz to 508kHz. For example, if the frequency f1 is 400kHz, the period Ta (=time t11 to t17) will be 2.5μs. The duty cycle of clock CLK1 may be 50%.

[0057] The frequency f2 of clock CLK2 may be the same as, for example, the frequency f1 of clock CLK1. For example, if the frequency f2 is 400 kHz, the period Tb (= time t12~t18) will be 2.5 μs. The duty cycle of clock CLK2 may be 50%.

[0058] At time t11, clock CLK1 rises from a low level to a high level. At time t12, clock CLK2 rises from a low level to a high level. The delay period Tg (=times t11~t12) from when clock CLK1 rises to a high level until when clock CLK2 rises to a high level may be the same as or a constant multiple of the reference period (1 / f0) of the reference clock CLK0. The delay period Tg may be, for example, 50ns.

[0059] Between times t12 and t13, the dead time Tc of the charge pump 17 is set in synchronization with the clock CLK2. The charge pump 17 turns off transistors M11 to M14 during the dead time Tc, thereby creating a high impedance state across both ends of capacitor C1. The dead time Tc may be, for example, 100ns.

[0060] At time t14, clock CLK1 falls from a high level to a low level. At time t15, clock CLK2 falls from a high level to a low level. The delay period Th (=times t14~t15) from when clock CLK1 falls to a low level until when clock CLK2 falls to a low level may be the same as the reference period (1 / f0) of the reference clock CLK0, or a constant multiple, just like the delay period Tg mentioned earlier. The delay period Th may be, for example, 50ns.

[0061] Between times t13 and t15, the charge pump 17 enters the first phase φ1. At this time, the upper charge pump voltage CPH becomes low (≒VB), and the lower charge pump voltage CPL becomes low (≒GND).

[0062] Between times t15 and t16, the dead time Td of the charge pump 17 is set in synchronization with the clock CLK2. During the dead time Td, the charge pump 17 turns off transistors M11 to M14, thereby creating a high impedance state across both ends of capacitor C1. The dead time Td may be, for example, 100ns.

[0063] At time t17, clock CLK1 rises from a low level to a high level. At time t18, clock CLK2 rises from a low level to a high level with a delay of Tg. Between times t16 and t18, charge pump 17 enters the second phase φ2. At this time, the upper charge pump voltage CPH becomes high (≒VCP), and the lower charge pump voltage CPL becomes low (≒VREG).

[0064] Thus, in a semiconductor device 10 in which multiple clocks CLK1 and CLK2 are used within a single chip, the timing at which the logic level of clock CLK1 switches is different from the timing at which the logic level of clock CLK2 switches.

[0065] Specifically, the auto-zero amplifier 16 switches the sample / hold state of the input offset OFS in synchronization with the clock CLK1, except for the dead times Tc and Td.

[0066] As shown in the diagram, clock CLK1 completes its rising edge from low to high level by a delay period Tg before the start of the dead time Tc. Also, clock CLK1 completes its falling edge from high to low level by a delay period Th before the start of the dead time Td. The delay periods Tg and Th may be, as mentioned above, for example, 50 μs. In this way, it is desirable that the logic level of clock CLK2 be switched after the logic level of clock CLK1 has been switched.

[0067] Alternatively, clock CLK1 falls from a high level to a low level after a sufficient waiting period Te has elapsed from the completion of the dead time Tc. Similarly, clock CLK1 rises from a low level to a high level after a sufficient waiting period Tf has elapsed from the completion of the dead time Td. The waiting periods Te and Tf are at least 400 ns, and may be, for example, 0.874 μs to 1.497 μs. In this way, the timing is controlled so that the logic level of clock CLK2 does not switch immediately before the logic level of clock CLK1 switches.

[0068] According to the first example of operation described above, the logic level of the clock CLK2 does not switch at the timing when the auto-zero amplifier 16 is most susceptible to switching noise, for example, immediately before the input offset OFS is sampled. Therefore, the auto-zero amplifier 16 becomes less susceptible to switching noise caused by the clock CLK2.

[0069] Figure 5 shows a second example of operation of the semiconductor device 10. In this figure, as in Figure 4 above, the clock CLK1, clock CLK2, upper charge pump voltage CPH, and lower charge pump voltage CPL are depicted from top to bottom.

[0070] The frequency f1 of clock CLK1 may be, for example, 160kHz to 254kHz. For example, if the frequency f1 is 200kHz, the period Ta (=time t21 to t2B) will be 5μs. The duty cycle of clock CLK1 may be 50%.

[0071] The frequency f2 of clock CLK2 may be, for example, twice the frequency f1 of clock CLK1. For example, if the frequency f2 is 400 kHz, the period Tb (= time t22~t27) will be 2.5 μs. The duty cycle of clock CLK2 may be 50%.

[0072] At time t21, clock CLK1 falls from a high level to a low level. At time t22, clock CLK2 rises from a low level to a high level. The delay period Tm (=times t21~t22) from when clock CLK1 falls to a low level until when clock CLK2 rises to a high level may be the same as or a constant multiple of the reference period (1 / f0) of the reference clock CLK0. The delay period Tm may be, for example, 50ns.

[0073] Between times t22 and t23, the dead time Tc (e.g., 100 μs) of the charge pump 17 is set in synchronization with the clock CLK2. At time t24, the clock CLK2 falls from a high level to a low level. Between times t23 and t24, the charge pump 17 enters its first phase φ1. Between times t24 and t25, the dead time Td (e.g., 100 μs) of the charge pump 17 is set in synchronization with the clock CLK2.

[0074] At time t26, clock CLK1 rises from a low level to a high level. At time t27, clock CLK2 rises from a low level to a high level. The delay period Tn (=times t26~t27) from when clock CLK1 rises to a high level until when clock CLK2 rises to a high level may be the same as or a constant multiple of the reference period (1 / f0) of the reference clock CLK0. The delay period Tn may be, for example, 50ns. At time t25~t26, the charge pump 17 enters the second phase φ2.

[0075] Between times t27 and t28, the dead time Tc (e.g., 100 μs) of the charge pump 17 is set in synchronization with the clock CLK2. At time t29, the clock CLK2 falls from a high level to a low level. Between times t28 and t29, the charge pump 17 enters its first phase φ1. Between times t29 and t2A, the dead time Td (e.g., 100 μs) of the charge pump 17 is set in synchronization with the clock CLK2. At time t2B, the clock CLK1 rises from a high level to a low level.

[0076] In the second operation example, as in the first operation example described earlier, the logic level of clock CLK1 is switched before the logic level of clock CLK2 is switched. Alternatively, the timing is controlled so that the logic level of clock CLK2 does not switch immediately before the logic level of clock CLK1 is switched. Therefore, the auto-zero amplifier 16 becomes less susceptible to switching noise caused by clock CLK2.

[0077] Furthermore, the charge pump 16's current output capability increases as the frequency f2 of the clock CLK2 increases. On the other hand, the auto-zero amplifier 17 needs to secure gain over a higher bandwidth as the frequency f1 of the clock CLK1 increases, so the circuit size becomes larger.

[0078] Therefore, considering the balance between circuit size and characteristic accuracy, the frequency f2 of clock CLK2 may be set to twice the frequency f1 of clock CLK1, as shown in this figure. However, the frequency f2 is not limited to twice the frequency f1, but may also be a constant multiple (for example, an integer multiple) of the frequency f1.

[0079] <Note> This disclosure makes it possible to suppress malfunctions caused by switching noise. Further details regarding the above disclosure are provided below.

[0080] [Note 1] A first analog circuit (16) configured to operate in synchronization with a first clock (CLK1) of a first frequency (f1), A second analog circuit (17) configured to operate in synchronization with a second clock (CLK2) of a second frequency (f2), Equipped with, The second frequency (f2) is the same as or a constant multiple of the first frequency (f1). A semiconductor device (10) in which the timing at which the logic level of the first clock (CLK1) switches is different from the timing at which the logic level of the second clock (CLK2) switches.

[0081] [Note 2] The first analog circuit (16) is an auto-zero amplifier (16) configured to amplify the analog input signal (AIN) and generate an analog output signal (AOUT) while correcting the input offset (OFS) in synchronization with the first clock (CLK1), The semiconductor device (10) described in Appendix 1 is a charge pump (17) configured to generate a boost voltage (VCP) higher than the power supply voltage (VB) by driving a flying capacitor (C1) in synchronization with the second clock (CLK2).

[0082] [Note 3] The charge pump (17) sets both ends of the flying capacitor (C1) to a high impedance state during the dead time (Tc, Td) which is set in synchronization with the second clock (CLK2). The auto-zero amplifier (16) is a semiconductor device (10) as described in Appendix 2, which switches the sample / hold state of the input offset (OFS) in synchronization with the first clock (CLK1) and other than the dead time (Tc, Td).

[0083] [Note 4] The system further includes an oscillator (15) configured to generate a reference clock (CLK0) at a reference frequency (f0), The first clock (CLK1) and the second clock (CLK2) are generated by dividing the reference clock (CLK0) by any of the semiconductor device (10) described in Appendix 1 to 3.

[0084] [Note 5] The semiconductor device (10) described in Appendix 4, wherein the delay period (Tg, Th, Tm, Tn) from the time the logic level of the first clock (CLK1) switches until the logic level of the second clock (CLK2) switches is the same as or a constant multiple of the reference period (1 / f0) of the reference clock (CLK0).

[0085] [Note 6] The system comprises at least one-phase upper drivers (11H, 12H) and lower drivers (11L, 12L) configured to drive at least one-phase upper switches (21, 22) and lower switches (23, 24) that form a switch output stage (20), respectively. The aforementioned boost voltage (VCP) is the drive voltage of the upper drivers (11H, 12H), The aforementioned analog input signal (AIN) is a current detection signal corresponding to the drive current (I20) flowing through the switch output stage (20), as described in Appendix 2 or 3, for the semiconductor device (10).

[0086] [Note 7] The semiconductor device (10) described in Appendix 6, The aforementioned switch output stage (20) and, A load (30) configured to be driven by the aforementioned switch output stage (20), An electronic device (1) equipped with [a certain feature].

[0087] [Note 8] The aforementioned load (30) is a motor, which is the electronic device (1) described in Appendix 7.

[0088] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive. Moreover, the technical scope of this disclosure is defined by the claims and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of Symbols]

[0089] 1 Electronic equipment 10 Semiconductor Devices 11H, 12H Upper Driver 11L, 12L Lower Driver 13 Controllers 14 Regulator 15 Oscillators 16 Auto Zero Amplifier 17 Charge pump 171 Control Circuit 20 Switch output stage 21, 22 Upper switch 23, 24 Lower switch 30 motors A1, A2 Amplifiers C1, C2, C3 Capacitors D1H, D1L, D2H, D2L drivers M1-M10, M11-M14 Transistors R1~R6 resistance Rcs sense resistor T1~T19 External terminals

Claims

1. A first analog circuit configured to operate in synchronization with a first clock of a first frequency, A second analog circuit configured to operate in synchronization with a second clock of a second frequency, Equipped with, The second frequency is the same as or a constant multiple of the first frequency. A semiconductor device wherein the timing at which the logic level of the first clock switches is different from the timing at which the logic level of the second clock switches.

2. The first analog circuit is an auto-zero amplifier configured to amplify an analog input signal while correcting the input offset in synchronization with the first clock to generate an analog output signal. The semiconductor device according to claim 1, wherein the second analog circuit is a charge pump configured to generate a boosted voltage higher than the power supply voltage by driving a flying capacitor in synchronization with the second clock.

3. The charge pump sets both ends of the flying capacitor to a high impedance state during the dead time, which is set in synchronization with the second clock. The semiconductor device according to claim 2, wherein the auto-zero amplifier switches the sample / hold state of the input offset in synchronization with the first clock, except during the dead time.

4. It further includes an oscillator configured to generate a reference clock of a reference frequency, The semiconductor device according to any one of claims 1 to 3, wherein the first clock and the second clock are generated by dividing the frequency of the reference clock.

5. The semiconductor device according to claim 4, wherein the delay period from when the logic level of the first clock switches to when the logic level of the second clock switches is the same as or a constant multiple of the reference period of the reference clock.

6. It comprises at least one upper driver and a lower driver configured to drive at least one phase upper switch and lower switch, respectively, which form a switch output stage, The boosted voltage is the drive voltage of the upper driver. The semiconductor device according to claim 2 or 3, wherein the analog input signal is a current detection signal corresponding to the drive current flowing through the switch output stage.

7. The semiconductor device according to claim 6, The aforementioned switch output stage, A load configured to be driven by the aforementioned switch output stage, An electronic device equipped with the following features.

8. The electronic device according to claim 7, wherein the load is a motor.

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