Sum-accumulate circuit, control method for sum-accumulate circuit, and arithmetic system

Abstract

This invention provides a multiply-accumulate circuit that can streamline the multiply-accumulate operation. [Solution] A sum-of-accumulate circuit comprising a plurality of multiplication circuits and an adder circuit that adds the multiplication results of each of the plurality of multiplication circuits and outputs the sum result, each of the plurality of multiplication circuits comprising a capacitance array including a plurality of capacitive elements and an inverting amplifier connected to the capacitance array in a switchable manner, when multiplication is performed in the multiplication circuit, the first side of the capacitance array is connected to the inverting input terminal of the inverting amplifier, the second side of the capacitance array opposite to the first side is connected to the output terminal of the inverting amplifier, a predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier, and when the multiplication result of the multiplication circuit is transferred to the adder circuit, the first side of the capacitance array is connected to the non-inverting input terminal of the inverting amplifier, and the second side is connected to the inverting input terminal and the output terminal.

Description

Technical Field

[0001] This embodiment relates to a multiplication and accumulation circuit, a control method for the multiplication and accumulation circuit, and an arithmetic system.

Background Art

[0002] A semiconductor integrated circuit may perform a multiplication and accumulation operation of adding a plurality of results obtained by multiplying each of a plurality of input values by weights, and techniques for performing the multiplication and accumulation operation have been developed (see Patent Document 1). The multiplication and accumulation operation is an operation of multiplying each of a plurality of input values by a load and adding the multiplication results to each other. For example, it is used for recognition processing of images, voices, etc. by neural networks, etc., and it is desired to improve the efficiency of the multiplication and accumulation operation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] According to the present invention, it is possible to provide a sum-of-accumulate circuit that can perform sum-of-accumulate operations more efficiently. [Brief explanation of the drawing]

[0007] [Figure 1A] A diagram showing an example of the configuration of the sum-of-accumulate circuit 10 corresponding to the embodiment. [Figure 1B] A diagram showing an example of the configuration of an arithmetic system including multiple multiply-accumulate circuits 10 corresponding to the embodiment. [Figure 2] A diagram showing an example of a schematic configuration of the multiplication circuit 101 corresponding to the embodiment. [Figure 3] A diagram illustrating an example of the multiplication process in the multiplication circuit 101 corresponding to the embodiment. [Figure 4] A diagram illustrating another example of the multiplication process in the multiplication circuit 101 corresponding to the embodiment. [Figure 5A] A diagram illustrating the charge transfer process from the multiplication circuit 101A to the adder circuit 102, corresponding to the embodiment. [Figure 5B] A diagram illustrating the switching of the amplifier connection method corresponding to the embodiment. [Figure 6] A diagram showing an example of a differential configuration of a sum-of-accumulate circuit corresponding to the embodiment. [Figure 7] A circuit diagram illustrating a control method for a differential configuration of a sum-of-accumulate circuit corresponding to an embodiment. [Figure 8]A diagram for explaining an example of a method for generating differential capacitance corresponding to an embodiment. [Figure 9] A diagram showing an example of a timing chart for controlling the operation of a product-sum operation circuit corresponding to an embodiment. [Figure 10] A diagram showing another example of a timing chart for controlling the operation of a product-sum operation circuit corresponding to an embodiment. [Figure 11] A flowchart corresponding to an example of the operation control of a product-sum operation circuit corresponding to an embodiment. [Figure 12] A diagram showing an example of a schematic configuration of a multiplication circuit 101 corresponding to a modification of an embodiment. [Figure 13] A flowchart corresponding to an example of the operation control of a product-sum operation circuit corresponding to a modification of an embodiment.

Best Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential for the invention. Two or more of the features described in the embodiments may be arbitrarily combined. Also, the same or similar configurations are given the same reference numerals, and duplicate descriptions are omitted.

[0009] Hereinafter, an arithmetic system according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by these embodiments.

[0010] The computing system according to this embodiment can be used, for example, to perform a part of the processing of a neural network such as an AI (artificial intelligence) accelerator. An AI accelerator performs a multiply-accumulate operation, multiplying a multiplicative input by a multiplicative weight and adding the results of the multiplication, in order to learn a task or perform inference. The computing system is required to perform this operation quickly and efficiently in parallel. For example, the computing system performs multiply-accumulate operations in parallel for multiple neurons in a certain layer of a neural network (parallel operation). Parallel operation includes operations in which a multiplicative input containing multiple bits and a multiplicative weight containing multiple bits are multiplied with arbitrary bit precision.

[0011] This parallel operation can be implemented in hardware using in-memory semiconductor integrated circuits, characterized by the integration of memory circuits and arithmetic circuits into a single unit or in close proximity. In in-memory semiconductor integrated circuits, weights for multiplication are set fixedly rather than dynamically. In-memory configurations include digital, analog-current, and analog-charge configurations.

[0012] The digital configuration performs calculations within memory by using bit-level logic circuits located within the memory to perform operations on input bits according to the weight bits. The analog current configuration applies voltage to each row of an array of weighted resistors and adds up the currents using Kirchhoff's laws.

[0013] On the other hand, the analog-charge method performs a bitwise AND operation on multiple bits of input and multiple bits of weights in parallel, and stores the voltage corresponding to the multi-bit operation result in multiple capacitive elements of the capacitive array. Then, the charges of the multiple capacitive elements in the capacitive array are read out sequentially, converted to AD, and a digital signal is generated, and the digital signal is bit-shifted and added repeatedly to perform the addition of the digital signals.

[0014] The analog-charge architecture is superior to the digital architecture in that it offers faster calculation speeds when performing calculations with moderate bit precision. The analog-charge architecture is also superior to the analog-current architecture in that it is more effective at minimizing the effects of variations between components.

[0015] However, in analog charge-based configurations, bit shift operations are performed a number of times proportional to the number of bits in at least one of the input and weights for signal addition. Therefore, as the number of bits in at least one of the input and weights increases, the efficiency of parallel operations tends to decrease, and the processing time for parallel operations tends to become long, depending on the bit precision of at least one of the input and weights.

[0016] This embodiment proposes a more efficient analog charge-based circuit configuration. Figure 1A shows an example of a multiply-accumulate circuit corresponding to this embodiment. The multiply-accumulate circuit 10 shown in Figure 1 is configured by connecting an adder 102 to multiplier circuits 101A and 101B. The operation of the multiply-accumulate circuit 10 is controlled by a control circuit 103. Inputs A and B are input serially to the multiplier circuit 101A, and the multiplication operation A × B is performed, with the multiplication result A * B output to the adder circuit 102. Similarly, inputs C and D are input serially to the multiplier circuit 101B, and the multiplication operation C × D is performed, with the multiplication result C * D output to the adder circuit 102. The adder circuit 102 performs the addition of the input A * B and C * D and outputs the summation result A * B + C * D. In Figure 1, only two multiplier circuits 101A and 101B are shown, but more multiplier circuits 101 can be connected in parallel. The control circuit 103 provides signals to control the switches of the multiplier circuit 101 and the adder circuit 102, as well as signals and charges representing the multiplication value, and control voltages, thereby controlling the operation of the multiplier circuit 101 and the adder circuit 102. An arithmetic system can be constructed by arranging multiple multiply-accumulate circuits 10 as shown in Figure 1A.

[0017] Figure 1B shows an example of the configuration of an arithmetic system 1, which is composed of multiple multiply-accumulate circuits 10. In Figure 1B, the arithmetic system 1 includes a multiplication circuit 101, an addition circuit 102, a control circuit 103, a memory 104, and a processing circuit 105. The multiplication circuit 101, the addition circuit 102, and the control circuit 103 are the same as those described in Figure 1A. In Figure 1B, the solid lines connecting each circuit block represent data signals, and the dotted lines supplied from the control circuit 103 to each circuit block represent control signals. Memory 104 is a memory circuit that holds various data for arithmetic processing. The data held may be digital data or analog data. The output from the adder circuit 102 may be stored in memory 104 before being provided to the next stage, or it may be directly input to the next stage's multiply-accumulate circuit 10.

[0018] The processing circuit 105 is a circuit that performs predetermined processing based on the calculation results performed in the upstream arithmetic circuit. Processing that can be performed here includes, for example, nonlinear processing using functions such as ReLU (Rectified Linear Unit), Softmax, Sigmoid, and Tanh functions, which are used in deep learning. In addition to nonlinear processing, it can also perform processes such as Maxpooling and Average-pooling. The output from the processing circuit 105 may be digital or analog, but for ReLU functions, Maxpooling, and Average-pooling, analog output is possible.

[0019] Although Figure 1B does not show an example of inputting the processing result from the processing circuit 105 to the multiply-accumulate circuit 10, the embodiments of the invention are not limited to this, and the processing result from the processing circuit 105 can be input to the multiply-accumulate circuit 10 for calculation. Furthermore, although the processing circuit 105 is configured to receive data input from memory, the addition result from the adder circuit 102 may be directly input. In addition, the processing in the processing circuit 105 is executed according to the control signal supplied from the control circuit 103.

[0020] In Figure 1B, the dotted lines 10A and 10B, and the dashed line 10C, correspond to the multiply-accumulate circuits 10 described in Figure 1A, respectively. Multiply-accumulate circuits 10A and 10C are circuits that add the multiplication results of a two-stage multiplier circuit 101 in an adder circuit 102, while multiply-accumulate circuit 10B is a circuit that adds the multiplication results of a three-stage multiplier circuit 101 in an adder circuit 102. Here, the multiplication process in the multiplier circuit 101 in multiply-accumulate circuits 10A and 10B can be performed as a multiplication process of digital values ​​supplied from memory 104. On the other hand, a part of the multiplication circuit in multiply-accumulate circuit 10B receives an analog value supplied from the adder circuit 102 of multiply-accumulate circuit 10C, enabling multiplication using analog values. In addition to direct input from the adder circuit 102, digital values ​​obtained from memory 104 can also be converted to analog charges and then input. Alternatively, the analog output from the processing circuit 105 may be input. In Figure 1B, the number of stages in the multiplication circuit 101 is limited to three, but it can also be four or more stages.

[0021] Figure 2 shows an example of a schematic configuration of the multiplication circuit 101. Figure 2 shows the case where the multiplication circuit 101 is configured as a 3-bit capacitance array. The configuration in Figure 2 is merely an example, and the multiplication circuit 101 may also be configured as a 4-bit, 5-bit, or even more than n-bit capacitance array. In that case, the capacitance of the capacitance elements (capacitors) is set to a power of 2. For example, in the case of 4 (n=4) bits, an additional capacitor with a capacitance of 8C is added, and the capacitances of the capacitance elements corresponding to 1 bit, 2 bits, 3 bits, and 4 bits are given as 1C, 2C, 4C, and 8C, respectively. Also, in the case of 5 (n=5) bits, an additional capacitor with a capacitance of 16C is added, and the capacitances of the capacitance elements corresponding to 1 bit to 5 bits are given as 1C, 2C, 4C, 8C, and 16C, respectively.

[0022] When a multiplication circuit is configured as a 3-bit capacitance array, the capacitance array 201 consists of four capacitance elements (capacitors) with capacitances of 4C, 2C, 1C, and 1C. Here, C is the reference capacitance (unit: F). C may be the smallest unit capacitance in the capacitance array, or any other arbitrary capacitance. The bottommost 1C is a dummy capacitance and is short-circuited during the multiplication process. The bottommost dummy capacitance is always provided regardless of the number of bits in the capacitance array 201. The input is provided to the capacitance array 201 as a charge Q. Also, Cst1 and Cst2 represent parasitic capacitances at both ends of the capacitance array 201. In this embodiment, the side to which the parasitic capacitance Cst1 of the capacitance array 201 is connected is sometimes referred to as the input side or the first side, and the side to which the parasitic capacitance Cst2 is connected is sometimes referred to as the output side or the second side. Parasitic capacitances are set considering, for example, wiring and switch capacitances. However, this parasitic capacitance can be eliminated by using the inverting amplifier 202.

[0023] The inverting amplifier 202 has a charge Q1 input to its inverting input terminal (-). The inverting input terminal is connected in parallel to the input side of the capacitance array 201 and the parasitic capacitance Cst1. The non-inverting input terminal (+) of the inverting amplifier 202 is grounded at a predetermined ground voltage. In this embodiment, 0.6V is used as this ground voltage for illustrative purposes, so 0.6V is input to the non-inverting input terminal. The output side of the inverting amplifier 202 is connected in parallel to the output side of the capacitance array 201 and the parasitic capacitance Cst2.

[0024] The gain of the inverting amplifier 202 can be sufficiently large, for example, 1000 times. When the potential difference between the potential of the inverting input terminal and the potential of the non-inverting input terminal (ground potential) disappears, a virtual short circuit is established between the inverting input terminal and the non-inverting input terminal. In the virtual short circuit state, the terminal voltage of the parasitic capacitance Cst1 is also defined as the potential difference between the potential of the inverting input terminal of the inverting amplifier 202 and the ground potential, so it also becomes 0, and the parasitic capacitance Cst1 can be ignored regardless of its magnitude. Therefore, the input charge Q1 does not flow into Cst1 but is supplied to the capacitance array 201. In addition, the output-side parasitic capacitance Cst2 is connected to the output of the inverting amplifier 202, and the charge flowing into the parasitic capacitance Cst2 is provided from the output of the inverting amplifier 202. Therefore, the charge flowing into the parasitic capacitance Cst2 does not affect the amount of charge stored in the capacitance array 201.

[0025] Next, with reference to Figure 3, the multiplication process performed in the multiplication circuit 101 of this embodiment will be described. Figure 3 is a conceptual diagram for simplifying the explanation of the multiplication process in the multiplication circuit, and mainly shows the operation on the capacitance array 201. Figure 3(A) shows the state in which a charge Q is applied to the capacitance array 201 as input A or input C. The input here is an analog signal. Prior to inputting the charge Q, the capacitance array 201 is reset. The reset can be achieved by setting the voltage across both ends of each capacitor to 0.6V. When the charge Q is input, each capacitor in the capacitance array 201 holds a charge corresponding to its respective capacitance. That is, a capacitor with a capacitance of 4C holds 4Q / 8, a capacitor with a capacitance of 2C holds 2Q / 8, and a capacitor with a capacitance of 1C holds 1Q / 8. At this time, the potential difference V of the capacitance array 201 is Q / 8C.

[0026] The multiplication circuit 101A is then input B. Input B is a digital signal and is a 3-bit signal. Input B has seven possible values, for example, 000, 001, 010, 011, 100, 101, and 111. These values ​​represent 0, 1 / 8, 2 / 8, 3 / 8, 4 / 8, 5 / 8, 6 / 8, and 7 / 8, respectively. 8 / 8 (=1) is skipped in this multiplication process because the result of the multiplication is the same as input A. Each bit corresponds to a capacitance of 4C, 2C, and 1C, respectively, from the most significant bit. Note that the dummy capacitance is short-circuited as described above during the multiplication process. Similarly, input D of the multiplication circuit 101B can take any of the seven possible values. The following describes the operation using input B.

[0027] In the multiplication process of this embodiment, the bit positions in input B that have 0 are short-circuited. For example, if input B is 101, the capacitor with capacitance 2C is short-circuited. As a result, the charge held in the capacitor with capacitance 2C is discharged. On the other hand, the charges held in 4C and 1C remain unchanged. The dummy capacitor is also short-circuited. Figure 3(B) shows the state after multiplying by B. The total charge remaining in the capacitance array 201 is 5 / 8Q, and the multiplication result A*B is obtained. At this point, the charge may be immediately discharged and the multiplication result transferred to another capacitance array.

[0028] Figure 3(C) shows the state in Figure 3(B) after reconnecting all the capacitors in the capacitance array to the same potential, thereby redistributing the charge to each element in a power of 2 ratio. As a result, the capacitor with capacitance 2C and the dummy capacitance capacitor also hold charge again, and each capacitor holds charges of 5Q / 16, 5Q / 32, 5Q / 64, and 5Q / 64, respectively. The potential difference V across the capacitance array 201 at this time is 5Q / 64C. This allows for continued multiplication (for example, A × B × E based on a new input E).

[0029] Figure 3 illustrates the case where analog signals are input as inputs A and C. In contrast, Figure 4 illustrates the operation when inputs A and C are input as digital signals. In Figure 4(A), for input A or input C, the capacitor corresponding to the digit with a value of 1 in the 3 bits is charged to a specified value, and the capacitor corresponding to the digit with a value of 0 is short-circuited and discharged. In Figure 4, the input voltage is V i , the ground voltage is V g This is assumed. The dummy capacitance is also short-circuited. In Figure 4(A), the input value is 011, so the capacitors with capacitances of 2C and 1C have a specified value V1 (=V i -V g The capacitor is charged with 4C and the dummy capacitance of 1C is short-circuited. As a result, the total charge charged to the capacitance array 201 is 2C × V1 + 1C × V1 = 3CV1. In this embodiment, as an example, V i 0.9V, V g It can be set to 0.6V, in which case V1 will be 0.3V.

[0030] Next, in Figure 4(B), all capacitors in the capacitance array 201 are reconnected and brought to the same potential. This redistributes the charge held in Figure 4(A) to each capacitor in a ratio of powers of 2. In the case of digital signals, it is always necessary to redistribute the charge beforehand when performing multiplication. As a result, when 3CV1 is distributed to the capacitors with capacitances 4C, 2C, C, and C, the respective charges become 12CV1 / 8, 6CV1 / 8, 3CV1 / 8, and 3CV1 / 8.

[0031] Next, Figure 4(C) shows the state after multiplying Figure 4(B) by input B. Here, input B is set to 101. As before, the dummy capacitance is short-circuited, so the capacitor with capacitance 2C is short-circuited, and the total charge remaining in the capacitance array 201 becomes 15CV1 / 8, and the multiplication result A*B is obtained. At this point, the charge can be immediately discharged and the multiplication result can be transferred to other capacitance arrays. Furthermore, the charge can be redistributed and additional multiplication can be performed. Multiplication can be performed similarly for input D.

[0032] Next, with reference to Figure 5A, the charge transfer process from the multiplier circuit 101A to the adder circuit 102 will be explained. The multiplier circuit 101A is the same as the multiplier circuit shown in Figure 2. The configuration of the adder circuit 102 can also be the same as the multiplier circuit shown in Figure 2. Switches can be appropriately placed in the charge transfer path, but they are omitted in Figure 5A for the sake of simplicity. It is not necessarily required to adopt the configuration of a multiplier circuit as the adder circuit 102, but using a multiplier circuit allows for further multiplication. When transferring charge from the multiplier circuit 101A to the adder circuit 102, the inverting amplifier 202 of the capacitance array 201 of the multiplier circuit 101A is replaced with a 1x gain amplifier by switching the connection from a state where the gain is sufficiently large. As a result, the charge transfer from the multiplier circuit 101A to the adder circuit 102 is performed from the input side of the capacitance array 201. The potential difference of the capacitance array 201 connected to the inverting amplifier 202 is forcibly set to 0, so the charge held in the capacitance array 201 is discharged to the adder circuit 102 side. In this case, the parasitic capacitance Cst1 of the sending multiplication circuit 101A is incorporated into the parasitic capacitance of the adder circuit 102. However, including the parasitic capacitance Cst3 of the adder circuit 102 itself, the effect can be eliminated by virtually short-circuiting the inverting amplifier 502 connected to the input side of the capacitance array 501 of the receiving adder circuit 102.

[0033] In Figure 5A, only one multiplier circuit 101A is shown on the input side of the adder circuit 102. However, by connecting multiple multiplier circuits 101 in parallel, the charge transfers from each multiplier circuit 101 can be added together. In this case, the charge transfer timings from each multiplier circuit 101 may be simultaneous or at different times.

[0034] The charge Q2 transferred to the adder circuit 102 is held in the capacitance array 501 of the adder circuit 102. The capacitance array 501 can hold charges transferred from multiple multiplier circuits 101. Furthermore, the charges held in the capacitance array 501 can be further multiplied in the same manner as the multiplier circuit 101 described above. Alternatively, if no multiplication is performed, at least one predetermined capacitance element may be placed instead of the capacitance array 501.

[0035] Alternatively, instead of transferring the charge result of the multiplication in the multiplication circuit 101, multiplication and charge transfer may be performed simultaneously. For example, in the example shown in Figure 4 above, the state in Figure 4(B) was further multiplied by the value of 101 to form the state in Figure 4(C). Here, instead of multiplying by the value of 101, the same effect as performing multiplication simultaneously with the transfer can be obtained by transferring the charge held in the 3rd bit 4C capacitor and the 1st bit 1C capacitor.

[0036] In Figure 5A, to change the inverting amplifier 202 to a 1x amplifier, the inverting input terminal (-) of the inverting amplifier 202 can be connected to the output side to apply 100% feedback, and the non-inverting input terminal (+) can be connected to the capacitance array 201. The switching of the connection of the inverting amplifier 202 will be explained in detail with reference to Figure 5B. The switching of the connection of the inverting amplifier 202 is performed by a control signal from the control circuit 103.

[0037] Figure 5B(A) shows an example of the switch configuration around the inverting amplifier 202. In Figure 5B(A), all switches are open. In Figure 5B, for illustrative purposes, a parasitic capacitance Cst1 is placed on the input side of the inverting amplifier 202 and a parasitic capacitance Cst2 is placed on the output side so that the positional relationship with the capacitance array can be understood.

[0038] In the configuration shown in Figure 5B(A), the on / off switch can be switched by a control signal from the control circuit 103, thereby switching between the connection configuration in which the input side is virtually short-circuited as shown in Figure 2 and the connection configuration for operation as a 1x amplifier as shown in Figure 5B. Figure 5B(B) shows the connection configuration with a virtual short circuit.

[0039] In Figure 5B(B), solid lines indicate connections that are activated by the switch, and dotted lines indicate connections that are deactivated. In this connection example, the input side of the capacitance array 201, where the parasitic capacitance Cst1 is located, is connected to the inverting input terminal of the inverting amplifier 202, and the non-inverting input terminal is grounded. The output side of the capacitance array 201, where the parasitic capacitance Cst2 is located, is connected to the output terminal of the inverting amplifier 202, and the connection between the output terminal of the inverting amplifier 202 and the inverting output terminal is interrupted by a switch.

[0040] In Figure 5B(C), the parts that are activated as connections by switching them on are shown with solid lines, and the parts that are deactivated as connections are shown with dotted lines. In this connection example, the output side of the capacitance array 201, where the parasitic capacitance Cst2 is located, is connected to the inverting input terminal of the inverting amplifier 202, and is also connected to the output terminal of the inverting amplifier 202. The input side of the capacitance array 201, where the parasitic capacitance Cst1 is located, is connected to the non-inverting input terminal of the inverting amplifier 202.

[0041] By using the inverting amplifier 202 in this manner, the connection relationship between the inverting amplifier 202 and the capacitance array 201 can be switched according to the processing status in the multiplication circuit 101.

[0042] The sum-of-accumulate circuit of this embodiment can also be configured with a differential circuit as shown in Figure 6. In the differential configuration, a first sum-of-accumulate circuit for positive phase and a second sum-of-accumulate circuit for negative phase are combined. Figure 6 shows an example of a differential configuration of the sum-of-accumulate circuit. The multiplier circuit 101A is composed of a positive-phase circuit 101A+ and a negative-phase circuit 101A-, and the adder circuit 102 is composed of a positive-phase circuit 102+ and a negative-phase circuit 102-. The first sum-of-accumulate circuit is composed of a positive-phase multiplier circuit 101A+ and a positive-phase adder circuit 102+, and the second sum-of-accumulate circuit is composed of a negative-phase multiplier circuit 101A- and a negative-phase adder circuit 102-.

[0043] The parasitic capacitances Cst1 and Cst2 of the positive-sequence multiplier circuit 101A+ and Cst5 and Cst6 of the negative-sequence multiplier circuit 101A- ideally coincide, but they may differ. Similarly, the parasitic capacitances Cst3 and Cst4 of the positive-sequence adder circuit 102+ and Cst7 and Cst8 of the negative-sequence adder circuit 102- ideally coincide, but they may differ. Even if the parasitic capacitance values ​​do not match, there is no problem because each parasitic capacitance can be ignored by virtually short-circuiting the inverting amplifiers 202+, 202-, 502+, and 502-. The output obtained is Q2-(-Q2)=2Q2, and in this case, the common-mode component is canceled, so the effects of disturbance noise and DC offset can be reduced.

[0044] Next, the control method for the multiplication circuit 101 will be explained with reference to Figure 7. Figure 7 shows the circuit configuration when the multiplication circuit is configured as a 3-bit capacitance array. In Figure 7, the capacitance array 201 has a capacitance array 201+ for the positive-sequence circuit and a capacitance array 201- for the negative-sequence circuit. Furthermore, the two capacitors with a capacitance of 1C are shown to be generated as differential capacitances. Here, differential capacitance refers to realizing a capacitor with a small capacitance by combining capacitors with a large capacitance. When configuring the multiply-accumulate circuit corresponding to this embodiment, the minimum capacitance of the capacitor is determined by the circuit specifications, so configuring the capacitance element as a differential capacitance is effective when it is not possible to create a capacitance element with a capacitance below the minimum capacitance on its own.

[0045] In Figure 7, for example, a capacitor with a capacitance of 1C can be created by arranging two capacitors with capacitances of 3C and 2C in parallel. Here, the differential capacitance is generated by combining capacitors with capacitances of 3C and 2C, but the ratio of the capacitances combined will differ depending on the size of the smallest unit capacitance.

[0046] In Figure 7, the capacitor C1a+ and dummy capacitance Cda+ on the positive-sequence circuit side have a capacitance of 3C, while the capacitor C1b+ and dummy capacitance Cdb+ have a capacitance of 2C. One end of the capacitor C1b+ and dummy capacitance Cdb+ is connected to COMP on the negative-sequence circuit side. Similarly, on the negative-sequence circuit side, the capacitor C1a- and dummy capacitance Cda- have a capacitance of 3C, while the capacitor C1b- and dummy capacitance Cdb- have a capacitance of 2C. One end of the capacitor C1b- and dummy capacitance Cdb- is connected to COMP on the positive-sequence circuit side.

[0047] By using differential capacitance in this way, not only can the capacitance of the first bit's capacitive element and dummy capacitance be reduced, but the total capacitance and the capacitance of the capacitive element with the maximum capacitance can also be reduced. For example, consider the case of configuring a 4-bit capacitive array with the minimum capacitance being 1C, which is the difference between 2C and 3C (Case 1), and the case where the minimum capacitance is 2C (Case 2). The capacitance of the first bit's capacitive element is 2C, which is smaller in Case 2 than 5C, but from the second to the fourth bit, the difference widens, as 2C and 4C, 4C and 8C, 8C and 16C, and so on. In Case 1, even with a 4-bit capacitive array, the total capacitance including the dummy capacitance is only 24C, but in Case 2, the total capacitance is 32C, so it is unavoidable that the capacitance will be larger than when using differential capacitance. Furthermore, if the number of bits in the capacitive array increases further, this difference will widen even more. In this way, by using differential capacitance, the implementation area of ​​the capacitive array can be reduced.

[0048] In Figure 7, the capacitors C4+, C2+, C1a+, C1b+, Cda+, and Cdb+ constituting the capacitance array 201+ are each supplied with charge via INP on the input side. The capacitors C4-, C2-, C1a-, C1b-, Cda-, and Cdb- constituting the capacitance array 201- are each supplied with charge via INN on the input side. INP and INN are in opposite phase, with INN being positive phase and INP being negative phase. In addition, the input terminal is configured to receive a VRC input when the switch is ON for reset. In this embodiment, VRC can be set to 0.6V, thereby resetting each capacitor in the capacitance array 201. On the terminals opposite the input side of the capacitance arrays 201+ and 201-, VRP (0.9V), VRC (0.6V), and VRN (0.3V) can be input by switching. COMP is a wiring that connects to each capacitor element when the switch is ON during charge redistribution. These switching operations allow for charge retention, differential capacitance generation, resetting, and charge redistribution in the capacitor.

[0049] In the configuration shown in Figure 7, the voltages in VRP, VRC, and VRN, the voltage and charge supply to INP and INN, and the control signals for switching each switch on and off are supplied from the control circuit 103.

[0050] Capacitance arrays 201 and 501 corresponding to this embodiment are configured by connecting multiple capacitive elements in parallel. The minimum capacitance among the multiple capacitive elements is determined, for example, by the design rules of the semiconductor circuit. However, instead of realizing this minimum capacitance with a single capacitive element, there is a method of realizing it as a differential capacitance by combining multiple capacitive elements. In other words, the multiple capacitive elements constituting the capacitive arrays 201 and 501 in this embodiment can include a first type of capacitive element that realizes a predetermined capacitance with a single capacitive element, and a second type of capacitive element that realizes it by combining multiple capacitive elements.

[0051] Figure 8 illustrates an example of a method for generating differential capacitance. Here, we will explain the case of generating a capacitor with a capacitance of 1C. To do this, capacitors with capacitances of 3C and 2C are connected in parallel, VRP (0.9V) is applied to the 3C capacitor C1, and VRN (0.3V) is applied to the 2C capacitor C2. At this time, the input voltage INP is 0.6V, so 0.3V is applied to C1 and -0.3V is applied to C2. Therefore, the charge Q1 accumulated in C1 is 3C * 0.3 = 0.9C, and the charge Q1 accumulated in C2 is 2C * (-0.3) = -0.6C. Adding Q1 and Q2 together gives 0.3C, and when converted to the positive-sequence potential difference of 0.3V applied to capacitor C1, the capacitance becomes 1C. In this way, 1C in the multiplication circuit 101 of Figure 7 can be realized by differential capacitance.

[0052] In the circuit shown in Figure 7, the operation when charge transfer occurs after multiplying the first input value (input A) and the second input value (input B) will be explained with reference to the timing chart in Figure 9. Figure 9 shows the control operation of the positive-phase side of the differential circuit in Figure 7. The negative-phase side can be controlled in the same way as in Figure 9.

[0053] In the timing chart shown in Figure 9, the control of the capacitance array 201+ is divided into five periods: reset period, input period 1, input period 2, charge redistribution period, and charge transfer period. The process corresponding to the timing chart is shown as a flowchart in Figure 11. This flowchart shows the flow of processing executed by the control circuit 103. Figure 9 shows the state of the control signals controlled by switch SW during each period supplied by the control circuit 103. During the reset period, all capacitors of the capacitance array 201+ are reset. In this embodiment, the ground voltage is set to 0.6V, so only the VRC switch is High, and the VRP, VRN, and COMP switches are Low. Also, by setting the INP switch to High and inputting a voltage of 0.6V, the potential difference across each capacitor becomes 0 and is reset. The above operation during the reset period corresponds to the reset operation of S1101.

[0054] In the subsequent input period 1, the input charge is received from INP. At this time, the VRP, VRC, and VRN switches are set to Low, and only the COMP switch is set to High. Also, the INP switch is set to Low, and the inverting input terminal of the capacitor is made floating. As a result, charge is supplied to each capacitor, and charge according to the capacitance of each capacitor is accumulated. At this time, the COMP voltage is 0.7875V. Since the voltage of the inverting input terminal of the capacitor is 0.6V, the potential difference across each capacitor is 0.1875V. Note that in input period 1, the transfer path from the transmitting side's capacitance array to INP is in a floating state (voltage is not controlled from the outside), and charge transfer is performed based on 0.6V, so the voltage at INP is 0.6V. When performing charge injection in input period 1, the INP switch is kept off because turning on the VRC switch of the INP node will prevent charge transfer from occurring.

[0055] The first total charge Qt held during input period 1 is expressed by the following formula. This value is based on the charge amount corresponding to 10¹ in digital signal representation. Qt=(4C+2C+C+C)*0.1875=1.5C...(Formula 1) The operations during input period 1 described above correspond to the process of storing the first input value of S1102 in the capacity array 201.

[0056] Next, in input period 2, a digital signal is input that will be multiplied by the analog signal input in input period 1. Here, we assume that "010" is input. Therefore, for C4+, C1a+, C1b+, C1da+, and C1db+, VRC becomes High for reset, and the other switches become Low. Also, by setting the INP switch High and inputting VRC (0.6V), the potential difference across C4+, C1a+, C1b+, C1da+, and C1db+ becomes 0V, and the held charge is released. On the other hand, all switches for C2+ become Low, and the held charge is maintained. At this time, COMP is maintained at 0.6V. As a result, the charges of capacitors C4, C1a, and C1b are canceled out, and only the charge remains on C2. At this time, the inverting amplifier 202+ enters a virtual short circuit state because the voltages input to the inverting input terminal and the non-inverting input terminal coincide at 0.6V, and the parasitic capacitance around the capacitance array can be ignored when performing multiplication in input period 2.

[0057] The second total charge Qt' held during input period 2 is expressed by the following formula. Qt'=2C*0.1875=0.375C...(Formula 2) The operations during the input period 2 described above correspond to the process of storing the second input value of S1104 in the capacity array 201.

[0058] During the subsequent charge redistribution period, the COM switch is set to High, and all other switches are set to Low. INP is also set to Low. This connects all capacitors in parallel, and the charge held in C2 is distributed to each capacitor. At this time, the voltage at COMP becomes 0.375C / 8C+0.6=0.6469V. The operation during the above charge redistribution period corresponds to the charge redistribution process in S1105.

[0059] During the subsequent charge transfer period, similar to the charge redistribution period, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. At this time, since the voltage at the inverting input terminal of the capacitor is 0.6V, the potential difference across each capacitor is 0.0469V. Also, during the charge transfer period, the connection relationship between the inverting amplifier 202 and the capacitance array 201 is switched to the state shown in Figure 5. The operation during the charge transfer period described above corresponds to the process of transferring the charge held by the capacitance array 201 of S1106 to the adder circuit 102. Note that the capacitance array 501 of the adder circuit 102 is reset before the first charge transfer takes place.

[0060] In the flowchart of Figure 11, the charge redistribution process in S1103 was omitted because the first input value in S1102 was an analog input value. Also, although charge redistribution is performed in S1105 in Figure 11, this charge redistribution may also be omitted and charge transfer may be performed in S1106. Furthermore, in the process of holding the second input value in S1103, S1103 and S1106 may be integrated by transferring the charge held in the capacitive element corresponding to the significant bit of the second input value to the adder circuit 102.

[0061] By executing the process shown in the flowchart of Figure 11 above in parallel for multiple multiplier circuits 101, the charges transferred to the adder circuit 102 are added in the capacitance array 501, and the sum of the multiplication results from each multiplier circuit is obtained, and this sum is output in S1107. The execution timing of the process in Figure 11 may be simultaneous or with a time lag.

[0062] Figure 9 shows the timing chart when an analog input is multiplied by a digital input, while Figure 10 shows the timing chart when a digital input is multiplied by another digital input. Figure 10 shows the control operation of the positive-phase side of the differential circuit in Figure 7. The negative-phase side can be controlled in the same way as in Figure 10. The flowchart in Figure 11 also corresponds to the processing of the timing chart in Figure 10.

[0063] In the timing chart shown in Figure 10, the control of the capacitance array 201+ is divided into six periods: reset period, input period 1, charge redistribution period, input period 2, charge redistribution period, and charge transfer period. Figure 10 shows the control operation of switch SW during each period. During the reset period, the capacitance of all capacitors in the capacitance array 201+ is reset. In this embodiment, the ground voltage is set to 0.6V, so only the VRC switch is set to High, and the VRP, VRN, and COMP switches are set to Low. Also, by setting the INP switch to High and inputting 0.6V, the potential difference across each capacitor becomes 0 and is reset. The above operation during the reset period corresponds to the reset operation of S1101.

[0064] In the following input period 1, a digital signal is input. Since the input signal is a value of 101, C4+ has VRP High, C2+ has all Lows, C1a+ has VRP High, C1b+ has VRN High, and Cda+ and Cdb+ have all Lows. Also, the INP switch is set to High, fixing the inverting input terminal of the capacitors to 0.6V. This supplies charge to each capacitor, and charge according to the capacitance of each capacitor is accumulated. At this time, the COMP voltage is 0.6V. As a result, the voltages input to the inverting input terminal and the non-inverting input terminal of the inverting amplifier 202+ match at 0.6V, creating a virtual short circuit state, and the parasitic capacitance around the capacitance array can be ignored in input period 1.

[0065] The first total charge Qtd held during input period 1 is expressed by the following equation. This value is the same as the total charge Qt obtained by equation 1, which is the charge amount corresponding to 10¹ in digital signal representation. Qtd=4C*0.3+C*0.3=1.5C...(Formula 3) The operations during input period 1 described above correspond to the process of storing the first input value of S1102 in the capacity array 201.

[0066] In the subsequent charge redistribution period 1, the COM switch is set to High, and all other switches are set to Low. INP is also set to Low. As a result, all capacitors are connected in parallel, and the charge held in C4+ and C1a+ is distributed to each capacitor according to its capacitance. At this time, the voltage at COMP becomes 1.5C / 8C+0.6=0.7875V. The above operation in charge redistribution period 1 corresponds to the charge redistribution process in S1103.

[0067] Next, during input period 2, a digital signal is input to each capacitor that holds the charge redistributed during charge redistribution period 1. Here, we assume that "010" is input. Therefore, for C4+, C1a+, C1b+, C1da+, and C1db+, VRC becomes High for reset, and the other switches become Low. Also, by setting the INP switch High and inputting VRC (0.6V), the potential difference across C4+, C1a+, C1b+, C1da+, and C1db+ becomes 0V, and the held charge is released. On the other hand, all switches for C2+ become Low, and the held charge is maintained. At this time, COMP is maintained at 0.6V. As a result, the charges of capacitors C4, C1a, and C1b are erased, and only the charge of C2 remains. Here again, the inverting amplifier 202+ is in a virtual short-circuit state because the voltages input to the inverting input terminal and the non-inverting input terminal match at 0.6V, and the parasitic capacitance around the capacitance array can be ignored when performing multiplication in input period 2.

[0068] At this time, the second total charge Qtd' held during input period 2 is expressed by the following equation, which yields the same result as equation 2. Qtd'=2C*0.1875=0.375C...(Formula 4) The operations during the input period 2 described above correspond to the process of storing the second input value of S1104 in the capacity array 201.

[0069] In the subsequent charge redistribution period 2, the COM switch is set to High, and all other switches are set to Low. INP is also set to Low. As a result, all capacitors are connected in parallel, and the charge held in C2 is distributed to each capacitor. At this time, the voltage at COMP becomes 0.375C / 8C+0.6=0.6469V. The above operation in charge redistribution period 2 corresponds to the charge redistribution process in S1105.

[0070] During the subsequent charge transfer period, similar to the charge redistribution period, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. At this time, since the voltage at the inverting input terminal of the capacitor is 0.6V, the potential difference across each capacitor is 0.0469V. Also, at this time, the control circuit 103 switches the connection relationship between the inverting amplifier 202 and the capacitance array 201 to the state shown in Figure 5. The operation during the above charge transfer period corresponds to the process of transferring the charge held by the capacitance array 201 in S1106 to the adder circuit 102. Note that the capacitance array 501 of the adder circuit 102 is reset before the first charge transfer takes place.

[0071] In the flowchart of Figure 11, which corresponds to the timing chart of Figure 10, charge redistribution is performed in S1105 in Figure 11. However, this charge redistribution may be omitted, and charge transfer may be performed in S1106. Furthermore, in the process of holding the second input value in S1103, S1103 and S1106 may be integrated by transferring the charge held in the capacitive element corresponding to the significant bit of the second input value to the adder circuit 102.

[0072] By executing the process shown in the flowchart of Figure 11 above in parallel for multiple multiplier circuits 101, the charges transferred to the adder circuit 102 are added in the capacitance array 501, and the sum of the multiplication results from each multiplier circuit is obtained, and this sum is output in S1107. The execution timing of the process in Figure 11 may be simultaneous or with a time lag.

[0073] An example of an embodiment has been described above. According to the multiply-accumulate unit corresponding to this embodiment, the multiply-accumulate operation can be performed as an analog operation rather than a digital operation, and the calculation speed can be increased compared to conventional multiply-accumulate operations. Specifically, in the case of digital operations, only one value can be added together, but in the case of analog operations, by using a circuit as shown in Figure 5 and providing multiple stages of the input-side multiplication circuit 101, it is possible to add multiple values ​​simultaneously. The operation of the multiplication circuit 101 can be performed synchronously and in parallel, and the input to the adder circuit 102 can be performed almost simultaneously, so the number of processing steps can be minimized, and speed can be increased compared to digital circuits. From the viewpoint of power consumption, analog circuits that operate with an intermediate amplitude according to the charge consume less power compared to digital circuits that operate with a fixed amplitude. In addition, since the charge addition operation can be performed asynchronously, there is no need to run a clock, which also has advantages in terms of circuit layout.

[0074] Furthermore, when implemented with an FPGA, the clock frequency tends to be lower and power consumption higher due to the influence of wiring capacitance. However, in the circuit configuration corresponding to this embodiment, the influence of parasitic capacitance can be reduced, so high speed can be achieved while keeping power consumption down. In addition, as mentioned above, the number of processing steps can be reduced, which also improves power consumption.

[0075] [Differentiation] In the above-described embodiment, the case where each multiplication circuit 101 is configured as a circuit using a single-stage capacitive array was explained, but each multiplication circuit 101 can also be configured using a multi-stage capacitive array.

[0076] Figure 12 shows an example in which the multiplication circuit 101 is configured using a two-stage capacitance array. The multiplication circuit 101 is configured such that the first subcircuit 1201 and the second subcircuit 1202 are connected to form a loop. Switch 1203 controls the charge transfer from the first subcircuit 1201 to the second subcircuit 1202. It is used to switch the charge transfer path on and off when performing the operation. Switch 1204 is also used to switch the charge transfer path on and off when performing charge transfer from the second subcircuit 1202 to the first subcircuit 1201. As shown in Figure 12, in this modified example, a charge transfer path from the second subcircuit 1202 to the first subcircuit 1201 is also secured. The first subcircuit 1201 includes the first stage first capacitance array 201A and the first inverting amplifier 202A, and the second subcircuit 1202 includes the second stage second capacitance array 201B and the second inverting amplifier 202B. In Figure 12, the multiplication circuit 101 is shown as a configuration using two stages of capacitance arrays, but it is also possible to have a configuration that further includes three or more stages of capacitance arrays, i.e., a third subcircuit, a fourth subcircuit, etc.

[0077] In Figure 12, (A) shows the circuit connection state when charge is stored in the first stage capacitance array 201A, (B) shows the circuit connection state when the charge held in the first stage capacitance array 201A is transferred to the second stage capacitance array 201B, and (C) shows the circuit connection state when the charge held in the second stage capacitance array 201B is transferred to the first stage capacitance array 201A. Note that in Figure 12(C), the positional relationship between the first subcircuit 1201 and the second subcircuit 1202 is reversed compared to Figures 12(A) and (B), but this is for illustrative purposes only and does not change the actual circuit arrangement. In Figures 12(A), (B), and (C), the capacitance arrays 201A, 201B, inverting amplifiers 202A, 202B, and parasitic capacitors Cst1 and Cst2 are the same as those shown in Figure 2. Furthermore, parasitic capacities Cst5 and Cst6 represent parasitic capacities related to the second-stage capacity array 201B, and their properties are the same as those of parasitic capacities Cst1 and Cst2. Therefore, the explanation of these elements will be based on the explanation in Figure 2, and will be omitted here.

[0078] The operation of the multiplication circuit 101A shown in Figure 12 will be explained below with reference to the flowchart in Figure 13. The flowchart shows the flow of processing performed by the control circuit 103. When using a multi-stage capacitive array 201, multiplication can be performed during charge transfer. First, the processing when the first input value A is an analog value, and the second input value B and third input value C are digital values ​​will be explained.

[0079] Before inputting the first input value A, the multiplication circuit 101A is reset in S1301. Specifically, the capacitance arrays 201A and 201B are reset. In Figure 12(A), the inverting amplifier 202A connected to the capacitance array 201A is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst1 is negligible. In the following S1302, the first input value A is held in the first capacitance array 201A. Here, we will explain assuming that the first total charge amount Qt in Figure 9 is held as an analog value as the first input value A. The charge Qt corresponding to the first input value A is distributed and held in each capacitance element of the capacitance array 201A according to the magnitude of the capacitance. Note that a switch 1201 is placed between the first stage capacitance array 201A and the second stage capacitance array 201B, and at this point, switch 1201 is turned off so that the capacitance array 201A is separated from the capacitance array 201B.

[0080] Next, in S1303, charge transfer is performed from the first capacitance array 201A to the second capacitance array 201B. When performing charge transfer, as shown in Figure 12(B), only the charge held by the capacitance elements whose bits are 1 (i.e., have a significant value) at the second input value B is transferred. For example, the charge of the capacitance element corresponding to the significant value may be maintained, and the charge held by the capacitance element whose bits are 0 may be reset before the charge is transferred. Here, we assume that "010" is given as the digital value of input B, similar to the example explained in Figure 9. Therefore, only the charge of the capacitance element with capacitance 2C is maintained, and the rest are reset. Then, switch 1201 is turned on to connect the first capacitance array 201A to the second capacitance array 201B, and the connection is switched so that the first inverting amplifier 202A operates as a 1x amplifier. As a result, only the charge held by the capacitance elements in the first capacitance array 201A whose bits are 1 is transferred and input to the second capacitance array 201B. On the second capacitance array 201B side, the second inverting amplifier 202B is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst5 is negligible. Therefore, the input charge is distributed and held to each capacitance element of the second capacitance array 201B according to the magnitude of its capacitance. At this point, the multiplication of the first input value A and the second input value B is complete, and the charge redistribution is also complete. At this time, the total amount of charge held by the second capacitance array 201B corresponds to the second total charge amount Qt'.

[0081] Next, in S1304, charge transfer is performed from the second capacitance array 201B to the first capacitance array 201A. When performing charge transfer, as shown in Figure 12(C), only the charge held by the capacitance elements whose bits are 1 (have a significant value) at the third input value C is transferred. Similar to S1303, the charge of the capacitance elements corresponding to the significant value may be maintained, and the charge held by the capacitance elements whose bits are 0 may be reset before the charge transfer. Here, for example, we assume that "110" is given as the digital value of the third input value C. Therefore, only the charges of the capacitance elements with capacitances of 4C and 2C are maintained, and the rest are reset. Then, switch 1204 is turned on to connect the second capacitance array 201B to the first capacitance array 201A, and the connection is switched so that the inverting amplifier 202B operates as a 1x amplifier. As a result, only the charge held by the capacitance elements whose bits are 1 in the second capacitance array B is transferred and re-input to the first capacitance array 201A. On the first capacitance array 201A side, the inverting amplifier 202A is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst1 is negligible. Therefore, the input charge is distributed and held to each capacitance element of the first capacitance array 201A according to the magnitude of its capacitance. At this point, the multiplication of the result of multiplying the first input value A and the second input value B by the third input value C is completed, and further charge redistribution is completed.

[0082] After processing in S1304, the process may proceed to S1305 to transfer the charge held in the first capacitance array 201A to the adder circuit 102, or it may return to S1303. If it returns to S1303, the charge held in the first capacitance array 201A is multiplied by the fourth input value D and the charge is transferred to the second capacitance array 201B. After that, the process may proceed to S1305 to transfer the charge held in the second capacitance array 201B to the adder circuit 102, or it may proceed to S1304. These multiplication processes are performed until the desired number of multiplications is reached, and once the desired number of multiplications is reached, in S1305 the charge corresponding to the multiplication result is transferred from the first capacitance array 201A or the second capacitance array 201B to the adder circuit 102. After that, in S1306, the charge transferred to the adder circuit 102 is added in the capacitance array 501 and the sum of the multiplication results in each multiplication circuit is output.

[0083] Next, we will explain the processing when the first input value A, the second input value B, and the third input value C are digital values. Before inputting the first input value A, the multiplication circuit 101A is reset in S1301. In particular, the capacitance arrays 201A and 201B are reset. In the following S1302, the first input value A is held in the first capacitance array 201A. Since the first input value A is given as the digital value "101", charge is held only in the capacitance elements with capacitances of 4C and 1C, and the capacitance element with capacitance of 2C and the dummy element are reset. At this point, switch 1201 is turned off so that the first capacitance array 201A is separated from the second capacitance array 201B. Next, charge redistribution is performed in the first capacitance array 201A, and charge corresponding to the magnitude of the capacitance is held in each capacitance element of the capacitance array 201A. The processing from S1303 onwards is the same as when the first input value A was an analog value.

[0084] In the above explanation, the case in which a predetermined input value is multiplied during charge transfer from the first capacitance array 201A or the second capacitance array B to the next stage was described. However, multiplication may not be performed during charge transfer, and the next input value multiplication may be performed in the capacitance array 201 after the charge has been transferred to the next stage capacitance array 201. In this case, only some of the capacitance elements in the source capacitance array 201 will retain the charge. However, when this charge is transferred, charge redistribution will occur at the destination, whether it be the adder circuit 102 or the capacitance array 201, so multiplication can be performed immediately.

[0085] As described above, a multiplier circuit 101 can be constructed by connecting multiple subcircuits, each having a capacitance array 201 and an inverting amplifier 202, in stages. In this configuration, charge transfer from the subcircuit to the adder circuit 102 is performed according to the number of multiplications. For example, when performing two multiplications, in the above configuration, the charge held in the second capacitance array 201B is transferred to the adder circuit 102. Also, when performing three multiplications, the charge held in the first capacitance array 201A is transferred to the adder circuit 102. In this embodiment, the desired number of multiplications can be achieved by forming a loop using the output of the preceding subcircuit as the input to the next subcircuit. The modified versions described above also achieve the same effects as the embodiments. In particular, by using multiple subcircuits in a loop, any number of multiplication operations can be realized in the common circuit. Furthermore, since charge redistribution can be performed during charge transfer, the number of processing steps can be reduced, enabling further speed improvements and further reductions in power consumption.

[0086] <Summary of Embodiments> The above embodiments disclose at least the following sum-of-accumulate circuit, control method for the sum-of-accumulate circuit, and arithmetic system. (1) A sum-of-accumulate circuit The system comprises multiple multiplication circuits and an adder circuit that adds the multiplication results from each of the multiple multiplication circuits and outputs an added result. Each of the above-mentioned multiple multiplication circuits is A capacitance array containing multiple capacitance elements, An inverting amplifier is connected to the aforementioned capacitance array in a switchable manner. Includes, When performing multiplication in the aforementioned multiplication circuit, The first side of the capacitance array is connected to the inverting input terminal of the inverting amplifier, and the second side of the capacitance array opposite the first side is connected to the output terminal of the inverting amplifier. A predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier. When the multiplication result of the multiplication circuit is transferred to the adder circuit, A sum-of-accumulate circuit, wherein the first side of the capacitance array is connected to the non-inverting input terminal of the inverting amplifier, and the second side is connected to the inverting input terminal and the output terminal. (2) The capacitance array is configured by connecting a plurality of capacitance elements in parallel, The magnitude of the capacitance of each of the plurality of capacitive elements is set to have a power of 2 relationship, as described in (1) for the sum-of-accumulate circuit. (3) The sum-of-products circuit according to (1) or (2), wherein the capacitance array includes a dummy capacitance, and the capacitance of the dummy capacitance is the same as the smallest capacitance among the multiple capacitance elements constituting the capacitance array. (4) The sum-of-accumulate circuit according to any one of (1) to (3), wherein when multiplication is performed in the multiplication circuit, voltages are supplied to the inverting input terminal and the non-inverting input terminal such that the inverting amplifier is in a virtual short-circuit state. (5) The plurality of capacitive elements constituting the capacitive array are composed of either a first type of capacitive element consisting of a single capacitive element or a second type of capacitive element consisting of a combination of a plurality of capacitive elements with different capacitances. The sum-of-accumulate circuit according to any one of (1) to (4), wherein the second type of capacitive element consists of a combination of a capacitive element having the smallest first capacitance in the sum-of-accumulate circuit and a capacitive element having a second capacitance larger than the first capacitance. (6) The sum-of-products operation circuit is configured by differential operation using a first sum-of-products operation circuit in positive phase and a second sum-of-products operation circuit in negative phase, and when multiplication is performed in the multiplication circuit, Among the second type of capacitive elements in the first sum-of-accumulate circuit, The second side terminal of the second capacitance element is connected to the output terminal of the inverting amplifier of the first multiply-accumulate circuit. The terminal on the second side of the first capacitance element is connected to the output terminal of the inverting amplifier of the second multiply-accumulate circuit. Among the second type of capacitive elements in the second multiply-accumulate circuit, The second side terminal of the second capacitance element is connected to the output terminal of the inverting amplifier of the second sum-of-products circuit. The multiply-accumulate circuit according to (5), wherein the terminal on the second side of the capacitive element having the first capacitance is connected to the output terminal of the inverting amplifier of the first multiply-accumulate circuit. (7) The sum-of-products operation circuit according to any one of (1) to (6), wherein the summing circuit comprises a capacitance array including a plurality of capacitive elements and an inverting amplifier connected to the capacitance array in a switchable manner, or comprises at least one capacitive element. (8) The multiplication circuit is configured by arranging a plurality of subcircuits, each subcircuit including a capacitance array containing a plurality of capacitive elements and an inverting amplifier connected to the capacitance array in a switchable manner. (9) When multiplication is performed in the first subcircuit among the multiple subcircuits arranged above, The first side of the first capacitance array of the first subcircuit is connected to the inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the output terminal of the first inverting amplifier. The predetermined ground voltage is supplied to the non-inverting input terminal of the first inverting amplifier. When transferring the charge result of the multiplication in the first subcircuit from the first subcircuit to a second subcircuit different from the first subcircuit, The sum-of-accumulate circuit according to (8), wherein the first side of the first capacitance array is connected to the non-inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the inverting input terminal and the output terminal of the first inverting amplifier. (10) The multiplication circuit described in (9), wherein the multiplication circuit is configured to repeat multiplication a predetermined number of times by supplying the output of the second subcircuit as the input of the first subcircuit. (11) An arithmetic system comprising multiple multiply-accumulate circuits as described in any one of (1) through (10). (12) A method for controlling a sum-of-accumulate circuit as described in any one of (1) to (6), A first step of resetting the multiplication circuit, A second step of supplying a first charge amount to the reset multiplication circuit's capacitance array, A third step is to perform a multiplication process of the predetermined digital value by resetting the charge of at least some of the capacitive elements corresponding to a predetermined digital value in the capacitance array that holds the charge of the first charge amount, A fourth step of transferring the charge of the second charge amount held by the capacitance array, whose charge of at least some of the capacitance elements has been reset, to the adding circuit; A fifth step in which the first to fourth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above. (13) In the third step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the inverting amplifier such that the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit is in a virtual short-circuit state. The control method for a sum-of-accumulate circuit according to (12), wherein in the fourth step, the inverting amplifier operates as a 1:1 amplifier, thereby transferring the charge held in the capacitance array to the adder circuit. (14) A method for controlling a sum-of-accumulate circuit according to (12) or (13), wherein in the fourth step, the charge of the second charge quantity is redistributed in the capacitance array, and the redistributed charge is transferred to the adder circuit. (15) The second step is, A sixth step of supplying charge to at least some of the multiple capacitive elements constituting the capacitive array to maintain the first charge amount, and resetting the capacitive elements that are not supplied with charge, In the capacitance array that holds the charge of the first charge amount, a seventh step is to redistribute the charge of the first charge amount. Includes, The method of operating a sum-of-accumulate circuit according to any one of (12) to (14), wherein in the sixth step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the inverting amplifier such that the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit is in a virtual short-circuit state. (16) A method for controlling a sum-of-accumulate circuit as described in any one of (1) to (6), A first step of resetting the multiplication circuit, A second step of supplying a first charge amount to the reset multiplication circuit's capacitance array, A third step is to perform a multiplication process of the predetermined digital value by transferring only the charge of at least some of the capacitive elements corresponding to a predetermined digital value to the adder circuit in the capacitance array that holds the charge of the first charge amount, A fourth step in which the first to third steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above. (17) A method for controlling a sum-of-accumulate circuit as described in (9) or (10), A first step of resetting the multiplication circuit, A second step of supplying a charge amount corresponding to a first input value to the first capacitance array of the first subcircuit of the reset multiplier circuit, A second step of transferring the charge of at least some of the capacitive elements in the first capacitive array that correspond to the second input value to the second capacitive array of the second subcircuit, A third step of transferring the charge of at least some of the capacitive elements in the second capacitive array that correspond to the third input value to the first capacitive array of the first subcircuit, A fourth step is performed in which the second and third steps are repeated according to a desired number of multiplication steps, after the third step described above. A fifth step, after the third or fourth step, is to transfer the charge held by the first or second capacitance array to the adder circuit. A sixth step in which the first to fifth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above. (18) In the second step described above, When the first input value is an analog value, the charge of the first charge amount is distributed according to the capacitance of each capacitive element in the first capacitive array and held in each capacitive element, thereby holding the charge amount corresponding to the first input value in the first capacitive array, or, A control method for a sum-of-accumulate circuit according to (17), wherein, when the first input value is a digital value, charge is held only in the capacitance element corresponding to the significant value of the first input value among the capacitance elements constituting the first capacitance array, and then the held charge is redistributed to each capacitance element of the first capacitance array to hold the charge of the first charge amount in the first capacitance. (19) A method for controlling a sum-of-accumulate circuit as described in (9) or (10), A first step of resetting the multiplication circuit, A second step of supplying a charge amount corresponding to a first input value to the first capacitance array of the first subcircuit of the reset multiplier circuit, A third step of transferring the charge held in the first capacitance array to the second capacitance array of the second subcircuit, A fourth step is to perform a multiplication process of the charge held by the second capacitance array by the second input value by resetting the charge of at least some of the capacitance elements corresponding to the second input value in the second capacitance array, A fifth step is to transfer the charge held in the second capacitance array after the multiplication of the second input value to the first capacitance array of the first subcircuit, A sixth step in which the charge of the first capacitance array is multiplied by the third input value by resetting the charge of at least some of the capacitance elements corresponding to the third input value, A seventh step is performed, in which the third and fourth steps, and the fifth and sixth steps are repeated according to a desired number of multiplication steps, after the sixth step. An eighth step, after the sixth or seventh step, of transferring the charge held by the first or second capacitance array to the adder circuit, A ninth step in which the first to eighth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above. (20) In the second step described above, When the first input value is an analog value, the charge of the first charge amount is distributed according to the capacitance of each capacitive element in the first capacitive array and held in each capacitive element, thereby holding the charge amount corresponding to the first input value in the first capacitive array, or, A control method for a sum-of-accumulate circuit according to (19), wherein, when the first input value is a digital value, the charge of the first charge amount is held in the first capacitance by holding charge only in the capacitance element corresponding to the significant value of the first input value among the capacitance elements constituting the first capacitance array. (21) The method of operating the sum-of-accumulate circuit according to (19) or (20), wherein in the third step, the fifth step, and the eighth step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the first inverting amplifier and the second inverting amplifier, respectively, so that they are in a virtual short-circuit state.

[0087] [Other embodiments] The invention is not limited to the embodiments described above, and various modifications and changes are possible within the scope of the invention. Accordingly, the following claims are attached to make the scope of the invention public. [Explanation of symbols]

[0088] 10: Add-accumulate circuit, 101: Multiplier circuit, 102: Adder circuit, 103: Control circuit

Claims

1. It is a sum-of-accumulate circuit. The system comprises multiple multiplication circuits and an adder circuit that adds the multiplication results from each of the multiple multiplication circuits and outputs an added result. Each of the above-mentioned multiple multiplication circuits is A capacitance array containing multiple capacitance elements, An inverting amplifier is connected to the aforementioned capacitance array in a switchable manner. Includes, When performing multiplication in the aforementioned multiplication circuit, The first side of the capacitance array is connected to the inverting input terminal of the inverting amplifier, and the second side of the capacitance array opposite to the first side is connected to the output terminal of the inverting amplifier. A predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier. When the multiplication result of the multiplication circuit is transferred to the adder circuit, A sum-of-accumulate circuit, wherein the first side of the capacitance array is connected to the non-inverting input terminal of the inverting amplifier, and the second side is connected to the inverting input terminal and the output terminal.

2. The aforementioned capacitance array is configured by connecting multiple capacitance elements in parallel. The sum-of-products circuit according to claim 1, wherein the magnitudes of the capacitances of the plurality of capacitive elements are set to have a power of 2 relationship.

3. The sum-of-products circuit according to claim 2, wherein the capacitance array includes a dummy capacitance, and the capacitance of the dummy capacitance is the same as the smallest capacitance among the plurality of capacitance elements constituting the capacitance array.

4. The sum-of-products circuit according to claim 3, wherein when multiplication is performed in the multiplication circuit, voltages are supplied to the inverting input terminal and the non-inverting input terminal such that the inverting amplifier is in a virtual short-circuit state.

5. The plurality of capacitive elements constituting the capacitive array are composed of either a first type of capacitive element consisting of a single capacitive element, or a second type of capacitive element consisting of a combination of a plurality of capacitive elements with different capacitances. The sum-of-products circuit according to claim 1, wherein the second type of capacitive element comprises a combination of a capacitive element having the smallest first capacitance in the sum-of-products circuit and a capacitive element having a second capacitance larger than the first capacitance.

6. The sum-of-accumulate circuit is configured by differential operation using a first sum-of-accumulate circuit in positive phase and a second sum-of-accumulate circuit in negative phase, and when multiplication is performed in the multiplication circuit, Among the second type of capacitive elements in the first sum-of-accumulate circuit, The second side terminal of the second capacitance element is connected to the output terminal of the inverting amplifier of the first sum-of-accumulate circuit. The terminal on the second side of the first capacitance element is connected to the output terminal of the inverting amplifier of the second sum-of-accumulate circuit. Among the second type of capacitive elements in the second multiply-accumulate circuit, The second side terminal of the second capacitance element is connected to the output terminal of the inverting amplifier of the second sum-of-products circuit. The multiply-accumulate circuit according to claim 5, wherein the terminal on the second side of the capacitive element having the first capacitance is connected to the output terminal of the inverting amplifier of the first multiply-accumulate circuit.

7. The aforementioned adding circuit is The sum-of-accumulate circuit according to claim 1, comprising a capacitance array including a plurality of capacitive elements and an inverting amplifier connected to the capacitance array in a switchable manner, or comprising at least one capacitive element.

8. The multiplication circuit is configured by arranging a plurality of subcircuits, each subcircuit including a capacitance array containing a plurality of capacitive elements and an inverting amplifier connected to the capacitance array in a switchable manner.

9. When multiplication is performed in the first subcircuit among the multiple subcircuits arranged above, The first side of the first capacitance array of the first subcircuit is connected to the inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the output terminal of the first inverting amplifier. The predetermined ground voltage is supplied to the non-inverting input terminal of the first inverting amplifier. When transferring the charge of the multiplication result in the first subcircuit from the first subcircuit to a second subcircuit different from the first subcircuit, The sum-of-accumulate circuit according to claim 8, wherein the first side of the first capacitance array is connected to the non-inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the inverting input terminal and the output terminal of the first inverting amplifier.

10. The multiplication circuit is configured to perform multiplication a predetermined number of times by supplying the output of the second subcircuit as the input of the first subcircuit, as described in claim 9.

11. A calculation system comprising a plurality of sum-of-accumulate circuits as described in any one of claims 1 to 10.

12. A method for controlling a sum-of-accumulate circuit according to any one of claims 1 to 6, A first step of resetting the multiplication circuit, A second step of supplying a first charge amount to the reset multiplication circuit's capacitance array, A third step is to perform a multiplication process of the predetermined digital value by resetting the charge of at least some of the capacitive elements corresponding to a predetermined digital value in the capacitance array that holds the charge of the first charge amount, A fourth step is to transfer the charge of the second charge amount held by the capacitance array, whose charge has been reset by at least some of the capacitance elements, to the adding circuit. A fifth step in which the first to fourth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above.

13. In the third step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the inverting amplifier such that the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit is in a virtual short-circuit state. The method for controlling a sum-of-accumulate circuit according to claim 12, wherein in the fourth step, the inverting amplifier operates as a 1:1 amplifier, thereby transferring the charge held in the capacitance array to the adder circuit.

14. The method for controlling a sum-of-accumulate circuit according to claim 13, wherein in the fourth step, the charge of the second charge quantity is redistributed in the capacitance array, and the redistributed charge is transferred to the adder circuit.

15. The second step described above is: A sixth step involves supplying charge to at least some of the multiple capacitive elements constituting the capacitive array to maintain the first charge amount, and resetting the capacitive elements that are not supplied with charge. In the capacitance array that holds the charge of the first charge amount, a seventh step is to redistribute the charge of the first charge amount. Includes, The method for operating a sum-of-accumulate circuit according to claim 12, wherein in the sixth step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the inverting amplifier such that the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit is in a virtual short-circuit state.

16. A method for controlling a sum-of-accumulate circuit according to any one of claims 1 to 6, A first step of resetting the multiplication circuit, A second step of supplying a first charge amount to the reset multiplication circuit's capacitance array, A third step is to perform a multiplication process of the predetermined digital value by transferring only the charge of at least some of the capacitive elements corresponding to a predetermined digital value to the adder circuit in the capacitance array that holds the charge of the first charge amount, A fourth step in which the first to third steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above.

17. A method for controlling a sum-of-accumulate circuit according to claim 9 or 10, A first step of resetting the multiplication circuit, A second step of supplying a charge amount corresponding to a first input value to the first capacitance array of the first subcircuit of the reset multiplier circuit, A second step of transferring the charge of at least some of the capacitive elements in the first capacitive array that correspond to the second input value to the second capacitive array of the second subcircuit, A third step of transferring the charge of at least some of the capacitive elements in the second capacitive array that correspond to the third input value to the first capacitive array of the first subcircuit, A fourth step is performed, in which the second and third steps are repeated according to a desired number of multiplication steps, after the third step described above. A fifth step, after the third or fourth step, is to transfer the charge held by the first or second capacitance array to the adding circuit. A sixth step in which the first to fifth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above.

18. In the second step described above, When the first input value is an analog value, the charge of the first charge amount is distributed according to the capacitance of each capacitive element in the first capacitive array and held in each capacitive element, thereby holding the charge amount corresponding to the first input value in the first capacitive array, or, A control method for a sum-of-accumulate circuit according to claim 17, wherein, when the first input value is a digital value, charge is held only in the capacitance element corresponding to the significant value of the first input value among the capacitance elements constituting the first capacitance array, and then the held charge is redistributed to each capacitance element of the first capacitance array to hold the charge of the first charge amount in the first capacitance.

19. A method for controlling a sum-of-accumulate circuit according to claim 9 or 10, A first step of resetting the multiplication circuit, A second step of supplying a charge amount corresponding to a first input value to the first capacitance array of the first subcircuit of the reset multiplier circuit, A third step of transferring the charge held in the first capacitance array to the second capacitance array of the second subcircuit, A fourth step is to perform a multiplication process of the charge held by the second capacitance array by the second input value by resetting the charge of at least some of the capacitance elements corresponding to the second input value in the second capacitance array, A fifth step is to transfer the charge held in the second capacitance array after the multiplication of the second input value to the first capacitance array of the first subcircuit, A sixth step is to perform a multiplication process of the charge held by the first capacitance array by the third input value by resetting the charge of at least some of the capacitance elements corresponding to the third input value in the first capacitance array, A seventh step is performed, in which the third and fourth steps, and the fifth and sixth steps are repeated according to a desired number of multiplication steps, after the sixth step. An eighth step, after the sixth or seventh step, of transferring the charge held by the first or second capacitance array to the adder circuit, A ninth step in which the first to eighth steps are performed for each of the plurality of multiplication circuits in the sum-of-accumulate circuit, and the sum of the charges transferred from each of the plurality of multiplication circuits is output. A control method for a sum-of-accumulate circuit, including the above.

20. In the second step described above, When the first input value is an analog value, the charge of the first charge amount is distributed according to the capacitance of each capacitive element in the first capacitive array and held in each capacitive element, thereby holding the charge amount corresponding to the first input value in the first capacitive array, or, A method for controlling a sum-of-accumulate circuit according to claim 19, wherein, when the first input value is a digital value, the charge of the first charge amount is held in the first capacitance by holding charge only in the capacitance element corresponding to the significant value of the first input value among the capacitance elements constituting the first capacitance array.

21. The method for operating a sum-of-accumulate circuit according to claim 20, wherein in the third step, the fifth step, and the eighth step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of the first inverting amplifier and the second inverting amplifier, respectively, so that they are in a virtual short-circuit state.

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