Semiconductor devices, motor drivers

Abstract

This prevents malfunctions caused by negative voltage. [Solution] The semiconductor device 10 includes, for example, a connection terminal BR, a ground terminal GND, a pull-down circuit 13 that conducts between the connection terminal BR and the ground terminal GND, and a cutoff circuit 30 that cuts off the current path from the ground terminal GND to the connection terminal BR via the pull-down circuit 13 when the voltage of the connection terminal BR is lower than that of the ground terminal GND.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a motor driver.

Background Art

[0002] Some semiconductor devices drive inductive loads such as motors.

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] However, there has been room for improvement in preventing malfunction due to negative voltage in conventional semiconductor devices.

[0006] The semiconductor device according to the present disclosure includes, for example, a connection terminal, a ground terminal, a pull-down circuit configured to conduct between the connection terminal and the ground terminal, and a cutoff circuit configured to cut off a current path from the ground terminal to the connection terminal through the pull-down circuit when the voltage of the connection terminal is lower than that of the ground terminal.

Brief Description of the Drawings

[0007] [Figure 1] FIG. 1 is a configuration diagram of a motor driver according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a brake circuit provided in the control circuit of the motor driver according to the embodiment. [Figure 3]Figure 3 shows the relationship between the motor terminal voltage V1 and the signal voltage V2 input to the inverting input terminal of the comparator provided in the brake circuit in the brake mode of the motor driver according to the embodiment. [Figure 4] Figure 4 shows the relationship between the motor terminal voltage V1 and the output voltage V3 of the comparator provided in the brake circuit in the brake mode of the motor driver according to the embodiment. [Figure 5] Figure 5 shows a first example configuration of the control circuit. [Figure 6] Figure 6 shows a second example configuration of the control circuit.

[0008] [Detailed explanation] The motor driver according to the embodiments will be described in detail below with reference to the drawings. The embodiments described below are general or specific examples. The numerical values, shapes, materials, components, installation positions of components, and connection configurations shown in the embodiments below are examples and are not intended to limit the scope of this disclosure. In addition, among the components in the embodiments below, components that are not described in the independent claim indicating the highest-level concept will be described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios. Also, the embodiments and their modifications below may include similar components, and similar components will be given the same reference numerals, and redundant descriptions will be omitted.

[0009] Referring to Figure 1, the basic configuration of the motor driver 1 according to this embodiment will be described.

[0010] The motor driver 1 includes an H-bridge circuit for driving a brushed DC motor M (hereinafter referred to as motor M), and a control circuit 10 for controlling the H-bridge circuit and motor M.

[0011] Motor M is, for example, an in-vehicle motor used to drive windows, seats, seat belts, mirrors, wipers, etc.

[0012] The H-bridge circuit comprises a first half-bridge output stage HB1 consisting of a first high-side transistor QH1 and a first low-side transistor QL1, and a second half-bridge output stage HB2 consisting of a second high-side transistor QH2 and a second low-side transistor QL2. The first high-side transistor QH1, the first low-side transistor QL1, the second high-side transistor QH2, and the second low-side transistor QL2 can be, for example, N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0013] The first electrode (e.g., drain) of the first high-side transistor QH1 and the first electrode (e.g., drain) of the second high-side transistor QH2 are connected to terminal VB, to which a DC power supply for driving the motor M is connected. The second electrode (e.g., source) of the first high-side transistor QH1 is connected in series with the first electrode (e.g., drain) of the first low-side transistor QL1. The second electrode (e.g., source) of the second high-side transistor QH2 is connected in series with the first electrode (e.g., drain) of the second low-side transistor QL2. The second electrode (e.g., source) of the first low-side transistor QL1 and the second electrode (e.g., source) of the second low-side transistor QL2 are connected to ground potential (earth potential) GND. The connection point of the first high-side transistor QH1 and the first low-side transistor QL1 is connected to the + terminal of the motor M, and the connection point of the second high-side transistor QH2 and the second low-side transistor QL2 is connected to the - terminal of the motor M.

[0014] The control circuit 10 comprises high-side drive circuits 11-1 and 11-2, low-side drive circuits 12-1 and 12-2, and a brake circuit 13. The high-side drive circuit 11-1 is connected via terminal GH1 to the control electrode (e.g., gate) of the first high-side transistor QH1 and controls the on / off state of the first high-side transistor QH1. The high-side drive circuit 11-2 is connected via terminal GH2 to the control electrode (e.g., gate) of the second high-side transistor QH2 and controls the on / off state of the second high-side transistor QH2. The low-side drive circuit 12-1 is connected via terminal GL1 to the control electrode (e.g., gate) of the first low-side transistor QL1 and controls the on / off state of the first low-side transistor QL1. The low-side drive circuit 12-2 is connected via terminal GL2 to the control electrode (e.g., gate) of the second low-side transistor QL2 and controls the on / off state of the second low-side transistor QL2. The brake circuit 13 is connected to the + terminal of the motor M via connection terminal BR1 and to the - terminal of the motor M via connection terminal BR2.

[0015] When the motor M is rotated in the forward direction, the control circuit 10 controls the first high-side transistor QH1 and the second low-side transistor QL2 to be turned on, and the second high-side transistor QH2 and the first low-side transistor QL1 to be turned off. When the motor M is rotated in the reverse direction, the control circuit 10 controls the second high-side transistor QH2 and the first low-side transistor QL1 to be turned on, and the first high-side transistor QH1 and the second low-side transistor QL2 to be turned off. More detailed control methods for the rotational operation of the motor M can be found using existing methods, such as the method described in Patent Document 1 (Japanese Patent Application Publication No. 2021-29084), so such details are omitted here.

[0016] Next, with reference to Figure 2, the configuration of the brake circuit 13 provided in the control circuit 10 of the motor driver 1 according to this embodiment will be described. Figure 2 is a circuit diagram of the brake circuit 13. The brake circuit 13 is used to maintain the stopped state of the motor M in the brake mode, which stops the rotation of the motor M, by short-circuiting the + terminal and - terminal of the motor M by connecting them to the ground potential GND. Note that the potential to which the + terminal and - terminal of the motor M are connected is not limited to the ground potential GND, but can be any potential that can maintain the stopped state of the motor M.

[0017] In Figure 2, the half-bridge output stage HB has a common configuration for both the first half-bridge output stage HB1 and the second half-bridge output stage HB2. Therefore, the description is simplified compared to Figure 1, using the terms high-side transistor QH, low-side transistor QL, connection terminal BR, terminal GH, and terminal GL. The high-side drive circuit 11, which controls the high-side transistor QH, is connected to terminal GH, which is connected to the control electrode of the high-side transistor QH. The low-side drive circuit 12, which controls the low-side transistor QL, is connected to terminal GL, which is connected to the control electrode of the low-side transistor QL. The connection point between the high-side transistor QH and the low-side transistor QL is connected to the connection terminal BR and the terminal of the motor M.

[0018] The brake circuit 13 is configured as follows: The first electrode of the first switch S1 is connected to the connection terminal BR via resistor R7, and the second electrode of the first switch S1 is connected to the ground potential GND. The output terminal of comparator C1 is connected to the control electrode of the first switch S1. The first electrode of the second switch S2 is connected to the control electrode of the first switch S1, and the second electrode of the second switch S2 is connected to the ground potential GND. The control electrode of the second switch S2 is connected to terminal EN via inverter 21. A series circuit of resistors R4, R5, and R6 is connected between the connection terminal BR and the ground potential GND. The third switch S3 has its first electrode connected to the connection point of resistors R5 and R6, its second electrode connected to the ground potential GND, and its control electrode connected to the output terminal of comparator C1. For example, N-channel MOSFETs can be used for the first switch S1, second switch S2, and third switch S3. A series circuit of resistors R1, R2, and R3 is connected between terminal SB and the ground potential GND. The fourth switch S4 has its first electrode connected to ground potential GND, its second electrode connected to the connection point of resistors R4 and R5 and the inverting input terminal - of comparator C1, and its control electrode connected to the connection point of resistors R1 and R2. For example, a P-channel MOSFET can be used for the fourth switch S4. The connection point of resistors R2 and R3 is connected to the non-inverting input terminal + of comparator C1. The positive power supply terminal of comparator C1 is connected to terminal SB via a DC current source 22, and the negative power supply terminal is connected to ground potential GND.

[0019] The setting circuit 20 comprises a comparator C1, a third switch S3, a fourth switch S4, and resistors R1 to R6, configured as described above. The setting circuit 20 monitors the terminal voltage V1 input to the brake circuit 13 from the connection terminal BR and controls the on / off state of the first switch S1 according to the terminal voltage V1.

[0020] Next, referring to FIGS. 2, 3, and 4, the operation of the brake mode of the motor driver 1 will be described. FIG. 3 is a diagram showing the relationship between the terminal voltage V1 and the signal voltage V2 input to the inverting input terminal - of the comparator C1 in the brake mode of the motor driver 1. FIG. 4 is a diagram showing the relationship between the terminal voltage V1 and the output voltage V3 of the comparator C1 in the brake mode of the motor driver 1.

[0021] When operating the motor driver 1 in the brake mode, the operation switching voltage Ven input to the terminal EN is Vh2 (HI potential, for example, 5V), and a predetermined control voltage Vsb is input to the terminal SB.

[0022] Since the operation switching voltage Ven is Vh2, the operation switching voltage Ven is inverted by the inverter 21, and the voltage V4 input to the control electrode of the second switch S2 is zero (LO potential). Therefore, the second switch S2 is in the off state. Since the second switch S2 is in the off state, the first switch S1 and the third switch S3 are in a state controllable by the output voltage V3 of the comparator C1.

[0023] When a predetermined control voltage Vsb is input to the terminal SB, a predetermined reference voltage Vr = Vsb × R3 / (R1 + R2 + R3) is input to the non-inverting input terminal + of the comparator C1. Also, Vsb × (R2 + R3) / (R1 + R2 + R3) is input to the control electrode of the fourth switch S4. Thereby, the maximum value of the signal voltage V2 input to the inverting input terminal - of the comparator C1 can be suppressed by the clamp voltage Vc = Vsb × (R2 + R3) / (R1 + R2 + R3) + Vs4. Here, Vs4 is the threshold voltage of the fourth switch S4. Thus, by setting the clamp voltage Vc, the brake circuit 13 can be protected from high voltages. When it is not necessary to set the clamp voltage Vc, the fourth switch S4 can be omitted.

[0024] Then, to initiate brake mode, the control circuit 10 shuts down the high-side drive circuit 11 to turn off the high-side transistor QH, and the low-side drive circuit 12 turns on the low-side transistor QL. As a result, the terminal voltage V1 decreases toward zero, and the rotation of the motor M stops. Once the terminal voltage V1 begins to decrease, the control circuit 10 turns off the low-side transistor QL using the low-side drive circuit 12.

[0025] When the terminal voltage V1 is large and V1 × (R5 + R6) / (R4 + R5 + R6) is greater than the clamp voltage Vc, the signal voltage V2 is suppressed by the clamp voltage Vc, as shown in section (1) of Figure 3. Then, as the terminal voltage V1 decreases further and V1 × (R5 + R6) / (R4 + R5 + R6) becomes less than or equal to the clamp voltage Vc, the signal voltage V2 becomes V1 × (R5 + R6) / (R4 + R5 + R6), as shown in section (2) of Figure 3.

[0026] Then, when the terminal voltage V1 drops to the first set voltage Vth1, the signal voltage V2 becomes smaller than the reference voltage Vr input to the non-inverting input terminal + of comparator C1. As shown in Figure 4, the output voltage V3 of comparator C1 switches from zero (LO potential) to Vh1 (HI potential, e.g., 5V), which turns on the first switch S1 and the third switch S3. When the first switch S1 is turned on, the connection terminal BR is connected to ground potential GND via resistor R7, the terminal voltage V1 becomes zero, and the motor M enters a short-circuit brake state.

[0027] Furthermore, when the third switch S3 is turned on, as shown in section (3) of Figure 3, the signal voltage V2 input to the inverting input terminal - of comparator C1 switches to V2 = V1 × R5 / (R4 + R5). This sets a second setting voltage Vth2, which is greater than the first setting voltage Vth1, as a setting voltage that allows the first switch S1 to be turned off when the terminal voltage V1 rises. By setting the first setting voltage Vth1 and the second setting voltage Vth2 to different values, it is possible to prevent chattering in the output voltage V3 when the output voltage V3 of comparator C1 switches from zero to Vh1 or from Vh1 to zero.

[0028] According to the brake circuit 13, since the connection terminal BR is connected to ground potential GND via resistor R7, the short-circuit brake of motor M can be maintained even when the low-side transistor QL is turned off. If the short-circuit brake of motor M is maintained by turning on the low-side transistor QL, the internal power supply or gate drive circuit or other circuit for turning on the low-side transistor QL will operate, resulting in a current consumption of several mA. In contrast, the brake circuit 13 allows the short-circuit brake of motor M to be maintained even when the low-side transistor QL is turned off, thereby suppressing the current consumption caused by the operation of the low-side transistor QL.

[0029] Furthermore, when the terminal voltage V1 is large, there is a concern that the first switch S1, which is composed of an N-channel MOSFET, may be destroyed if it is turned on and abruptly connected to the ground potential GND. For this reason, the setting circuit 20 turns on the first switch S1 when the terminal voltage V1 drops to a predetermined first setting voltage Vth1, thereby suppressing the destruction of the first switch S1.

[0030] Next, we will explain the operation when releasing the brake mode of motor driver 1.

[0031] When releasing the brake mode and switching to the operating mode to operate the motor M, the operating switching voltage Ven input to terminal EN is set to zero (LO potential). By setting the operating switching voltage Ven to zero, the operating switching voltage Ven is inverted by the inverter 21, and the voltage V4 input to the control electrode of the second switch S2 becomes HI potential (for example, 5V), so the second switch S2 is switched on. When the second switch S2 is on, the control electrodes of the first switch S1 and the third switch S3 are connected to ground potential GND, so the first switch S1 and the third switch S3 are always off regardless of the output voltage V3 of the comparator C1, and their switching operation is disabled. As a result, in the operating mode, the operation of the brake circuit 13 is disabled regardless of the value of the terminal voltage V1, and it is possible to prevent the motor M from entering a short-circuit brake state.

[0032] Then, when the high-side transistor QH is turned on, the terminal voltage V1 starts to rise from zero. At this time, as shown in section (3) of Figure 3, the signal voltage V2 = V1 × R5 / (R4 + R5) is input to the inverting input terminal - of comparator C1.

[0033] Then, when the terminal voltage V1 rises to the second setting voltage Vth2, which is greater than the first setting voltage Vth1, the signal voltage V2 becomes greater than the reference voltage Vr input to the non-inverting input terminal + of comparator C1. At this point, the output voltage V3 of comparator C1 switches from Vh1 (HI potential) to zero (LO potential).

[0034] The control voltage Vsb and the resistance values ​​of resistors R1 to R7 can be arbitrarily set according to the desired clamp voltage Vc, signal voltage V2, reference voltage Vr, first setting voltage Vth1, and second setting voltage Vth2. While an example of setting circuit 20 is shown where the control voltage Vsb is divided by resistors R1 to R3 using the reference voltage Vr and clamp voltage Vc, and the terminal voltage V1 is divided by resistors R4 to R6 using the signal voltage V2, the circuit is not limited to this configuration. The setting circuit 20 only needs to be able to turn on the first switch S1 when the terminal voltage V1 drops to a predetermined first setting voltage Vth1, and its configuration can be arbitrarily determined by the designer.

[0035] According to the motor driver 1 of this embodiment, in brake mode, by turning on the first switch S1 in the brake circuit 13, the connection terminal BR, which is the connection point between the high-side transistor QH and the low-side transistor QL, is connected to ground potential GND via resistor R7. By connecting the connection terminal BR to ground potential GND via resistor R7, the motor M can be put into a short-circuit brake state. Therefore, the high-side transistor QH and the low-side transistor QL can be turned off and current consumption can be suppressed, so the motor M can be kept in a stopped state with low current consumption.

[0036] According to the motor driver 1 of this embodiment, in brake mode, the brake circuit 13 uses a setting circuit 20 to turn on the first switch S1 when the terminal voltage V1 drops to a predetermined first setting voltage Vth1. This prevents damage to the first switch S1.

[0037] The brake circuit 13 can be integrated into, for example, a pre-driver IC (Integrated Circuit) used to drive an H-bridge circuit. By integrating the brake circuit 13 into the pre-driver IC, the mounting area can be reduced compared to constructing the brake circuit 13 as a separate IC, and current consumption and manufacturing costs can also be reduced.

[0038] <Considerations on preventing malfunctions caused by negative voltage> Incidentally, if the high-side transistor QH is turned off while the motor M is in operation, the back electromotive force can cause the terminal voltage V1 of the connection terminal BR to become a negative voltage lower than the ground potential GND.

[0039] However, the first switch S1 of the brake circuit 13 is parasitic with a body diode BD0. The body diode BD0 is forward-biased when the terminal voltage V1 is a negative voltage. Therefore, the terminal voltage V1 is clamped by the forward voltage drop Vf of the body diode BD0. In other words, the terminal voltage V1 only drops down to GND-Vf. This may interfere with the operation of a circuit that monitors the terminal voltage V1, such as a current detection circuit (not shown).

[0040] In light of the above considerations, a control circuit 10 that is less prone to malfunction due to negative voltage is proposed.

[0041] <Control circuit (first configuration example)> Figure 5 shows a first configuration example of the control circuit 10. The control circuit 10 in the first configuration example is based on Figure 2 shown above, but includes a high-side drive circuit 11, a low-side drive circuit 12, and a brake circuit 13, in addition to a cutoff circuit 30. In the following explanation, for convenience, the terminal to which the ground potential GND is applied may be referred to as the ground terminal GND.

[0042] The control circuit 10 can be understood as a semiconductor device for driving an H-bridge circuit, a so-called pre-driver IC.

[0043] The brake circuit 13 can be understood as a type of pull-down circuit that conducts between the connection terminal BR and the ground terminal GND when the terminal voltage V1 applied to the connection terminal BR is lower than the first set voltage Vth1 in the brake mode of the motor driver 1.

[0044] The interruption circuit 30 interrupts the current path from the ground terminal GND to the connection terminal BR via the brake circuit 13 (particularly the body diode BD0 of the first switch S1) when the voltage at the connection terminal BR is lower than that at the ground terminal GND, that is, when the terminal voltage V1 is a negative voltage.

[0045] Referring to this figure, the cutoff circuit 30 includes transistors M1 and M2, resistors R8 and R9, and a current source CS1. Transistor M1 may be an N-channel MOSFET. Transistor M2 may be a P-channel MOSFET.

[0046] Transistor M1 is connected between the connection terminal BR and the ground terminal GND. Specifically, the source of transistor M1 is connected to the connection terminal BR via resistor R7. The drain of transistor M1 is connected to the drain of the first switch S1. A body diode BD1 is parasitic on transistor M1. The body diode BD1 is in a reverse bias state when the connection terminal BR is at a lower potential than the ground terminal GND, that is, when the terminal voltage V1 is a negative voltage.

[0047] Resistor R8 is connected between the gate and source of transistor M1. The drain of transistor M2 is connected to terminal SB via current source CS1. The source and gate of transistor M2 are connected to the gate of transistor M1 via resistor R9. Transistor M2, resistors R8 and R9, and current source CS1 function as a drive circuit DRV that drives the gate of transistor M1.

[0048] When the control voltage Vsb is applied to terminal SB, that is, when the motor driver 1 is in brake mode, transistor M1 is turned ON. Therefore, conduction occurs between resistor R7 and the first switch S1 via the low-impedance transistor M1. As a result, the characteristics of the brake circuit 13 are hardly affected even when the cutoff circuit 30 is introduced.

[0049] On the other hand, when the control voltage Vsb is not applied to terminal SB, that is, when the motor driver 1 is not in brake mode, the transistor M1 is in the off state. Therefore, the body diode BD1 inserted between resistor R7 and the first switch S1 becomes active.

[0050] Here, when the terminal voltage V1 becomes a negative voltage, the body diode BD1 of transistor M1 enters a reverse bias state. Consequently, the current path from the ground terminal GND to the connection terminal BR via the brake circuit 13 (especially the body diode BD0 of the first switch S1) is blocked by the body diode BD1. As a result, the clamping of the terminal voltage V1 by the body diode BD0 is eliminated.

[0051] Furthermore, a resistor R8 is connected between the gate and source of transistor M1. Therefore, malfunction and breakdown of transistor M1 due to fluctuations in the terminal voltage V1 can be prevented.

[0052] Furthermore, transistor M2 is connected between the current source CS1 and the gate of transistor M1. Transistor M2 functions as a gate protection element for transistor M1. A transistor with a higher voltage rating than transistor M1 may be used for transistor M2.

[0053] <Control circuit (second configuration example)> Figure 6 shows a second configuration example of the control circuit 10. The control circuit 10 in the second configuration example includes an open / short detection circuit 40 as another example of a circuit to which the interruption circuit 30 is to be introduced.

[0054] The open / short detection circuit 40 detects the open and short states of the motor M by receiving the terminal voltage V1 applied to the connection terminal BR. The open state of the motor M can be understood as a state in which one end of the motor M is not properly connected to the connection terminal BR. The short state of the motor M can be understood as a state in which one end of the motor M is short-circuited to terminal VB or ground potential GND.

[0055] Referring to this diagram, the open / short detection circuit 40 includes a voltage monitoring circuit 41, a pull-down circuit 42, and a pull-up circuit 43.

[0056] The voltage monitoring circuit 41 generates an open / short detection signal by monitoring the terminal voltage V1.

[0057] The pull-down circuit 42 is part of a self-diagnostic circuit that conducts between the connection terminal BR and the ground terminal GND during testing of the open / short detection circuit 40. As shown in the figure, the pull-down circuit 42 includes a current source CS2 and a current mirror CM1.

[0058] The current mirror CM1 is switched between operating and non-operating states according to the switching signal SLT. The current mirror CM1 is set to the operating state when testing the open / short detection circuit 40. When the current mirror CM1 is operating, it generates a test current that flows from the connection terminal BR to the ground terminal GND by mirroring the constant current generated by the current source CS2.

[0059] The pull-up circuit 43 is part of a self-diagnostic circuit that conducts between connection terminal BR and terminal VB during testing of the open / short detection circuit 40. Referring to this figure, the pull-up circuit 43 includes a current source CS3, a current mirror CM2, and a transistor M3. The transistor M3 may be, for example, a P-channel MOSFET.

[0060] The current mirror CM2 switches between operating and non-operating states according to the switching signal SLT. The current mirror CM2 is set to the operating state when testing the open / short detection circuit 40. When the current mirror CM2 is operating, it generates a test current that flows from terminal VB to connection terminal BR by mirroring the constant current generated by the current source CS3. Transistor M3 functions as a voltage-resistant protection element for the current mirror CM2.

[0061] Incidentally, the current mirror CM1 of the pull-down circuit 42 has a body diode BD0 parasitic on the output side N-channel MOSFET (not shown). The body diode BD0 is in a forward bias state when the terminal voltage V1 is a negative voltage. Therefore, the control circuit 10 of the second configuration example includes the previously mentioned cutoff circuit 30.

[0062] The interruption circuit 30 interrupts the current path from the ground terminal GND to the connection terminal BR via the pull-down circuit 42 (especially the body diode BD0) when the voltage at the connection terminal BR is lower than that at the ground terminal GND, that is, when the terminal voltage V1 is a negative voltage.

[0063] Referring to this figure, the cutoff circuit 30 includes transistors M1, M2, and M4, and resistors R8 and R9. Transistors M1 and M2 and resistors R8 and R9 are the same as in the first configuration example (Figure 5) described earlier. Therefore, redundant explanations are omitted. Transistor M4 may be a P-channel MOSFET.

[0064] The source of transistor M4 is connected to the application terminal of the power supply voltage VCC. The drain of transistor M4 is connected to the drain of transistor M2. The gate of transistor M4 is connected to the application terminal of the operating switching voltage Ven. Transistor M4 can be understood as a component of the drive circuit DRV.

[0065] During testing of the open / short detection circuit 40, the operating switching voltage Ven is set to zero (LO potential). At this time, transistor M4 is turned on. As a result, a voltage is applied to the gate of transistor M1, causing transistor M1 to turn on. Consequently, conduction occurs between the connection terminal BR and the current mirror CM1 via the low-impedance transistor M1. Therefore, even if the cutoff circuit 30 is introduced, it has almost no effect on the characteristics of the pull-down circuit 42.

[0066] On the other hand, when the open / short detection circuit 40 is not being tested (during normal operation), the operating switching voltage Ven is set to Vh2 (HI potential, e.g., 5V). At this time, transistor M4 is in the off state. Therefore, no voltage is applied to the gate of transistor M1, and transistor M1 is in the off state. Consequently, the body diode BD1 inserted between the connection terminal BR and the current mirror CM1 becomes effective.

[0067] Here, when the terminal voltage V1 becomes a negative voltage, the body diode BD1 of transistor M1 becomes reverse-biased. Consequently, the current path from the ground terminal GND to the connection terminal BR via the pull-down circuit 42 is blocked by the body diode BD1. As a result, the clamping of the terminal voltage V1 by the body diode BD0 is eliminated.

[0068] It should be noted that the introduction of the interruption circuit 30 is not limited to the brake circuit 13 and the open / short detection circuit 40. In other words, if the control circuit 10 incorporates a circuit that forms a current path from the ground terminal GND to the connection terminal BR when the connection terminal BR becomes negative voltage, the interruption circuit 30 described above can be suitably introduced.

[0069] <Note> This disclosure makes it possible to prevent malfunctions caused by negative voltage. Further details regarding the above disclosure are provided below.

[0070] [Note 1] Connection terminals (BR, BR1, BR2), Grounding terminal (GND), A pull-down circuit (13, 42) configured to conduct electricity between the connection terminal (BR) and the ground terminal (GND), A blocking circuit (30) is configured to interrupt the current path from the ground terminal (GND) to the connection terminals (BR, BR1, BR2) via the pull-down circuits (13, 42) when the voltage of the connection terminals (BR, BR1, BR2) is lower than that of the ground terminal (GND), A semiconductor device (10) comprising the above.

[0071] [Note 2] The interruption circuit (30) includes a transistor (M1) configured to be connected between the connection terminal (BR) and the ground terminal (GND), and a drive circuit (DRV) configured to drive the gate of the transistor (M1), wherein the transistor (M1) is parasitic with a body diode (BD1) that is in a reverse bias state when the connection terminals (BR, BR1, BR2) are at a lower potential than the ground terminal (GND), as described in Appendix 1, semiconductor device (10).

[0072] [Note 3] The drive circuit (DRV) is a semiconductor device (10) as described in Appendix 2, which includes a resistor (R8) configured to be connected between the gate and source of the transistor (M1).

[0073] [Note 4] The semiconductor device (10) described in Appendix 3 further includes a protection element (M2) configured to protect the gate of the transistor (M1) as the drive circuit (DRV).

[0074] [Note 5] A high-side drive circuit (11, 11-1, 11-2) configured to drive high-side transistors (QH, QH1, QH2), Low-side drive circuits (12, 12-1, 12-2) configured to drive low-side transistors (QL, QL1, QL2), Furthermore, The aforementioned connection terminals (BR, BR1, BR2) are connected to the connection nodes between the high-side transistors (QH, QH1, QH2) and the low-side transistors (QL, QL1, QL2), and the semiconductor device (10) described in any of Appendix 1 to 4.

[0075] [Note 6] A half-bridge output stage configured to drive a motor (M) by switching the high-side transistors (QH, QH1, QH2) and the low-side transistors (QL, QL1, QL2) on and off, The semiconductor device (10) described in Appendix 5, A motor driver (1) equipped with the following:

[0076] [Note 7] The motor driver (1) described in Appendix 6 is a brake circuit (13) configured to conduct electricity between the connection terminals (BR, BR1, BR2) and the ground terminal (GND) when the terminal voltage (V1) applied to the connection terminals (BR, BR1, BR2) is lower than the set voltage (Vth1).

[0077] [Note 8] The semiconductor device (10) includes an open / short detection circuit (40) configured to detect the open and short states of the motor (M) by receiving a terminal voltage (V1) applied to the connection terminals (BR, BR1, BR2). The motor driver (1) described in Appendix 6 is part of a self-diagnostic circuit configured to conduct electricity between the connection terminals (BR, BR1, BR2) and the ground terminal (GND) when the open / short detection circuit (40) is being tested.

[0078] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive. Moreover, the technical scope of this disclosure is defined by the claims and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of Symbols]

[0079] 1 Motor Driver 10. Control circuits (semiconductor devices) 11,11-1,11-2 High-side drive circuit 12, 12-1, 12-2 Low-side drive circuit 13. Brake circuit (pull-down circuit) 20 Setting Circuit 21 Inverter 22 DC current source 30. Cutoff circuit 40 Open / Short Detection Circuit 41 Voltage monitoring circuit 42 Pull-down circuits 43. Pull-up circuit BD0, BD1 Body Diodes BR connection terminal C1 Comparator CM1, CM2 Current Mirror CS1,CS2,CS3 Current source GND Ground potential (earth potential) HB, HB1, HB2 Half-bridge output stage M Motor M1, M2, M3, M4 Transistors QH, QH1, QH2 High-Side Transistors QL, QL1, QL2 Low-side transistors R1,R2,R3,R4,R5,R6,R7,R8,R9 Resistor S1 First switch (switch) S2 Second Switch S3 3rd switch S4 4th Switch SLT selection signal V1 terminal voltage V2 signal voltage V3 Output voltage of comparator C1 Ven Operating switching voltage Vr Reference Voltage Vsb control voltage Vth1 First set voltage Vth2 Second set voltage

Claims

1. Connection terminals, Grounding terminal and A pull-down circuit configured to provide electrical conductivity between the aforementioned connection terminal and the aforementioned ground terminal, A blocking circuit configured to interrupt the current path from the ground terminal to the connection terminal via the pull-down circuit when the voltage of the connection terminal is lower than that of the ground terminal, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the interruption circuit includes a transistor configured to be connected between the connection terminal and the ground terminal, and a drive circuit configured to drive the gate of the transistor, and the transistor has a parasitic body diode that is in a reverse bias state when the connection terminal is at a lower potential than the ground terminal.

3. The semiconductor device according to claim 2, wherein the drive circuit includes a resistor configured to be connected between the gate and source of the transistor.

4. The semiconductor device according to claim 3, wherein the drive circuit further includes a protection element configured to protect the gate of the transistor.

5. A high-side drive circuit configured to drive a high-side transistor, A low-side drive circuit configured to drive a low-side transistor, Furthermore, The semiconductor device according to any one of claims 1 to 4, wherein the connection terminal is connected to the connection node between the high-side transistor and the low-side transistor.

6. A half-bridge output stage configured to drive a motor by switching the high-side transistor and the low-side transistor on and off, The semiconductor device according to claim 5, A motor driver equipped with the following features.

7. The motor driver according to claim 6, wherein the pull-down circuit is a brake circuit configured to conduct electricity between the connection terminal and the ground terminal when the terminal voltage applied to the connection terminal is lower than a set voltage.

8. The semiconductor device includes an open / short detection circuit configured to detect open and short states of the motor by receiving a terminal voltage applied to the connection terminal, The motor driver according to claim 6, wherein the pull-down circuit is part of a self-diagnostic circuit configured to conduct electricity between the connection terminal and the ground terminal when the open / short detection circuit is being tested.

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