Template substrates and methods for manufacturing the same, semiconductor substrates and methods for manufacturing the same, semiconductor devices, and electronic devices.

Abstract

This invention provides template substrates, semiconductor substrates, and methods for manufacturing semiconductor devices using GaN (gallium nitride). [Solution] The template substrate 7 comprises a main substrate containing silicon and having a main surface and side surfaces, a mask 6 having an opening KS and a mask portion 5, a seed layer having a seed portion that overlaps with the opening in a plan view, a buffer portion located at least between the main substrate and the seed layer, and a protective portion PS containing a material different from gallium. The buffer portion has a first portion that overlaps with the main surface in a plan view and a second portion that overlaps with the side surfaces in a side view, and the second portion has a first region that is thinner than the first portion. The protective portion overlaps with at least the first region in a side view. The template substrate is used for forming GaN-based semiconductors by the ELO method.

Description

Technical Field

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[0001] The present disclosure relates to a template substrate and the like.

Background Art

[0002] [[ID=ll]] Conventionally, research has been conducted on techniques for forming GaN-based semiconductor elements in order to manufacture semiconductor devices using GaN (gallium nitride). For example, Patent Document 1 discloses a method of forming a GaN-based semiconductor layer on a GaN-based substrate or a heterogeneous substrate (e.g., a silicon substrate or a sapphire substrate) using the ELO (Epitaxial Lateral Overgrowth) method.<000001o>

Prior Art Document

Patent Document

Patent Document 1

Summary of the Invention

[0004] A template substrate according to an aspect of the present disclosure includes a main substrate containing silicon and having a side surface, a mask located above the main substrate and having an opening, a seed portion located in the opening above the main substrate, and a protection portion that overlaps the side surface in a side view and contains a material different from gallium.

Brief Description of the Drawings

[0005] [Figure 1] It is a plan view showing the configuration of a template substrate in an embodiment of the present disclosure. [Figure 2] It is a cross-sectional view taken along the line II-II shown in FIG. 1. [Figure 3] It is a cross-sectional view taken along the line III-III shown in FIG. 1. [Figure 4] It is a cross-sectional view for explaining a semiconductor substrate in an embodiment of the present disclosure. [Figure 5A]This is a partially enlarged plan view showing the configuration of a semiconductor substrate in one embodiment of the present disclosure. [Figure 5B] This is a cross-sectional view taken along the line BV shown in Figure 5A. [Figure 6] This flowchart shows an example of a method for manufacturing a template substrate and a semiconductor substrate in one embodiment of the present disclosure. [Figure 7] This is a block diagram showing an example of a manufacturing apparatus in one embodiment of the present disclosure. [Figure 8] This flowchart shows an example of a method for manufacturing a semiconductor device in one embodiment of the present disclosure. [Figure 9] This is a plan view showing an example of the separation of the element section. [Figure 10] This is a cross-sectional view showing an example of the separation and separation of the element section. [Figure 11] This is a schematic diagram showing the configuration of an electronic device in one embodiment of the present disclosure. [Figure 12] This is a schematic diagram showing an alternative configuration of an electronic device in one embodiment of the present disclosure. [Figure 13A] This is a cross-sectional view showing the configuration of a template substrate in another embodiment of the present disclosure. [Figure 13B] This is a cross-sectional view showing the configuration of a template substrate in another embodiment of the present disclosure. [Figure 14] This is a plan view showing the configuration of the template substrate in Example 1. [Figure 15A] Figure 14 shows a cross-sectional view taken along the line A-XV. [Figure 15B] Figure 14 shows a cross-sectional view taken along the line B-XV. [Figure 16] This is a plan view showing the configuration of the template substrate in Example 2. [Figure 17A] Figure 16 shows a cross-sectional view taken along the line A-XVII. [Figure 17B] Figure 16 shows a cross-sectional view taken along the line B-XVII. [Figure 18] This is a plan view showing the configuration of the template substrate in Example 3. [Figure 19]It is a cross-sectional view taken along the line XIX-XIX shown in FIG. 18. [Figure 20] It is a cross-sectional view showing the configuration of the template substrate in Example 4. [Figure 21] It is a cross-sectional view showing another configuration of the template substrate in Example 4. [Figure 22] It is a plan view showing the configuration of the template substrate in Example 5. [Figure 23] It is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. 22. [Figure 24] It is a cross-sectional view for explaining the manufacturing method of the template substrate in Example 5. [Figure 25] It is a plan view showing the configuration of the template substrate in Example 6. [Figure 26] It is a cross-sectional view taken along the line XXVI-XXVI shown in FIG. 25. [Figure 27] It is a plan view showing the configuration of the template substrate in Example 7. [Figure 28] It is a cross-sectional view taken along the line XXVIII-XXVIII shown in FIG. 27. [Figure 29] It is a cross-sectional view showing the configuration of the template substrate in Example 8. [Figure 30] It is a cross-sectional view showing the configuration of the template substrate in Example 9. [Figure 31] It is a cross-sectional view showing the configuration of the template substrate in Example 10. [Figure 32] It is a cross-sectional view showing the configuration of the template substrate in Example 11. [Figure 33] It is a cross-sectional view showing another configuration of the template substrate in Example 11. [Figure 34] It is a cross-sectional view showing the configuration of the template substrate in Example 12.

BEST MODE FOR CARRYING OUT THE INVENTION

[0006] Embodiments will be described below with reference to the drawings. The following description is intended to help you better understand the spirit of the invention and does not limit this disclosure unless otherwise specified. Unless otherwise specified in this specification, "A to B" representing a numerical range means "A or more and B or less". In addition, the shapes and dimensions (length, width, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions, but have been modified as appropriate for clarity and simplification of the drawings.

[0007] In the following description, to facilitate understanding of the template substrate in one aspect of this disclosure, we will first provide a general overview of the findings of this disclosure.

[0008] [Summary of findings in this disclosure] Conventionally, it is known that GaN-based semiconductor layers can be grown on silicon substrates, for example, using the ELO method. Generally, commercially available wafers (hereinafter referred to as commercially available wafers CW) are not sold as products for the purpose of forming GaN-based semiconductor layers using the ELO method. However, by using commercially available wafers CW as substrates and forming a mask on the substrate, it is possible to form GaN-based semiconductors on the substrate using the ELO method.

[0009] In their investigation into the technique for fabricating GaN-based semiconductor layers using the ELO method, the inventors obtained the following findings. Specifically, they found that when a GaN-based semiconductor layer is formed using the above-mentioned substrate, melt-back etching may occur on the edge (side) portion of the substrate, potentially causing damage to a part of the substrate. Hereinafter, for convenience of explanation, in this specification, melt-back etching occurring on the edge (side) portion of the base substrate or template substrate will be referred to as melt-back etching SMB. When a part of the substrate is damaged due to melt-back etching SMB, the effective area of ​​the GaN-based semiconductor layer usable for device formation may decrease (i.e., the device yield may decrease).

[0010] The present inventors have diligently studied techniques that can reduce the occurrence of meltback etching (SMB) under film deposition conditions for GaN-based semiconductor layers by the ELO method, and have conceived of a template substrate in one aspect of this disclosure.

[0011] [Template board] A template substrate 7 in one embodiment of this disclosure will be described below with reference to Figures 1, 2, and 3. Figure 1 is a plan view showing the configuration of the template substrate 7. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 1.

[0012] As shown in Figures 1, 2, and 3, the template substrate 7 in this embodiment includes a main substrate 1 containing silicon and having an edge E (end face, side surface), a base portion 4 located above the main substrate 1, a mask 6 located above the main substrate 1 and having an opening KS, and a protective portion PS that overlaps with the edge E in a side view. The template substrate 7 may have a buffer portion 2 and a seed portion 3 provided as the base portion 4, in that order from the main substrate 1 side. The seed portion 3 may be located above the main substrate 1 and at the opening KS. The protective portion PS may contain a material other than gallium (Ga).

[0013] The base layer 4, buffer layer 2, seed layer 3, and mask layer 6 are typically layered. Therefore, the base layer 4 can also be called the base layer 4. Similarly, the buffer layer 2 can be called the buffer layer 2, the seed layer 3 can be called the seed layer 3, and the mask layer 6 can be called the mask layer 6. In the following explanation, these will be referred to as the base layer 4, buffer layer 2, seed layer 3, and mask layer 6, but they are not necessarily limited to being layered.

[0014] The main substrate 1 has edges E (sides, end faces) that have an uneven shape (angular shape) in cross-sectional view. Such edges E can be formed by chamfering during the manufacturing process of the main substrate 1. In the template substrate 7 of this embodiment, the edges E of the main substrate 1 include curved portions Er and flat portions Ef, but are not limited to this, and the edges E may consist only of curved or flat surfaces. The main substrate 1 may also have edges E that have not been chamfered.

[0015] In the main substrate 1, one of the two surfaces (the top surface) is referred to as the main surface 1a, and the other surface is referred to as the bottom surface 1b. The template substrate 7 may have multiple layers stacked on the main surface 1a. In this specification, the stacking direction in which multiple layers are stacked on the main surface 1a is referred to as the "upward direction," and viewing a substrate-like object such as the template substrate 7 from a line of sight parallel to the normal of the main surface 1a is sometimes referred to as a "planar view." Furthermore, for a substrate-like object such as the template substrate 7, it is sometimes assumed that the main surface 1a is a plane and the side surface of the object is a plane that includes the direction of the normal of the main surface 1a in the in-plane direction, and viewing the object in the direction of the normal of the side surface (a hypothetical plane) is sometimes referred to as a "side view." For example, a side view of the template substrate 7 means viewing the template substrate 7 in the direction of arrow A1 shown in Figures 2 and 3. In a side view, the overlapping of two components may also mean that, in a view perpendicular to the substrate normal of the template substrate 7 (including perspective viewing), at least a portion of one component overlaps the other component. The two components may be in contact or separated without contact. In a plan view, the overlapping of two components means that, in a view in the direction normal to the main substrate 1 (including perspective viewing), at least a portion of one component overlaps the other component. The two components may overlap separately (for example, in the vertical direction).

[0016] The template substrate 7 may have a buffer layer 2 and a seed layer 3 that overlap the entire surface 1a of the main substrate 1 in a plan view. Hereinafter, the main substrate 1 and the base layer 4 together may be referred to as the base substrate UK. The mask layer 6 formed on the base substrate UK has a plurality of mask portions 5 and a plurality of openings KS. Both the mask portions 5 and the openings KS have a longitudinal shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the longitudinal direction. The openings KS may also have a tapered shape (a shape that narrows in width towards the bottom). The mask layer 6 may have a shape in which both ends of the openings KS in the longitudinal direction are open, that is, a shape in which there are no mask portions 5 at both ends in the longitudinal direction, and may be formed on the base substrate UK in a so-called edge-to-edge shape. The mask layer 6 may be a mask pattern including the mask portions 5 and the openings KS. An opening KS is a region in which there are no mask portions 5, and the openings KS do not have to be surrounded by the mask portions 5.

[0017] For example, if a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, the two (main substrate and seed layer) may melt together. Therefore, by providing a buffer layer 2 that includes at least one of an AlN layer and a SiC (silicon carbide) layer, the possibility of the main substrate 1 and seed layer 3 melting together can be reduced. If a main substrate 1 that does not melt with the seed layer 3 is used, a configuration without a buffer layer 2 is also possible. Furthermore, if a seed layer 3 with low reactivity with the main substrate 1 is used, a configuration without a buffer layer 2 is also possible. Note that the configuration is not limited to the seed layer 3 overlapping the entire mask portion 5, as shown in Figures 2 and 3. Since the seed layer 3 only needs to be exposed from the opening KS, the seed layer 3 may be formed locally so as not to overlap part or all of the mask portion 5.

[0018] The mask layer 6 may be formed, for example, as follows: an SiO2 film is formed over the entire surface of the substrate UK using the sputtering method, and then wet etching is performed while partially protecting it with a resist. The mask portion 5 and the opening KS are formed by the removal of a portion of the SiO2 film. Generally, the sides of the substrate UK are not covered with the SiO2 film. This is due to reasons such as (i) insufficient coverage of the SiO2 film to the sides of the substrate UK in the sputtering method, and (ii) the fact that the resist is not sufficiently applied to the sides of the substrate UK unless intentionally applied, and therefore the SiO2 film is removed by etching.

[0019] The template substrate 7 can be used for forming semiconductor parts, for example, for depositing GaN-based semiconductor films by the ELO method. GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and examples include GaN, AlGaN, AlGaInN, and InGaN. In the ELO method, for example, a seed layer 3 containing a GaN-based semiconductor is used, and an inorganic compound film such as an SiO2 film is used as the mask layer 6, allowing the GaN-based semiconductor part to be grown laterally on the mask part 5. The thickness direction (Z direction) of the GaN-based semiconductor part is the GaN-based crystal. <0001> The direction (c-axis direction) and the width direction of the aperture KS (X-axis direction) can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y-direction) of the aperture KS can be the <1-100> direction (m-axis direction) of the GaN-based crystal. The GaN-based semiconductor portion is typically layered. Therefore, the GaN-based semiconductor portion can also be called a GaN-based semiconductor layer. In the following explanation, it will be referred to as a GaN-based semiconductor layer, but the GaN-based semiconductor layer is not necessarily limited to a layered structure. A layer formed by the ELO method is sometimes referred to as an ELO semiconductor layer.

[0020] As mentioned above, meltback etching (SMB) can occur when forming the ELO semiconductor layer. The reason for this is not entirely clear, but it is thought to be as follows.

[0021] In other words, the buffer layer 2 is formed under conditions that do not prevent the film-forming material from wrapping around (covering) the side surface of the main substrate 1. However, it is a thin layer with a thickness of about 100 nm, and due to its inherent properties, it is difficult to form in a way that covers the side surface of the main substrate 1. Therefore, it is thought that the thickness of the buffer layer 2 is uneven in the side surface area of ​​the template substrate 7 due to reasons such as the uneven shape of the side surface of the main substrate 1 and the thinning of the buffer layer 2. As a result, it is thought that there may be areas where the main substrate 1 and the seed layer 3 are not sufficiently separated by the buffer layer 2. In other words, it is thought that there may be minute areas in the side surface area of ​​the template substrate 7 where the buffer layer 2 is too thin, where there are cracks in the buffer layer 2, or where the main substrate 1 is not completely (effectively) protected by the buffer layer 2. Hereinafter, in this specification, the area that can be the starting point for meltback etching SMB (the above minute area) will be referred to as the "abnormal area DP".

[0022] Here, if the thickness of the buffer layer 2 on the side surface of the template substrate 7 is increased, the thickness of the buffer layer 2 on the main surface 1a of the main substrate 1 will also increase simultaneously, which may impair the original function of the buffer layer 2. Specifically, cracks may occur in the buffer layer 2 due to internal stress in the buffer layer 2, as well as stress resulting from the difference in thermal expansion coefficients and lattice constants between the buffer layer 2 and the main substrate 1. As a result, meltback etching between the main substrate 1 and the seed layer 3 may occur through these cracks. Therefore, the thickness of the buffer layer 2 cannot be freely increased.

[0023] Furthermore, the film deposition conditions when forming the ELO semiconductor layer affect the occurrence of melt-back etching (SMB). For example, if the deposition temperature exceeds 1050°C to ensure a sufficient lateral deposition rate, melt-back etching (SMB) is more likely to occur. Also, if the deposition time is relatively long, the area of ​​the melt-back etching (SMB) region expands.

[0024] Therefore, in one aspect of this disclosure, the template substrate 7 may be configured to include a protective portion PS formed along the outer periphery of the base substrate UK. The protective portion PS covers the side (end face) of the base substrate UK and overlaps with the edge E of the main substrate 1 in a side view. The protective portion PS includes, for example, a silicon-containing nitride film, a silicon-containing oxide film, or a silicon-containing oxynitride film. Typically, the protective portion PS may include a silicon nitride (SiN) film or an SiO2 film.

[0025] Furthermore, the protective PS may contain materials other than gallium (Ga), and more specifically, it may contain materials other than elemental Ga and Ga compounds (hereinafter, for convenience of explanation, referred to as non-Ga materials). Examples of non-Ga materials included in the protective PS include silicon nitride, silicon oxide, silicon oxynitride, aluminum silicon oxide, etc. The protective PS may contain multiple types of the above non-Ga materials.

[0026] Furthermore, the protective PS may contain more of the non-Ga material than Ga, and more specifically, the content of the non-Ga material may be greater than the sum of the content of pure Ga and the content of Ga compounds. When the protective PS contains multiple types of non-Ga materials, the content of all types of non-Ga materials contained in the protective PS means the sum of the content of all types of non-Ga materials contained in the protective PS.

[0027] Furthermore, the protective layer PS may be an inorganic insulating film or inorganic insulating layer that does not contain Ga or is substantially Ga-free. "Substantially Ga-free" means that Ga may be present in the protective layer PS as an unavoidable impurity, or that Ga may be present in the protective layer PS due to the diffusion of atoms from the seed layer 3. The protective layer PS only needs to have the function of reducing the occurrence of melt-back etching (SMB) on the side portion of the template substrate 7, and may contain Ga within an acceptable concentration range. For example, the protective layer PS may contain Ga at a molar ratio of 1% or less in its component composition.

[0028] The protective layer PS may be formed using, for example, CVD (Chemical Vapor Deposition), plasma CVD, or other methods. Below, a template substrate 7 in which the protective layer PS is formed using plasma CVD will be described.

[0029] As shown in Figure 2, the height H is defined as the distance from the lowest to the highest position of the protective layer PS in the thickness direction (Z direction) of the template substrate 7, the thickness of the main substrate 1 is t1, and the thickness of the underlayer 4 is t2. The protective layer PS may have a height H greater than the thickness t1, and may have a height H greater than the sum of the thickness t1 and the layer thickness t2. The height H may be, for example, 200 μm or more and 1200 μm or less, or 300 μm or more and 1100 μm or less.

[0030] In this specification, the ridge line (intersection point in a cross-sectional view) where edge E of the main substrate 1 intersects with the main surface 1a is referred to as RH, and the ridge line (intersection point in a cross-sectional view) where edge E of the main substrate 1 intersects with the bottom surface 1b is referred to as RL. The side portion of the base substrate UK that is located on the outer periphery (further from the center) than ridge line RH is referred to as the side portion SP of the base substrate UK. In other words, the side portion SP of the base substrate UK is the portion that is located outside the main surface 1a in the XY plane (plan view) and includes the main substrate 1, buffer layer 2, and seed layer 3.

[0031] The protective portion PS may be in contact with the seed layer 3 on the side portion SP of the substrate UK, or it may cover the entire surface of the seed layer 3. The protective portion PS may cover the side portion SP of the substrate UK from the position of the bottom surface 1b (in other words, the position of the edge line RL) to the position of the main surface 1a (in other words, the position of the edge line RH) in the Z direction, in which case the protective portion PS will overlap the entire edge E in a side view. The protective portion PS may cover the side portion SP of the substrate UK from the position of the bottom surface 1b in the Z direction beyond the position of the main surface 1a of the seed layer 3 (in other words, the position of the edge line RH), in which case it may cover the side portion SP so that the seed layer 3 is not exposed on the side portion SP. In addition, a part of the side portion SP and the mask portion 5 may be in contact with each other. In this specification, "contact" between two different members means not only that they are in direct contact with each other, but also that they may be indirectly in contact with each other through some other thin layer (for example, a layer with a thickness of 2 μm or less, which may be a single layer or multiple layers).

[0032] The template substrate 7 has a protective section PS. By using the template substrate 7, when forming the ELO semiconductor layer by the ELO method, the Ga supplied from the Ga raw material is prevented from reaching the main substrate 1. Therefore, the possibility of the Ga supplied from the Ga raw material reacting with the main substrate 1 via an abnormal area DP can be reduced.

[0033] For example, in an abnormal point DP, the absence of buffer layer 2 or the thinness of buffer layer 2 may cause a reaction between seed layer 3 and main substrate 1. If buffer layer 2 is thin, Ga can permeate through buffer layer 2. In template substrate 7, even if a reaction occurs in the abnormal point DP, there is no new supply of Ga to the reaction site, so the reaction can be limited to a localized reaction between seed layer 3 and main substrate 1 in the abnormal point DP.

[0034] Alternatively, in the template substrate 7, the possibility of the above reaction occurring can be reduced by not supplying Ga to the abnormal area DP from the outside. As a result, the possibility of meltback etching SMB occurring can be reduced, and even if meltback etching SMB occurs, the area of ​​the meltback etching SMB occurrence can be reduced.

[0035] The protective layer PS may have a thickness of 100 nm or more at the point where the distance between the surface of the protective layer PS and the surface of the seed layer 3 is smallest; in other words, the thickness of the part of the protective layer PS closest to the surface of the seed layer 3 (the thinnest part). This effectively reduces the possibility of Ga being supplied to the abnormal area DP.

[0036] Furthermore, the lowest point of the protective part PS in the Z direction may be below the position of the bottom surface 1b (in other words, the position of the edge line RL), and in this case, it may be in contact with the bottom surface 1b of the main substrate 1. Also, the protective part PS may cover at least a part of the bottom surface 1b, including the edge line RL. In other words, the protective part PS may overlap a part of the bottom surface 1b when viewed from a line of sight parallel to the normal of the bottom surface 1b. Hereinafter, the part of the protective part PS that covers the lower side (bottom surface 1b side) of the template substrate 7 may be referred to as the lower protective part PS1. The lower protective part PS1 may be a part of the protective part PS.

[0037] In the template substrate 7, the buffer layer 2 and seed layer 3 may slightly wrap around to the bottom surface 1b. For example, in a cross-sectional view as shown in Figure 2, the buffer layer 2 and seed layer 3 may cover a portion of the bottom surface 1b, and the outer edges of the buffer layer 2 and seed layer 3 may be located a few micrometers in the Y direction from the ridge line RL.

[0038] In the cross-sectional view shown in Figure 2, the end of the lower protective portion PS1 on the central side of the template substrate 7 is referred to as the PSE. Also, in the cross-sectional view shown in Figure 2, W1 is defined as the distance between the position closest to the center of the template substrate 7 in the Y direction (among the positions of the ridge line RL, the end of the buffer layer 2, and the end of the seed layer 3) and the position of the end PSE on the lower side of the template substrate 7. The template substrate 7 may have a distance W1 of, for example, 1 μm or more in the lower protective portion PS1. In this case, the possibility of meltback etching SMB occurring due to Ga raw material gas that has leaked around to the lower surface 1b can be effectively reduced. As a result, the possibility of meltback etching SMB occurring can be further reduced. The lower protective portion PS1 may have a distance W1 of, for example, 1 μm or more and 5000 μm or less. Such a lower protective portion PS1 can be formed, for example, by forming the protective portion PS using a plasma CVD method.

[0039] Furthermore, a protective portion PS can be provided on the outside of the side surface of the main substrate 1 so that the main substrate 1 is not exposed on the side surface of the template substrate 7. The material of the protective portion PS may be a gallium-free semiconductor such as AlN or SiC, or an amorphous material such as SiNx. A nitride semiconductor (e.g., a GaN-based semiconductor) may be located between the side surface of the main substrate 1 and the protective portion PS. The side surface of the main substrate 1 and the protective portion PS may be in contact. The protective portion PS may have a shape that wraps around from above to the side of the main substrate 1. The protective portion PS may be formed in the same layer as the mask portion 5 or in a layer above the mask portion 5. The thermal oxide film of the main substrate 1 (e.g., a Si substrate) may be used as the protective portion PS. The distance between the longitudinally shaped opening KS and the side surface of the template substrate 7 may be greater than the width of the opening KS. The distance between the seed layer 3 and the side surface of the template substrate 7 may be greater than the width of the opening K.

[0040] [Semiconductor substrates] A semiconductor substrate 10 in one embodiment of this disclosure will be described below with reference to Figures 4, 5A, and 5B. Figure 4 is a cross-sectional view illustrating the semiconductor substrate 10 of this embodiment. Figure 4 shows a cross-section corresponding to Figure 3, as well as an example of lateral growth.

[0041] As shown in Figure 4, in the process of forming an ELO semiconductor layer on a template substrate 7 by the ELO method, first, an initial growth layer SL is formed starting from the seed layer 3 exposed at the opening KS. Then, the initial growth layer SL is further grown and grown laterally to form the ELO semiconductor portion 8. The ELO semiconductor portion 8 includes, for example, a GaN-based semiconductor. Furthermore, a functional portion 9 may be formed on the semiconductor substrate 10 above the ELO semiconductor portion 8. The functional portion 9 may be a single layer or a multilayer. The functional portion 9 may have at least one of the following functions: function as a component of a semiconductor device, light emission function, protection function from external forces, protection function from static electricity, protection function to prevent the intrusion of foreign substances such as water and oxygen, protection function from etchants, optical function, and sensing function.

[0042] The ELO semiconductor section 8 and the functional section 9 are typically layered. Therefore, the ELO semiconductor section 8 can also be called the ELO semiconductor layer 8, and the functional section 9 can also be called the functional layer 9. In the following explanation, we will refer to them as the ELO semiconductor layer 8 and the functional layer 9, but the ELO semiconductor layer 8 and the functional layer 9 are not necessarily limited to being layered.

[0043] The ELO semiconductor layer 8 includes an effective region EK that overlaps with the mask region 5 in a plan view and has relatively few through-dislocations, and a non-effective region NS that overlaps with the opening KS in a plan view and has relatively many through-dislocations. If the functional layer 9 above the ELO semiconductor layer 8 includes an active layer (for example, a layer in which electrons and holes bond), the functional layer 9 on the effective region EK (in other words, the position that overlaps with the effective region EK in a plan view) can be formed to include an active layer with few defects and high crystallinity. A current injection region can be formed in this effective region EK, and a device in which the active layer functions can be formed. This makes it possible to fabricate, for example, a device with high luminescence efficiency.

[0044] The effective part EK is, <0001> A configuration can be achieved in which the non-penetrating dislocation density in a cross-section parallel to the direction is greater than the penetrating dislocation density on the top surface. Penetrating dislocations are dislocations (defects) that extend from the bottom surface or interior of the ELO semiconductor layer 8 to its surface or surface layer along the thickness direction (Z direction) of the ELO semiconductor layer 8. Penetrating dislocations can be observed by performing a CL (Cathode luminescence) measurement on the surface (parallel to the c-plane) of the ELO semiconductor layer 8. Non-penetrating dislocations are dislocations measured by CL in a cross-section with a plane parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.

[0045] Figure 5A is a partially enlarged plan view showing the configuration of the semiconductor substrate 10. Figure 5B is a cross-sectional view taken along the line BV shown in Figure 5A. Figures 5A and 5B show the semiconductor substrate 10 before the formation of the functional layer 9.

[0046] As shown in Figures 5A and 5B, when an edge-to-edge template substrate 7 is used for the semiconductor substrate 10, the ELO semiconductor layer 8 grown by the ELO method starting from the opening KS can be formed so that it wraps around to the sides of the semiconductor substrate 10. This is because the ELO semiconductor layer 8 grows in the Y direction (m-axis direction of the GaN-based crystal) at a slower growth rate than in the X direction. In particular, by depositing the film under conditions that increase the width of the effective area EK, the ELO semiconductor layer 8 is more likely to wrap around to the sides of the semiconductor substrate 10. Even in such cases, the semiconductor substrate 10 is equipped with a protective area PS, which effectively reduces the possibility of melt-back etching SMB occurring under the ELO semiconductor layer 8 deposition conditions. Therefore, the effective area of ​​the effective area EK on the semiconductor substrate 10 can be increased. As a result, the yield of devices fabricated using the semiconductor substrate 10 can be improved.

[0047] Furthermore, the semiconductor substrate 10 may be equipped with a protective portion PS including a lower protective portion PS1. In this case, even if an ELO semiconductor layer 8 is formed or Ga raw material gas is supplied so as to wrap around to the underside of the semiconductor substrate 10, the possibility of Ga coming into contact with the main substrate 1 can be reduced. Therefore, the possibility of meltback etching SMB occurring can be effectively reduced.

[0048] Although not shown in the figures, the semiconductor substrate 10 may have an ELO semiconductor layer 8 formed by the association of semiconductor films that have grown laterally in opposite directions from adjacent apertures KS, and the ELO semiconductor layer 8 may have a configuration in which it does not have edges on the mask portion 5 (association type). The semiconductor substrate 10 may also have a functional layer 9 on top of the association type ELO semiconductor layer 8.

[0049] [Manufacturing of template substrates and semiconductor substrates] Figure 6 is a flowchart showing an example of a method for manufacturing the semiconductor substrate 10 in this embodiment. The flowchart shown in Figure 6 may also include a method for manufacturing the template substrate 7.

[0050] As shown in Figure 6, in one example of a manufacturing method for the template substrate 7 and the semiconductor substrate 10, first, a base substrate UK is prepared. This base substrate UK may be made by forming a base layer 4 on the main substrate 1. Next, the template substrate 7 is made by forming a mask layer 6 on the base substrate UK, followed by a step of forming a protective layer PS. Note that the mask layer 6 may be formed after the protective layer PS is formed. Alternatively, for example, if the mask layer 6 includes a protective layer PS (see Example 1 described later), the step of forming the protective layer PS may be included in the step of forming the mask layer 6. Next, an ELO semiconductor layer 8 is formed on the template substrate 7 using the ELO method. After the step of forming the ELO semiconductor layer 8, a step of forming a functional layer 9 may be performed as needed.

[0051] Figure 7 is a block diagram showing an example of the manufacturing apparatus 70 in this embodiment. As shown in Figure 7, the manufacturing apparatus 70 includes a mask layer forming unit 71 for forming a mask layer 6 on a base substrate UK, a protective unit forming unit 72 for forming a protective unit PS, and a semiconductor layer forming unit 73 for forming an ELO semiconductor layer 8 on a template substrate 7. The manufacturing apparatus 70 also includes a control unit 74 for controlling the mask layer forming unit 71, the protective unit forming unit 72, and the semiconductor layer forming unit 73.

[0052] The mask layer formation unit 71 may include one or more devices that perform various processes for forming the mask layer 6 on the base substrate UK, and known devices can be used as such devices. The protective part formation unit 72 may be a configuration of a combination of multiple known devices so as to be able to form the protective part PS. The protective part formation unit 72 may include a plasma CVD apparatus. The semiconductor layer formation unit 73 forms an ELO semiconductor layer 8 (see Figure 4, etc.) containing a GaN-based semiconductor by the ELO method so as to be in contact with the seed layer 3 and the mask part 5. The semiconductor layer formation unit 73 may include an MOCVD (metal-organic CVD) apparatus. The manufacturing apparatus 70 may be configured to form the functional layer 9, or it may be configured to form the base layer 4 on the main substrate 1.

[0053] The control unit 74 may include a processor and memory. The control unit 74 may be configured to control the mask layer forming unit 71, the protection unit forming unit 72, and the semiconductor layer forming unit 73 by executing a program stored, for example, in built-in memory, a communication device, or an accessible network. The above program and the recording medium on which the above program is stored are also included in this embodiment.

[0054] [Manufacturing of semiconductor devices] Figure 8 is a flowchart showing an example of a semiconductor device manufacturing method in this embodiment. Figure 9 is a plan view showing an example of element separation. Figure 10 is a cross-sectional view showing an example of element separation and separation.

[0055] As shown in Figure 8, in an example of a semiconductor device manufacturing method, after the step of preparing the semiconductor substrate 10, a step of forming a functional layer 9 on the ELO semiconductor layer 8 is performed as needed. Subsequently, as shown in Figures 9 and 10, a step of forming multiple trenches TR (separation grooves) in the semiconductor substrate 10 is performed to separate the element portion DS (including the effective portion EK of the ELO semiconductor layer 8 and the functional layer 9). The element portion DS is connected to the substrate (underlying substrate UK) at the opening KS, and at the effective portion EK, the back surface of the element portion DS and the mask portion 5 are weakly bonded to each other by van der Waals forces. Therefore, by forming trenches TR (separation grooves) on the opening KS, forming the trenches TR such that the bottom of the trenches is lower than the surface height of the mask portion 5, and by making the opening width of the trenches TR greater than or equal to the width of the opening KS, the element portion DS can be easily peeled off from the substrate. The trenches TR penetrate the functional layer 9 and the ELO semiconductor layer 8. The mask portion 5 and the main substrate 1 may be exposed in the trenches TR. Subsequently, a step of separating the element portion DS from the template substrate 7 is performed to form a semiconductor device. The process for preparing the semiconductor substrate 10 shown in Figure 8 may include the steps for manufacturing the template substrate 7 and the semiconductor substrate 10, as shown in Figure 6.

[0056] The template substrate 7 may include a base substrate UK and a mask pattern on the base substrate UK. The template substrate 7 may have a growth suppression region corresponding to the mask portion 5 (for example, a region that suppresses crystal growth in the Z direction) and a seed region corresponding to the opening KS. For example, the growth suppression region and the seed region can be formed on the base substrate UK, and an ELO semiconductor layer 8 can be formed on the growth suppression region and the seed region using the ELO method.

[0057] [Semiconductor devices] As shown in Figure 10, a semiconductor device 20 (including the ELO semiconductor layer 8) can be formed by separating the element portion DS from the template substrate 7. For example, after separating the element portion DS from the template substrate 7, an n electrode or the like may be formed on the back surface of the separated element portion DS. Specific examples of the semiconductor device 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron-mobility transistors).

[0058] [Electronic equipment] Figure 11 is a schematic diagram showing the configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 11 includes a semiconductor substrate 10 (configured to function as a semiconductor device including a template substrate 7, for example, when the template substrate 7 is translucent), a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0059] Figure 12 is a schematic diagram showing an alternative configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 12 includes a semiconductor device 20 including at least an effective portion EK, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0060] Examples of electronic devices 30 include display devices, laser emission devices (including Fabry-Perot type and surface-emitting type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like.

[0061] [Other components] [1] Figures 13A and 13B are cross-sectional views showing the configuration of the template substrate 7 in other embodiments of the present disclosure. Figure 13A shows a cross-section corresponding to Figure 2, and Figure 13B shows a cross-section corresponding to Figure 3.

[0062] As shown in Figures 13A and 13B, the template substrate 7 does not necessarily have a buffer layer 2 on the side portion SP of the base substrate UK. In this case as well, as described above, the template substrate 7 has a protective portion PS, which reduces the possibility that Ga supplied from the Ga raw material reaches the main substrate 1 when forming the ELO semiconductor layer 8 by the ELO method. As a result, the possibility of meltback etching SMB occurring can be reduced, and even if meltback etching SMB occurs, the area of ​​the meltback etching SMB occurrence region can be reduced.

[0063] [2] In other embodiments of the present disclosure, the template substrate 7 may not have a buffer layer 2, as described above, and for example, a seed layer 3 with low reactivity with the main substrate 1 may be used. With respect to the template substrate 7 in one embodiment that does not have a buffer layer 2, the following can be said. That is, the above-mentioned points regarding abnormal locations DP can be understood by appropriately substituting the buffer layer 2 with the seed layer 3. For example, the material used as the buffer layer 2 may be used as the material for the seed layer 3, and abnormal locations DP may occur in the seed layer 3. In this case as well, as described above, the template substrate 7 has a protective section PS, which reduces the possibility that Ga supplied from the Ga raw material reaches the main substrate 1 when forming the ELO semiconductor layer 8 by the ELO method. As a result, the possibility of meltback etching SMB occurring can be reduced, and even if meltback etching SMB occurs, the area of ​​the meltback etching SMB occurrence region can be reduced.

[0064] In the following, a template substrate 7 having a buffer layer 2 on the side portion SP of the base substrate UK will be described as an example. However, as mentioned above, the template substrate 7 may also have a configuration in which the buffer layer 2 is not present on the side portion SP of the base substrate UK. Although not repeated below, unless otherwise specified, the template substrate 7 in each embodiment may not have a buffer layer 2 on the side portion SP of the base substrate UK, and it should be understood that such a template substrate 7 also falls within the scope of this disclosure.

[0065] [Example 1] The template substrate and the like of this disclosure will be described in more detail below with reference to examples, but this disclosure is not limited to the configurations described below, and various modifications are possible within the scope of the claims. In addition, in the following description, the same or corresponding parts of the configurations of the multiple embodiments of this disclosure will be denoted by the same reference numerals in the figures, but unless otherwise specified, forms obtained by appropriately combining the technical means disclosed in the embodiments described above and in different embodiments described later are also included in the technical scope of this disclosure.

[0066] (Overall Configuration) Figure 14 is a plan view showing the configuration of the template substrate 7 in Example 1. Figure 15A is a cross-sectional view taken along the line A-XV shown in Figure 14. Figure 15B is a cross-sectional view taken along the line B-XV shown in Figure 14.

[0067] As shown in Figures 14, 15A, and 15B, the template substrate 7 in Example 1 has a main substrate 1, a base layer 4, and a mask layer 6, and the mask layer 6 has a mask portion 5 including a protective portion PS. In the template substrate 7 in Example 1, the protective portion PS and the mask portion 5 may be one and the same.

[0068] (Main Substrate) The main substrate 1 is a silicon-containing substrate, and a substrate made of a different material from the GaN-based semiconductor (a different type of substrate) can be used. The main substrate 1 is typically a silicon substrate, or a silicon-based substrate containing silicon as the main component. The main substrate 1 may be, for example, a silicon-based substrate containing 90% or more silicon by molar ratio, or a silicon-based substrate containing 95% or more silicon. The main substrate 1 may be a single-crystal substrate, or an amorphous substrate. The plane orientation of the main substrate 1 may be, for example, the (111) plane or the (100) plane of the silicon substrate.

[0069] The main substrate 1 may be a silicon-containing material and surface orientation on which the ELO semiconductor layer 8 can be grown using the ELO method. The main substrate 1 may be a silicon carbide (SiC) substrate, but SiC substrates have relatively low reactivity with Ga. Therefore, SiC substrates inherently have the property of being less prone to melt-back etching (SMB). Thus, the main substrate 1 may be a silicon-containing substrate other than a SiC substrate.

[0070] In Example 1, the edge E of the main substrate 1 is configured to have a curved portion Er and a flat portion Ef connected to the curved portion Er and having a normal parallel to the X direction, but the invention is not limited to this configuration. The main substrate 1 may also be disc-shaped. The flat portion Ef may function as an orientation marker (orientation flat). The orientation marker can also be configured as a notch.

[0071] (Underlayment) The template substrate 7 may have a buffer layer 2 and a seed layer 3 as the underlayment 4, in that order from the main substrate 1 side. In Embodiment 1, the buffer layer 2 and seed layer 3 are formed to overlap the entire main surface 1a of the main substrate 1 in a plan view.

[0072] The buffer layer 2 has the function of reducing the melting of the main substrate 1 and the seed layer 3 due to contact. For example, if a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, providing a buffer layer 2 between the silicon substrate and the GaN-based semiconductor can reduce the melting of the silicon substrate and the GaN-based semiconductor. In addition, the buffer layer 2 may have at least one of the effects of improving the crystallinity of the seed layer 3 and relaxing the internal stress of the seed layer 3.

[0073] The buffer layer 2 is typically an AlN layer, but may also be a SiC layer. The SiC used in the buffer layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (3C-SiC). The buffer layer 2 may be a multilayer film containing at least one of the AlN film and the SiC film. The buffer layer 2 may also contain a strain relaxation layer. Examples of strain relaxation layers include a superlattice structure of AlGaN and a graded structure in which the Al composition of AlGaN is changed stepwise. The strain relaxation layer can relieve stress in the longitudinal direction of the ELO semiconductor layer 8. An example of the buffer layer 2, an AlN layer, can be formed to a thickness of about 10 nm to 5 μm using, for example, an MOCVD apparatus. The buffer layer 2 may also contain a Ga composition of 1% or less. Ga may be inevitably introduced into the buffer layer 2 by atomic diffusion of Ga.

[0074] The seed layer 3 is the starting point for the growth of the ELO semiconductor layer 8 when it is deposited. The seed layer 3 can be made of GaN-based semiconductors, aluminum nitride (AlN), silicon carbide (SiC), graphene, etc. The silicon carbide used in the seed layer 3 may be hexagonal 6H-SiC or 4H-SiC.

[0075] The seed layer 3 may be, for example, an AlGaN layer, or a graded layer whose Al composition approaches that of GaN. The graded layer is, for example, a laminate in which a first layer, an Al0.7Ga0.3N layer, and a second layer, an Al0.3Ga0.7N layer, are provided in order from the AlN layer side. In this case, the composition ratio of Ga in the second layer (Al:Ga:N=0.3:0.7:1) (0.7 / 2=0.35) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.7:0.3:1) (0.3 / 2=0.15). The graded layer can be easily formed by the MOCVD method and may consist of three or more layers. By using a graded layer for the seed layer 3, stress from the main substrate 1, which is a dissimilar substrate, can be relieved. The seed layer 3 may have a configuration that includes a GaN layer. In this case, seed layer 3 may be a single layer of GaN, or the top layer of the graded layer which is seed layer 3 may be a GaN layer.

[0076] For example, at least one of the buffer layer 2 (e.g., aluminum nitride) and the seed layer 3 (e.g., GaN-based semiconductor) can be deposited using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).

[0077] The base layer 4 can be formed by laminating various layers on the main substrate 1 using an MOCVD apparatus or sputtering apparatus. However, as mentioned above, generally, the buffer layer 2 is not sufficiently formed on the edge E of the main substrate 1. Therefore, the aforementioned abnormal area DP may exist on the side surface SP of the base substrate UK.

[0078] (Mask layer) As the mask layer 6, for example, a single layer film containing one of the following can be used: a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), an aluminum-silicon oxide film (AlSiO), and a metal film having a high melting point (e.g., 1000°C or higher), or a multilayer film containing at least two of these.

[0079] The openings KS are longitudinal in shape, and multiple openings KS may be periodically arranged in the a-axis direction (X-direction) of the ELO semiconductor layer 8 with a first period. The width of the openings KS may be approximately 0.1 μm to 20 μm. The smaller the width of the openings KS, the fewer the number of through-dislocations propagating from the openings KS to the ELO semiconductor layer 8. Furthermore, the peeling of the ELO semiconductor layer 8 in subsequent processes becomes easier. In addition, the area of ​​the effective portion EK with fewer surface defects can be increased.

[0080] In Example 1, a mask layer 6 having a mask portion 5 including a protective portion PS may be formed as follows. First, a silicon oxide film with a thickness of approximately 100 nm to 4 μm (preferably approximately 150 nm to 2 μm) is formed over the entire surface of the substrate layer 4 using a sputtering method. In Example 1, a silicon oxide film is also formed on the side portion SP of the substrate UK. Then, in Example 1, a resist is applied to the entire surface of the silicon oxide film, including the silicon oxide film formed on the side portion SP of the substrate UK. After that, the resist is patterned using a photolithography method to form a resist with multiple stripe-shaped openings. In Example 1, the resist covering the silicon oxide film formed on the side portion SP of the substrate UK is not removed. Then, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a mask portion 5 including multiple openings KS and a protective portion PS. Next, the mask layer 6 is formed by removing the resist with organic cleaning.

[0081] Furthermore, the mask portion 5 may include a protective portion PS having a lower protective portion PS1. For example, by using the plasma CVD method, it is easier to form the mask portion 5 so as to wrap around to the underside of the substrate UK.

[0082] (Specific example of template substrate) For the main substrate 1, a silicon substrate having a (111) plane was used, and the buffer layer 2 of the underlayer 4 was an AlN layer (e.g., 180 nm). The seed layer 3 of the underlayer 4 was a graded layer in which the first layer, an Al0.6Ga0.4N layer (e.g., 300 nm), and the second layer, a GaN layer (e.g., 1-2 μm), were formed in this order. That is, the composition ratio of Ga in the second layer (Ga:N=1:1) (1 / 2=0.5) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.6:0.4:1) (0.6 / 2=0.3).

[0083] The mask layer 6 used a laminate in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) were formed in that order. The thickness of the silicon oxide film was, for example, 0.3 μm, and the thickness of the silicon nitride film was, for example, 70 nm. The mask layer 6 was formed to have a mask portion 5 including a protective portion PS. Plasma CVD was used for the deposition of the silicon oxide film and the silicon nitride film, respectively.

[0084] (Deposition of ELO semiconductor layer) Although not shown in the diagram, the semiconductor substrate 10 comprises a template substrate 7 and an ELO semiconductor layer 8 located above the mask layer 6. A semiconductor substrate means a substrate containing a semiconductor layer. The ELO semiconductor layer 8 may be doped (for example, n-type including a donor or p-type including an acceptor) or undoped. Examples of the donor include silicon and germanium, and examples of the acceptor include magnesium. If the ELO semiconductor layer 8 is doped, it may contain both a donor and an acceptor.

[0085] The ELO semiconductor layer 8 includes, for example, a nitride semiconductor. Nitride semiconductors can be represented as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride).

[0086] The ELO semiconductor layer 8 was made of GaN, and ELO film deposition was performed on the template substrate 7 of Example 1 using an MOCVD apparatus. As an example of ELO film deposition conditions, the substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, and V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied) can be used. The ELO semiconductor layer 8 was selectively grown on the seed layer 3 (the uppermost GaN layer of the seed layer 3) exposed in the opening KS, and subsequently grew laterally on the mask portion 5. Then, before the ELO semiconductor layers 8 growing laterally from both sides on the mask portion 5 could meet, their lateral growth was stopped.

[0087] The width of the mask portion 5 was 50 μm, the width of the opening KS was 5 μm, the width of the ELO semiconductor layer 8 was 53 μm, the width of the effective portion EK (size in the X direction) was 24 μm, and the thickness of the ELO semiconductor layer 8 was 5 μm. The aspect ratio of the ELO semiconductor layer 8 was 53 μm / 5 μm = 10.6, achieving a very high aspect ratio.

[0088] In the formation of the ELO semiconductor layer 8 in Example 1, the lateral deposition rate is increased. The method for increasing the lateral deposition rate is as follows: First, a longitudinal growth layer (initial growth layer SL) growing in the Z direction (c-axis direction) is formed on the seed layer 3 exposed from the opening KS, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. In this case, by setting the thickness of the longitudinal growth layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the lateral growth layer can be kept low, and the lateral deposition rate can be increased.

[0089] As described above, in the semiconductor substrate 10 manufactured by depositing an ELO semiconductor layer 8 on a template substrate 7 using the ELO method, the area of ​​the region where meltback etching SMB occurred was relatively reduced. By using the template substrate 7 of Example 1, the possibility of meltback etching SMB occurring in the semiconductor substrate 10 was reduced compared to when using a conventional template substrate without a protective portion PS.

[0090] [Example 2] Figure 16 is a plan view showing the configuration of the template substrate 7 in Example 2. Figure 17A is a cross-sectional view taken along the line A-XVII shown in Figure 16. Figure 17B is a cross-sectional view taken along the line B-XVII shown in Figure 16.

[0091] In Example 1, a mask layer 6 having a mask portion 5 including a protective portion PS was formed on the base substrate UK, but in Example 2, the protective portion PS may be provided separately from the mask portion 5. As shown in Figures 16, 17A, and 17B, the template substrate 7 in Example 2 has a main substrate 1, a base layer 4, a mask layer 6, and a protective portion PS.

[0092] In Example 2, the protective part PS may be made of a different material than the mask part 5. The protective part PS may include an inorganic insulating film or inorganic insulating layer that does not contain or substantially contains Ga. Alternatively, the protective part PS may be, for example, a resin member, a metal member, or a ceramic member that does not contain or substantially contains Ga. The protective part PS is not particularly limited to any specific material that can reduce the possibility of meltback etching SMB occurring.

[0093] In addition, in Example 2, the protective part PS may have a shape that fits onto the side surface of the substrate UK, and in this case, the entire outer periphery of the substrate UK may be covered by combining multiple protective parts PS. The protective part PS may cover at least a part of the mask part 5 on the upper surface of the substrate UK, and may extend into at least a part of the opening KS. That is, the protective part PS may overlap with the edge E in a side view and with at least a part of the main surface 1a in a plan view. The protective part PS may also cover at least a part of the lower surface 1b, i.e., it may have a lower protective part PS1.

[0094] In Example 2, the thickness t3 of the protective portion PS may be greater than the thickness of the mask portion 5 in the layer above the main surface 1a. The thickness t3 may be, for example, 0.05 μm or more and 3 μm or less. As a result, a protective portion PS with a relatively large thickness exists from the upper surface of the substrate UK to the side portion SP of the substrate UK. Therefore, it is easy to increase the thickness of the protective portion PS covering the side portion SP of the substrate UK. As a result, it is possible to protect the side portion SP of the substrate UK. Thus, the possibility of meltback etching SMB occurring can be reduced.

[0095] In Example 2, for example, after the mask layer 6 is formed on the base substrate UK, an additional protective portion PS can be formed on the peripheral edge of the base substrate UK. Alternatively, the protective portion PS may be formed on the peripheral edge of the base substrate UK, and then the mask layer 6 may be formed. Furthermore, the template substrate 7 may be formed by attaching a pre-formed protective portion PS so as to cover the peripheral edge of the base substrate UK. In Example 2, the material, shape, thickness, etc., of the protective portion PS can be adjusted relatively easily, and the protective portion PS can also have a lower protective portion PS1.

[0096] [Example 3] Figure 18 is a plan view showing the configuration of the template substrate 7 in Example 3. Figure 19 is a cross-sectional view taken along the line XIX-XIX shown in Figure 18.

[0097] Examples 1 and 2 had an edge-to-edge mask layer 6, but are not limited to this. In Example 3, the mask layer 6 may have a shape in which the mask portion 5 is present at both ends in the longitudinal direction of the opening KS.

[0098] As shown in Figures 18 and 19, the template substrate 7 in Embodiment 3 comprises a main substrate 1, a base layer 4, and a mask layer 6, the mask layer 6 having a mask portion 5 including a protective portion PS. The mask layer 6 has an opening KS that is longitudinally shaped, and in a plan view, there may be a gap D1 between the tip KE of the opening KS and the edge E of the main substrate 1 (in other words, the position of the aforementioned ridge line RH).

[0099] In Example 3, the mask layer 6 can be formed by slightly changing the shape of the openings and etching the resist when patterning the resist using photolithography in the same manner as in Example 1 described above.

[0100] In Example 3, when the ELO semiconductor layer 8 is deposited on the template substrate 7, the following can be said for a cross-sectional area such as that shown in Figure 19. That is, since the tip KE of the opening KS is located at a position with the above-mentioned spacing D1, the growth starting point of the ELO semiconductor layer 8 can be set to a position relatively far from the edge E of the main substrate 1. Therefore, the possibility of the ELO semiconductor layer 8 being formed to wrap around to the side of the semiconductor substrate 10 can be reduced. The spacing D1 may be 1 μm or more, and may be between 1 μm and 6000 μm. By setting the spacing D1 to 1 μm or more, the possibility of the ELO semiconductor layer 8 being formed to wrap around to the side of the semiconductor substrate 10 can be further reduced. As a result, during the deposition of the ELO semiconductor layer 8, it is difficult for Ga derived from the Ga raw material to be additionally supplied to the side surface SP of the underlying substrate UK. This means that even if a reaction occurs at the aforementioned abnormal location DP, it can be limited to a local reaction between the seed layer 3 and the main substrate 1 at the abnormal location DP. Therefore, the possibility of meltback etching SMB can be reduced.

[0101] [Example 4] Figure 20 is a cross-sectional view showing the configuration of the template substrate 7 in Example 4.

[0102] After forming the mask layer 6 as in Example 3, in Example 4, a protective portion PS may be formed further, in which case a first protective portion FPS and a second protective portion SPS may be provided that overlap the edge E of the main substrate 1 in a side view.

[0103] As shown in Figure 20, in Embodiment 4, the mask layer 6 may have a mask portion 5 that includes a first protective portion FPS. That is, the first protective portion FPS and the mask portion 5 may be the same entity. The first protective portion FPS may be formed to cover the side portion SP of the substrate UK. Furthermore, Embodiment 4 may include a second protective portion SPS that covers the first protective portion FPS. The second protective portion SPS may be made of a different material than the mask portion 5.

[0104] The first protective section FPS may be formed in the same manner as in the previously described embodiment 1. The second protective section SPS may be formed in the same manner as in the previously described protective section PS of embodiment 2. The first protective section FPS may cover at least a portion of the lower surface 1b of the main substrate 1, that is, it may have a lower protective section PS1. In another example, the second protective section SPS may have a lower protective section PS1. In embodiment 4, at least one of the first protective section FPS and the second protective section SPS may have a lower protective section PS1.

[0105] In Example 4, when the ELO semiconductor layer 8 is deposited on the template substrate 7, the following can be said for a cross-sectional area as shown in Figure 20, for example. That is, in Example 4, the side portion SP of the base substrate UK is protected by both the first protective portion FPS and the second protective portion SPS. As a result, even if a reaction occurs at the aforementioned abnormal location DP, the first protective portion FPS and the second protective portion SPS can effectively reduce the supply of new Ga to the reaction site. Therefore, the reaction can be limited to a localized reaction between the seed layer 3 and the main substrate 1 at the abnormal location DP. As a result, the possibility of meltback etching SMB occurring can be greatly reduced. Furthermore, even if meltback etching SMB occurs locally, the possibility of the area of ​​the meltback etching SMB occurrence region expanding can be effectively reduced.

[0106] Figure 21 is a cross-sectional view showing an alternative configuration of the template substrate 7 in Example 4. In this alternative configuration of Example 4, the first protective portion FPS is not present, and the mask layer 6 may have a gap D1. In other words, in this alternative configuration of Example 4, as shown in Figure 21, the second protective portion SPS in Example 4 becomes the protective portion PS. In this alternative configuration of Example 4, in a plan view, there may be a gap D2 between the outer peripheral edge 5E of the template substrate 7 in the mask portion 5 and the edge E of the main substrate 1 (in other words, the position of the aforementioned ridge line RH). The gap D2 may be smaller than the gap D1. The gap D2 may be 1 μm or more and 3000 μm or less.

[0107] The end portion 5E of the mask portion 5 may be covered by the protective portion PS. In this case, the seed layer 3 is not exposed on the side portion SP of the base substrate UK, nor is the seed layer 3 exposed between the side portion SP and the end portion 5E. This reduces the possibility of Ga being supplied to the abnormal area DP. As a result, the possibility of meltback etching SMB occurring can be reduced.

[0108] [Example 5] Figure 22 is a plan view showing the configuration of the template substrate 7 in Example 5. Figure 23 is a cross-sectional view taken along the line XXIII-XXIII shown in Figure 22.

[0109] In Example 3, the mask portion 5 including the protective portion PS was formed with a gap D1, and the seed layer 3 overlapped the edge E in a side view, but the example is not limited to this. In Example 5, the seed layer 3 may not be present on the side portion SP of the substrate UK. By not having a seed layer 3 on the wafer side, the occurrence of meltback etching SMB due to non-uniformity of the wafer side shape can be suppressed.

[0110] As shown in Figures 22 and 23, in Example 5, there may be a gap D3 between the end 3E of the seed layer 3 and the edge E of the main substrate 1. The gap D3 may be smaller than the gap D1. The gap D3 may be, for example, 1 μm or more and 6000 μm or less.

[0111] Figure 24 is a cross-sectional view illustrating the manufacturing method of the template substrate 7 in Example 5. As shown in Figure 24, in Example 5, for example, first, a base substrate UK is prepared. If a seed layer 3 is formed over the entire surface of the buffer layer 2 of the base substrate UK, a portion of the seed layer 3 is removed by etching or the like so that there is a gap D3. Alternatively, after forming the buffer layer 2 on the main substrate 1, the wafer periphery may be masked with a photoresist or a dielectric film such as SiO2, and then a seed layer 3 may be formed with a gap D3 using a method such as lift-off. In this way, a base substrate UK with a portion of the seed layer 3 removed can be obtained.

[0112] Next, the mask layer 6 can be formed with a spacing D1, similar to the example in Example 3 described above. In this case, by forming the mask layer 6 such that the spacing D1 is larger than the spacing D3, it is possible to avoid creating any exposed areas of the buffer layer 2.

[0113] In Example 5, the seed layer 3 is not present on the side portion SP of the substrate UK. Therefore, even if there are abnormal areas DP such as cracks or thinning areas on the side portion SP of the substrate UK, the seed layer 3 is not in contact with the abnormal area DP, so there is no factor causing a reaction between the seed layer 3 and the main substrate 1 at the abnormal area DP. Furthermore, the buffer layer 2 is covered by the protective portion PS on the side portion SP of the substrate UK. Therefore, during the deposition of the ELO semiconductor layer 8, it is difficult for Ga derived from the Ga raw material to be supplied to the abnormal area DP on the side portion SP of the substrate UK. Thus, the possibility of meltback etching SMB can be reduced even more effectively.

[0114] [Example 6] Figure 25 is a plan view showing the configuration of the template substrate 7 in Example 6. Figure 26 is a cross-sectional view taken along the line XXVI-XXVI shown in Figure 25.

[0115] In Example 5, a portion of the seed layer 3 was removed before forming the mask layer 6, but the method is not limited to this. In Example 6, after forming the mask layer 6 on the substrate UK, the seed layer 3 and a portion of the mask portion 5 may be removed, and a protective portion PS may be provided to cover the end 5E of the mask portion 5 and the end 3E of the seed layer 3.

[0116] As shown in Figures 25 and 26, in Embodiment 6, there may be a gap D2 between the outer peripheral edge 5E of the template substrate 7 in the mask portion 5 and the edge E of the main substrate 1, and there may also be a gap D3 between the edge 3E of the seed layer 3 and the edge E of the main substrate 1. The gaps D2 and D3 may be the same or approximately the same. The gaps D2 and D3 may be different from each other.

[0117] In Example 6, for example, first, a base substrate UK is prepared. If a seed layer 3 is formed over the entire surface of the buffer layer 2 of the base substrate UK, a portion of the seed layer 3 may be removed by etching or the like to have a gap D3, and then a mask layer 6 may be formed to have a gap D2. Alternatively, a buffer layer 2 may be formed on the main substrate 1, then a seed layer 3 may be formed to have a gap D3, and then a mask layer 6 may be formed to have a gap D2. Alternatively, a buffer layer 2, a seed layer 3, and a mask layer 6 may be formed on the main substrate 1, and then a portion of the seed layer 3 and the mask portion 5 may be removed.

[0118] In Example 6, the same effects as in Example 5 are achieved, and when the ELO semiconductor layer 8 is deposited on the template substrate 7, the ELO semiconductor layer 8 that grows laterally in the Y direction can be formed on the protective portion PS. In other words, the ELO semiconductor layer 8 does not come into contact with the buffer layer 2. Therefore, in Example 6, the possibility of meltback etching SMB occurring can be further reduced.

[0119] [Example 7] Figure 27 is a plan view showing the configuration of the template substrate 7 in Example 7. Figure 28 is a cross-sectional view taken along the line XXVIII-XXVIII shown in Figure 27.

[0120] In Example 6, a protective section PS, which is a separate component from each layer of the base substrate UK, was formed on the outer periphery of the template substrate 7, but the example is not limited to this. In Example 7, the protective section PS may be included in the buffer layer 2.

[0121] As shown in Figures 27 and 28, Example 7 has the same mask layer 6 and seed layer 3 as Example 6 described above, and the buffer layer 2 may be used as the protective part PS. In other words, the buffer layer 2 may contain the protective part PS, and the buffer layer 2 and the protective part PS may be identical. The buffer layer 2 may contain, for example, at least one of an aluminum nitride film and a silicon carbide film, and may be a multilayer film.

[0122] In Example 7, as in Example 5 described above, there is no seed layer 3 on the side portion SP of the base substrate UK. Furthermore, the edge E of the main substrate 1 is covered by the buffer layer 2 on the side portion SP of the base substrate UK. Even if there are abnormal areas DP such as cracks or thinning areas in the buffer layer 2, the following can be said: Since the seed layer 3 is not in contact with the abnormal area DP, there is no factor causing a reaction between the seed layer 3 and the main substrate 1 at the abnormal area DP. In addition, when the ELO semiconductor layer 8 is deposited on the template substrate 7, because the buffer layer 2 is made of a material with poor reactivity with Ga, Ga derived from the Ga raw material is selectively supplied to the seed layer 3 portion. Therefore, the possibility of Ga being supplied to the abnormal area DP and causing meltback etching SMB can be reduced.

[0123] [Example 8] Figure 29 is a cross-sectional view showing the configuration of the template substrate 7 in Example 8.

[0124] As shown in Figure 29, in Example 8, the opening KS and mask portion 5 may be formed on the surface treatment film formed by thermal oxidation treatment or nitriding treatment of the main substrate 1 by etching or the like. This makes it possible to form the mask portion 5 including the protective portion PS. That is, the mask portion 5 may be made of the processed film of the main substrate 1.

[0125] In Example 8, for example, first, the main substrate 1 is subjected to thermal oxidation or nitriding to form a substrate processing film (thermal oxidation film or nitrided film) as the mask portion 5 of the mask layer 6. Then, after coating the substrate processing film with a resist, the resist is patterned using photolithography to form openings in the resist. Next, the substrate processing film is etched with an etchant such as hydrofluoric acid to form the openings KS. Subsequently, while leaving the resist intact, a base layer 4 is deposited inside the openings KS using a sputtering method or the like. This allows the template substrate 7 of Example 8 to be manufactured.

[0126] In Example 8, the seed layer 3 is absent from the edge E portion of the main substrate 1, and the edge E of the main substrate 1 is covered by the mask portion 5. Therefore, the possibility of meltback etching SMB can be effectively reduced.

[0127] [Example 9] Figure 30 is a cross-sectional view showing the configuration of the template substrate 7 in Example 9.

[0128] In Example 8, there was a mask portion 5, which is a substrate processing film, covering the edge E of the main substrate 1, but the example is not limited to this. In Example 9, there is a mask portion 5 formed by plasma CVD or the like, and the underlayer 4 does not need to be formed over the entire surface of the main surface 1a of the main substrate 1.

[0129] In Example 9, for example, a silicon oxide film is formed over the entire surface 1a of the main substrate 1, and then, as in Example 8 described above, an opening KS is formed, followed by the formation of a base layer 4 inside the opening KS. In Example 9, the seed layer 3 is not present at the edge E of the main substrate 1, and the edge E of the main substrate 1 is covered by the mask portion 5. Therefore, the possibility of meltback etching SMB can be effectively reduced.

[0130] [Example 10] Figure 31 is a cross-sectional view showing the configuration of the template substrate 7 in Example 10.

[0131] In Example 5, the seed layer 3 was not present on the side portion SP of the substrate UK, but the configuration is not limited to this. In Example 10, both the buffer layer 2 and the seed layer 3 were not present on the side portion SP of the substrate UK, and the mask layer 6 had a shape in which mask portions 5 were present at both ends in the longitudinal direction of the opening KS.

[0132] As shown in Figure 31, the template substrate 7 in Example 10 comprises a main substrate 1, a base layer 4, and a mask layer 6, the mask layer 6 having a mask portion 5 including a protective portion PS. The mask layer 6 has an opening KS that is longitudinally shaped, and in a plan view, there may be a gap D1 between the tip KE of the opening KS and the edge E of the main substrate 1 (in other words, the position of the aforementioned ridge line RH).

[0133] In Example 10, there may be a gap D3 (see Example 5) between the end 3E of the seed layer 3 and the edge E of the main substrate 1. There may also be a gap D4 between the end 2E of the buffer layer 2 and the edge E of the main substrate 1. The gap D4 may be smaller than the gap D1. The gap D4 may be, for example, 1 μm or more and 6000 μm or less. The gaps D3 and D4 may be the same or approximately the same. The gaps D3 and D4 may be different.

[0134] In Example 10, for example, first, a substrate UK is prepared. If a seed layer 3 is formed over the entire surface of the buffer layer 2 of the substrate UK, a portion of the seed layer 3 may be removed by etching or the like so that there is a gap D3. Alternatively, a portion of the buffer layer 2 may be removed by etching or the like so that there is a gap D4. It is sufficient to obtain a substrate UK from which the seed layer 3 and buffer layer 2 have been partially removed, and the specific method is not particularly limited.

[0135] Next, a mask layer 6 can be formed with a spacing D1, similar to the previous example 3. In this case, by forming the mask layer 6 such that spacing D1 is larger than spacing D3 and spacing D4, it is possible to avoid creating any exposed areas of the main substrate 1.

[0136] In Example 10, the seed layer 3 and buffer layer 2 are absent on the side surface SP of the substrate UK, and the edge E of the main substrate 1 is covered by the protective portion PS, which is part of the mask portion 5. Therefore, the possibility of abnormal areas DP existing on the side surface SP of the substrate UK is reduced, and the possibility of atmospheric Ga reaching the main substrate 1 and reacting during the deposition of the ELO semiconductor layer 8 is also reduced. As a result, the possibility of meltback etching SMB occurring can be reduced.

[0137] [Example 11] Figure 32 is a cross-sectional view showing the configuration of the template substrate 7 in Example 11.

[0138] In the aforementioned Embodiment 1, the substrate UK was configured such that a buffer layer 2 and a seed layer 3 were provided in order from the main substrate 1 side as the substrate layer 4, but it is not limited to this configuration. In one embodiment of the present disclosure, a buffer layer 2 does not need to be provided between the main substrate 1 and the seed layer 3.

[0139] As shown in Figure 32, in Example 11, there is a seed layer 3 without a buffer layer 2, and the base substrate UK has a main substrate 1 and a seed layer 3. A mask layer 6 is formed on the base substrate UK. The mask layer 6 has a mask portion 5 including a protective portion PS. In Example 11, the protective portion PS and the mask portion 5 may be one and the same.

[0140] The seed layer 3 may be made of a material that has low reactivity with the main substrate 1 and can serve as a growth starting point for the ELO semiconductor layer 8. The seed layer 3 may be, for example, an AlN layer or a SiC layer, and may be a layer containing at least one of AlN and SiC. The seed layer 3 may be a single layer or a multilayer film. The seed layer 3 may be a graded structure in which the Al composition changes in steps, for example, with an AlN film on the side closer to the main substrate 1 and a GaN film or AlGaN film on the side farther from the main substrate 1.

[0141] In Example 11, if the seed layer 3 is not sufficiently formed on the edge E of the main substrate 1, an abnormal area DP may be formed in the seed layer 3 on the side surface SP of the underlying substrate UK. However, the seed layer 3 can be a layer that does not contain Ga or is substantially Ga-free, and the seed layer 3 on the side surface SP of the underlying substrate UK is covered by a protective layer PS. Therefore, the possibility of a reaction between the silicon-containing main substrate 1 and Ga at the abnormal area DP can be reduced. Furthermore, even if a reaction occurs at the abnormal area DP in the seed layer 3, the supply of new Ga to the reaction site is reduced by the protective layer PS. As a result, the possibility of meltback etching SMB can be effectively reduced.

[0142] Furthermore, the various embodiments described above may also include configurations without a buffer layer 2, that is, configurations in which a buffer layer 2 is not provided between the main substrate 1 and the seed layer 3, and such embodiments are also included in this disclosure.

[0143] Figure 33 is a cross-sectional view showing an alternative configuration of the template substrate 7 in Example 11. As shown in Figure 33, the seed layer 3 is located on the main substrate 1, and the edges of the seed layer 3 (the parts covering the sides of the main substrate 1) may function as protective parts PS. In this case, the seed layer 3 can be a single-layer or multi-layer film having at least one of AlN and SiC. The thickness of the part of the seed layer 3 that covers the sides of the main substrate 1 (protective parts PS) may be greater than or equal to the thickness of the part that covers the top surface of the main substrate 1, and it may also wrap around to the bottom surface of the main substrate 1.

[0144] [Example 12] Figure 34 is a cross-sectional view showing the configuration of the template substrate 7 in Example 12. As shown in Figure 34, a buffer layer 2 is located on the main substrate 1, and a seed layer 3 is locally provided on the buffer layer 2 so as to overlap with the opening KS of the mask 6, and the edge of the buffer layer 2 (the part covering the side surface of the main substrate 1) may function as a protective part PS. In this case, the buffer layer 2 can be a single-layer or multi-layer film having at least one of AlN and SiC. The thickness of the part of the buffer layer 2 that covers the side surface of the main substrate 1 (protective part PS) may be greater than or equal to the thickness of the part that covers the top surface of the main substrate 1, and it may also wrap around to the bottom surface of the main substrate 1.

[0145] [Additional notes] The inventions described in this disclosure have been explained above based on the drawings and embodiments. However, the inventions described in this disclosure are not limited to the embodiments described above. For example, although the above examples describe the use of a main substrate containing silicon, this disclosure is effective when using a main substrate that may cause meltback etching during the formation of the semiconductor layer, and the scope of application of this disclosure is not limited to main substrates containing silicon. Thus, the inventions described in this disclosure can be modified in various ways within the scope shown in this disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the inventions described in this disclosure. In other words, it should be noted that it is easy for those skilled in the art to make various modifications or alterations based on this disclosure. Furthermore, it should be noted that these modifications or alterations are included in the scope of this disclosure. [Explanation of symbols]

[0146] 1 Main board 1a Main surface 1b Bottom side 2. Buffer layer (buffer section) 3. Seed layer (seed portion) 3E, 5E end 4 Base layer (base part) 5 Mask section 6 Mask Layers (Mask) 7. Template board 8 ELO semiconductor layer (ELO semiconductor part) 9. Functional Layer (Functional Part) 10 Semiconductor substrates 20 Semiconductor Devices 23 Drive board 25 Control circuits 30 Electronic equipment 70 Manufacturing equipment 71 Mask layer formation section 72 Protective part forming part 73 Semiconductor layer formation section 74 Control Unit D1, D2, D3, D4 intervals E edge (side) Ef flat part Er curved surface KS opening PS protection part PS1 lower protection part

Claims

1. A main substrate containing silicon and having a main surface and side surfaces, A mask having an opening located above the main substrate and a mask portion, A seed layer having a seed portion that overlaps the opening in a plan view, A buffer portion having at least a first portion located between the main substrate and the seed layer, which overlaps with the main surface in a plan view, and a second portion which overlaps with the side surface in a side view, It includes a protective section containing a material different from gallium, The buffer portion has a first region in the second portion that is thinner in thickness compared to the first portion. The protective portion is a template substrate used for forming a GaN-based semiconductor by the ELO method, which overlaps with at least the first region in a side view.

2. The template substrate according to claim 1, wherein the seed layer overlaps with the first portion in a plan view and overlaps with the second portion in a side view.

3. The template substrate according to claim 1 or 2, wherein the second portion overlaps with the entire side surface in a side view.

4. The template substrate according to claim 1 or 2, wherein the protective portion is in contact with the mask portion.

5. The template substrate according to claim 1 or 2, wherein the protective portion is located from a position overlapping the main surface in a plan view to a position overlapping the side surface in a side view.

6. The main substrate further has a lower surface, The template substrate according to claim 1 or 2, wherein the protective portion is in contact with the lower surface of the main substrate.

7. The main substrate further has a lower surface, The template substrate according to claim 1 or 2, wherein the protective portion is located from a position overlapping the main surface in a plan view to the lower surface.

8. The template substrate according to claim 1 or 2, wherein the entire seed portion is in contact with either the mask portion or the protective portion.

9. The template substrate according to claim 1 or 2, wherein the thickness of the protective portion is greater than the thickness of the mask portion.

10. The template substrate according to claim 1 or 2, wherein the thickness of the protective portion located on the side is greater than the thickness of the portion located on the main surface.

11. The template substrate according to claim 1 or 2, wherein the protective portion is made of a different material from the mask portion.

12. The template substrate according to claim 1 or 2, wherein the protective portion is made of the same material as the mask portion.

13. The template substrate according to claim 12, wherein the protective portion and the mask portion are integrally formed.

14. The template substrate according to claim 1 or 2, wherein the protective portion comprises at least one of a silicon nitride, a silicon oxide, or a silicon oxynitride.

15. The template substrate according to claim 1 or 2, wherein the buffer portion comprises at least one of aluminum nitride or silicon carbide.

16. The template substrate according to claim 1 or 2, wherein the seed portion includes a GaN-based semiconductor.

17. A semiconductor substrate having a template substrate and a semiconductor portion, The aforementioned template substrate is A main substrate containing silicon and having a main surface and side surfaces, A mask having an opening located above the main substrate and a mask portion, A seed layer having a seed portion that overlaps the opening in a plan view, A buffer portion having at least a first portion located between the main substrate and the seed layer, which overlaps with the main surface in a plan view, and a second portion which overlaps with the side surface in a side view, It includes a protective section containing a material different from gallium, The buffer portion has a first region in the second portion that is thinner in thickness compared to the first portion. The protective portion is positioned so as to overlap with at least the first region in a side view, The semiconductor portion is a semiconductor substrate located above the template substrate and having a portion that extends in a direction along the main surface.

18. The semiconductor substrate according to claim 17, wherein the semiconductor portion includes a GaN-based semiconductor.

19. A semiconductor substrate according to claim 17 or 18, having a functional portion located above the semiconductor portion.

20. A semiconductor device having the semiconductor portion according to claim 17.

21. The electronic device comprising the semiconductor portion according to claim 17.

22. A step of preparing a main substrate containing silicon and having a main surface and side surfaces, A step of forming a buffer portion having at least a first portion that contacts the main surface of the main substrate and a second portion that contacts the side surface, A step of forming a seed portion that contacts at least the first portion, A step of forming a mask that comes into contact with the seed portion, The process includes forming a protective portion that overlaps with the side surface in a side view, The buffer portion has a first region in the second portion that is thinner than the first portion. A method for manufacturing a template substrate used in the formation of a GaN-based semiconductor by the ELO method, wherein the protective portion is formed so as to overlap with at least the first region in a side view.

23. A step of preparing a main substrate containing silicon and having a main surface and side surfaces, A step of forming a buffer portion having at least a first portion that contacts the main surface of the main substrate and a second portion that contacts the side surface, A step of forming a seed portion that contacts at least the first portion, A step of forming a mask portion and a protective portion that come into contact with the seed portion, The process includes forming at least one opening in the mask portion, The buffer portion has a first region in the second portion that is thinner than the first portion. A method for manufacturing a template substrate used in the formation of a GaN-based semiconductor by the ELO method, wherein the protective portion is formed so as to overlap with at least the first region in a side view.

24. A step of preparing a template substrate as described in claim 1, A method for manufacturing a semiconductor substrate, comprising the step of forming a semiconductor portion located above the mask portion and having a portion extending in a direction along the main surface.

Images